Root/target/linux/octeon/patches-2.6.30/003_pci_pcie_support.patch

1This patch adds support for PCI and PCIe to the base Cavium OCTEON
2processor support.
3
4Signed-off-by: David Daney <ddaney@caviumnetworks.com>
5---
6 arch/mips/Kconfig | 2 +
7 arch/mips/cavium-octeon/Makefile | 4 +
8 arch/mips/cavium-octeon/dma-octeon.c | 310 ++++++-
9 arch/mips/cavium-octeon/executive/Makefile | 2 +
10 .../cavium-octeon/executive/cvmx-helper-errata.c | 379 +++++++
11 .../cavium-octeon/executive/cvmx-helper-util.c | 502 ++++++++++
12 arch/mips/cavium-octeon/executive/cvmx-pcie.c | 1053 ++++++++++++++++++++
13 arch/mips/cavium-octeon/msi.c | 288 ++++++
14 arch/mips/cavium-octeon/octeon-irq.c | 2 +
15 arch/mips/cavium-octeon/pci-common.c | 137 +++
16 arch/mips/cavium-octeon/pci-common.h | 39 +
17 arch/mips/cavium-octeon/pci.c | 568 +++++++++++
18 arch/mips/cavium-octeon/pcie.c | 441 ++++++++
19 arch/mips/include/asm/octeon/cvmx-asm.h | 3 +-
20 arch/mips/include/asm/octeon/cvmx-helper-errata.h | 92 ++
21 arch/mips/include/asm/octeon/cvmx-helper-util.h | 266 +++++
22 arch/mips/include/asm/octeon/cvmx-packet.h | 16 +-
23 arch/mips/include/asm/octeon/cvmx-pcie.h | 284 ++++++
24 arch/mips/include/asm/octeon/cvmx-wqe.h | 422 ++++++++
25 arch/mips/include/asm/octeon/cvmx.h | 12 +
26 arch/mips/include/asm/octeon/octeon.h | 2 +
27 21 files changed, 4816 insertions(+), 8 deletions(-)
28 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
29 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-util.c
30 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-pcie.c
31 create mode 100644 arch/mips/cavium-octeon/msi.c
32 create mode 100644 arch/mips/cavium-octeon/pci-common.c
33 create mode 100644 arch/mips/cavium-octeon/pci-common.h
34 create mode 100644 arch/mips/cavium-octeon/pci.c
35 create mode 100644 arch/mips/cavium-octeon/pcie.c
36 create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-errata.h
37 create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-util.h
38 create mode 100644 arch/mips/include/asm/octeon/cvmx-pcie.h
39 create mode 100644 arch/mips/include/asm/octeon/cvmx-wqe.h
40
41--- a/arch/mips/Kconfig
42+++ b/arch/mips/Kconfig
43@@ -618,6 +618,8 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
44     select SYS_HAS_EARLY_PRINTK
45     select SYS_HAS_CPU_CAVIUM_OCTEON
46     select SWAP_IO_SPACE
47+ select HW_HAS_PCI
48+ select ARCH_SUPPORTS_MSI
49     help
50       This option supports all of the Octeon reference boards from Cavium
51       Networks. It builds a kernel that dynamically determines the Octeon
52--- a/arch/mips/cavium-octeon/Makefile
53+++ b/arch/mips/cavium-octeon/Makefile
54@@ -14,5 +14,9 @@ obj-y += dma-octeon.o flash_setup.o
55 obj-y += octeon-memcpy.o
56 
57 obj-$(CONFIG_SMP) += smp.o
58+obj-$(CONFIG_PCI) += pci-common.o
59+obj-$(CONFIG_PCI) += pci.o
60+obj-$(CONFIG_PCI) += pcie.o
61+obj-$(CONFIG_PCI_MSI) += msi.o
62 
63 EXTRA_CFLAGS += -Werror
64--- a/arch/mips/cavium-octeon/dma-octeon.c
65+++ b/arch/mips/cavium-octeon/dma-octeon.c
66@@ -13,20 +13,326 @@
67  */
68 #include <linux/types.h>
69 #include <linux/mm.h>
70+#include <linux/module.h>
71+#include <linux/string.h>
72+#include <linux/dma-mapping.h>
73+#include <linux/platform_device.h>
74+#include <linux/scatterlist.h>
75+
76+#include <linux/cache.h>
77+#include <linux/io.h>
78+
79+#include <asm/octeon/octeon.h>
80+#include <asm/octeon/cvmx-npi-defs.h>
81+#include <asm/octeon/cvmx-pci-defs.h>
82 
83 #include <dma-coherence.h>
84 
85+#ifdef CONFIG_PCI
86+#include "pci-common.h"
87+#endif
88+
89+#define BAR2_PCI_ADDRESS 0x8000000000ul
90+
91+struct bar1_index_state {
92+ int16_t ref_count; /* Number of PCI mappings using this index */
93+ uint16_t address_bits; /* Upper bits of physical address. This is
94+ shifted 22 bits */
95+};
96+
97+#ifdef CONFIG_PCI
98+static DEFINE_SPINLOCK(bar1_lock);
99+static struct bar1_index_state bar1_state[32];
100+#endif
101+
102 dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
103 {
104+#ifndef CONFIG_PCI
105     /* Without PCI/PCIe this function can be called for Octeon internal
106        devices such as USB. These devices all support 64bit addressing */
107     mb();
108     return virt_to_phys(ptr);
109+#else
110+ unsigned long flags;
111+ uint64_t dma_mask;
112+ int64_t start_index;
113+ dma_addr_t result = -1;
114+ uint64_t physical = virt_to_phys(ptr);
115+ int64_t index;
116+
117+ mb();
118+ /*
119+ * Use the DMA masks to determine the allowed memory
120+ * region. For us it doesn't limit the actual memory, just the
121+ * address visible over PCI. Devices with limits need to use
122+ * lower indexed Bar1 entries.
123+ */
124+ if (dev) {
125+ dma_mask = dev->coherent_dma_mask;
126+ if (dev->dma_mask)
127+ dma_mask = *dev->dma_mask;
128+ } else
129+ dma_mask = 0xfffffffful;
130+
131+ /*
132+ * Platform devices, such as the internal USB, skip all
133+ * translation and use Octeon physical addresses directly.
134+ */
135+ if (dev->bus == &platform_bus_type)
136+ return physical;
137+
138+ switch (octeon_dma_bar_type) {
139+ case OCTEON_DMA_BAR_TYPE_PCIE:
140+ if (unlikely(physical < (16ul << 10)))
141+ panic("dma_map_single: Not allowed to map first 16KB."
142+ " It interferes with BAR0 special area\n");
143+ else if ((physical + size >= (256ul << 20)) &&
144+ (physical < (512ul << 20)))
145+ panic("dma_map_single: Not allowed to map bootbus\n");
146+ else if ((physical + size >= 0x400000000ull) &&
147+ physical < 0x410000000ull)
148+ panic("dma_map_single: "
149+ "Attempt to map illegal memory address 0x%lx\n",
150+ physical);
151+ else if (physical >= 0x420000000ull)
152+ panic("dma_map_single: "
153+ "Attempt to map illegal memory address 0x%lx\n",
154+ physical);
155+ else if ((physical + size >=
156+ (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
157+ && physical < (4ull<<30))
158+ pr_warning("dma_map_single: Warning: "
159+ "Mapping memory address that might "
160+ "conflict with devices 0x%lx-0x%lx\n",
161+ physical, physical+size-1);
162+ /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
163+ if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
164+ result = physical - 0x400000000ull;
165+ else
166+ result = physical;
167+ if (((result+size-1) & dma_mask) != result+size-1)
168+ panic("dma_map_single: Attempt to map address "
169+ "0x%lx-0x%lx, which can't be accessed according "
170+ "to the dma mask 0x%lx\n",
171+ physical, physical+size-1, dma_mask);
172+ goto done;
173+
174+ case OCTEON_DMA_BAR_TYPE_BIG:
175+#ifdef CONFIG_64BIT
176+ /* If the device supports 64bit addressing, then use BAR2 */
177+ if (dma_mask > BAR2_PCI_ADDRESS) {
178+ result = physical + BAR2_PCI_ADDRESS;
179+ goto done;
180+ }
181+#endif
182+ if (unlikely(physical < (4ul << 10))) {
183+ panic("dma_map_single: Not allowed to map first 4KB. "
184+ "It interferes with BAR0 special area\n");
185+ } else if (physical < (256ul << 20)) {
186+ if (unlikely(physical + size > (256ul << 20)))
187+ panic("dma_map_single: Requested memory spans "
188+ "Bar0 0:256MB and bootbus\n");
189+ result = physical;
190+ goto done;
191+ } else if (unlikely(physical < (512ul << 20))) {
192+ panic("dma_map_single: Not allowed to map bootbus\n");
193+ } else if (physical < (2ul << 30)) {
194+ if (unlikely(physical + size > (2ul << 30)))
195+ panic("dma_map_single: Requested memory spans "
196+ "Bar0 512MB:2GB and BAR1\n");
197+ result = physical;
198+ goto done;
199+ } else if (physical < (2ul << 30) + (128 << 20)) {
200+ /* Fall through */
201+ } else if (physical <
202+ (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
203+ if (unlikely
204+ (physical + size >
205+ (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
206+ panic("dma_map_single: Requested memory "
207+ "extends past Bar1 (4GB-%luMB)\n",
208+ OCTEON_PCI_BAR1_HOLE_SIZE);
209+ result = physical;
210+ goto done;
211+ } else if ((physical >= 0x410000000ull) &&
212+ (physical < 0x420000000ull)) {
213+ if (unlikely(physical + size > 0x420000000ull))
214+ panic("dma_map_single: Requested memory spans "
215+ "non existant memory\n");
216+ /* BAR0 fixed mapping 256MB:512MB ->
217+ * 16GB+256MB:16GB+512MB */
218+ result = physical - 0x400000000ull;
219+ goto done;
220+ } else {
221+ /* Continued below switch statement */
222+ }
223+ break;
224+
225+ case OCTEON_DMA_BAR_TYPE_SMALL:
226+#ifdef CONFIG_64BIT
227+ /* If the device supports 64bit addressing, then use BAR2 */
228+ if (dma_mask > BAR2_PCI_ADDRESS) {
229+ result = physical + BAR2_PCI_ADDRESS;
230+ goto done;
231+ }
232+#endif
233+ /* Continued below switch statement */
234+ break;
235+
236+ default:
237+ panic("dma_map_single: Invalid octeon_dma_bar_type\n");
238+ }
239+
240+ /* Don't allow mapping to span multiple Bar entries. The hardware guys
241+ won't guarantee that DMA across boards work */
242+ if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
243+ panic("dma_map_single: "
244+ "Requested memory spans more than one Bar1 entry\n");
245+
246+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
247+ start_index = 31;
248+ else if (unlikely(dma_mask < (1ul << 27)))
249+ start_index = (dma_mask >> 22);
250+ else
251+ start_index = 31;
252+
253+ /* Only one processor can access the Bar register at once */
254+ spin_lock_irqsave(&bar1_lock, flags);
255+
256+ /* Look through Bar1 for existing mapping that will work */
257+ for (index = start_index; index >= 0; index--) {
258+ if ((bar1_state[index].address_bits == physical >> 22) &&
259+ (bar1_state[index].ref_count)) {
260+ /* An existing mapping will work, use it */
261+ bar1_state[index].ref_count++;
262+ if (unlikely(bar1_state[index].ref_count < 0))
263+ panic("dma_map_single: "
264+ "Bar1[%d] reference count overflowed\n",
265+ (int) index);
266+ result = (index << 22) | (physical & ((1 << 22) - 1));
267+ /* Large BAR1 is offset at 2GB */
268+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
269+ result += 2ul << 30;
270+ goto done_unlock;
271+ }
272+ }
273+
274+ /* No existing mappings, look for a free entry */
275+ for (index = start_index; index >= 0; index--) {
276+ if (unlikely(bar1_state[index].ref_count == 0)) {
277+ union cvmx_pci_bar1_indexx bar1_index;
278+ /* We have a free entry, use it */
279+ bar1_state[index].ref_count = 1;
280+ bar1_state[index].address_bits = physical >> 22;
281+ bar1_index.u32 = 0;
282+ /* Address bits[35:22] sent to L2C */
283+ bar1_index.s.addr_idx = physical >> 22;
284+ /* Don't put PCI accesses in L2. */
285+ bar1_index.s.ca = 1;
286+ /* Endian Swap Mode */
287+ bar1_index.s.end_swp = 1;
288+ /* Set '1' when the selected address range is valid. */
289+ bar1_index.s.addr_v = 1;
290+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
291+ bar1_index.u32);
292+ /* An existing mapping will work, use it */
293+ result = (index << 22) | (physical & ((1 << 22) - 1));
294+ /* Large BAR1 is offset at 2GB */
295+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
296+ result += 2ul << 30;
297+ goto done_unlock;
298+ }
299+ }
300+
301+ pr_err("dma_map_single: "
302+ "Can't find empty BAR1 index for physical mapping 0x%llx\n",
303+ (unsigned long long) physical);
304+
305+done_unlock:
306+ spin_unlock_irqrestore(&bar1_lock, flags);
307+done:
308+ pr_debug("dma_map_single 0x%lx->0x%lx\n", physical, result);
309+ return result;
310+#endif
311 }
312 
313 void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
314 {
315- /* Without PCI/PCIe this function can be called for Octeon internal
316- * devices such as USB. These devices all support 64bit addressing */
317+#ifndef CONFIG_PCI
318+ /*
319+ * Without PCI/PCIe this function can be called for Octeon internal
320+ * devices such as USB. These devices all support 64bit addressing.
321+ */
322+ return;
323+#else
324+ unsigned long flags;
325+ uint64_t index;
326+
327+ /*
328+ * Platform devices, such as the internal USB, skip all
329+ * translation and use Octeon physical addresses directly.
330+ */
331+ if (dev->bus == &platform_bus_type)
332+ return;
333+
334+ switch (octeon_dma_bar_type) {
335+ case OCTEON_DMA_BAR_TYPE_PCIE:
336+ /* Nothing to do, all mappings are static */
337+ goto done;
338+
339+ case OCTEON_DMA_BAR_TYPE_BIG:
340+#ifdef CONFIG_64BIT
341+ /* Nothing to do for addresses using BAR2 */
342+ if (dma_addr >= BAR2_PCI_ADDRESS)
343+ goto done;
344+#endif
345+ if (unlikely(dma_addr < (4ul << 10)))
346+ panic("dma_unmap_single: Unexpect DMA address 0x%lx\n",
347+ dma_addr);
348+ else if (dma_addr < (2ul << 30))
349+ /* Nothing to do for addresses using BAR0 */
350+ goto done;
351+ else if (dma_addr < (2ul << 30) + (128ul << 20))
352+ /* Need to unmap, fall through */
353+ index = (dma_addr - (2ul << 30)) >> 22;
354+ else if (dma_addr <
355+ (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
356+ goto done; /* Nothing to do for the rest of BAR1 */
357+ else
358+ panic("dma_unmap_single: Unexpect DMA address 0x%lx\n",
359+ dma_addr);
360+ /* Continued below switch statement */
361+ break;
362+
363+ case OCTEON_DMA_BAR_TYPE_SMALL:
364+#ifdef CONFIG_64BIT
365+ /* Nothing to do for addresses using BAR2 */
366+ if (dma_addr >= BAR2_PCI_ADDRESS)
367+ goto done;
368+#endif
369+ index = dma_addr >> 22;
370+ /* Continued below switch statement */
371+ break;
372+
373+ default:
374+ panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
375+ }
376+
377+ if (unlikely(index > 31))
378+ panic("dma_unmap_single: "
379+ "Attempt to unmap an invalid address (0x%llx)\n",
380+ (unsigned long long) dma_addr);
381+
382+ spin_lock_irqsave(&bar1_lock, flags);
383+ bar1_state[index].ref_count--;
384+ if (bar1_state[index].ref_count == 0)
385+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
386+ else if (unlikely(bar1_state[index].ref_count < 0))
387+ panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
388+ (int) index);
389+ spin_unlock_irqrestore(&bar1_lock, flags);
390+done:
391+ pr_debug("dma_unmap_single 0x%lx\n", dma_addr);
392     return;
393+#endif
394 }
395--- a/arch/mips/cavium-octeon/executive/Makefile
396+++ b/arch/mips/cavium-octeon/executive/Makefile
397@@ -11,3 +11,5 @@
398 
399 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
400 
401+obj-$(CONFIG_PCI) += cvmx-pcie.o
402+obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-util.o
403--- /dev/null
404+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
405@@ -0,0 +1,379 @@
406+/***********************license start***************
407+ * Author: Cavium Networks
408+ *
409+ * Contact: support@caviumnetworks.com
410+ * This file is part of the OCTEON SDK
411+ *
412+ * Copyright (c) 2003-2008 Cavium Networks
413+ *
414+ * This file is free software; you can redistribute it and/or modify
415+ * it under the terms of the GNU General Public License, Version 2, as
416+ * published by the Free Software Foundation.
417+ *
418+ * This file is distributed in the hope that it will be useful, but
419+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
420+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
421+ * NONINFRINGEMENT. See the GNU General Public License for more
422+ * details.
423+ *
424+ * You should have received a copy of the GNU General Public License
425+ * along with this file; if not, write to the Free Software
426+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
427+ * or visit http://www.gnu.org/licenses/.
428+ *
429+ * This file may also be available under a different license from Cavium.
430+ * Contact Cavium Networks for more information
431+ ***********************license end**************************************/
432+
433+/**
434+ *
435+ * Fixes and workaround for Octeon chip errata. This file
436+ * contains functions called by cvmx-helper to workaround known
437+ * chip errata. For the most part, code doesn't need to call
438+ * these functions directly.
439+ *
440+ */
441+#include <asm/octeon/octeon.h>
442+
443+#include <asm/octeon/cvmx-helper-util.h>
444+
445+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
446+
447+/**
448+ * @INTERNAL
449+ * Function to adjust internal IPD pointer alignments
450+ *
451+ * Returns 0 on success
452+ * !0 on failure
453+ */
454+int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
455+{
456+#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \
457+ (CVMX_FPA_PACKET_POOL_SIZE - 8 - CVMX_HELPER_FIRST_MBUFF_SKIP)
458+#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \
459+ (CVMX_FPA_PACKET_POOL_SIZE - 8 - CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
460+#define FIX_IPD_OUTPORT 0
461+ /* Ports 0-15 are interface 0, 16-31 are interface 1 */
462+#define INTERFACE(port) (port >> 4)
463+#define INDEX(port) (port & 0xf)
464+ uint64_t *p64;
465+ cvmx_pko_command_word0_t pko_command;
466+ cvmx_buf_ptr_t g_buffer, pkt_buffer;
467+ cvmx_wqe_t *work;
468+ int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
469+ cvmx_gmxx_prtx_cfg_t gmx_cfg;
470+ int retry_cnt;
471+ int retry_loop_cnt;
472+ int mtu;
473+ int i;
474+ cvmx_helper_link_info_t link_info;
475+
476+ /* Save values for restore at end */
477+ uint64_t prtx_cfg =
478+ cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT),
479+ INTERFACE(FIX_IPD_OUTPORT)));
480+ uint64_t tx_ptr_en =
481+ cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
482+ uint64_t rx_ptr_en =
483+ cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
484+ uint64_t rxx_jabber =
485+ cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT),
486+ INTERFACE(FIX_IPD_OUTPORT)));
487+ uint64_t frame_max =
488+ cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT),
489+ INTERFACE(FIX_IPD_OUTPORT)));
490+
491+ /* Configure port to gig FDX as required for loopback mode */
492+ cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
493+
494+ /*
495+ * Disable reception on all ports so if traffic is present it
496+ * will not interfere.
497+ */
498+ cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
499+
500+ cvmx_wait(100000000ull);
501+
502+ for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
503+ retry_cnt = 100000;
504+ wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
505+ pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
506+ wqe_pcnt &= 0x7f;
507+
508+ num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
509+
510+ if (num_segs == 0)
511+ goto fix_ipd_exit;
512+
513+ num_segs += 1;
514+
515+ size =
516+ FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES +
517+ ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
518+ (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
519+
520+ cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)),
521+ 1 << INDEX(FIX_IPD_OUTPORT));
522+ CVMX_SYNC;
523+
524+ g_buffer.u64 = 0;
525+ g_buffer.s.addr =
526+ cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
527+ if (g_buffer.s.addr == 0) {
528+ cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer "
529+ "allocation failure.\n");
530+ goto fix_ipd_exit;
531+ }
532+
533+ g_buffer.s.pool = CVMX_FPA_WQE_POOL;
534+ g_buffer.s.size = num_segs;
535+
536+ pkt_buffer.u64 = 0;
537+ pkt_buffer.s.addr =
538+ cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
539+ if (pkt_buffer.s.addr == 0) {
540+ cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer "
541+ "allocation failure.\n");
542+ goto fix_ipd_exit;
543+ }
544+ pkt_buffer.s.i = 1;
545+ pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
546+ pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
547+
548+ p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr);
549+ p64[0] = 0xffffffffffff0000ull;
550+ p64[1] = 0x08004510ull;
551+ p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull;
552+ p64[3] = 0x3a5fc0a81073c0a8ull;
553+
554+ for (i = 0; i < num_segs; i++) {
555+ if (i > 0)
556+ pkt_buffer.s.size =
557+ FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
558+
559+ if (i == (num_segs - 1))
560+ pkt_buffer.s.i = 0;
561+
562+ *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr +
563+ 8 * i) = pkt_buffer.u64;
564+ }
565+
566+ /* Build the PKO command */
567+ pko_command.u64 = 0;
568+ pko_command.s.segs = num_segs;
569+ pko_command.s.total_bytes = size;
570+ pko_command.s.dontfree = 0;
571+ pko_command.s.gather = 1;
572+
573+ gmx_cfg.u64 =
574+ cvmx_read_csr(CVMX_GMXX_PRTX_CFG
575+ (INDEX(FIX_IPD_OUTPORT),
576+ INTERFACE(FIX_IPD_OUTPORT)));
577+ gmx_cfg.s.en = 1;
578+ cvmx_write_csr(CVMX_GMXX_PRTX_CFG
579+ (INDEX(FIX_IPD_OUTPORT),
580+ INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
581+ cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
582+ 1 << INDEX(FIX_IPD_OUTPORT));
583+ cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
584+ 1 << INDEX(FIX_IPD_OUTPORT));
585+
586+ mtu =
587+ cvmx_read_csr(CVMX_GMXX_RXX_JABBER
588+ (INDEX(FIX_IPD_OUTPORT),
589+ INTERFACE(FIX_IPD_OUTPORT)));
590+ cvmx_write_csr(CVMX_GMXX_RXX_JABBER
591+ (INDEX(FIX_IPD_OUTPORT),
592+ INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
593+ cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
594+ (INDEX(FIX_IPD_OUTPORT),
595+ INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
596+
597+#if CVMX_PKO_USE_FAU_FOR_OUTPUT_QUEUES
598+ cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT,
599+ cvmx_pko_get_base_queue
600+ (FIX_IPD_OUTPORT),
601+ CVMX_PKO_LOCK_NONE);
602+ cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT,
603+ cvmx_pko_get_base_queue
604+ (FIX_IPD_OUTPORT), pko_command,
605+ g_buffer, CVMX_PKO_LOCK_NONE);
606+#else
607+ cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT,
608+ cvmx_pko_get_base_queue
609+ (FIX_IPD_OUTPORT),
610+ CVMX_PKO_LOCK_CMD_QUEUE);
611+ cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT,
612+ cvmx_pko_get_base_queue
613+ (FIX_IPD_OUTPORT), pko_command,
614+ g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
615+#endif
616+ CVMX_SYNC;
617+
618+ do {
619+ work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
620+ retry_cnt--;
621+ } while ((work == NULL) && (retry_cnt > 0));
622+
623+ if (!retry_cnt)
624+ cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
625+ "get_work() timeout occured.\n");
626+
627+ /* Free packet */
628+ if (work)
629+ cvmx_helper_free_packet_data(work);
630+ }
631+
632+fix_ipd_exit:
633+
634+ /* Return CSR configs to saved values */
635+ cvmx_write_csr(CVMX_GMXX_PRTX_CFG
636+ (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
637+ prtx_cfg);
638+ cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
639+ tx_ptr_en);
640+ cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
641+ rx_ptr_en);
642+ cvmx_write_csr(CVMX_GMXX_RXX_JABBER
643+ (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
644+ rxx_jabber);
645+ cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
646+ (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
647+ frame_max);
648+ cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
649+ /* Set link to down so autonegotiation will set it up again */
650+ link_info.u64 = 0;
651+ cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
652+
653+ /*
654+ * Bring the link back up as autonegotiation is not done in
655+ * user applications.
656+ */
657+ cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
658+
659+ CVMX_SYNC;
660+ if (num_segs)
661+ cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
662+
663+ return !!num_segs;
664+
665+}
666+
667+/**
668+ * @INTERNAL
669+ * Workaround ASX setup errata with CN38XX pass1
670+ *
671+ * @interface: Interface to setup
672+ * @port: Port to setup (0..3)
673+ * @cpu_clock_hz:
674+ * Chip frequency in Hertz
675+ *
676+ * Returns Zero on success, negative on failure
677+ */
678+int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz)
679+{
680+ /* Set hi water mark as per errata GMX-4 */
681+ if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
682+ cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
683+ else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
684+ cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
685+ else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
686+ cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
687+ else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
688+ cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
689+ else
690+ cvmx_dprintf("Illegal clock frequency (%d). "
691+ "CVMX_ASXX_TX_HI_WATERX not set\n",
692+ cpu_clock_hz);
693+ return 0;
694+}
695+
696+/**
697+ * This function needs to be called on all Octeon chips with
698+ * errata PKI-100.
699+ *
700+ * The Size field is 8 too large in WQE and next pointers
701+ *
702+ * The Size field generated by IPD is 8 larger than it should
703+ * be. The Size field is <55:40> of both:
704+ * - WORD3 in the work queue entry, and
705+ * - the next buffer pointer (which precedes the packet data
706+ * in each buffer).
707+ *
708+ * @work: Work queue entry to fix
709+ * Returns Zero on success. Negative on failure
710+ */
711+int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
712+{
713+ uint64_t number_buffers = work->word2.s.bufs;
714+
715+ /* We only need to do this if the work has buffers */
716+ if (number_buffers) {
717+ cvmx_buf_ptr_t buffer_ptr = work->packet_ptr;
718+ /* Check for errata PKI-100 */
719+ if ((buffer_ptr.s.pool == 0) &&
720+ (((uint64_t) buffer_ptr.s.size +
721+ ((uint64_t) buffer_ptr.s.back << 7) +
722+ ((uint64_t) buffer_ptr.s.addr & 0x7F)) !=
723+ (CVMX_FPA_PACKET_POOL_SIZE + 8))) {
724+ /* fix is not needed */
725+ return 0;
726+ }
727+ /* Decrement the work packet pointer */
728+ buffer_ptr.s.size -= 8;
729+ work->packet_ptr = buffer_ptr;
730+
731+ /*
732+ * Now loop through decrementing the size for each
733+ * additional buffer.
734+ */
735+ while (--number_buffers) {
736+ /* Chain pointers are 8 bytes before the data */
737+ cvmx_buf_ptr_t *ptr =
738+ (cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
739+ buffer_ptr = *ptr;
740+ buffer_ptr.s.size -= 8;
741+ *ptr = buffer_ptr;
742+ }
743+ }
744+ /*
745+ * Make sure that these write go out before other operations
746+ * such as FPA frees.
747+ */
748+ CVMX_SYNCWS;
749+ return 0;
750+}
751+
752+#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
753+
754+/**
755+ * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
756+ * 1 doesn't work properly. The following code disables 2nd order
757+ * CDR for the specified QLM.
758+ *
759+ * @qlm: QLM to disable 2nd order CDR for.
760+ */
761+void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
762+{
763+ int lane;
764+ cvmx_helper_qlm_jtag_init();
765+ /* We need to load all four lanes of the QLM, a total of 1072 bits */
766+ for (lane = 0; lane < 4; lane++) {
767+ /*
768+ * Each lane has 268 bits. We need to set
769+ * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
770+ * 1. All other bits are zero. Bits go in LSB first,
771+ * so start off with the zeros for bits <63:0>.
772+ */
773+ cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
774+ /* cfg_cdr_incx<67:64>=3 */
775+ cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
776+ /* Zeros for bits <76:68> */
777+ cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
778+ /* cfg_cdr_secord<77>=1 */
779+ cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
780+ /* Zeros for bits <267:78> */
781+ cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
782+ }
783+ cvmx_helper_qlm_jtag_update(qlm);
784+}
785--- /dev/null
786+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
787@@ -0,0 +1,502 @@
788+/***********************license start***************
789+ * Author: Cavium Networks
790+ *
791+ * Contact: support@caviumnetworks.com
792+ * This file is part of the OCTEON SDK
793+ *
794+ * Copyright (c) 2003-2008 Cavium Networks
795+ *
796+ * This file is free software; you can redistribute it and/or modify
797+ * it under the terms of the GNU General Public License, Version 2, as
798+ * published by the Free Software Foundation.
799+ *
800+ * This file is distributed in the hope that it will be useful, but
801+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
802+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
803+ * NONINFRINGEMENT. See the GNU General Public License for more
804+ * details.
805+ *
806+ * You should have received a copy of the GNU General Public License
807+ * along with this file; if not, write to the Free Software
808+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
809+ * or visit http://www.gnu.org/licenses/.
810+ *
811+ * This file may also be available under a different license from Cavium.
812+ * Contact Cavium Networks for more information
813+ ***********************license end**************************************/
814+
815+/**
816+ *
817+ * Small helper utilities.
818+ *
819+ */
820+
821+#include <asm/octeon/octeon.h>
822+
823+#include <asm/octeon/cvmx-helper-util.h>
824+
825+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
826+
827+/**
828+ * Get the version of the CVMX libraries.
829+ *
830+ * Returns Version string. Note this buffer is allocated statically
831+ * and will be shared by all callers.
832+ */
833+const char *cvmx_helper_get_version(void)
834+{
835+ return OCTEON_SDK_VERSION_STRING;
836+}
837+
838+/**
839+ * Convert a interface mode into a human readable string
840+ *
841+ * @mode: Mode to convert
842+ *
843+ * Returns String
844+ */
845+const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t
846+ mode)
847+{
848+ switch (mode) {
849+ case CVMX_HELPER_INTERFACE_MODE_DISABLED:
850+ return "DISABLED";
851+ case CVMX_HELPER_INTERFACE_MODE_RGMII:
852+ return "RGMII";
853+ case CVMX_HELPER_INTERFACE_MODE_GMII:
854+ return "GMII";
855+ case CVMX_HELPER_INTERFACE_MODE_SPI:
856+ return "SPI";
857+ case CVMX_HELPER_INTERFACE_MODE_PCIE:
858+ return "PCIE";
859+ case CVMX_HELPER_INTERFACE_MODE_XAUI:
860+ return "XAUI";
861+ case CVMX_HELPER_INTERFACE_MODE_SGMII:
862+ return "SGMII";
863+ case CVMX_HELPER_INTERFACE_MODE_PICMG:
864+ return "PICMG";
865+ case CVMX_HELPER_INTERFACE_MODE_NPI:
866+ return "NPI";
867+ case CVMX_HELPER_INTERFACE_MODE_LOOP:
868+ return "LOOP";
869+ }
870+ return "UNKNOWN";
871+}
872+
873+/**
874+ * Debug routine to dump the packet structure to the console
875+ *
876+ * @work: Work queue entry containing the packet to dump
877+ */
878+int cvmx_helper_dump_packet(cvmx_wqe_t *work)
879+{
880+ uint64_t count;
881+ uint64_t remaining_bytes;
882+ cvmx_buf_ptr_t buffer_ptr;
883+ uint64_t start_of_buffer;
884+ uint8_t *data_address;
885+ uint8_t *end_of_data;
886+
887+ cvmx_dprintf("Packet Length: %u\n", work->len);
888+ cvmx_dprintf(" Input Port: %u\n", work->ipprt);
889+ cvmx_dprintf(" QoS: %u\n", work->qos);
890+ cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs);
891+
892+ if (work->word2.s.bufs == 0) {
893+ cvmx_ipd_wqe_fpa_queue_t wqe_pool;
894+ wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE);
895+ buffer_ptr.u64 = 0;
896+ buffer_ptr.s.pool = wqe_pool.s.wqe_pool;
897+ buffer_ptr.s.size = 128;
898+ buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data);
899+ if (cvmx_likely(!work->word2.s.not_IP)) {
900+ if (work->word2.s.is_v6)
901+ buffer_ptr.s.addr += 2;
902+ else
903+ buffer_ptr.s.addr += 6;
904+ }
905+ } else
906+ buffer_ptr = work->packet_ptr;
907+ remaining_bytes = work->len;
908+
909+ while (remaining_bytes) {
910+ start_of_buffer =
911+ ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
912+ cvmx_dprintf(" Buffer Start:%llx\n",
913+ (unsigned long long)start_of_buffer);
914+ cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i);
915+ cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back);
916+ cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool);
917+ cvmx_dprintf(" Buffer Data: %llx\n",
918+ (unsigned long long)buffer_ptr.s.addr);
919+ cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size);
920+
921+ cvmx_dprintf("\t\t");
922+ data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr);
923+ end_of_data = data_address + buffer_ptr.s.size;
924+ count = 0;
925+ while (data_address < end_of_data) {
926+ if (remaining_bytes == 0)
927+ break;
928+ else
929+ remaining_bytes--;
930+ cvmx_dprintf("%02x", (unsigned int)*data_address);
931+ data_address++;
932+ if (remaining_bytes && (count == 7)) {
933+ cvmx_dprintf("\n\t\t");
934+ count = 0;
935+ } else
936+ count++;
937+ }
938+ cvmx_dprintf("\n");
939+
940+ if (remaining_bytes)
941+ buffer_ptr =
942+ *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.
943+ addr - 8);
944+ }
945+ return 0;
946+}
947+
948+/**
949+ * Setup Random Early Drop on a specific input queue
950+ *
951+ * @queue: Input queue to setup RED on (0-7)
952+ * @pass_thresh:
953+ * Packets will begin slowly dropping when there are less than
954+ * this many packet buffers free in FPA 0.
955+ * @drop_thresh:
956+ * All incomming packets will be dropped when there are less
957+ * than this many free packet buffers in FPA 0.
958+ * Returns Zero on success. Negative on failure
959+ */
960+int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
961+{
962+ cvmx_ipd_qos_red_marks_t red_marks;
963+ cvmx_ipd_red_quex_param_t red_param;
964+
965+ /*
966+ * Set RED to begin dropping packets when there are
967+ * pass_thresh buffers left. It will linearly drop more
968+ * packets until reaching drop_thresh buffers.
969+ */
970+ red_marks.u64 = 0;
971+ red_marks.s.drop = drop_thresh;
972+ red_marks.s.pass = pass_thresh;
973+ cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);
974+
975+ /* Use the actual queue 0 counter, not the average */
976+ red_param.u64 = 0;
977+ red_param.s.prb_con =
978+ (255ul << 24) / (red_marks.s.pass - red_marks.s.drop);
979+ red_param.s.avg_con = 1;
980+ red_param.s.new_con = 255;
981+ red_param.s.use_pcnt = 1;
982+ cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);
983+ return 0;
984+}
985+
986+/**
987+ * Setup Random Early Drop to automatically begin dropping packets.
988+ *
989+ * @pass_thresh:
990+ * Packets will begin slowly dropping when there are less than
991+ * this many packet buffers free in FPA 0.
992+ * @drop_thresh:
993+ * All incomming packets will be dropped when there are less
994+ * than this many free packet buffers in FPA 0.
995+ * Returns Zero on success. Negative on failure
996+ */
997+int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
998+{
999+ cvmx_ipd_portx_bp_page_cnt_t page_cnt;
1000+ cvmx_ipd_bp_prt_red_end_t ipd_bp_prt_red_end;
1001+ cvmx_ipd_red_port_enable_t red_port_enable;
1002+ int queue;
1003+ int interface;
1004+ int port;
1005+
1006+ /* Disable backpressure based on queued buffers. It needs SW support */
1007+ page_cnt.u64 = 0;
1008+ page_cnt.s.bp_enb = 0;
1009+ page_cnt.s.page_cnt = 100;
1010+ for (interface = 0; interface < 2; interface++) {
1011+ for (port = cvmx_helper_get_first_ipd_port(interface);
1012+ port < cvmx_helper_get_last_ipd_port(interface); port++)
1013+ cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port),
1014+ page_cnt.u64);
1015+ }
1016+
1017+ for (queue = 0; queue < 8; queue++)
1018+ cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
1019+
1020+ /* Shutoff the dropping based on the per port page count. SW isn't
1021+ decrementing it right now */
1022+ ipd_bp_prt_red_end.u64 = 0;
1023+ ipd_bp_prt_red_end.s.prt_enb = 0;
1024+ cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
1025+
1026+ red_port_enable.u64 = 0;
1027+ red_port_enable.s.prt_enb = 0xfffffffffull;
1028+ red_port_enable.s.avg_dly = 10000;
1029+ red_port_enable.s.prb_dly = 10000;
1030+ cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
1031+
1032+ return 0;
1033+}
1034+
1035+/**
1036+ * Setup the common GMX settings that determine the number of
1037+ * ports. These setting apply to almost all configurations of all
1038+ * chips.
1039+ *
1040+ * @interface: Interface to configure
1041+ * @num_ports: Number of ports on the interface
1042+ *
1043+ * Returns Zero on success, negative on failure
1044+ */
1045+int __cvmx_helper_setup_gmx(int interface, int num_ports)
1046+{
1047+ cvmx_gmxx_tx_prts_t gmx_tx_prts;
1048+ cvmx_gmxx_rx_prts_t gmx_rx_prts;
1049+ cvmx_pko_reg_gmx_port_mode_t pko_mode;
1050+
1051+ /* Tell GMX the number of TX ports on this interface */
1052+ gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
1053+ gmx_tx_prts.s.prts = num_ports;
1054+ cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
1055+
1056+ /*
1057+ * Tell GMX the number of RX ports on this interface. This only
1058+ * applies to *GMII and XAUI ports.
1059+ */
1060+ if (cvmx_helper_interface_get_mode(interface) ==
1061+ CVMX_HELPER_INTERFACE_MODE_RGMII
1062+ || cvmx_helper_interface_get_mode(interface) ==
1063+ CVMX_HELPER_INTERFACE_MODE_SGMII
1064+ || cvmx_helper_interface_get_mode(interface) ==
1065+ CVMX_HELPER_INTERFACE_MODE_GMII
1066+ || cvmx_helper_interface_get_mode(interface) ==
1067+ CVMX_HELPER_INTERFACE_MODE_XAUI) {
1068+ if (num_ports > 4) {
1069+ cvmx_dprintf("__cvmx_helper_setup_gmx: "
1070+ "Illegal num_ports\n");
1071+ return -1;
1072+ }
1073+
1074+ gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));
1075+ gmx_rx_prts.s.prts = num_ports;
1076+ cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
1077+ }
1078+
1079+ /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX and 31XX */
1080+ if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
1081+ || OCTEON_IS_MODEL(OCTEON_CN50XX))
1082+ return 0;
1083+
1084+ /* Tell PKO the number of ports on this interface */
1085+ pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
1086+ if (interface == 0) {
1087+ if (num_ports == 1)
1088+ pko_mode.s.mode0 = 4;
1089+ else if (num_ports == 2)
1090+ pko_mode.s.mode0 = 3;
1091+ else if (num_ports <= 4)
1092+ pko_mode.s.mode0 = 2;
1093+ else if (num_ports <= 8)
1094+ pko_mode.s.mode0 = 1;
1095+ else
1096+ pko_mode.s.mode0 = 0;
1097+ } else {
1098+ if (num_ports == 1)
1099+ pko_mode.s.mode1 = 4;
1100+ else if (num_ports == 2)
1101+ pko_mode.s.mode1 = 3;
1102+ else if (num_ports <= 4)
1103+ pko_mode.s.mode1 = 2;
1104+ else if (num_ports <= 8)
1105+ pko_mode.s.mode1 = 1;
1106+ else
1107+ pko_mode.s.mode1 = 0;
1108+ }
1109+ cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
1110+ return 0;
1111+}
1112+
1113+/**
1114+ * Returns the IPD/PKO port number for a port on the given
1115+ * interface.
1116+ *
1117+ * @interface: Interface to use
1118+ * @port: Port on the interface
1119+ *
1120+ * Returns IPD/PKO port number
1121+ */
1122+int cvmx_helper_get_ipd_port(int interface, int port)
1123+{
1124+ switch (interface) {
1125+ case 0:
1126+ return port;
1127+ case 1:
1128+ return port + 16;
1129+ case 2:
1130+ return port + 32;
1131+ case 3:
1132+ return port + 36;
1133+ }
1134+ return -1;
1135+}
1136+
1137+#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
1138+
1139+/**
1140+ * Returns the interface number for an IPD/PKO port number.
1141+ *
1142+ * @ipd_port: IPD/PKO port number
1143+ *
1144+ * Returns Interface number
1145+ */
1146+int cvmx_helper_get_interface_num(int ipd_port)
1147+{
1148+ if (ipd_port < 16)
1149+ return 0;
1150+ else if (ipd_port < 32)
1151+ return 1;
1152+ else if (ipd_port < 36)
1153+ return 2;
1154+ else if (ipd_port < 40)
1155+ return 3;
1156+ else
1157+ cvmx_dprintf("cvmx_helper_get_interface_num: "
1158+ "Illegal IPD port number\n");
1159+
1160+ return -1;
1161+}
1162+
1163+/**
1164+ * Returns the interface index number for an IPD/PKO port
1165+ * number.
1166+ *
1167+ * @ipd_port: IPD/PKO port number
1168+ *
1169+ * Returns Interface index number
1170+ */
1171+int cvmx_helper_get_interface_index_num(int ipd_port)
1172+{
1173+ if (ipd_port < 32)
1174+ return ipd_port & 15;
1175+ else if (ipd_port < 36)
1176+ return ipd_port & 3;
1177+ else if (ipd_port < 40)
1178+ return ipd_port & 3;
1179+ else
1180+ cvmx_dprintf("cvmx_helper_get_interface_index_num: "
1181+ "Illegal IPD port number\n");
1182+
1183+ return -1;
1184+}
1185+
1186+/**
1187+ * Initialize the internal QLM JTAG logic to allow programming
1188+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
1189+ * These functions should only be used at the direction of Cavium
1190+ * Networks. Programming incorrect values into the JTAG chain
1191+ * can cause chip damage.
1192+ */
1193+void cvmx_helper_qlm_jtag_init(void)
1194+{
1195+ union cvmx_ciu_qlm_jtgc jtgc;
1196+ int clock_div = 0;
1197+ int divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
1198+ divisor = (divisor - 1) >> 2;
1199+ /* Convert the divisor into a power of 2 shift */
1200+ CVMX_CLZ(clock_div, divisor);
1201+ clock_div = 32 - clock_div;
1202+
1203+ /*
1204+ * Clock divider for QLM JTAG operations. eclk is divided by
1205+ * 2^(CLK_DIV + 2).
1206+ */
1207+ jtgc.u64 = 0;
1208+ jtgc.s.clk_div = clock_div;
1209+ jtgc.s.mux_sel = 0;
1210+ if (OCTEON_IS_MODEL(OCTEON_CN52XX))
1211+ jtgc.s.bypass = 0x3;
1212+ else
1213+ jtgc.s.bypass = 0xf;
1214+ cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
1215+ cvmx_read_csr(CVMX_CIU_QLM_JTGC);
1216+}
1217+
1218+/**
1219+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
1220+ * into the MSB and out the LSB, so you should shift in the low
1221+ * order bits followed by the high order bits. The JTAG chain is
1222+ * 4 * 268 bits long, or 1072.
1223+ *
1224+ * @qlm: QLM to shift value into
1225+ * @bits: Number of bits to shift in (1-32).
1226+ * @data: Data to shift in. Bit 0 enters the chain first, followed by
1227+ * bit 1, etc.
1228+ *
1229+ * Returns The low order bits of the JTAG chain that shifted out of the
1230+ * circle.
1231+ */
1232+uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
1233+{
1234+ union cvmx_ciu_qlm_jtgd jtgd;
1235+ jtgd.u64 = 0;
1236+ jtgd.s.shift = 1;
1237+ jtgd.s.shft_cnt = bits - 1;
1238+ jtgd.s.shft_reg = data;
1239+ if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
1240+ jtgd.s.select = 1 << qlm;
1241+ cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
1242+ do {
1243+ jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
1244+ } while (jtgd.s.shift);
1245+ return jtgd.s.shft_reg >> (32 - bits);
1246+}
1247+
1248+/**
1249+ * Shift long sequences of zeros into the QLM JTAG chain. It is
1250+ * common to need to shift more than 32 bits of zeros into the
1251+ * chain. This function is a convience wrapper around
1252+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
1253+ * zeros at a time.
1254+ *
1255+ * @qlm: QLM to shift zeros into
1256+ * @bits:
1257+ */
1258+void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
1259+{
1260+ while (bits > 0) {
1261+ int n = bits;
1262+ if (n > 32)
1263+ n = 32;
1264+ cvmx_helper_qlm_jtag_shift(qlm, n, 0);
1265+ bits -= n;
1266+ }
1267+}
1268+
1269+/**
1270+ * Program the QLM JTAG chain into all lanes of the QLM. You must
1271+ * have already shifted in 268*4, or 1072 bits into the JTAG
1272+ * chain. Updating invalid values can possibly cause chip damage.
1273+ *
1274+ * @qlm: QLM to program
1275+ */
1276+void cvmx_helper_qlm_jtag_update(int qlm)
1277+{
1278+ union cvmx_ciu_qlm_jtgd jtgd;
1279+
1280+ /* Update the new data */
1281+ jtgd.u64 = 0;
1282+ jtgd.s.update = 1;
1283+ if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
1284+ jtgd.s.select = 1 << qlm;
1285+ cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
1286+ do {
1287+ jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
1288+ } while (jtgd.s.update);
1289+}
1290--- /dev/null
1291+++ b/arch/mips/cavium-octeon/executive/cvmx-pcie.c
1292@@ -0,0 +1,1053 @@
1293+/***********************license start***************
1294+ * Author: Cavium Networks
1295+ *
1296+ * Contact: support@caviumnetworks.com
1297+ * This file is part of the OCTEON SDK
1298+ *
1299+ * Copyright (c) 2003-2008 Cavium Networks
1300+ *
1301+ * This file is free software; you can redistribute it and/or modify
1302+ * it under the terms of the GNU General Public License, Version 2, as
1303+ * published by the Free Software Foundation.
1304+ *
1305+ * This file is distributed in the hope that it will be useful, but
1306+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
1307+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1308+ * NONINFRINGEMENT. See the GNU General Public License for more
1309+ * details.
1310+ *
1311+ * You should have received a copy of the GNU General Public License
1312+ * along with this file; if not, write to the Free Software
1313+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1314+ * 02110-1301 USA or visit http://www.gnu.org/licenses/.
1315+ *
1316+ * This file may also be available under a different license from Cavium.
1317+ * Contact Cavium Networks for more information
1318+ ***********************license end**************************************/
1319+
1320+/**
1321+ *
1322+ * Interface to PCIe as a host(RC) or target(EP)
1323+ *
1324+ */
1325+#include <linux/delay.h>
1326+#include <asm/byteorder.h>
1327+
1328+#include <asm/octeon/octeon.h>
1329+#include <asm/octeon/cvmx-npei-defs.h>
1330+#include <asm/octeon/cvmx-pciercx-defs.h>
1331+#include <asm/octeon/cvmx-pescx-defs.h>
1332+#include <asm/octeon/cvmx-pexp-defs.h>
1333+#include <asm/octeon/cvmx-pcieep-defs.h>
1334+#include <asm/octeon/cvmx-helper-errata.h>
1335+#include <asm/octeon/cvmx-pcie.h>
1336+
1337+/**
1338+ * Return the Core virtual base address for PCIe IO access. IOs are
1339+ * read/written as an offset from this address.
1340+ *
1341+ * @pcie_port: PCIe port the IO is for
1342+ *
1343+ * Returns 64bit Octeon IO base address for read/write
1344+ */
1345+uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
1346+{
1347+ union cvmx_pcie_address pcie_addr;
1348+ pcie_addr.u64 = 0;
1349+ pcie_addr.io.upper = 0;
1350+ pcie_addr.io.io = 1;
1351+ pcie_addr.io.did = 3;
1352+ pcie_addr.io.subdid = 2;
1353+ pcie_addr.io.es = 1;
1354+ pcie_addr.io.port = pcie_port;
1355+ return pcie_addr.u64;
1356+}
1357+
1358+/**
1359+ * Size of the IO address region returned at address
1360+ * cvmx_pcie_get_io_base_address()
1361+ *
1362+ * @pcie_port: PCIe port the IO is for
1363+ *
1364+ * Returns Size of the IO window
1365+ */
1366+uint64_t cvmx_pcie_get_io_size(int pcie_port)
1367+{
1368+ return 1ull << 32;
1369+}
1370+
1371+/**
1372+ * Return the Core virtual base address for PCIe MEM access. Memory is
1373+ * read/written as an offset from this address.
1374+ *
1375+ * @pcie_port: PCIe port the IO is for
1376+ *
1377+ * Returns 64bit Octeon IO base address for read/write
1378+ */
1379+uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
1380+{
1381+ union cvmx_pcie_address pcie_addr;
1382+ pcie_addr.u64 = 0;
1383+ pcie_addr.mem.upper = 0;
1384+ pcie_addr.mem.io = 1;
1385+ pcie_addr.mem.did = 3;
1386+ pcie_addr.mem.subdid = 3 + pcie_port;
1387+ return pcie_addr.u64;
1388+}
1389+
1390+/**
1391+ * Size of the Mem address region returned at address
1392+ * cvmx_pcie_get_mem_base_address()
1393+ *
1394+ * @pcie_port: PCIe port the IO is for
1395+ *
1396+ * Returns Size of the Mem window
1397+ */
1398+uint64_t cvmx_pcie_get_mem_size(int pcie_port)
1399+{
1400+ return 1ull << 36;
1401+}
1402+
1403+/**
1404+ * Initialize the RC config space CSRs
1405+ *
1406+ * @pcie_port: PCIe port to initialize
1407+ */
1408+static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
1409+{
1410+ union cvmx_pciercx_cfg030 pciercx_cfg030;
1411+ union cvmx_npei_ctl_status2 npei_ctl_status2;
1412+ union cvmx_pciercx_cfg070 pciercx_cfg070;
1413+ union cvmx_pciercx_cfg001 pciercx_cfg001;
1414+ union cvmx_pciercx_cfg032 pciercx_cfg032;
1415+ union cvmx_pciercx_cfg006 pciercx_cfg006;
1416+ union cvmx_pciercx_cfg008 pciercx_cfg008;
1417+ union cvmx_pciercx_cfg009 pciercx_cfg009;
1418+ union cvmx_pciercx_cfg010 pciercx_cfg010;
1419+ union cvmx_pciercx_cfg011 pciercx_cfg011;
1420+ union cvmx_pciercx_cfg035 pciercx_cfg035;
1421+ union cvmx_pciercx_cfg075 pciercx_cfg075;
1422+ union cvmx_pciercx_cfg034 pciercx_cfg034;
1423+
1424+ /* Max Payload Size (PCIE*_CFG030[MPS]) */
1425+ /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
1426+ /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
1427+ /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
1428+ pciercx_cfg030.u32 =
1429+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
1430+ /*
1431+ * Max payload size = 128 bytes for best Octeon DMA
1432+ * performance.
1433+ */
1434+ pciercx_cfg030.s.mps = 0;
1435+ /*
1436+ * Max read request size = 128 bytes for best Octeon DMA
1437+ * performance.
1438+ */
1439+ pciercx_cfg030.s.mrrs = 0;
1440+ /* Enable relaxed ordering. */
1441+ pciercx_cfg030.s.ro_en = 1;
1442+ /* Enable no snoop. */
1443+ pciercx_cfg030.s.ns_en = 1;
1444+ /* Correctable error reporting enable. */
1445+ pciercx_cfg030.s.ce_en = 1;
1446+ /* Non-fatal error reporting enable. */
1447+ pciercx_cfg030.s.nfe_en = 1;
1448+ /* Fatal error reporting enable. */
1449+ pciercx_cfg030.s.fe_en = 1;
1450+ /* Unsupported request reporting enable. */
1451+ pciercx_cfg030.s.ur_en = 1;
1452+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
1453+ pciercx_cfg030.u32);
1454+
1455+ /*
1456+ * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
1457+ * PCIE*_CFG030[MPS]
1458+ *
1459+ * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
1460+ * exceed PCIE*_CFG030[MRRS].
1461+ */
1462+ npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
1463+ /* Max payload size = 128 bytes for best Octeon DMA performance */
1464+ npei_ctl_status2.s.mps = 0;
1465+ /* Max read request size = 128 bytes for best Octeon DMA performance */
1466+ npei_ctl_status2.s.mrrs = 0;
1467+ cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
1468+
1469+ /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
1470+ pciercx_cfg070.u32 =
1471+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
1472+ pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
1473+ pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
1474+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
1475+ pciercx_cfg070.u32);
1476+
1477+ /*
1478+ * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
1479+ * always be set.
1480+ *
1481+ * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
1482+ * Message Enable (PCIE*_CFG001[SEE])
1483+ */
1484+ pciercx_cfg001.u32 =
1485+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
1486+ pciercx_cfg001.s.msae = 1; /* Memory space enable. */
1487+ pciercx_cfg001.s.me = 1; /* Bus master enable. */
1488+ pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
1489+ pciercx_cfg001.s.see = 1; /* SERR# enable */
1490+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
1491+ pciercx_cfg001.u32);
1492+
1493+ /* Advanced Error Recovery Message Enables */
1494+ /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
1495+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
1496+ /* Use CVMX_PCIERCX_CFG067 hardware default */
1497+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
1498+
1499+ /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
1500+ pciercx_cfg032.u32 =
1501+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1502+ pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
1503+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
1504+ pciercx_cfg032.u32);
1505+
1506+ /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
1507+
1508+ /*
1509+ * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
1510+ * cvmx_pcie_rc_initialize_link()
1511+ *
1512+ * Primary Bus Number (PCIERCn_CFG006[PBNUM])
1513+ *
1514+ * We set the primary bus number to 1 so IDT bridges are
1515+ * happy. They don't like zero.
1516+ */
1517+ pciercx_cfg006.u32 = 0;
1518+ pciercx_cfg006.s.pbnum = 1;
1519+ pciercx_cfg006.s.sbnum = 1;
1520+ pciercx_cfg006.s.subbnum = 1;
1521+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
1522+ pciercx_cfg006.u32);
1523+
1524+ /*
1525+ * Memory-mapped I/O BAR (PCIERCn_CFG008)
1526+ * Most applications should disable the memory-mapped I/O BAR by
1527+ * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
1528+ */
1529+ pciercx_cfg008.u32 = 0;
1530+ pciercx_cfg008.s.mb_addr = 0x100;
1531+ pciercx_cfg008.s.ml_addr = 0;
1532+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
1533+ pciercx_cfg008.u32);
1534+
1535+ /*
1536+ * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
1537+ * Most applications should disable the prefetchable BAR by setting
1538+ * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
1539+ * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
1540+ */
1541+ pciercx_cfg009.u32 =
1542+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
1543+ pciercx_cfg010.u32 =
1544+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
1545+ pciercx_cfg011.u32 =
1546+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
1547+ pciercx_cfg009.s.lmem_base = 0x100;
1548+ pciercx_cfg009.s.lmem_limit = 0;
1549+ pciercx_cfg010.s.umem_base = 0x100;
1550+ pciercx_cfg011.s.umem_limit = 0;
1551+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
1552+ pciercx_cfg009.u32);
1553+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
1554+ pciercx_cfg010.u32);
1555+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
1556+ pciercx_cfg011.u32);
1557+
1558+ /*
1559+ * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
1560+ * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
1561+ */
1562+ pciercx_cfg035.u32 =
1563+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
1564+ /* System error on correctable error enable. */
1565+ pciercx_cfg035.s.secee = 1;
1566+ /* System error on fatal error enable. */
1567+ pciercx_cfg035.s.sefee = 1;
1568+ /* System error on non-fatal error enable. */
1569+ pciercx_cfg035.s.senfee = 1;
1570+ /* PME interrupt enable. */
1571+ pciercx_cfg035.s.pmeie = 1;
1572+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
1573+ pciercx_cfg035.u32);
1574+
1575+ /*
1576+ * Advanced Error Recovery Interrupt Enables
1577+ * (PCIERCn_CFG075[CERE,NFERE,FERE])
1578+ */
1579+ pciercx_cfg075.u32 =
1580+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
1581+ /* Correctable error reporting enable. */
1582+ pciercx_cfg075.s.cere = 1;
1583+ /* Non-fatal error reporting enable. */
1584+ pciercx_cfg075.s.nfere = 1;
1585+ /* Fatal error reporting enable. */
1586+ pciercx_cfg075.s.fere = 1;
1587+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
1588+ pciercx_cfg075.u32);
1589+
1590+ /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
1591+ * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
1592+ */
1593+ pciercx_cfg034.u32 =
1594+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
1595+ /* Hot-plug interrupt enable. */
1596+ pciercx_cfg034.s.hpint_en = 1;
1597+ /* Data Link Layer state changed enable */
1598+ pciercx_cfg034.s.dlls_en = 1;
1599+ /* Command completed interrupt enable. */
1600+ pciercx_cfg034.s.ccint_en = 1;
1601+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
1602+ pciercx_cfg034.u32);
1603+}
1604+
1605+/**
1606+ * Initialize a host mode PCIe link. This function takes a PCIe
1607+ * port from reset to a link up state. Software can then begin
1608+ * configuring the rest of the link.
1609+ *
1610+ * @pcie_port: PCIe port to initialize
1611+ *
1612+ * Returns Zero on success
1613+ */
1614+static int __cvmx_pcie_rc_initialize_link(int pcie_port)
1615+{
1616+ uint64_t start_cycle;
1617+ union cvmx_pescx_ctl_status pescx_ctl_status;
1618+ union cvmx_pciercx_cfg452 pciercx_cfg452;
1619+ union cvmx_pciercx_cfg032 pciercx_cfg032;
1620+ union cvmx_pciercx_cfg448 pciercx_cfg448;
1621+
1622+ /* Set the lane width */
1623+ pciercx_cfg452.u32 =
1624+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
1625+ pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
1626+ if (pescx_ctl_status.s.qlm_cfg == 0) {
1627+ /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
1628+ pciercx_cfg452.s.lme = 0xf;
1629+ } else {
1630+ /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
1631+ pciercx_cfg452.s.lme = 0x7;
1632+ }
1633+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
1634+ pciercx_cfg452.u32);
1635+
1636+ /*
1637+ * CN52XX pass 1.x has an errata where length mismatches on UR
1638+ * responses can cause bus errors on 64bit memory
1639+ * reads. Turning off length error checking fixes this.
1640+ */
1641+ if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1642+ union cvmx_pciercx_cfg455 pciercx_cfg455;
1643+ pciercx_cfg455.u32 =
1644+ cvmx_pcie_cfgx_read(pcie_port,
1645+ CVMX_PCIERCX_CFG455(pcie_port));
1646+ pciercx_cfg455.s.m_cpl_len_err = 1;
1647+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
1648+ pciercx_cfg455.u32);
1649+ }
1650+
1651+ /* Lane swap needs to be manually enabled for CN52XX */
1652+ if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
1653+ pescx_ctl_status.s.lane_swp = 1;
1654+ cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
1655+ pescx_ctl_status.u64);
1656+ }
1657+
1658+ /* Bring up the link */
1659+ pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
1660+ pescx_ctl_status.s.lnk_enb = 1;
1661+ cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
1662+
1663+ /*
1664+ * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
1665+ * be disabled.
1666+ */
1667+ if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
1668+ __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
1669+
1670+ /* Wait for the link to come up */
1671+ cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
1672+ start_cycle = cvmx_get_cycle();
1673+ do {
1674+ if (cvmx_get_cycle() - start_cycle >
1675+ 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
1676+ cvmx_dprintf("PCIe: Port %d link timeout\n",
1677+ pcie_port);
1678+ return -1;
1679+ }
1680+ cvmx_wait(10000);
1681+ pciercx_cfg032.u32 =
1682+ cvmx_pcie_cfgx_read(pcie_port,
1683+ CVMX_PCIERCX_CFG032(pcie_port));
1684+ } while (pciercx_cfg032.s.dlla == 0);
1685+
1686+ /* Display the link status */
1687+ cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
1688+ pciercx_cfg032.s.nlw);
1689+
1690+ /*
1691+ * Update the Replay Time Limit. Empirically, some PCIe
1692+ * devices take a little longer to respond than expected under
1693+ * load. As a workaround for this we configure the Replay Time
1694+ * Limit to the value expected for a 512 byte MPS instead of
1695+ * our actual 256 byte MPS. The numbers below are directly
1696+ * from the PCIe spec table 3-4.
1697+ */
1698+ pciercx_cfg448.u32 =
1699+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1700+ switch (pciercx_cfg032.s.nlw) {
1701+ case 1: /* 1 lane */
1702+ pciercx_cfg448.s.rtl = 1677;
1703+ break;
1704+ case 2: /* 2 lanes */
1705+ pciercx_cfg448.s.rtl = 867;
1706+ break;
1707+ case 4: /* 4 lanes */
1708+ pciercx_cfg448.s.rtl = 462;
1709+ break;
1710+ case 8: /* 8 lanes */
1711+ pciercx_cfg448.s.rtl = 258;
1712+ break;
1713+ }
1714+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
1715+ pciercx_cfg448.u32);
1716+
1717+ return 0;
1718+}
1719+
1720+/**
1721+ * Initialize a PCIe port for use in host(RC) mode. It doesn't
1722+ * enumerate the bus.
1723+ *
1724+ * @pcie_port: PCIe port to initialize
1725+ *
1726+ * Returns Zero on success
1727+ */
1728+int cvmx_pcie_rc_initialize(int pcie_port)
1729+{
1730+ int i;
1731+ union cvmx_ciu_soft_prst ciu_soft_prst;
1732+ union cvmx_pescx_bist_status pescx_bist_status;
1733+ union cvmx_pescx_bist_status2 pescx_bist_status2;
1734+ union cvmx_npei_ctl_status npei_ctl_status;
1735+ union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
1736+ union cvmx_npei_mem_access_subidx mem_access_subid;
1737+ union cvmx_npei_dbg_data npei_dbg_data;
1738+ union cvmx_pescx_ctl_status2 pescx_ctl_status2;
1739+
1740+ /*
1741+ * Make sure we aren't trying to setup a target mode interface
1742+ * in host mode.
1743+ */
1744+ npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1745+ if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
1746+ cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
1747+ "on port0, but port0 is not in host mode\n");
1748+ return -1;
1749+ }
1750+
1751+ /*
1752+ * Make sure a CN52XX isn't trying to bring up port 1 when it
1753+ * is disabled.
1754+ */
1755+ if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1756+ npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1757+ if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
1758+ cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
1759+ "called on port1, but port1 is disabled\n");
1760+ return -1;
1761+ }
1762+ }
1763+
1764+ /*
1765+ * PCIe switch arbitration mode. '0' == fixed priority NPEI,
1766+ * PCIe0, then PCIe1. '1' == round robin.
1767+ */
1768+ npei_ctl_status.s.arb = 1;
1769+ /* Allow up to 0x20 config retries */
1770+ npei_ctl_status.s.cfg_rtry = 0x20;
1771+ /*
1772+ * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
1773+ * don't reset.
1774+ */
1775+ if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1776+ npei_ctl_status.s.p0_ntags = 0x20;
1777+ npei_ctl_status.s.p1_ntags = 0x20;
1778+ }
1779+ cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
1780+
1781+ /* Bring the PCIe out of reset */
1782+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
1783+ /*
1784+ * The EBH5200 board swapped the PCIe reset lines on
1785+ * the board. As a workaround for this bug, we bring
1786+ * both PCIe ports out of reset at the same time
1787+ * instead of on separate calls. So for port 0, we
1788+ * bring both out of reset and do nothing on port 1.
1789+ */
1790+ if (pcie_port == 0) {
1791+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1792+ /*
1793+ * After a chip reset the PCIe will also be in
1794+ * reset. If it isn't, most likely someone is
1795+ * trying to init it again without a proper
1796+ * PCIe reset.
1797+ */
1798+ if (ciu_soft_prst.s.soft_prst == 0) {
1799+ /* Reset the ports */
1800+ ciu_soft_prst.s.soft_prst = 1;
1801+ cvmx_write_csr(CVMX_CIU_SOFT_PRST,
1802+ ciu_soft_prst.u64);
1803+ ciu_soft_prst.u64 =
1804+ cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1805+ ciu_soft_prst.s.soft_prst = 1;
1806+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
1807+ ciu_soft_prst.u64);
1808+ /* Wait until pcie resets the ports. */
1809+ udelay(2000);
1810+ }
1811+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1812+ ciu_soft_prst.s.soft_prst = 0;
1813+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1814+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1815+ ciu_soft_prst.s.soft_prst = 0;
1816+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1817+ }
1818+ } else {
1819+ /*
1820+ * The normal case: The PCIe ports are completely
1821+ * separate and can be brought out of reset
1822+ * independently.
1823+ */
1824+ if (pcie_port)
1825+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1826+ else
1827+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1828+ /*
1829+ * After a chip reset the PCIe will also be in
1830+ * reset. If it isn't, most likely someone is trying
1831+ * to init it again without a proper PCIe reset.
1832+ */
1833+ if (ciu_soft_prst.s.soft_prst == 0) {
1834+ /* Reset the port */
1835+ ciu_soft_prst.s.soft_prst = 1;
1836+ if (pcie_port)
1837+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
1838+ ciu_soft_prst.u64);
1839+ else
1840+ cvmx_write_csr(CVMX_CIU_SOFT_PRST,
1841+ ciu_soft_prst.u64);
1842+ /* Wait until pcie resets the ports. */
1843+ udelay(2000);
1844+ }
1845+ if (pcie_port) {
1846+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1847+ ciu_soft_prst.s.soft_prst = 0;
1848+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1849+ } else {
1850+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1851+ ciu_soft_prst.s.soft_prst = 0;
1852+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1853+ }
1854+ }
1855+
1856+ /*
1857+ * Wait for PCIe reset to complete. Due to errata PCIE-700, we
1858+ * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
1859+ * fixed number of cycles.
1860+ */
1861+ cvmx_wait(400000);
1862+
1863+ /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
1864+ CN52XX, so we only probe it on newer chips */
1865+ if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
1866+ && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1867+ /* Clear PCLK_RUN so we can check if the clock is running */
1868+ pescx_ctl_status2.u64 =
1869+ cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
1870+ pescx_ctl_status2.s.pclk_run = 1;
1871+ cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
1872+ pescx_ctl_status2.u64);
1873+ /*
1874+ * Now that we cleared PCLK_RUN, wait for it to be set
1875+ * again telling us the clock is running.
1876+ */
1877+ if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
1878+ union cvmx_pescx_ctl_status2,
1879+ pclk_run, ==, 1, 10000)) {
1880+ cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
1881+ pcie_port);
1882+ return -1;
1883+ }
1884+ }
1885+
1886+ /*
1887+ * Check and make sure PCIe came out of reset. If it doesn't
1888+ * the board probably hasn't wired the clocks up and the
1889+ * interface should be skipped.
1890+ */
1891+ pescx_ctl_status2.u64 =
1892+ cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
1893+ if (pescx_ctl_status2.s.pcierst) {
1894+ cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
1895+ pcie_port);
1896+ return -1;
1897+ }
1898+
1899+ /*
1900+ * Check BIST2 status. If any bits are set skip this interface. This
1901+ * is an attempt to catch PCIE-813 on pass 1 parts.
1902+ */
1903+ pescx_bist_status2.u64 =
1904+ cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
1905+ if (pescx_bist_status2.u64) {
1906+ cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
1907+ "port isn't hooked up, skipping.\n",
1908+ pcie_port);
1909+ return -1;
1910+ }
1911+
1912+ /* Check BIST status */
1913+ pescx_bist_status.u64 =
1914+ cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
1915+ if (pescx_bist_status.u64)
1916+ cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
1917+ pcie_port, CAST64(pescx_bist_status.u64));
1918+
1919+ /* Initialize the config space CSRs */
1920+ __cvmx_pcie_rc_initialize_config_space(pcie_port);
1921+
1922+ /* Bring the link up */
1923+ if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
1924+ cvmx_dprintf
1925+ ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
1926+ return -1;
1927+ }
1928+
1929+ /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1930+ npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
1931+ /* Allow 16 words to combine */
1932+ npei_mem_access_ctl.s.max_word = 0;
1933+ /* Wait up to 127 cycles for more data */
1934+ npei_mem_access_ctl.s.timer = 127;
1935+ cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
1936+
1937+ /* Setup Mem access SubDIDs */
1938+ mem_access_subid.u64 = 0;
1939+ /* Port the request is sent to. */
1940+ mem_access_subid.s.port = pcie_port;
1941+ /* Due to an errata on pass 1 chips, no merging is allowed. */
1942+ mem_access_subid.s.nmerge = 1;
1943+ /* Endian-swap for Reads. */
1944+ mem_access_subid.s.esr = 1;
1945+ /* Endian-swap for Writes. */
1946+ mem_access_subid.s.esw = 1;
1947+ /* No Snoop for Reads. */
1948+ mem_access_subid.s.nsr = 1;
1949+ /* No Snoop for Writes. */
1950+ mem_access_subid.s.nsw = 1;
1951+ /* Disable Relaxed Ordering for Reads. */
1952+ mem_access_subid.s.ror = 0;
1953+ /* Disable Relaxed Ordering for Writes. */
1954+ mem_access_subid.s.row = 0;
1955+ /* PCIe Adddress Bits <63:34>. */
1956+ mem_access_subid.s.ba = 0;
1957+
1958+ /*
1959+ * Setup mem access 12-15 for port 0, 16-19 for port 1,
1960+ * supplying 36 bits of address space.
1961+ */
1962+ for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1963+ cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
1964+ mem_access_subid.u64);
1965+ /* Set each SUBID to extend the addressable range */
1966+ mem_access_subid.s.ba += 1;
1967+ }
1968+
1969+ /*
1970+ * Disable the peer to peer forwarding register. This must be
1971+ * setup by the OS after it enumerates the bus and assigns
1972+ * addresses to the PCIe busses.
1973+ */
1974+ for (i = 0; i < 4; i++) {
1975+ cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
1976+ cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
1977+ }
1978+
1979+ /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1980+ cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
1981+
1982+ /*
1983+ * Disable Octeon's BAR1. It isn't needed in RC mode since
1984+ * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
1985+ * the 2nd 256MB of memory.
1986+ */
1987+ cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
1988+
1989+ /*
1990+ * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
1991+ * precedence where they overlap. It also overlaps with the
1992+ * device addresses, so make sure the peer to peer forwarding
1993+ * is set right.
1994+ */
1995+ cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
1996+
1997+ /*
1998+ * Setup BAR2 attributes
1999+ *
2000+ * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
2001+ * - PTLP_RO,CTLP_RO should normally be set (except for debug).
2002+ * - WAIT_COM=0 will likely work for all applications.
2003+ *
2004+ * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
2005+ */
2006+ if (pcie_port) {
2007+ union cvmx_npei_ctl_port1 npei_ctl_port;
2008+ npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
2009+ npei_ctl_port.s.bar2_enb = 1;
2010+ npei_ctl_port.s.bar2_esx = 1;
2011+ npei_ctl_port.s.bar2_cax = 0;
2012+ npei_ctl_port.s.ptlp_ro = 1;
2013+ npei_ctl_port.s.ctlp_ro = 1;
2014+ npei_ctl_port.s.wait_com = 0;
2015+ npei_ctl_port.s.waitl_com = 0;
2016+ cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
2017+ } else {
2018+ union cvmx_npei_ctl_port0 npei_ctl_port;
2019+ npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
2020+ npei_ctl_port.s.bar2_enb = 1;
2021+ npei_ctl_port.s.bar2_esx = 1;
2022+ npei_ctl_port.s.bar2_cax = 0;
2023+ npei_ctl_port.s.ptlp_ro = 1;
2024+ npei_ctl_port.s.ctlp_ro = 1;
2025+ npei_ctl_port.s.wait_com = 0;
2026+ npei_ctl_port.s.waitl_com = 0;
2027+ cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
2028+ }
2029+ return 0;
2030+}
2031+
2032+/**
2033+ * Shutdown a PCIe port and put it in reset
2034+ *
2035+ * @pcie_port: PCIe port to shutdown
2036+ *
2037+ * Returns Zero on success
2038+ */
2039+int cvmx_pcie_rc_shutdown(int pcie_port)
2040+{
2041+ /* Wait for all pending operations to complete */
2042+ if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CPL_LUT_VALID(pcie_port),
2043+ union cvmx_pescx_cpl_lut_valid,
2044+ tag, ==, 0, 2000))
2045+ cvmx_dprintf("PCIe: Port %d shutdown timeout\n", pcie_port);
2046+
2047+ /* Force reset */
2048+ if (pcie_port) {
2049+ union cvmx_ciu_soft_prst ciu_soft_prst;
2050+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
2051+ ciu_soft_prst.s.soft_prst = 1;
2052+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
2053+ } else {
2054+ union cvmx_ciu_soft_prst ciu_soft_prst;
2055+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
2056+ ciu_soft_prst.s.soft_prst = 1;
2057+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
2058+ }
2059+ return 0;
2060+}
2061+
2062+/**
2063+ * Build a PCIe config space request address for a device
2064+ *
2065+ * @pcie_port: PCIe port to access
2066+ * @bus: Sub bus
2067+ * @dev: Device ID
2068+ * @fn: Device sub function
2069+ * @reg: Register to access
2070+ *
2071+ * Returns 64bit Octeon IO address
2072+ */
2073+static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
2074+ int dev, int fn, int reg)
2075+{
2076+ union cvmx_pcie_address pcie_addr;
2077+ union cvmx_pciercx_cfg006 pciercx_cfg006;
2078+
2079+ pciercx_cfg006.u32 =
2080+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
2081+ if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
2082+ return 0;
2083+
2084+ pcie_addr.u64 = 0;
2085+ pcie_addr.config.upper = 2;
2086+ pcie_addr.config.io = 1;
2087+ pcie_addr.config.did = 3;
2088+ pcie_addr.config.subdid = 1;
2089+ pcie_addr.config.es = 1;
2090+ pcie_addr.config.port = pcie_port;
2091+ pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
2092+ pcie_addr.config.bus = bus;
2093+ pcie_addr.config.dev = dev;
2094+ pcie_addr.config.func = fn;
2095+ pcie_addr.config.reg = reg;
2096+ return pcie_addr.u64;
2097+}
2098+
2099+/**
2100+ * Read 8bits from a Device's config space
2101+ *
2102+ * @pcie_port: PCIe port the device is on
2103+ * @bus: Sub bus
2104+ * @dev: Device ID
2105+ * @fn: Device sub function
2106+ * @reg: Register to access
2107+ *
2108+ * Returns Result of the read
2109+ */
2110+uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
2111+ int fn, int reg)
2112+{
2113+ uint64_t address =
2114+ __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2115+ if (address)
2116+ return cvmx_read64_uint8(address);
2117+ else
2118+ return 0xff;
2119+}
2120+
2121+/**
2122+ * Read 16bits from a Device's config space
2123+ *
2124+ * @pcie_port: PCIe port the device is on
2125+ * @bus: Sub bus
2126+ * @dev: Device ID
2127+ * @fn: Device sub function
2128+ * @reg: Register to access
2129+ *
2130+ * Returns Result of the read
2131+ */
2132+uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn,
2133+ int reg)
2134+{
2135+ uint64_t address =
2136+ __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2137+ if (address)
2138+ return le16_to_cpu(cvmx_read64_uint16(address));
2139+ else
2140+ return 0xffff;
2141+}
2142+
2143+/**
2144+ * Read 32bits from a Device's config space
2145+ *
2146+ * @pcie_port: PCIe port the device is on
2147+ * @bus: Sub bus
2148+ * @dev: Device ID
2149+ * @fn: Device sub function
2150+ * @reg: Register to access
2151+ *
2152+ * Returns Result of the read
2153+ */
2154+uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn,
2155+ int reg)
2156+{
2157+ uint64_t address =
2158+ __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2159+ if (address)
2160+ return le32_to_cpu(cvmx_read64_uint32(address));
2161+ else
2162+ return 0xffffffff;
2163+}
2164+
2165+/**
2166+ * Write 8bits to a Device's config space
2167+ *
2168+ * @pcie_port: PCIe port the device is on
2169+ * @bus: Sub bus
2170+ * @dev: Device ID
2171+ * @fn: Device sub function
2172+ * @reg: Register to access
2173+ * @val: Value to write
2174+ */
2175+void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
2176+ int reg, uint8_t val)
2177+{
2178+ uint64_t address =
2179+ __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2180+ if (address)
2181+ cvmx_write64_uint8(address, val);
2182+}
2183+
2184+/**
2185+ * Write 16bits to a Device's config space
2186+ *
2187+ * @pcie_port: PCIe port the device is on
2188+ * @bus: Sub bus
2189+ * @dev: Device ID
2190+ * @fn: Device sub function
2191+ * @reg: Register to access
2192+ * @val: Value to write
2193+ */
2194+void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
2195+ int reg, uint16_t val)
2196+{
2197+ uint64_t address =
2198+ __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2199+ if (address)
2200+ cvmx_write64_uint16(address, cpu_to_le16(val));
2201+}
2202+
2203+/**
2204+ * Write 32bits to a Device's config space
2205+ *
2206+ * @pcie_port: PCIe port the device is on
2207+ * @bus: Sub bus
2208+ * @dev: Device ID
2209+ * @fn: Device sub function
2210+ * @reg: Register to access
2211+ * @val: Value to write
2212+ */
2213+void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
2214+ int reg, uint32_t val)
2215+{
2216+ uint64_t address =
2217+ __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2218+ if (address)
2219+ cvmx_write64_uint32(address, cpu_to_le32(val));
2220+}
2221+
2222+/**
2223+ * Read a PCIe config space register indirectly. This is used for
2224+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
2225+ *
2226+ * @pcie_port: PCIe port to read from
2227+ * @cfg_offset: Address to read
2228+ *
2229+ * Returns Value read
2230+ */
2231+uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
2232+{
2233+ union cvmx_pescx_cfg_rd pescx_cfg_rd;
2234+ pescx_cfg_rd.u64 = 0;
2235+ pescx_cfg_rd.s.addr = cfg_offset;
2236+ cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
2237+ pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
2238+ return pescx_cfg_rd.s.data;
2239+}
2240+
2241+/**
2242+ * Write a PCIe config space register indirectly. This is used for
2243+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
2244+ *
2245+ * @pcie_port: PCIe port to write to
2246+ * @cfg_offset: Address to write
2247+ * @val: Value to write
2248+ */
2249+void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val)
2250+{
2251+ union cvmx_pescx_cfg_wr pescx_cfg_wr;
2252+ pescx_cfg_wr.u64 = 0;
2253+ pescx_cfg_wr.s.addr = cfg_offset;
2254+ pescx_cfg_wr.s.data = val;
2255+ cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
2256+}
2257+
2258+/**
2259+ * Initialize a PCIe port for use in target(EP) mode.
2260+ *
2261+ * Returns Zero on success
2262+ */
2263+int cvmx_pcie_ep_initialize(void)
2264+{
2265+ int pcie_port = 0;
2266+ union cvmx_npei_ctl_status npei_ctl_status;
2267+ union cvmx_pciercx_cfg030 pciercx_cfg030;
2268+ union cvmx_npei_ctl_status2 npei_ctl_status2;
2269+ union cvmx_npei_mem_access_subidx mem_access_subid;
2270+
2271+ npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
2272+ if (npei_ctl_status.s.host_mode)
2273+ return -1;
2274+
2275+ /* Enable bus master and memory */
2276+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIEEP_CFG001, 0x6);
2277+
2278+ /*
2279+ * Max Payload Size (PCIE*_CFG030[MPS])
2280+ * Max Read Request Size (PCIE*_CFG030[MRRS])
2281+ * Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN]
2282+ * Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN])
2283+ */
2284+ pciercx_cfg030.u32 =
2285+ cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
2286+ /* Max payload size = 128 bytes (Limit of most PCs) */
2287+ pciercx_cfg030.s.mps = 0;
2288+ /*
2289+ * Max read request size = 128 bytes for best Octeon DMA
2290+ * performance.
2291+ */
2292+ pciercx_cfg030.s.mrrs = 0;
2293+ /* Enable relaxed ordering. */
2294+ pciercx_cfg030.s.ro_en = 1;
2295+ /* Enable no snoop. */
2296+ pciercx_cfg030.s.ns_en = 1;
2297+ /* Correctable error reporting enable. */
2298+ pciercx_cfg030.s.ce_en = 1;
2299+ /* Non-fatal error reporting enable. */
2300+ pciercx_cfg030.s.nfe_en = 1;
2301+ /* Fatal error reporting enable. */
2302+ pciercx_cfg030.s.fe_en = 1;
2303+ /* Unsupported request reporting enable. */
2304+ pciercx_cfg030.s.ur_en = 1;
2305+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
2306+ pciercx_cfg030.u32);
2307+
2308+ /*
2309+ * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
2310+ * PCIE*_CFG030[MPS]
2311+ *
2312+ * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
2313+ * exceed PCIE*_CFG030[MRRS]
2314+ */
2315+ npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
2316+ /* Max payload size = 128 bytes (Limit of most PCs) */
2317+ npei_ctl_status2.s.mps = 0;
2318+ /* Max read request size = 128 bytes for best Octeon DMA performance */
2319+ npei_ctl_status2.s.mrrs = 0;
2320+ cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
2321+
2322+ /* Setup Mem access SubDID 12 to access Host memory */
2323+ mem_access_subid.u64 = 0;
2324+ /* Port the request is sent to. */
2325+ mem_access_subid.s.port = pcie_port;
2326+ /* Merging is allowed in this window. */
2327+ mem_access_subid.s.nmerge = 1;
2328+ /* Endian-swap for Reads. */
2329+ mem_access_subid.s.esr = 0;
2330+ /* Endian-swap for Writes. */
2331+ mem_access_subid.s.esw = 0;
2332+ /* No Snoop for Reads. */
2333+ mem_access_subid.s.nsr = 1;
2334+ /* No Snoop for Writes. */
2335+ mem_access_subid.s.nsw = 1;
2336+ /* Disable Relaxed Ordering for Reads. */
2337+ mem_access_subid.s.ror = 0;
2338+ /* Disable Relaxed Ordering for Writes. */
2339+ mem_access_subid.s.row = 0;
2340+ /* PCIe Adddress Bits <63:34>. */
2341+ mem_access_subid.s.ba = 0;
2342+ cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(12),
2343+ mem_access_subid.u64);
2344+ return 0;
2345+}
2346--- /dev/null
2347+++ b/arch/mips/cavium-octeon/msi.c
2348@@ -0,0 +1,288 @@
2349+/*
2350+ * This file is subject to the terms and conditions of the GNU General Public
2351+ * License. See the file "COPYING" in the main directory of this archive
2352+ * for more details.
2353+ *
2354+ * Copyright (C) 2005-2007 Cavium Networks
2355+ */
2356+#include <linux/kernel.h>
2357+#include <linux/init.h>
2358+#include <linux/msi.h>
2359+#include <linux/spinlock.h>
2360+#include <linux/interrupt.h>
2361+
2362+#include <asm/octeon/octeon.h>
2363+#include <asm/octeon/cvmx-npi-defs.h>
2364+#include <asm/octeon/cvmx-pci-defs.h>
2365+#include <asm/octeon/cvmx-npei-defs.h>
2366+#include <asm/octeon/cvmx-pexp-defs.h>
2367+
2368+#include "pci-common.h"
2369+
2370+/*
2371+ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
2372+ * in use.
2373+ */
2374+static uint64_t msi_free_irq_bitmask;
2375+
2376+/*
2377+ * Each bit in msi_multiple_irq_bitmask tells that the device using
2378+ * this bit in msi_free_irq_bitmask is also using the next bit. This
2379+ * is used so we can disable all of the MSI interrupts when a device
2380+ * uses multiple.
2381+ */
2382+static uint64_t msi_multiple_irq_bitmask;
2383+
2384+/*
2385+ * This lock controls updates to msi_free_irq_bitmask and
2386+ * msi_multiple_irq_bitmask.
2387+ */
2388+static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
2389+
2390+
2391+/**
2392+ * Called when a driver request MSI interrupts instead of the
2393+ * legacy INT A-D. This routine will allocate multiple interrupts
2394+ * for MSI devices that support them. A device can override this by
2395+ * programming the MSI control bits [6:4] before calling
2396+ * pci_enable_msi().
2397+ *
2398+ * @param dev Device requesting MSI interrupts
2399+ * @param desc MSI descriptor
2400+ *
2401+ * Returns 0 on success.
2402+ */
2403+int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2404+{
2405+ struct msi_msg msg;
2406+ uint16_t control;
2407+ int configured_private_bits;
2408+ int request_private_bits;
2409+ int irq;
2410+ int irq_step;
2411+ uint64_t search_mask;
2412+
2413+ /*
2414+ * Read the MSI config to figure out how many IRQs this device
2415+ * wants. Most devices only want 1, which will give
2416+ * configured_private_bits and request_private_bits equal 0.
2417+ */
2418+ pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
2419+ &control);
2420+
2421+ /*
2422+ * If the number of private bits has been configured then use
2423+ * that value instead of the requested number. This gives the
2424+ * driver the chance to override the number of interrupts
2425+ * before calling pci_enable_msi().
2426+ */
2427+ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
2428+ if (configured_private_bits == 0) {
2429+ /* Nothing is configured, so use the hardware requested size */
2430+ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
2431+ } else {
2432+ /*
2433+ * Use the number of configured bits, assuming the
2434+ * driver wanted to override the hardware request
2435+ * value.
2436+ */
2437+ request_private_bits = configured_private_bits;
2438+ }
2439+
2440+ /*
2441+ * The PCI 2.3 spec mandates that there are at most 32
2442+ * interrupts. If this device asks for more, only give it one.
2443+ */
2444+ if (request_private_bits > 5)
2445+ request_private_bits = 0;
2446+
2447+try_only_one:
2448+ /*
2449+ * The IRQs have to be aligned on a power of two based on the
2450+ * number being requested.
2451+ */
2452+ irq_step = 1 << request_private_bits;
2453+
2454+ /* Mask with one bit for each IRQ */
2455+ search_mask = (1 << irq_step) - 1;
2456+
2457+ /*
2458+ * We're going to search msi_free_irq_bitmask_lock for zero
2459+ * bits. This represents an MSI interrupt number that isn't in
2460+ * use.
2461+ */
2462+ spin_lock(&msi_free_irq_bitmask_lock);
2463+ for (irq = 0; irq < 64; irq += irq_step) {
2464+ if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
2465+ msi_free_irq_bitmask |= search_mask << irq;
2466+ msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
2467+ break;
2468+ }
2469+ }
2470+ spin_unlock(&msi_free_irq_bitmask_lock);
2471+
2472+ /* Make sure the search for available interrupts didn't fail */
2473+ if (irq >= 64) {
2474+ if (request_private_bits) {
2475+ pr_err("arch_setup_msi_irq: Unable to find %d free "
2476+ "interrupts, trying just one",
2477+ 1 << request_private_bits);
2478+ request_private_bits = 0;
2479+ goto try_only_one;
2480+ } else
2481+ panic("arch_setup_msi_irq: Unable to find a free MSI "
2482+ "interrupt");
2483+ }
2484+
2485+ /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
2486+ irq += OCTEON_IRQ_MSI_BIT0;
2487+
2488+ switch (octeon_dma_bar_type) {
2489+ case OCTEON_DMA_BAR_TYPE_SMALL:
2490+ /* When not using big bar, Bar 0 is based at 128MB */
2491+ msg.address_lo =
2492+ ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
2493+ msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
2494+ case OCTEON_DMA_BAR_TYPE_BIG:
2495+ /* When using big bar, Bar 0 is based at 0 */
2496+ msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
2497+ msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
2498+ break;
2499+ case OCTEON_DMA_BAR_TYPE_PCIE:
2500+ /* When using PCIe, Bar 0 is based at 0 */
2501+ /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
2502+ msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
2503+ msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
2504+ break;
2505+ default:
2506+ panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
2507+ }
2508+ msg.data = irq - OCTEON_IRQ_MSI_BIT0;
2509+
2510+ /* Update the number of IRQs the device has available to it */
2511+ control &= ~PCI_MSI_FLAGS_QSIZE;
2512+ control |= request_private_bits << 4;
2513+ pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
2514+ control);
2515+
2516+ set_irq_msi(irq, desc);
2517+ write_msi_msg(irq, &msg);
2518+ return 0;
2519+}
2520+
2521+
2522+/**
2523+ * Called when a device no longer needs its MSI interrupts. All
2524+ * MSI interrupts for the device are freed.
2525+ *
2526+ * @irq: The devices first irq number. There may be multple in sequence.
2527+ */
2528+void arch_teardown_msi_irq(unsigned int irq)
2529+{
2530+ int number_irqs;
2531+ uint64_t bitmask;
2532+
2533+ if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
2534+ panic("arch_teardown_msi_irq: Attempted to teardown illegal "
2535+ "MSI interrupt (%d)", irq);
2536+ irq -= OCTEON_IRQ_MSI_BIT0;
2537+
2538+ /*
2539+ * Count the number of IRQs we need to free by looking at the
2540+ * msi_multiple_irq_bitmask. Each bit set means that the next
2541+ * IRQ is also owned by this device.
2542+ */
2543+ number_irqs = 0;
2544+ while ((irq+number_irqs < 64) &&
2545+ (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
2546+ number_irqs++;
2547+ number_irqs++;
2548+ /* Mask with one bit for each IRQ */
2549+ bitmask = (1 << number_irqs) - 1;
2550+ /* Shift the mask to the correct bit location */
2551+ bitmask <<= irq;
2552+ if ((msi_free_irq_bitmask & bitmask) != bitmask)
2553+ panic("arch_teardown_msi_irq: Attempted to teardown MSI "
2554+ "interrupt (%d) not in use", irq);
2555+
2556+ /* Checks are done, update the in use bitmask */
2557+ spin_lock(&msi_free_irq_bitmask_lock);
2558+ msi_free_irq_bitmask &= ~bitmask;
2559+ msi_multiple_irq_bitmask &= ~bitmask;
2560+ spin_unlock(&msi_free_irq_bitmask_lock);
2561+}
2562+
2563+
2564+/**
2565+ * Called by the interrupt handling code when an MSI interrupt
2566+ * occurs.
2567+ *
2568+ * @param cpl
2569+ * @param dev_id
2570+ *
2571+ * @return
2572+ */
2573+static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
2574+{
2575+ uint64_t msi_bits;
2576+ int irq;
2577+
2578+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
2579+ msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
2580+ else
2581+ msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
2582+ irq = fls64(msi_bits);
2583+ if (irq) {
2584+ irq += OCTEON_IRQ_MSI_BIT0 - 1;
2585+ if (irq_desc[irq].action) {
2586+ do_IRQ(irq);
2587+ return IRQ_HANDLED;
2588+ } else {
2589+ pr_err("Spurious MSI interrupt %d\n", irq);
2590+ if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
2591+ /* These chips have PCIe */
2592+ cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
2593+ 1ull << (irq -
2594+ OCTEON_IRQ_MSI_BIT0));
2595+ } else {
2596+ /* These chips have PCI */
2597+ cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
2598+ 1ull << (irq -
2599+ OCTEON_IRQ_MSI_BIT0));
2600+ }
2601+ }
2602+ }
2603+ return IRQ_NONE;
2604+}
2605+
2606+
2607+/**
2608+ * Initializes the MSI interrupt handling code
2609+ *
2610+ * @return
2611+ */
2612+int octeon_msi_initialize(void)
2613+{
2614+ int r;
2615+ if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
2616+ r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
2617+ IRQF_SHARED,
2618+ "MSI[0:63]", octeon_msi_interrupt);
2619+ } else if (octeon_is_pci_host()) {
2620+ r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
2621+ IRQF_SHARED,
2622+ "MSI[0:15]", octeon_msi_interrupt);
2623+ r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
2624+ IRQF_SHARED,
2625+ "MSI[16:31]", octeon_msi_interrupt);
2626+ r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
2627+ IRQF_SHARED,
2628+ "MSI[32:47]", octeon_msi_interrupt);
2629+ r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
2630+ IRQF_SHARED,
2631+ "MSI[48:63]", octeon_msi_interrupt);
2632+ }
2633+ return 0;
2634+}
2635+
2636+subsys_initcall(octeon_msi_initialize);
2637--- a/arch/mips/cavium-octeon/octeon-irq.c
2638+++ b/arch/mips/cavium-octeon/octeon-irq.c
2639@@ -10,6 +10,8 @@
2640 #include <linux/hardirq.h>
2641 
2642 #include <asm/octeon/octeon.h>
2643+#include <asm/octeon/cvmx-pexp-defs.h>
2644+#include <asm/octeon/cvmx-npi-defs.h>
2645 
2646 DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
2647 DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
2648--- /dev/null
2649+++ b/arch/mips/cavium-octeon/pci-common.c
2650@@ -0,0 +1,137 @@
2651+/*
2652+ * This file is subject to the terms and conditions of the GNU General Public
2653+ * License. See the file "COPYING" in the main directory of this archive
2654+ * for more details.
2655+ *
2656+ * Copyright (C) 2005-2007 Cavium Networks
2657+ */
2658+#include <linux/kernel.h>
2659+#include <linux/init.h>
2660+#include <linux/pci.h>
2661+#include <linux/interrupt.h>
2662+#include <linux/time.h>
2663+#include <linux/delay.h>
2664+#include "pci-common.h"
2665+
2666+typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
2667+enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
2668+
2669+/**
2670+ * Map a PCI device to the appropriate interrupt line
2671+ *
2672+ * @param dev The Linux PCI device structure for the device to map
2673+ * @param slot The slot number for this device on __BUS 0__. Linux
2674+ * enumerates through all the bridges and figures out the
2675+ * slot on Bus 0 where this device eventually hooks to.
2676+ * @param pin The PCI interrupt pin read from the device, then swizzled
2677+ * as it goes through each bridge.
2678+ * @return Interrupt number for the device
2679+ */
2680+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
2681+{
2682+ if (octeon_pcibios_map_irq)
2683+ return octeon_pcibios_map_irq(dev, slot, pin);
2684+ else
2685+ panic("octeon_pcibios_map_irq doesn't point to a "
2686+ "pcibios_map_irq() function");
2687+}
2688+
2689+
2690+/**
2691+ * Called to perform platform specific PCI setup
2692+ *
2693+ * @param dev
2694+ * @return
2695+ */
2696+int pcibios_plat_dev_init(struct pci_dev *dev)
2697+{
2698+ uint16_t config;
2699+ uint32_t dconfig;
2700+ int pos;
2701+ /*
2702+ * Force the Cache line setting to 64 bytes. The standard
2703+ * Linux bus scan doesn't seem to set it. Octeon really has
2704+ * 128 byte lines, but Intel bridges get really upset if you
2705+ * try and set values above 64 bytes. Value is specified in
2706+ * 32bit words.
2707+ */
2708+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
2709+ /* Set latency timers for all devices */
2710+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
2711+
2712+ /* Enable reporting System errors and parity errors on all devices */
2713+ /* Enable parity checking and error reporting */
2714+ pci_read_config_word(dev, PCI_COMMAND, &config);
2715+ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2716+ pci_write_config_word(dev, PCI_COMMAND, config);
2717+
2718+ if (dev->subordinate) {
2719+ /* Set latency timers on sub bridges */
2720+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
2721+ /* More bridge error detection */
2722+ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
2723+ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
2724+ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
2725+ }
2726+
2727+ /* Enable the PCIe normal error reporting */
2728+ pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2729+ if (pos) {
2730+ /* Update Device Control */
2731+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
2732+ /* Correctable Error Reporting */
2733+ config |= PCI_EXP_DEVCTL_CERE;
2734+ /* Non-Fatal Error Reporting */
2735+ config |= PCI_EXP_DEVCTL_NFERE;
2736+ /* Fatal Error Reporting */
2737+ config |= PCI_EXP_DEVCTL_FERE;
2738+ /* Unsupported Request */
2739+ config |= PCI_EXP_DEVCTL_URRE;
2740+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
2741+ }
2742+
2743+ /* Find the Advanced Error Reporting capability */
2744+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
2745+ if (pos) {
2746+ /* Clear Uncorrectable Error Status */
2747+ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
2748+ &dconfig);
2749+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
2750+ dconfig);
2751+ /* Enable reporting of all uncorrectable errors */
2752+ /* Uncorrectable Error Mask - turned on bits disable errors */
2753+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
2754+ /*
2755+ * Leave severity at HW default. This only controls if
2756+ * errors are reported as uncorrectable or
2757+ * correctable, not if the error is reported.
2758+ */
2759+ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
2760+ /* Clear Correctable Error Status */
2761+ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
2762+ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
2763+ /* Enable reporting of all correctable errors */
2764+ /* Correctable Error Mask - turned on bits disable errors */
2765+ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
2766+ /* Advanced Error Capabilities */
2767+ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
2768+ /* ECRC Generation Enable */
2769+ if (config & PCI_ERR_CAP_ECRC_GENC)
2770+ config |= PCI_ERR_CAP_ECRC_GENE;
2771+ /* ECRC Check Enable */
2772+ if (config & PCI_ERR_CAP_ECRC_CHKC)
2773+ config |= PCI_ERR_CAP_ECRC_CHKE;
2774+ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
2775+ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
2776+ /* Report all errors to the root complex */
2777+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
2778+ PCI_ERR_ROOT_CMD_COR_EN |
2779+ PCI_ERR_ROOT_CMD_NONFATAL_EN |
2780+ PCI_ERR_ROOT_CMD_FATAL_EN);
2781+ /* Clear the Root status register */
2782+ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
2783+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
2784+ }
2785+
2786+ return 0;
2787+}
2788--- /dev/null
2789+++ b/arch/mips/cavium-octeon/pci-common.h
2790@@ -0,0 +1,39 @@
2791+/*
2792+ * This file is subject to the terms and conditions of the GNU General Public
2793+ * License. See the file "COPYING" in the main directory of this archive
2794+ * for more details.
2795+ *
2796+ * Copyright (C) 2005-2007 Cavium Networks
2797+ */
2798+#ifndef __OCTEON_PCI_COMMON_H__
2799+#define __OCTEON_PCI_COMMON_H__
2800+
2801+#include <linux/pci.h>
2802+
2803+/* Some PCI cards require delays when accessing config space. */
2804+#define PCI_CONFIG_SPACE_DELAY 10000
2805+
2806+/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
2807+ Octeon specific version pointed to by this variable. This function needs to
2808+ change for PCI or PCIe based hosts */
2809+extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
2810+
2811+/* The following defines are only used when octeon_dma_bar_type =
2812+ OCTEON_DMA_BAR_TYPE_BIG */
2813+#define OCTEON_PCI_BAR1_HOLE_BITS 5
2814+#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
2815+
2816+enum octeon_dma_bar_type {
2817+ OCTEON_DMA_BAR_TYPE_INVALID,
2818+ OCTEON_DMA_BAR_TYPE_SMALL,
2819+ OCTEON_DMA_BAR_TYPE_BIG,
2820+ OCTEON_DMA_BAR_TYPE_PCIE
2821+};
2822+
2823+/**
2824+ * This is a variable to tell the DMA mapping system in dma-octeon.c
2825+ * how to map PCI DMA addresses.
2826+ */
2827+extern enum octeon_dma_bar_type octeon_dma_bar_type;
2828+
2829+#endif
2830--- /dev/null
2831+++ b/arch/mips/cavium-octeon/pci.c
2832@@ -0,0 +1,568 @@
2833+/*
2834+ * This file is subject to the terms and conditions of the GNU General Public
2835+ * License. See the file "COPYING" in the main directory of this archive
2836+ * for more details.
2837+ *
2838+ * Copyright (C) 2005-2007 Cavium Networks
2839+ */
2840+#include <linux/kernel.h>
2841+#include <linux/init.h>
2842+#include <linux/pci.h>
2843+#include <linux/interrupt.h>
2844+#include <linux/time.h>
2845+#include <linux/delay.h>
2846+
2847+#include <asm/time.h>
2848+
2849+#include <asm/octeon/octeon.h>
2850+#include <asm/octeon/cvmx-npi-defs.h>
2851+#include <asm/octeon/cvmx-pci-defs.h>
2852+
2853+#include "pci-common.h"
2854+
2855+#define USE_OCTEON_INTERNAL_ARBITER
2856+
2857+/*
2858+ * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
2859+ * addresses. Use PCI endian swapping 1 so no address swapping is
2860+ * necessary. The Linux io routines will endian swap the data.
2861+ */
2862+#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
2863+#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
2864+
2865+/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
2866+#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
2867+
2868+/**
2869+ * This is the bit decoding used for the Octeon PCI controller addresses
2870+ */
2871+union octeon_pci_address {
2872+ uint64_t u64;
2873+ struct {
2874+ uint64_t upper:2;
2875+ uint64_t reserved:13;
2876+ uint64_t io:1;
2877+ uint64_t did:5;
2878+ uint64_t subdid:3;
2879+ uint64_t reserved2:4;
2880+ uint64_t endian_swap:2;
2881+ uint64_t reserved3:10;
2882+ uint64_t bus:8;
2883+ uint64_t dev:5;
2884+ uint64_t func:3;
2885+ uint64_t reg:8;
2886+ } s;
2887+};
2888+
2889+/**
2890+ * Return the mapping of PCI device number to IRQ line. Each
2891+ * character in the return string represents the interrupt
2892+ * line for the device at that position. Device 1 maps to the
2893+ * first character, etc. The characters A-D are used for PCI
2894+ * interrupts.
2895+ *
2896+ * Returns PCI interrupt mapping
2897+ */
2898+const char *octeon_get_pci_interrupts(void)
2899+{
2900+ /*
2901+ * Returning an empty string causes the interrupts to be
2902+ * routed based on the PCI specification. From the PCI spec:
2903+ *
2904+ * INTA# of Device Number 0 is connected to IRQW on the system
2905+ * board. (Device Number has no significance regarding being
2906+ * located on the system board or in a connector.) INTA# of
2907+ * Device Number 1 is connected to IRQX on the system
2908+ * board. INTA# of Device Number 2 is connected to IRQY on the
2909+ * system board. INTA# of Device Number 3 is connected to IRQZ
2910+ * on the system board. The table below describes how each
2911+ * agent's INTx# lines are connected to the system board
2912+ * interrupt lines. The following equation can be used to
2913+ * determine to which INTx# signal on the system board a given
2914+ * device's INTx# line(s) is connected.
2915+ *
2916+ * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
2917+ * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
2918+ * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
2919+ * INTD# = 3)
2920+ */
2921+ switch (octeon_bootinfo->board_type) {
2922+ case CVMX_BOARD_TYPE_NAO38:
2923+ /* This is really the NAC38 */
2924+ return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
2925+ case CVMX_BOARD_TYPE_THUNDER:
2926+ return "";
2927+ case CVMX_BOARD_TYPE_EBH3000:
2928+ return "";
2929+ case CVMX_BOARD_TYPE_EBH3100:
2930+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
2931+ case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
2932+ return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
2933+ case CVMX_BOARD_TYPE_BBGW_REF:
2934+ return "AABCD";
2935+ default:
2936+ return "";
2937+ }
2938+}
2939+
2940+/**
2941+ * Map a PCI device to the appropriate interrupt line
2942+ *
2943+ * @dev: The Linux PCI device structure for the device to map
2944+ * @slot: The slot number for this device on __BUS 0__. Linux
2945+ * enumerates through all the bridges and figures out the
2946+ * slot on Bus 0 where this device eventually hooks to.
2947+ * @pin: The PCI interrupt pin read from the device, then swizzled
2948+ * as it goes through each bridge.
2949+ * Returns Interrupt number for the device
2950+ */
2951+int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
2952+ u8 slot, u8 pin)
2953+{
2954+ int irq_num;
2955+ const char *interrupts;
2956+ int dev_num;
2957+
2958+ /* Get the board specific interrupt mapping */
2959+ interrupts = octeon_get_pci_interrupts();
2960+
2961+ dev_num = dev->devfn >> 3;
2962+ if (dev_num < strlen(interrupts))
2963+ irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
2964+ OCTEON_IRQ_PCI_INT0;
2965+ else
2966+ irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
2967+ return irq_num;
2968+}
2969+
2970+
2971+/**
2972+ * Read a value from configuration space
2973+ *
2974+ */
2975+static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
2976+ int reg, int size, u32 *val)
2977+{
2978+ union octeon_pci_address pci_addr;
2979+
2980+ pci_addr.u64 = 0;
2981+ pci_addr.s.upper = 2;
2982+ pci_addr.s.io = 1;
2983+ pci_addr.s.did = 3;
2984+ pci_addr.s.subdid = 1;
2985+ pci_addr.s.endian_swap = 1;
2986+ pci_addr.s.bus = bus->number;
2987+ pci_addr.s.dev = devfn >> 3;
2988+ pci_addr.s.func = devfn & 0x7;
2989+ pci_addr.s.reg = reg;
2990+
2991+#if PCI_CONFIG_SPACE_DELAY
2992+ udelay(PCI_CONFIG_SPACE_DELAY);
2993+#endif
2994+ switch (size) {
2995+ case 4:
2996+ *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
2997+ return PCIBIOS_SUCCESSFUL;
2998+ case 2:
2999+ *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
3000+ return PCIBIOS_SUCCESSFUL;
3001+ case 1:
3002+ *val = cvmx_read64_uint8(pci_addr.u64);
3003+ return PCIBIOS_SUCCESSFUL;
3004+ }
3005+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3006+}
3007+
3008+
3009+/**
3010+ * Write a value to PCI configuration space
3011+ *
3012+ * @bus:
3013+ * @devfn:
3014+ * @reg:
3015+ * @size:
3016+ * @val:
3017+ * Returns
3018+ */
3019+static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
3020+ int reg, int size, u32 val)
3021+{
3022+ union octeon_pci_address pci_addr;
3023+
3024+ pci_addr.u64 = 0;
3025+ pci_addr.s.upper = 2;
3026+ pci_addr.s.io = 1;
3027+ pci_addr.s.did = 3;
3028+ pci_addr.s.subdid = 1;
3029+ pci_addr.s.endian_swap = 1;
3030+ pci_addr.s.bus = bus->number;
3031+ pci_addr.s.dev = devfn >> 3;
3032+ pci_addr.s.func = devfn & 0x7;
3033+ pci_addr.s.reg = reg;
3034+
3035+#if PCI_CONFIG_SPACE_DELAY
3036+ udelay(PCI_CONFIG_SPACE_DELAY);
3037+#endif
3038+ switch (size) {
3039+ case 4:
3040+ cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
3041+ return PCIBIOS_SUCCESSFUL;
3042+ case 2:
3043+ cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
3044+ return PCIBIOS_SUCCESSFUL;
3045+ case 1:
3046+ cvmx_write64_uint8(pci_addr.u64, val);
3047+ return PCIBIOS_SUCCESSFUL;
3048+ }
3049+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3050+}
3051+
3052+
3053+static struct pci_ops octeon_pci_ops = {
3054+ octeon_read_config,
3055+ octeon_write_config,
3056+};
3057+
3058+static struct resource octeon_pci_mem_resource = {
3059+ .start = 0,
3060+ .end = 0,
3061+ .name = "Octeon PCI MEM",
3062+ .flags = IORESOURCE_MEM,
3063+};
3064+
3065+/*
3066+ * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
3067+ * bridge
3068+ */
3069+static struct resource octeon_pci_io_resource = {
3070+ .start = 0x4000,
3071+ .end = OCTEON_PCI_IOSPACE_SIZE - 1,
3072+ .name = "Octeon PCI IO",
3073+ .flags = IORESOURCE_IO,
3074+};
3075+
3076+static struct pci_controller octeon_pci_controller = {
3077+ .pci_ops = &octeon_pci_ops,
3078+ .mem_resource = &octeon_pci_mem_resource,
3079+ .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
3080+ .io_resource = &octeon_pci_io_resource,
3081+ .io_offset = 0,
3082+ .io_map_base = OCTEON_PCI_IOSPACE_BASE,
3083+};
3084+
3085+
3086+/**
3087+ * Low level initialize the Octeon PCI controller
3088+ *
3089+ * Returns
3090+ */
3091+static void octeon_pci_initialize(void)
3092+{
3093+ union cvmx_pci_cfg01 cfg01;
3094+ union cvmx_npi_ctl_status ctl_status;
3095+ union cvmx_pci_ctl_status_2 ctl_status_2;
3096+ union cvmx_pci_cfg19 cfg19;
3097+ union cvmx_pci_cfg16 cfg16;
3098+ union cvmx_pci_cfg22 cfg22;
3099+ union cvmx_pci_cfg56 cfg56;
3100+
3101+ /* Reset the PCI Bus */
3102+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
3103+ cvmx_read_csr(CVMX_CIU_SOFT_PRST);
3104+
3105+ udelay(2000); /* Hold PCI reset for 2 ms */
3106+
3107+ ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
3108+ ctl_status.s.max_word = 1;
3109+ ctl_status.s.timer = 1;
3110+ cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
3111+
3112+ /* Deassert PCI reset and advertize PCX Host Mode Device Capability
3113+ (64b) */
3114+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
3115+ cvmx_read_csr(CVMX_CIU_SOFT_PRST);
3116+
3117+ udelay(2000); /* Wait 2 ms after deasserting PCI reset */
3118+
3119+ ctl_status_2.u32 = 0;
3120+ ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set
3121+ before any PCI reads. */
3122+ ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */
3123+ ctl_status_2.s.bar2_enb = 1;
3124+ ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */
3125+ ctl_status_2.s.bar2_esx = 1;
3126+ ctl_status_2.s.pmo_amod = 1; /* Round robin priority */
3127+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
3128+ /* BAR1 hole */
3129+ ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
3130+ ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
3131+ ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
3132+ ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
3133+ ctl_status_2.s.bb1 = 1; /* BAR1 is big */
3134+ ctl_status_2.s.bb0 = 1; /* BAR0 is big */
3135+ }
3136+
3137+ octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
3138+ udelay(2000); /* Wait 2 ms before doing PCI reads */
3139+
3140+ ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
3141+ pr_notice("PCI Status: %s %s-bit\n",
3142+ ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
3143+ ctl_status_2.s.ap_64ad ? "64" : "32");
3144+
3145+ if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
3146+ union cvmx_pci_cnt_reg cnt_reg_start;
3147+ union cvmx_pci_cnt_reg cnt_reg_end;
3148+ unsigned long cycles, pci_clock;
3149+
3150+ cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
3151+ cycles = read_c0_cvmcount();
3152+ udelay(1000);
3153+ cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
3154+ cycles = read_c0_cvmcount() - cycles;
3155+ pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
3156+ (cycles / (mips_hpt_frequency / 1000000));
3157+ pr_notice("PCI Clock: %lu MHz\n", pci_clock);
3158+ }
3159+
3160+ /*
3161+ * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
3162+ * in PCI-X mode to allow four oustanding splits. Otherwise,
3163+ * should not change from its reset value. Don't write PCI_CFG19
3164+ * in PCI mode (0x82000001 reset value), write it to 0x82000004
3165+ * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
3166+ * MRBCM -> must be one.
3167+ */
3168+ if (ctl_status_2.s.ap_pcix) {
3169+ cfg19.u32 = 0;
3170+ /*
3171+ * Target Delayed/Split request outstanding maximum
3172+ * count. [1..31] and 0=32. NOTE: If the user
3173+ * programs these bits beyond the Designed Maximum
3174+ * outstanding count, then the designed maximum table
3175+ * depth will be used instead. No additional
3176+ * Deferred/Split transactions will be accepted if
3177+ * this outstanding maximum count is
3178+ * reached. Furthermore, no additional deferred/split
3179+ * transactions will be accepted if the I/O delay/ I/O
3180+ * Split Request outstanding maximum is reached.
3181+ */
3182+ cfg19.s.tdomc = 4;
3183+ /*
3184+ * Master Deferred Read Request Outstanding Max Count
3185+ * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
3186+ * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
3187+ * 5 2 110 6 3 111 7 3 For example, if these bits are
3188+ * programmed to 100, the core can support 2 DAC
3189+ * cycles, 4 SAC cycles or a combination of 1 DAC and
3190+ * 2 SAC cycles. NOTE: For the PCI-X maximum
3191+ * outstanding split transactions, refer to
3192+ * CRE0[22:20].
3193+ */
3194+ cfg19.s.mdrrmc = 2;
3195+ /*
3196+ * Master Request (Memory Read) Byte Count/Byte Enable
3197+ * select. 0 = Byte Enables valid. In PCI mode, a
3198+ * burst transaction cannot be performed using Memory
3199+ * Read command=4?h6. 1 = DWORD Byte Count valid
3200+ * (default). In PCI Mode, the memory read byte
3201+ * enables are automatically generated by the
3202+ * core. Note: N3 Master Request transaction sizes are
3203+ * always determined through the
3204+ * am_attr[<35:32>|<7:0>] field.
3205+ */
3206+ cfg19.s.mrbcm = 1;
3207+ octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
3208+ }
3209+
3210+
3211+ cfg01.u32 = 0;
3212+ cfg01.s.msae = 1; /* Memory Space Access Enable */
3213+ cfg01.s.me = 1; /* Master Enable */
3214+ cfg01.s.pee = 1; /* PERR# Enable */
3215+ cfg01.s.see = 1; /* System Error Enable */
3216+ cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */
3217+
3218+ octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
3219+
3220+#ifdef USE_OCTEON_INTERNAL_ARBITER
3221+ /*
3222+ * When OCTEON is a PCI host, most systems will use OCTEON's
3223+ * internal arbiter, so must enable it before any PCI/PCI-X
3224+ * traffic can occur.
3225+ */
3226+ {
3227+ union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
3228+
3229+ pci_int_arb_cfg.u64 = 0;
3230+ pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
3231+ cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
3232+ }
3233+#endif /* USE_OCTEON_INTERNAL_ARBITER */
3234+
3235+ /*
3236+ * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
3237+ * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
3238+ * 1..7.
3239+ */
3240+ cfg16.u32 = 0;
3241+ cfg16.s.mltd = 1; /* Master Latency Timer Disable */
3242+ octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
3243+
3244+ /*
3245+ * Should be written to 0x4ff00. MTTV -> must be zero.
3246+ * FLUSH -> must be 1. MRV -> should be 0xFF.
3247+ */
3248+ cfg22.u32 = 0;
3249+ /* Master Retry Value [1..255] and 0=infinite */
3250+ cfg22.s.mrv = 0xff;
3251+ /*
3252+ * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
3253+ * N3K operation.
3254+ */
3255+ cfg22.s.flush = 1;
3256+ octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
3257+
3258+ /*
3259+ * MOST Indicates the maximum number of outstanding splits (in -1
3260+ * notation) when OCTEON is in PCI-X mode. PCI-X performance is
3261+ * affected by the MOST selection. Should generally be written
3262+ * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
3263+ * depending on the desired MOST of 3, 2, 1, or 0, respectively.
3264+ */
3265+ cfg56.u32 = 0;
3266+ cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */
3267+ cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */
3268+ cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */
3269+ cfg56.s.roe = 1; /* Relaxed Ordering Enable */
3270+ cfg56.s.mmbc = 1; /* Maximum Memory Byte Count
3271+ [0=512B,1=1024B,2=2048B,3=4096B] */
3272+ cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1
3273+ .. 7=32] */
3274+
3275+ octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
3276+
3277+ /*
3278+ * Affects PCI performance when OCTEON services reads to its
3279+ * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
3280+ * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
3281+ * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
3282+ * these values need to be changed so they won't possibly prefetch off
3283+ * of the end of memory if PCI is DMAing a buffer at the end of
3284+ * memory. Note that these values differ from their reset values.
3285+ */
3286+ octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
3287+ octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
3288+ octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
3289+}
3290+
3291+
3292+/**
3293+ * Initialize the Octeon PCI controller
3294+ *
3295+ * Returns
3296+ */
3297+static int __init octeon_pci_setup(void)
3298+{
3299+ union cvmx_npi_mem_access_subidx mem_access;
3300+ int index;
3301+
3302+ /* Only these chips have PCI */
3303+ if (octeon_has_feature(OCTEON_FEATURE_PCIE))
3304+ return 0;
3305+
3306+ /* Point pcibios_map_irq() to the PCI version of it */
3307+ octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
3308+
3309+ /* Only use the big bars on chips that support it */
3310+ if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
3311+ OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
3312+ OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
3313+ octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
3314+ else
3315+ octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
3316+
3317+ /* PCI I/O and PCI MEM values */
3318+ set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
3319+ ioport_resource.start = 0;
3320+ ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
3321+ if (!octeon_is_pci_host()) {
3322+ pr_notice("Not in host mode, PCI Controller not initialized\n");
3323+ return 0;
3324+ }
3325+
3326+ pr_notice("%s Octeon big bar support\n",
3327+ (octeon_dma_bar_type ==
3328+ OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
3329+
3330+ octeon_pci_initialize();
3331+
3332+ mem_access.u64 = 0;
3333+ mem_access.s.esr = 1; /* Endian-Swap on read. */
3334+ mem_access.s.esw = 1; /* Endian-Swap on write. */
3335+ mem_access.s.nsr = 0; /* No-Snoop on read. */
3336+ mem_access.s.nsw = 0; /* No-Snoop on write. */
3337+ mem_access.s.ror = 0; /* Relax Read on read. */
3338+ mem_access.s.row = 0; /* Relax Order on write. */
3339+ mem_access.s.ba = 0; /* PCI Address bits [63:36]. */
3340+ cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
3341+
3342+ /*
3343+ * Remap the Octeon BAR 2 above all 32 bit devices
3344+ * (0x8000000000ul). This is done here so it is remapped
3345+ * before the readl()'s below. We don't want BAR2 overlapping
3346+ * with BAR0/BAR1 during these reads.
3347+ */
3348+ octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
3349+ octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
3350+
3351+ /* Disable the BAR1 movable mappings */
3352+ for (index = 0; index < 32; index++)
3353+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
3354+
3355+ if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
3356+ /* Remap the Octeon BAR 0 to 0-2GB */
3357+ octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
3358+ octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
3359+
3360+ /*
3361+ * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
3362+ * BAR 1 hole).
3363+ */
3364+ octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
3365+ octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
3366+
3367+ /* Devices go after BAR1 */
3368+ octeon_pci_mem_resource.start =
3369+ OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
3370+ (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3371+ octeon_pci_mem_resource.end =
3372+ octeon_pci_mem_resource.start + (1ul << 30);
3373+ } else {
3374+ /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
3375+ octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
3376+ octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
3377+
3378+ /* Remap the Octeon BAR 1 to map 0-128MB */
3379+ octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
3380+ octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
3381+
3382+ /* Devices go after BAR0 */
3383+ octeon_pci_mem_resource.start =
3384+ OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
3385+ (4ul << 10);
3386+ octeon_pci_mem_resource.end =
3387+ octeon_pci_mem_resource.start + (1ul << 30);
3388+ }
3389+
3390+ register_pci_controller(&octeon_pci_controller);
3391+
3392+ /*
3393+ * Clear any errors that might be pending from before the bus
3394+ * was setup properly.
3395+ */
3396+ cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
3397+ return 0;
3398+}
3399+
3400+arch_initcall(octeon_pci_setup);
3401--- /dev/null
3402+++ b/arch/mips/cavium-octeon/pcie.c
3403@@ -0,0 +1,441 @@
3404+/*
3405+ * This file is subject to the terms and conditions of the GNU General Public
3406+ * License. See the file "COPYING" in the main directory of this archive
3407+ * for more details.
3408+ *
3409+ * Copyright (C) 2007, 2008 Cavium Networks
3410+ */
3411+#include <linux/kernel.h>
3412+#include <linux/init.h>
3413+#include <linux/pci.h>
3414+#include <linux/interrupt.h>
3415+#include <linux/time.h>
3416+#include <linux/delay.h>
3417+
3418+#include <asm/octeon/octeon.h>
3419+#include <asm/octeon/cvmx-pcie.h>
3420+#include <asm/octeon/cvmx-npei-defs.h>
3421+#include <asm/octeon/cvmx-pexp-defs.h>
3422+
3423+#include "pci-common.h"
3424+
3425+/**
3426+ * Map a PCI device to the appropriate interrupt line
3427+ *
3428+ * @param dev The Linux PCI device structure for the device to map
3429+ * @param slot The slot number for this device on __BUS 0__. Linux
3430+ * enumerates through all the bridges and figures out the
3431+ * slot on Bus 0 where this device eventually hooks to.
3432+ * @param pin The PCI interrupt pin read from the device, then swizzled
3433+ * as it goes through each bridge.
3434+ * @return Interrupt number for the device
3435+ */
3436+int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
3437+ u8 slot, u8 pin)
3438+{
3439+ /*
3440+ * The EBH5600 board with the PCI to PCIe bridge mistakenly
3441+ * wires the first slot for both device id 2 and interrupt
3442+ * A. According to the PCI spec, device id 2 should be C. The
3443+ * following kludge attempts to fix this.
3444+ */
3445+ if (strstr(octeon_board_type_string(), "EBH5600") &&
3446+ dev->bus && dev->bus->parent) {
3447+ /*
3448+ * Iterate all the way up the device chain and find
3449+ * the root bus.
3450+ */
3451+ while (dev->bus && dev->bus->parent)
3452+ dev = to_pci_dev(dev->bus->bridge);
3453+ /* If the root bus is number 0 and the PEX 8114 is the
3454+ * root, assume we are behind the miswired bus. We
3455+ * need to correct the swizzle level by two. Yuck.
3456+ */
3457+ if ((dev->bus->number == 0) &&
3458+ (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
3459+ /*
3460+ * The pin field is one based, not zero. We
3461+ * need to swizzle it by minus two.
3462+ */
3463+ pin = ((pin - 3) & 3) + 1;
3464+ }
3465+ }
3466+ /*
3467+ * The -1 is because pin starts with one, not zero. It might
3468+ * be that this equation needs to include the slot number, but
3469+ * I don't have hardware to check that against.
3470+ */
3471+ return pin - 1 + OCTEON_IRQ_PCI_INT0;
3472+}
3473+
3474+/**
3475+ * Read a value from configuration space
3476+ *
3477+ * @param bus
3478+ * @param devfn
3479+ * @param reg
3480+ * @param size
3481+ * @param val
3482+ * @return
3483+ */
3484+static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
3485+ unsigned int devfn, int reg, int size,
3486+ u32 *val)
3487+{
3488+ union octeon_cvmemctl cvmmemctl;
3489+ union octeon_cvmemctl cvmmemctl_save;
3490+ int bus_number = bus->number;
3491+
3492+ /*
3493+ * We need to force the bus number to be zero on the root
3494+ * bus. Linux numbers the 2nd root bus to start after all
3495+ * buses on root 0.
3496+ */
3497+ if (bus->parent == NULL)
3498+ bus_number = 0;
3499+
3500+ /*
3501+ * PCIe only has a single device connected to Octeon. It is
3502+ * always device ID 0. Don't bother doing reads for other
3503+ * device IDs on the first segment.
3504+ */
3505+ if ((bus_number == 0) && (devfn >> 3 != 0))
3506+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3507+
3508+ /*
3509+ * The following is a workaround for the CN57XX, CN56XX,
3510+ * CN55XX, and CN54XX errata with PCIe config reads from non
3511+ * existent devices. These chips will hang the PCIe link if a
3512+ * config read is performed that causes a UR response.
3513+ */
3514+ if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
3515+ OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
3516+ /*
3517+ * For our EBH5600 board, port 0 has a bridge with two
3518+ * PCI-X slots. We need a new special checks to make
3519+ * sure we only probe valid stuff. The PCIe->PCI-X
3520+ * bridge only respondes to device ID 0, function
3521+ * 0-1
3522+ */
3523+ if ((bus_number == 0) && (devfn >= 2))
3524+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3525+ /*
3526+ * The PCI-X slots are device ID 2,3. Choose one of
3527+ * the below "if" blocks based on what is plugged into
3528+ * the board.
3529+ */
3530+#if 1
3531+ /* Use this option if you aren't using either slot */
3532+ if (bus_number == 1)
3533+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3534+#elif 0
3535+ /*
3536+ * Use this option if you are using the first slot but
3537+ * not the second.
3538+ */
3539+ if ((bus_number == 1) && (devfn >> 3 != 2))
3540+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3541+#elif 0
3542+ /*
3543+ * Use this option if you are using the second slot
3544+ * but not the first.
3545+ */
3546+ if ((bus_number == 1) && (devfn >> 3 != 3))
3547+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3548+#elif 0
3549+ /* Use this opion if you are using both slots */
3550+ if ((bus_number == 1) &&
3551+ !((devfn == (2 << 3)) || (devfn == (3 << 3))))
3552+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3553+#endif
3554+
3555+ /*
3556+ * The following #if gives a more complicated
3557+ * example. This is the required checks for running a
3558+ * Nitrox CN16XX-NHBX in the slot of the EBH5600. This
3559+ * card has a PLX PCIe bridge with four Nitrox PLX
3560+ * parts behind it.
3561+ */
3562+#if 0
3563+ /* PLX bridge with 4 ports */
3564+ if ((bus_number == 3) &&
3565+ !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
3566+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3567+ /* Nitrox behind PLX 1 */
3568+ if ((bus_number == 4) && (devfn >> 3 != 0))
3569+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3570+ /* Nitrox behind PLX 2 */
3571+ if ((bus_number == 5) && (devfn >> 3 != 0))
3572+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3573+ /* Nitrox behind PLX 3 */
3574+ if ((bus_number == 6) && (devfn >> 3 != 0))
3575+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3576+ /* Nitrox behind PLX 4 */
3577+ if ((bus_number == 7) && (devfn >> 3 != 0))
3578+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3579+#endif
3580+ /*
3581+ * Shorten the DID timeout so bus errors for PCIe
3582+ * config reads from non existent devices happen
3583+ * faster. This allows us to continue booting even if
3584+ * the above "if" checks are wrong. Once one of these
3585+ * errors happens, the PCIe port is dead.
3586+ */
3587+ cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
3588+ cvmmemctl.u64 = cvmmemctl_save.u64;
3589+ cvmmemctl.s.didtto = 2;
3590+ __write_64bit_c0_register($11, 7, cvmmemctl.u64);
3591+ }
3592+
3593+ switch (size) {
3594+ case 4:
3595+ *val = cvmx_pcie_config_read32(pcie_port, bus_number,
3596+ devfn >> 3, devfn & 0x7, reg);
3597+ break;
3598+ case 2:
3599+ *val = cvmx_pcie_config_read16(pcie_port, bus_number,
3600+ devfn >> 3, devfn & 0x7, reg);
3601+ break;
3602+ case 1:
3603+ *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
3604+ devfn & 0x7, reg);
3605+ break;
3606+ default:
3607+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3608+ }
3609+
3610+ if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
3611+ OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
3612+ __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
3613+ return PCIBIOS_SUCCESSFUL;
3614+}
3615+
3616+static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
3617+ int reg, int size, u32 *val)
3618+{
3619+ return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
3620+}
3621+
3622+static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
3623+ int reg, int size, u32 *val)
3624+{
3625+ return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
3626+}
3627+
3628+
3629+
3630+/**
3631+ * Write a value to PCI configuration space
3632+ *
3633+ * @param bus
3634+ * @param devfn
3635+ * @param reg
3636+ * @param size
3637+ * @param val
3638+ * @return
3639+ */
3640+static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
3641+ unsigned int devfn, int reg,
3642+ int size, u32 val)
3643+{
3644+ int bus_number = bus->number;
3645+ /*
3646+ * We need to force the bus number to be zero on the root
3647+ * bus. Linux numbers the 2nd root bus to start after all
3648+ * busses on root 0.
3649+ */
3650+ if (bus->parent == NULL)
3651+ bus_number = 0;
3652+
3653+ switch (size) {
3654+ case 4:
3655+ cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
3656+ devfn & 0x7, reg, val);
3657+ return PCIBIOS_SUCCESSFUL;
3658+ case 2:
3659+ cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
3660+ devfn & 0x7, reg, val);
3661+ return PCIBIOS_SUCCESSFUL;
3662+ case 1:
3663+ cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
3664+ devfn & 0x7, reg, val);
3665+ return PCIBIOS_SUCCESSFUL;
3666+ }
3667+#if PCI_CONFIG_SPACE_DELAY
3668+ udelay(PCI_CONFIG_SPACE_DELAY);
3669+#endif
3670+ return PCIBIOS_FUNC_NOT_SUPPORTED;
3671+}
3672+
3673+static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
3674+ int reg, int size, u32 val)
3675+{
3676+ return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
3677+}
3678+
3679+static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
3680+ int reg, int size, u32 val)
3681+{
3682+ return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
3683+}
3684+
3685+static struct pci_ops octeon_pcie0_ops = {
3686+ octeon_pcie0_read_config,
3687+ octeon_pcie0_write_config,
3688+};
3689+
3690+static struct resource octeon_pcie0_mem_resource = {
3691+ .name = "Octeon PCIe0 MEM",
3692+ .flags = IORESOURCE_MEM,
3693+};
3694+
3695+static struct resource octeon_pcie0_io_resource = {
3696+ .name = "Octeon PCIe0 IO",
3697+ .flags = IORESOURCE_IO,
3698+};
3699+
3700+static struct pci_controller octeon_pcie0_controller = {
3701+ .pci_ops = &octeon_pcie0_ops,
3702+ .mem_resource = &octeon_pcie0_mem_resource,
3703+ .io_resource = &octeon_pcie0_io_resource,
3704+};
3705+
3706+static struct pci_ops octeon_pcie1_ops = {
3707+ octeon_pcie1_read_config,
3708+ octeon_pcie1_write_config,
3709+};
3710+
3711+static struct resource octeon_pcie1_mem_resource = {
3712+ .name = "Octeon PCIe1 MEM",
3713+ .flags = IORESOURCE_MEM,
3714+};
3715+
3716+static struct resource octeon_pcie1_io_resource = {
3717+ .name = "Octeon PCIe1 IO",
3718+ .flags = IORESOURCE_IO,
3719+};
3720+
3721+static struct pci_controller octeon_pcie1_controller = {
3722+ .pci_ops = &octeon_pcie1_ops,
3723+ .mem_resource = &octeon_pcie1_mem_resource,
3724+ .io_resource = &octeon_pcie1_io_resource,
3725+};
3726+
3727+
3728+/**
3729+ * Initialize the Octeon PCIe controllers
3730+ *
3731+ * @return
3732+ */
3733+static int __init octeon_pcie_setup(void)
3734+{
3735+ union cvmx_npei_ctl_status npei_ctl_status;
3736+ int result;
3737+
3738+ /* These chips don't have PCIe */
3739+ if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
3740+ return 0;
3741+
3742+ /* Point pcibios_map_irq() to the PCIe version of it */
3743+ octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
3744+
3745+ /* Use the PCIe based DMA mappings */
3746+ octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
3747+
3748+ /*
3749+ * PCIe I/O range. It is based on port 0 but includes up until
3750+ * port 1's end.
3751+ */
3752+ set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
3753+ ioport_resource.start = 0;
3754+ ioport_resource.end =
3755+ cvmx_pcie_get_io_base_address(1) -
3756+ cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
3757+
3758+ npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
3759+ if (npei_ctl_status.s.host_mode) {
3760+ pr_notice("PCIe: Initializing port 0\n");
3761+ result = cvmx_pcie_rc_initialize(0);
3762+ if (result == 0) {
3763+ /* Memory offsets are physical addresses */
3764+ octeon_pcie0_controller.mem_offset =
3765+ cvmx_pcie_get_mem_base_address(0);
3766+ /* IO offsets are Mips virtual addresses */
3767+ octeon_pcie0_controller.io_map_base =
3768+ CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
3769+ (0));
3770+ octeon_pcie0_controller.io_offset = 0;
3771+ /*
3772+ * To keep things similar to PCI, we start
3773+ * device addresses at the same place as PCI
3774+ * uisng big bar support. This normally
3775+ * translates to 4GB-256MB, which is the same
3776+ * as most x86 PCs.
3777+ */
3778+ octeon_pcie0_controller.mem_resource->start =
3779+ cvmx_pcie_get_mem_base_address(0) +
3780+ (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3781+ octeon_pcie0_controller.mem_resource->end =
3782+ cvmx_pcie_get_mem_base_address(0) +
3783+ cvmx_pcie_get_mem_size(0) - 1;
3784+ /*
3785+ * Ports must be above 16KB for the ISA bus
3786+ * filtering in the PCI-X to PCI bridge.
3787+ */
3788+ octeon_pcie0_controller.io_resource->start = 4 << 10;
3789+ octeon_pcie0_controller.io_resource->end =
3790+ cvmx_pcie_get_io_size(0) - 1;
3791+ register_pci_controller(&octeon_pcie0_controller);
3792+ }
3793+ } else {
3794+ pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
3795+ }
3796+
3797+ /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
3798+ if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
3799+ union cvmx_npei_dbg_data npei_dbg_data;
3800+ npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
3801+ if (npei_dbg_data.cn52xx.qlm0_link_width)
3802+ return 0;
3803+ }
3804+
3805+ pr_notice("PCIe: Initializing port 1\n");
3806+ result = cvmx_pcie_rc_initialize(1);
3807+ if (result == 0) {
3808+ /* Memory offsets are physical addresses */
3809+ octeon_pcie1_controller.mem_offset =
3810+ cvmx_pcie_get_mem_base_address(1);
3811+ /* IO offsets are Mips virtual addresses */
3812+ octeon_pcie1_controller.io_map_base =
3813+ CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
3814+ octeon_pcie1_controller.io_offset =
3815+ cvmx_pcie_get_io_base_address(1) -
3816+ cvmx_pcie_get_io_base_address(0);
3817+ /*
3818+ * To keep things similar to PCI, we start device
3819+ * addresses at the same place as PCI uisng big bar
3820+ * support. This normally translates to 4GB-256MB,
3821+ * which is the same as most x86 PCs.
3822+ */
3823+ octeon_pcie1_controller.mem_resource->start =
3824+ cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
3825+ (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3826+ octeon_pcie1_controller.mem_resource->end =
3827+ cvmx_pcie_get_mem_base_address(1) +
3828+ cvmx_pcie_get_mem_size(1) - 1;
3829+ /*
3830+ * Ports must be above 16KB for the ISA bus filtering
3831+ * in the PCI-X to PCI bridge.
3832+ */
3833+ octeon_pcie1_controller.io_resource->start =
3834+ cvmx_pcie_get_io_base_address(1) -
3835+ cvmx_pcie_get_io_base_address(0);
3836+ octeon_pcie1_controller.io_resource->end =
3837+ octeon_pcie1_controller.io_resource->start +
3838+ cvmx_pcie_get_io_size(1) - 1;
3839+ register_pci_controller(&octeon_pcie1_controller);
3840+ }
3841+ return 0;
3842+}
3843+
3844+arch_initcall(octeon_pcie_setup);
3845--- a/arch/mips/include/asm/octeon/cvmx-asm.h
3846+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
3847@@ -119,7 +119,8 @@
3848     asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3849 #define CVMX_DPOP(result, input) \
3850     asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3851-
3852+#define CVMX_CLZ(result, input) \
3853+ asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3854 /* some new cop0-like stuff */
3855 #define CVMX_RDHWR(result, regstr) \
3856     asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
3857--- /dev/null
3858+++ b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
3859@@ -0,0 +1,92 @@
3860+/***********************license start***************
3861+ * Author: Cavium Networks
3862+ *
3863+ * Contact: support@caviumnetworks.com
3864+ * This file is part of the OCTEON SDK
3865+ *
3866+ * Copyright (c) 2003-2008 Cavium Networks
3867+ *
3868+ * This file is free software; you can redistribute it and/or modify
3869+ * it under the terms of the GNU General Public License, Version 2, as
3870+ * published by the Free Software Foundation.
3871+ *
3872+ * This file is distributed in the hope that it will be useful, but
3873+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
3874+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
3875+ * NONINFRINGEMENT. See the GNU General Public License for more
3876+ * details.
3877+ *
3878+ * You should have received a copy of the GNU General Public License
3879+ * along with this file; if not, write to the Free Software
3880+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
3881+ * or visit http://www.gnu.org/licenses/.
3882+ *
3883+ * This file may also be available under a different license from Cavium.
3884+ * Contact Cavium Networks for more information
3885+ ***********************license end**************************************/
3886+
3887+/**
3888+ * @file
3889+ *
3890+ * Fixes and workaround for Octeon chip errata. This file
3891+ * contains functions called by cvmx-helper to workaround known
3892+ * chip errata. For the most part, code doesn't need to call
3893+ * these functions directly.
3894+ *
3895+ */
3896+#ifndef __CVMX_HELPER_ERRATA_H__
3897+#define __CVMX_HELPER_ERRATA_H__
3898+
3899+
3900+#include "cvmx-wqe.h"
3901+
3902+/**
3903+ * @INTERNAL
3904+ * Function to adjust internal IPD pointer alignments
3905+ *
3906+ * Returns 0 on success
3907+ * !0 on failure
3908+ */
3909+extern int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);
3910+
3911+/**
3912+ * @INTERNAL
3913+ * Workaround ASX setup errata with CN38XX pass1
3914+ *
3915+ * @interface: Interface to setup
3916+ * @port: Port to setup (0..3)
3917+ * @cpu_clock_hz:
3918+ * Chip frequency in Hertz
3919+ *
3920+ * Returns Zero on success, negative on failure
3921+ */
3922+extern int __cvmx_helper_errata_asx_pass1(int interface, int port,
3923+ int cpu_clock_hz);
3924+
3925+/**
3926+ * This function needs to be called on all Octeon chips with
3927+ * errata PKI-100.
3928+ *
3929+ * The Size field is 8 too large in WQE and next pointers
3930+ *
3931+ * The Size field generated by IPD is 8 larger than it should
3932+ * be. The Size field is <55:40> of both:
3933+ * - WORD3 in the work queue entry, and
3934+ * - the next buffer pointer (which precedes the packet data
3935+ * in each buffer).
3936+ *
3937+ * @work: Work queue entry to fix
3938+ * Returns Zero on success. Negative on failure
3939+ */
3940+extern int cvmx_helper_fix_ipd_packet_chain(struct cvmx_wqe *work);
3941+
3942+/**
3943+ * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
3944+ * 1 doesn't work properly. The following code disables 2nd order
3945+ * CDR for the specified QLM.
3946+ *
3947+ * @qlm: QLM to disable 2nd order CDR for.
3948+ */
3949+extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
3950+
3951+#endif
3952--- /dev/null
3953+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
3954@@ -0,0 +1,266 @@
3955+/***********************license start***************
3956+ * Author: Cavium Networks
3957+ *
3958+ * Contact: support@caviumnetworks.com
3959+ * This file is part of the OCTEON SDK
3960+ *
3961+ * Copyright (c) 2003-2008 Cavium Networks
3962+ *
3963+ * This file is free software; you can redistribute it and/or modify
3964+ * it under the terms of the GNU General Public License, Version 2, as
3965+ * published by the Free Software Foundation.
3966+ *
3967+ * This file is distributed in the hope that it will be useful, but
3968+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
3969+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
3970+ * NONINFRINGEMENT. See the GNU General Public License for more
3971+ * details.
3972+ *
3973+ * You should have received a copy of the GNU General Public License
3974+ * along with this file; if not, write to the Free Software
3975+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
3976+ * or visit http://www.gnu.org/licenses/.
3977+ *
3978+ * This file may also be available under a different license from Cavium.
3979+ * Contact Cavium Networks for more information
3980+ ***********************license end**************************************/
3981+
3982+/**
3983+ *
3984+ * Small helper utilities.
3985+ *
3986+ */
3987+
3988+#ifndef __CVMX_HELPER_UTIL_H__
3989+#define __CVMX_HELPER_UTIL_H__
3990+
3991+#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
3992+
3993+/**
3994+ * Convert a interface mode into a human readable string
3995+ *
3996+ * @mode: Mode to convert
3997+ *
3998+ * Returns String
3999+ */
4000+extern const char
4001+ *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
4002+
4003+/**
4004+ * Debug routine to dump the packet structure to the console
4005+ *
4006+ * @work: Work queue entry containing the packet to dump
4007+ * Returns
4008+ */
4009+extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
4010+
4011+/**
4012+ * Setup Random Early Drop on a specific input queue
4013+ *
4014+ * @queue: Input queue to setup RED on (0-7)
4015+ * @pass_thresh:
4016+ * Packets will begin slowly dropping when there are less than
4017+ * this many packet buffers free in FPA 0.
4018+ * @drop_thresh:
4019+ * All incomming packets will be dropped when there are less
4020+ * than this many free packet buffers in FPA 0.
4021+ * Returns Zero on success. Negative on failure
4022+ */
4023+extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
4024+ int drop_thresh);
4025+
4026+/**
4027+ * Setup Random Early Drop to automatically begin dropping packets.
4028+ *
4029+ * @pass_thresh:
4030+ * Packets will begin slowly dropping when there are less than
4031+ * this many packet buffers free in FPA 0.
4032+ * @drop_thresh:
4033+ * All incomming packets will be dropped when there are less
4034+ * than this many free packet buffers in FPA 0.
4035+ * Returns Zero on success. Negative on failure
4036+ */
4037+extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
4038+
4039+/**
4040+ * Get the version of the CVMX libraries.
4041+ *
4042+ * Returns Version string. Note this buffer is allocated statically
4043+ * and will be shared by all callers.
4044+ */
4045+extern const char *cvmx_helper_get_version(void);
4046+
4047+/**
4048+ * @INTERNAL
4049+ * Setup the common GMX settings that determine the number of
4050+ * ports. These setting apply to almost all configurations of all
4051+ * chips.
4052+ *
4053+ * @interface: Interface to configure
4054+ * @num_ports: Number of ports on the interface
4055+ *
4056+ * Returns Zero on success, negative on failure
4057+ */
4058+extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
4059+
4060+/**
4061+ * Returns the IPD/PKO port number for a port on the given
4062+ * interface.
4063+ *
4064+ * @interface: Interface to use
4065+ * @port: Port on the interface
4066+ *
4067+ * Returns IPD/PKO port number
4068+ */
4069+extern int cvmx_helper_get_ipd_port(int interface, int port);
4070+
4071+/**
4072+ * Returns the IPD/PKO port number for the first port on the given
4073+ * interface.
4074+ *
4075+ * @interface: Interface to use
4076+ *
4077+ * Returns IPD/PKO port number
4078+ */
4079+static inline int cvmx_helper_get_first_ipd_port(int interface)
4080+{
4081+ return cvmx_helper_get_ipd_port(interface, 0);
4082+}
4083+
4084+/**
4085+ * Returns the IPD/PKO port number for the last port on the given
4086+ * interface.
4087+ *
4088+ * @interface: Interface to use
4089+ *
4090+ * Returns IPD/PKO port number
4091+ */
4092+static inline int cvmx_helper_get_last_ipd_port(int interface)
4093+{
4094+ extern int cvmx_helper_ports_on_interface(int interface);
4095+
4096+ return cvmx_helper_get_first_ipd_port(interface) +
4097+ cvmx_helper_ports_on_interface(interface) - 1;
4098+}
4099+
4100+/**
4101+ * Free the packet buffers contained in a work queue entry.
4102+ * The work queue entry is not freed.
4103+ *
4104+ * @work: Work queue entry with packet to free
4105+ */
4106+static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
4107+{
4108+ uint64_t number_buffers;
4109+ cvmx_buf_ptr_t buffer_ptr;
4110+ cvmx_buf_ptr_t next_buffer_ptr;
4111+ uint64_t start_of_buffer;
4112+
4113+ number_buffers = work->word2.s.bufs;
4114+ if (number_buffers == 0)
4115+ return;
4116+ buffer_ptr = work->packet_ptr;
4117+
4118+ /*
4119+ * Since the number of buffers is not zero, we know this is
4120+ * not a dynamic short packet. We need to check if it is a
4121+ * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is
4122+ * true, we need to free all buffers except for the first
4123+ * one. The caller doesn't expect their WQE pointer to be
4124+ * freed.
4125+ */
4126+ start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
4127+ if (cvmx_ptr_to_phys(work) == start_of_buffer) {
4128+ next_buffer_ptr =
4129+ *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
4130+ buffer_ptr = next_buffer_ptr;
4131+ number_buffers--;
4132+ }
4133+
4134+ while (number_buffers--) {
4135+ /*
4136+ * Remember the back pointer is in cache lines, not
4137+ * 64bit words.
4138+ */
4139+ start_of_buffer =
4140+ ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
4141+ /*
4142+ * Read pointer to next buffer before we free the
4143+ * current buffer.
4144+ */
4145+ next_buffer_ptr =
4146+ *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
4147+ cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer),
4148+ buffer_ptr.s.pool, 0);
4149+ buffer_ptr = next_buffer_ptr;
4150+ }
4151+}
4152+
4153+#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
4154+
4155+/**
4156+ * Returns the interface number for an IPD/PKO port number.
4157+ *
4158+ * @ipd_port: IPD/PKO port number
4159+ *
4160+ * Returns Interface number
4161+ */
4162+extern int cvmx_helper_get_interface_num(int ipd_port);
4163+
4164+/**
4165+ * Returns the interface index number for an IPD/PKO port
4166+ * number.
4167+ *
4168+ * @ipd_port: IPD/PKO port number
4169+ *
4170+ * Returns Interface index number
4171+ */
4172+extern int cvmx_helper_get_interface_index_num(int ipd_port);
4173+
4174+/**
4175+ * Initialize the internal QLM JTAG logic to allow programming
4176+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
4177+ * These functions should only be used at the direction of Cavium
4178+ * Networks. Programming incorrect values into the JTAG chain
4179+ * can cause chip damage.
4180+ */
4181+extern void cvmx_helper_qlm_jtag_init(void);
4182+
4183+/**
4184+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
4185+ * into the MSB and out the LSB, so you should shift in the low
4186+ * order bits followed by the high order bits. The JTAG chain is
4187+ * 4 * 268 bits long, or 1072.
4188+ *
4189+ * @qlm: QLM to shift value into
4190+ * @bits: Number of bits to shift in (1-32).
4191+ * @data: Data to shift in. Bit 0 enters the chain first, followed by
4192+ * bit 1, etc.
4193+ *
4194+ * Returns The low order bits of the JTAG chain that shifted out of the
4195+ * circle.
4196+ */
4197+extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
4198+
4199+/**
4200+ * Shift long sequences of zeros into the QLM JTAG chain. It is
4201+ * common to need to shift more than 32 bits of zeros into the
4202+ * chain. This function is a convience wrapper around
4203+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
4204+ * zeros at a time.
4205+ *
4206+ * @qlm: QLM to shift zeros into
4207+ * @bits:
4208+ */
4209+extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
4210+
4211+/**
4212+ * Program the QLM JTAG chain into all lanes of the QLM. You must
4213+ * have already shifted in 268*4, or 1072 bits into the JTAG
4214+ * chain. Updating invalid values can possibly cause chip damage.
4215+ *
4216+ * @qlm: QLM to program
4217+ */
4218+extern void cvmx_helper_qlm_jtag_update(int qlm);
4219+
4220+#endif /* __CVMX_HELPER_H__ */
4221--- a/arch/mips/include/asm/octeon/cvmx-packet.h
4222+++ b/arch/mips/include/asm/octeon/cvmx-packet.h
4223@@ -25,7 +25,8 @@
4224  * Contact Cavium Networks for more information
4225  ***********************license end**************************************/
4226 
4227-/*
4228+/**
4229+ *
4230  * Packet buffer defines.
4231  */
4232 
4233@@ -39,18 +40,23 @@ union cvmx_buf_ptr {
4234     void *ptr;
4235     uint64_t u64;
4236     struct {
4237- /* if set, invert the "free" pick of the overall
4238+ /*
4239+ * If set, invert the "free" pick of the overall
4240          * packet. HW always sets this bit to 0 on inbound
4241- * packet */
4242+ * packet.
4243+ */
4244         uint64_t i:1;
4245 
4246- /* Indicates the amount to back up to get to the
4247+ /*
4248+ * Indicates the amount to back up to get to the
4249          * buffer start in cache lines. In most cases this is
4250          * less than one complete cache line, so the value is
4251- * zero */
4252+ * zero.
4253+ */
4254         uint64_t back:4;
4255         /* The pool that the buffer came from / goes to */
4256         uint64_t pool:3;
4257+
4258         /* The size of the segment pointed to by addr (in bytes) */
4259         uint64_t size:16;
4260         /* Pointer to the first byte of the data, NOT buffer */
4261--- /dev/null
4262+++ b/arch/mips/include/asm/octeon/cvmx-pcie.h
4263@@ -0,0 +1,284 @@
4264+/***********************license start***************
4265+ * Author: Cavium Networks
4266+ *
4267+ * Contact: support@caviumnetworks.com
4268+ * This file is part of the OCTEON SDK
4269+ *
4270+ * Copyright (c) 2003-2008 Cavium Networks
4271+ *
4272+ * This file is free software; you can redistribute it and/or modify
4273+ * it under the terms of the GNU General Public License, Version 2, as
4274+ * published by the Free Software Foundation.
4275+ *
4276+ * This file is distributed in the hope that it will be useful, but
4277+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4278+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4279+ * NONINFRINGEMENT. See the GNU General Public License for more
4280+ * details.
4281+ *
4282+ * You should have received a copy of the GNU General Public License
4283+ * along with this file; if not, write to the Free Software
4284+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4285+ * or visit http://www.gnu.org/licenses/.
4286+ *
4287+ * This file may also be available under a different license from Cavium.
4288+ * Contact Cavium Networks for more information
4289+ ***********************license end**************************************/
4290+
4291+/**
4292+ * @file
4293+ *
4294+ * Interface to PCIe as a host(RC) or target(EP)
4295+ *
4296+ */
4297+
4298+#ifndef __CVMX_PCIE_H__
4299+#define __CVMX_PCIE_H__
4300+
4301+union cvmx_pcie_address {
4302+ uint64_t u64;
4303+ struct {
4304+ uint64_t upper:2; /* Normally 2 for XKPHYS */
4305+ uint64_t reserved_49_61:13; /* Must be zero */
4306+ uint64_t io:1; /* 1 for IO space access */
4307+ uint64_t did:5; /* PCIe DID = 3 */
4308+ uint64_t subdid:3; /* PCIe SubDID = 1 */
4309+ uint64_t reserved_36_39:4; /* Must be zero */
4310+ uint64_t es:2; /* Endian swap = 1 */
4311+ uint64_t port:2; /* PCIe port 0,1 */
4312+ uint64_t reserved_29_31:3; /* Must be zero */
4313+ /*
4314+ * Selects the type of the configuration request (0 = type 0,
4315+ * 1 = type 1).
4316+ */
4317+ uint64_t ty:1;
4318+ /* Target bus number sent in the ID in the request. */
4319+ uint64_t bus:8;
4320+ /*
4321+ * Target device number sent in the ID in the
4322+ * request. Note that Dev must be zero for type 0
4323+ * configuration requests.
4324+ */
4325+ uint64_t dev:5;
4326+ /* Target function number sent in the ID in the request. */
4327+ uint64_t func:3;
4328+ /*
4329+ * Selects a register in the configuration space of
4330+ * the target.
4331+ */
4332+ uint64_t reg:12;
4333+ } config;
4334+ struct {
4335+ uint64_t upper:2; /* Normally 2 for XKPHYS */
4336+ uint64_t reserved_49_61:13; /* Must be zero */
4337+ uint64_t io:1; /* 1 for IO space access */
4338+ uint64_t did:5; /* PCIe DID = 3 */
4339+ uint64_t subdid:3; /* PCIe SubDID = 2 */
4340+ uint64_t reserved_36_39:4; /* Must be zero */
4341+ uint64_t es:2; /* Endian swap = 1 */
4342+ uint64_t port:2; /* PCIe port 0,1 */
4343+ uint64_t address:32; /* PCIe IO address */
4344+ } io;
4345+ struct {
4346+ uint64_t upper:2; /* Normally 2 for XKPHYS */
4347+ uint64_t reserved_49_61:13; /* Must be zero */
4348+ uint64_t io:1; /* 1 for IO space access */
4349+ uint64_t did:5; /* PCIe DID = 3 */
4350+ uint64_t subdid:3; /* PCIe SubDID = 3-6 */
4351+ uint64_t reserved_36_39:4; /* Must be zero */
4352+ uint64_t address:36; /* PCIe Mem address */
4353+ } mem;
4354+};
4355+
4356+/**
4357+ * Return the Core virtual base address for PCIe IO access. IOs are
4358+ * read/written as an offset from this address.
4359+ *
4360+ * @pcie_port: PCIe port the IO is for
4361+ *
4362+ * Returns 64bit Octeon IO base address for read/write
4363+ */
4364+uint64_t cvmx_pcie_get_io_base_address(int pcie_port);
4365+
4366+/**
4367+ * Size of the IO address region returned at address
4368+ * cvmx_pcie_get_io_base_address()
4369+ *
4370+ * @pcie_port: PCIe port the IO is for
4371+ *
4372+ * Returns Size of the IO window
4373+ */
4374+uint64_t cvmx_pcie_get_io_size(int pcie_port);
4375+
4376+/**
4377+ * Return the Core virtual base address for PCIe MEM access. Memory is
4378+ * read/written as an offset from this address.
4379+ *
4380+ * @pcie_port: PCIe port the IO is for
4381+ *
4382+ * Returns 64bit Octeon IO base address for read/write
4383+ */
4384+uint64_t cvmx_pcie_get_mem_base_address(int pcie_port);
4385+
4386+/**
4387+ * Size of the Mem address region returned at address
4388+ * cvmx_pcie_get_mem_base_address()
4389+ *
4390+ * @pcie_port: PCIe port the IO is for
4391+ *
4392+ * Returns Size of the Mem window
4393+ */
4394+uint64_t cvmx_pcie_get_mem_size(int pcie_port);
4395+
4396+/**
4397+ * Initialize a PCIe port for use in host(RC) mode. It doesn't
4398+ * enumerate the bus.
4399+ *
4400+ * @pcie_port: PCIe port to initialize
4401+ *
4402+ * Returns Zero on success
4403+ */
4404+int cvmx_pcie_rc_initialize(int pcie_port);
4405+
4406+/**
4407+ * Shutdown a PCIe port and put it in reset
4408+ *
4409+ * @pcie_port: PCIe port to shutdown
4410+ *
4411+ * Returns Zero on success
4412+ */
4413+int cvmx_pcie_rc_shutdown(int pcie_port);
4414+
4415+/**
4416+ * Read 8bits from a Device's config space
4417+ *
4418+ * @pcie_port: PCIe port the device is on
4419+ * @bus: Sub bus
4420+ * @dev: Device ID
4421+ * @fn: Device sub function
4422+ * @reg: Register to access
4423+ *
4424+ * Returns Result of the read
4425+ */
4426+uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn,
4427+ int reg);
4428+
4429+/**
4430+ * Read 16bits from a Device's config space
4431+ *
4432+ * @pcie_port: PCIe port the device is on
4433+ * @bus: Sub bus
4434+ * @dev: Device ID
4435+ * @fn: Device sub function
4436+ * @reg: Register to access
4437+ *
4438+ * Returns Result of the read
4439+ */
4440+uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn,
4441+ int reg);
4442+
4443+/**
4444+ * Read 32bits from a Device's config space
4445+ *
4446+ * @pcie_port: PCIe port the device is on
4447+ * @bus: Sub bus
4448+ * @dev: Device ID
4449+ * @fn: Device sub function
4450+ * @reg: Register to access
4451+ *
4452+ * Returns Result of the read
4453+ */
4454+uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn,
4455+ int reg);
4456+
4457+/**
4458+ * Write 8bits to a Device's config space
4459+ *
4460+ * @pcie_port: PCIe port the device is on
4461+ * @bus: Sub bus
4462+ * @dev: Device ID
4463+ * @fn: Device sub function
4464+ * @reg: Register to access
4465+ * @val: Value to write
4466+ */
4467+void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg,
4468+ uint8_t val);
4469+
4470+/**
4471+ * Write 16bits to a Device's config space
4472+ *
4473+ * @pcie_port: PCIe port the device is on
4474+ * @bus: Sub bus
4475+ * @dev: Device ID
4476+ * @fn: Device sub function
4477+ * @reg: Register to access
4478+ * @val: Value to write
4479+ */
4480+void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg,
4481+ uint16_t val);
4482+
4483+/**
4484+ * Write 32bits to a Device's config space
4485+ *
4486+ * @pcie_port: PCIe port the device is on
4487+ * @bus: Sub bus
4488+ * @dev: Device ID
4489+ * @fn: Device sub function
4490+ * @reg: Register to access
4491+ * @val: Value to write
4492+ */
4493+void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg,
4494+ uint32_t val);
4495+
4496+/**
4497+ * Read a PCIe config space register indirectly. This is used for
4498+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
4499+ *
4500+ * @pcie_port: PCIe port to read from
4501+ * @cfg_offset: Address to read
4502+ *
4503+ * Returns Value read
4504+ */
4505+uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset);
4506+
4507+/**
4508+ * Write a PCIe config space register indirectly. This is used for
4509+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
4510+ *
4511+ * @pcie_port: PCIe port to write to
4512+ * @cfg_offset: Address to write
4513+ * @val: Value to write
4514+ */
4515+void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val);
4516+
4517+/**
4518+ * Write a 32bit value to the Octeon NPEI register space
4519+ *
4520+ * @address: Address to write to
4521+ * @val: Value to write
4522+ */
4523+static inline void cvmx_pcie_npei_write32(uint64_t address, uint32_t val)
4524+{
4525+ cvmx_write64_uint32(address ^ 4, val);
4526+ cvmx_read64_uint32(address ^ 4);
4527+}
4528+
4529+/**
4530+ * Read a 32bit value from the Octeon NPEI register space
4531+ *
4532+ * @address: Address to read
4533+ * Returns The result
4534+ */
4535+static inline uint32_t cvmx_pcie_npei_read32(uint64_t address)
4536+{
4537+ return cvmx_read64_uint32(address ^ 4);
4538+}
4539+
4540+/**
4541+ * Initialize a PCIe port for use in target(EP) mode.
4542+ *
4543+ * Returns Zero on success
4544+ */
4545+int cvmx_pcie_ep_initialize(void);
4546+
4547+#endif
4548--- /dev/null
4549+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
4550@@ -0,0 +1,422 @@
4551+/***********************license start***************
4552+ * Author: Cavium Networks
4553+ *
4554+ * Contact: support@caviumnetworks.com
4555+ * This file is part of the OCTEON SDK
4556+ *
4557+ * Copyright (c) 2003-2008 Cavium Networks
4558+ *
4559+ * This file is free software; you can redistribute it and/or modify
4560+ * it under the terms of the GNU General Public License, Version 2, as
4561+ * published by the Free Software Foundation.
4562+ *
4563+ * This file is distributed in the hope that it will be useful, but
4564+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4565+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4566+ * NONINFRINGEMENT. See the GNU General Public License for more
4567+ * details.
4568+ *
4569+ * You should have received a copy of the GNU General Public License
4570+ * along with this file; if not, write to the Free Software
4571+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4572+ * or visit http://www.gnu.org/licenses/.
4573+ *
4574+ * This file may also be available under a different license from Cavium.
4575+ * Contact Cavium Networks for more information
4576+ ***********************license end**************************************/
4577+
4578+/**
4579+ *
4580+ * This header file defines the work queue entry (wqe) data structure.
4581+ * Since this is a commonly used structure that depends on structures
4582+ * from several hardware blocks, those definitions have been placed
4583+ * in this file to create a single point of definition of the wqe
4584+ * format.
4585+ *
4586+ * Data structures are still named according to the block that they
4587+ * relate to.
4588+ *
4589+ */
4590+
4591+#ifndef __CVMX_WQE_H__
4592+#define __CVMX_WQE_H__
4593+
4594+#include "cvmx-packet.h"
4595+
4596+#define OCT_TAG_TYPE_STRING(x) ( \
4597+ { \
4598+ const char *r; \
4599+ switch (x) { \
4600+ case CVMX_POW_TAG_TYPE_ORDERED: \
4601+ r = "ORDERED"; \
4602+ break; \
4603+ case CVMX_POW_TAG_TYPE_ATOMIC: \
4604+ r = "ATOMIC"; \
4605+ break; \
4606+ case CVMX_POW_TAG_TYPE_NULL: \
4607+ r = "NULL"; \
4608+ break; \
4609+ default: \
4610+ r = "NULL_NULL"; \
4611+ break; \
4612+ } \
4613+ r; \
4614+ })
4615+
4616+/**
4617+ * HW decode / err_code in work queue entry
4618+ */
4619+union cvmx_pip_wqe_word2{
4620+ uint64_t u64;
4621+
4622+ /* Use this struct if the hardware determines that the packet is IP */
4623+ struct {
4624+ /* HW sets this to the number of buffers used by this packet */
4625+ uint64_t bufs:8;
4626+ /* HW sets to the number of L2 bytes prior to the IP */
4627+ uint64_t ip_offset:8;
4628+ /* Set to 1 if we found VLAN in the L2 */
4629+ uint64_t vlan_valid:1;
4630+ uint64_t unassigned:2;
4631+ /* HW sets to the VLAN CFI flag (valid when vlan_valid) */
4632+ uint64_t vlan_cfi:1;
4633+ /* HW sets to the VLAN_ID field (valid when vlan_valid) */
4634+ uint64_t vlan_id:12;
4635+
4636+ uint64_t unassigned2:12;
4637+ /* The packet needs to be decompressed */
4638+ uint64_t dec_ipcomp:1;
4639+ /* The packet is either TCP or UDP */
4640+ uint64_t tcp_or_udp:1;
4641+ /* The packet needs to be decrypted (ESP or AH) */
4642+ uint64_t dec_ipsec:1;
4643+ /* The packet is IPv6 */
4644+ uint64_t is_v6:1;
4645+
4646+ /*
4647+ * rcv_error, not_IP, IP_exc, is_frag, L4_error,
4648+ * software, etc.
4649+ */
4650+
4651+ /*
4652+ * Reserved for software use, hardware will clear on
4653+ * packet creation.
4654+ */
4655+ uint64_t software:1;
4656+ /* exceptional conditions below. */
4657+
4658+ /*
4659+ * The receive interface hardware detected an L4 error
4660+ * (only applies if !is_frag) (only applies if
4661+ * !rcv_error && !not_IP && !IP_exc && !is_frag)
4662+ * failure indicated in err_code below, decode:
4663+ *
4664+ * - 1 = Malformed L4
4665+ *
4666+ * - 2 = L4 Checksum Error: the L4 checksum value is
4667+ *
4668+ * - 3 = UDP Length Error: The UDP length field would
4669+ * make the UDP data longer than what remains in
4670+ * the IP packet (as defined by the IP header
4671+ * length field).
4672+ *
4673+ * - 4 = Bad L4 Port: either the source or destination
4674+ * TCP/UDP port is 0.
4675+ *
4676+ * - 8 = TCP FIN Only: the packet is TCP and only the
4677+ * FIN flag set.
4678+ *
4679+ * - 9 = TCP No Flags: the packet is TCP and no flags
4680+ * are set.
4681+ *
4682+ * - 10 = TCP FIN RST: the packet is TCP and both FIN
4683+ * and RST are set.
4684+ *
4685+ * - 11 = TCP SYN URG: the packet is TCP and both SYN
4686+ * and URG are set.
4687+ *
4688+ * - 12 = TCP SYN RST: the packet is TCP and both SYN
4689+ * and RST are set.
4690+ *
4691+ * - 13 = TCP SYN FIN: the packet is TCP and both SYN
4692+ * and FIN are set.
4693+ *
4694+ */
4695+ uint64_t L4_error:1;
4696+ /* Set if the packet is a fragment */
4697+ uint64_t is_frag:1;
4698+
4699+ /*
4700+ * The receive interface hardware detected an IP error
4701+ * / exception (only applies if !rcv_error && !not_IP)
4702+ * failure indicated in err_code below, decode:
4703+ *
4704+ * - 1 = Not IP: the IP version field is neither 4 nor
4705+ * 6.
4706+ *
4707+ * - 2 = IPv4 Header Checksum Error: the IPv4 header
4708+ * has a checksum violation.
4709+ *
4710+ * - 3 = IP Malformed Header: the packet is not long
4711+ * enough to contain the IP header.
4712+ *
4713+ * - 4 = IP Malformed: the packet is not long enough
4714+ * to contain the bytes indicated by the IP
4715+ * header. Pad is allowed.
4716+ *
4717+ * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
4718+ * Hop Count field are zero.
4719+ *
4720+ * - 6 = IP Options.
4721+ */
4722+ uint64_t IP_exc:1;
4723+ /*
4724+ * Set if the hardware determined that the packet is a
4725+ * broadcast.
4726+ */
4727+ uint64_t is_bcast:1;
4728+ /*
4729+ * Set if the hardware determined that the packet is a
4730+ * multi-cast.
4731+ */
4732+ uint64_t is_mcast:1;
4733+ /*
4734+ * Set if the packet may not be IP (must be zero in
4735+ * this case).
4736+ */
4737+ uint64_t not_IP:1;
4738+ /*
4739+ * The receive interface hardware detected a receive
4740+ * error (must be zero in this case)
4741+ *
4742+ * lower err_code = first-level descriptor of the work
4743+ *
4744+ * zero for packet submitted by hardware that isn't on
4745+ * the slow path.
4746+ */
4747+ uint64_t rcv_error:1;
4748+
4749+ /* Type is cvmx_pip_err_t */
4750+ uint64_t err_code:8;
4751+ } s;
4752+
4753+ /* Use this to get at the 16 vlan bits */
4754+ struct {
4755+ uint64_t unused1:16;
4756+ uint64_t vlan:16;
4757+ uint64_t unused2:32;
4758+ } svlan;
4759+
4760+ /*
4761+ * Use this struct if the hardware could not determine that
4762+ * the packet is ip.
4763+ */
4764+ struct {
4765+ /* HW sets this to the number of buffers used by this packet. */
4766+ uint64_t bufs:8;
4767+ uint64_t unused:8;
4768+ /* Set to 1 if we found VLAN in the L2. */
4769+ uint64_t vlan_valid:1;
4770+ uint64_t unassigned:2;
4771+ /* HW sets to the VLAN CFI flag (valid when vlan_valid). */
4772+ uint64_t vlan_cfi:1;
4773+ /* HW sets to the VLAN_ID field (valid when vlan_valid). */
4774+ uint64_t vlan_id:12;
4775+
4776+ uint64_t unassigned2:16;
4777+ /*
4778+ * Reserved for software use, hardware will clear on
4779+ * packet creation.
4780+ */
4781+ uint64_t software:1;
4782+ uint64_t unassigned3:1;
4783+ /* Set if the hardware determined that the packet is rarp. */
4784+ uint64_t is_rarp:1;
4785+ /* Set if the hardware determined that the packet is arp. */
4786+ uint64_t is_arp:1;
4787+ /*
4788+ * Set if the hardware determined that the packet is a
4789+ * broadcast.
4790+ */
4791+ uint64_t is_bcast:1;
4792+ /*
4793+ * Set if the hardware determined that the packet is a
4794+ * multi-cast.
4795+ */
4796+ uint64_t is_mcast:1;
4797+ /*
4798+ * Set if the packet may not be IP (must be one in
4799+ * this case).
4800+ */
4801+ uint64_t not_IP:1;
4802+ /*
4803+ * The receive interface hardware detected a receive
4804+ * error. Failure indicated in err_code below, decode:
4805+ *
4806+ * - 1 = partial error: a packet was partially
4807+ * received, but internal buffering / bandwidth
4808+ * was not adequate to receive the entire
4809+ * packet.
4810+ *
4811+ * - 2 = jabber error: the RGMII packet was too large
4812+ * and is truncated.
4813+ *
4814+ * - 3 = overrun error: the RGMII packet is longer
4815+ * than allowed and had an FCS error.
4816+ *
4817+ * - 4 = oversize error: the RGMII packet is longer
4818+ * than allowed.
4819+ *
4820+ * - 5 = alignment error: the RGMII packet is not an
4821+ * integer number of bytes and had an FCS error
4822+ * (100M and 10M only).
4823+ *
4824+ * - 6 = fragment error: the RGMII packet is shorter
4825+ * than allowed and had an FCS error.
4826+ *
4827+ * - 7 = GMX FCS error: the RGMII packet had an FCS
4828+ * error.
4829+ *
4830+ * - 8 = undersize error: the RGMII packet is shorter
4831+ * than allowed.
4832+ *
4833+ * - 9 = extend error: the RGMII packet had an extend
4834+ * error.
4835+ *
4836+ * - 10 = length mismatch error: the RGMII packet had
4837+ * a length that did not match the length field
4838+ * in the L2 HDR.
4839+ *
4840+ * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
4841+ * packet had one or more data reception errors
4842+ * (RXERR) or the SPI4 packet had one or more
4843+ * DIP4 errors.
4844+ *
4845+ * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
4846+ * packet was not large enough to cover the
4847+ * skipped bytes or the SPI4 packet was
4848+ * terminated with an About EOPS.
4849+ *
4850+ * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
4851+ * RGMII packet had a studder error (data not
4852+ * repeated - 10/100M only) or the SPI4 packet
4853+ * was sent to an NXA.
4854+ *
4855+ * - 16 = FCS error: a SPI4.2 packet had an FCS error.
4856+ *
4857+ * - 17 = Skip error: a packet was not large enough to
4858+ * cover the skipped bytes.
4859+ *
4860+ * - 18 = L2 header malformed: the packet is not long
4861+ * enough to contain the L2
4862+ */
4863+
4864+ /*
4865+ * lower err_code = first-level descriptor of the
4866+ * work.
4867+ *
4868+ * zero for packet submitted by hardware that isn't on
4869+ * the slow path.
4870+ */
4871+ uint64_t rcv_error:1;
4872+
4873+ /* Type is cvmx_pip_err_t (union, so can't use directly. */
4874+ uint64_t err_code:8;
4875+ } snoip;
4876+
4877+};
4878+
4879+/**
4880+ * Work queue entry format
4881+ *
4882+ * must be 8-byte aligned
4883+ */
4884+struct cvmx_wqe {
4885+
4886+ /*****************************************************************
4887+ * WORD 0
4888+ * HW WRITE: the following 64 bits are filled by HW when a packet arrives
4889+ */
4890+
4891+ /**
4892+ * raw chksum result generated by the HW
4893+ */
4894+ uint16_t hw_chksum;
4895+ /**
4896+ * Field unused by hardware - available for software
4897+ */
4898+ uint8_t unused;
4899+ /**
4900+ * Next pointer used by hardware for list maintenance.
4901+ * May be written/read by HW before the work queue
4902+ * entry is scheduled to a PP
4903+ * (Only 36 bits used in Octeon 1)
4904+ */
4905+ uint64_t next_ptr:40;
4906+
4907+ /*****************************************************************
4908+ * WORD 1
4909+ * HW WRITE: the following 64 bits are filled by HW when a packet arrives
4910+ */
4911+
4912+ /**
4913+ * HW sets to the total number of bytes in the packet
4914+ */
4915+ uint64_t len:16;
4916+ /**
4917+ * HW sets this to input physical port
4918+ */
4919+ uint64_t ipprt:6;
4920+
4921+ /**
4922+ * HW sets this to what it thought the priority of the input packet was
4923+ */
4924+ uint64_t qos:3;
4925+
4926+ /**
4927+ * the group that the work queue entry will be scheduled to
4928+ */
4929+ uint64_t grp:4;
4930+ /**
4931+ * the type of the tag (ORDERED, ATOMIC, NULL)
4932+ */
4933+ uint64_t tag_type:3;
4934+ /**
4935+ * the synchronization/ordering tag
4936+ */
4937+ uint64_t tag:32;
4938+
4939+ /**
4940+ * WORD 2 HW WRITE: the following 64-bits are filled in by
4941+ * hardware when a packet arrives This indicates a variety of
4942+ * status and error conditions.
4943+ */
4944+ union cvmx_pip_wqe_word2 word2;
4945+
4946+ /**
4947+ * Pointer to the first segment of the packet.
4948+ */
4949+ union cvmx_buf_ptr packet_ptr;
4950+
4951+ /**
4952+ * HW WRITE: octeon will fill in a programmable amount from the
4953+ * packet, up to (at most, but perhaps less) the amount
4954+ * needed to fill the work queue entry to 128 bytes
4955+ * If the packet is recognized to be IP, the hardware starts (except that
4956+ * the IPv4 header is padded for appropriate alignment) writing here where
4957+ * the IP header starts.
4958+ * If the packet is not recognized to be IP, the hardware starts writing
4959+ * the beginning of the packet here.
4960+ */
4961+ uint8_t packet_data[96];
4962+
4963+ /**
4964+ * If desired, SW can make the work Q entry any length. For the
4965+ * purposes of discussion here, Assume 128B always, as this is all that
4966+ * the hardware deals with.
4967+ *
4968+ */
4969+
4970+} CVMX_CACHE_LINE_ALIGNED;
4971+
4972+#endif /* __CVMX_WQE_H__ */
4973--- a/arch/mips/include/asm/octeon/cvmx.h
4974+++ b/arch/mips/include/asm/octeon/cvmx.h
4975@@ -376,6 +376,18 @@ static inline uint64_t cvmx_get_cycle(vo
4976 }
4977 
4978 /**
4979+ * Wait for the specified number of cycle
4980+ *
4981+ */
4982+static inline void cvmx_wait(uint64_t cycles)
4983+{
4984+ uint64_t done = cvmx_get_cycle() + cycles;
4985+
4986+ while (cvmx_get_cycle() < done)
4987+ ; /* Spin */
4988+}
4989+
4990+/**
4991  * Reads a chip global cycle counter. This counts CPU cycles since
4992  * chip reset. The counter is 64 bit.
4993  * This register does not exist on CN38XX pass 1 silicion
4994--- a/arch/mips/include/asm/octeon/octeon.h
4995+++ b/arch/mips/include/asm/octeon/octeon.h
4996@@ -245,4 +245,6 @@ static inline uint32_t octeon_npi_read32
4997     return cvmx_read64_uint32(address ^ 4);
4998 }
4999 
5000+extern struct cvmx_bootinfo *octeon_bootinfo;
5001+
5002 #endif /* __ASM_OCTEON_OCTEON_H */
5003

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