| 1 | /* |
| 2 | * linux/include/asm-mips/mach-jz4740/regs.h |
| 3 | * |
| 4 | * Ingenic's JZ4740 common include. |
| 5 | * |
| 6 | * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. |
| 7 | * |
| 8 | * Author: <yliu@ingenic.cn> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #ifndef __JZ4740_REGS_H__ |
| 16 | #define __JZ4740_REGS_H__ |
| 17 | |
| 18 | #if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY) |
| 19 | #define REG8(addr) (addr) |
| 20 | #define REG16(addr) (addr) |
| 21 | #define REG32(addr) (addr) |
| 22 | #else |
| 23 | #define REG8(addr) *((volatile unsigned char *)(addr)) |
| 24 | #define REG16(addr) *((volatile unsigned short *)(addr)) |
| 25 | #define REG32(addr) *((volatile unsigned int *)(addr)) |
| 26 | #endif |
| 27 | |
| 28 | /* |
| 29 | * Define the module base addresses |
| 30 | */ |
| 31 | #define CPM_BASE 0xB0000000 |
| 32 | #define INTC_BASE 0xB0001000 |
| 33 | #define TCU_BASE 0xB0002000 |
| 34 | #define WDT_BASE 0xB0002000 |
| 35 | #define RTC_BASE 0xB0003000 |
| 36 | #define GPIO_BASE 0xB0010000 |
| 37 | #define AIC_BASE 0xB0020000 |
| 38 | #define ICDC_BASE 0xB0020000 |
| 39 | #define MSC_BASE 0xB0021000 |
| 40 | #define UART0_BASE 0xB0030000 |
| 41 | #define UART1_BASE 0xB0031000 |
| 42 | #define I2C_BASE 0xB0042000 |
| 43 | #define SSI_BASE 0xB0043000 |
| 44 | #define SADC_BASE 0xB0070000 |
| 45 | #define EMC_BASE 0xB3010000 |
| 46 | #define DMAC_BASE 0xB3020000 |
| 47 | #define UHC_BASE 0xB3030000 |
| 48 | #define UDC_BASE 0xB3040000 |
| 49 | #define LCD_BASE 0xB3050000 |
| 50 | #define SLCD_BASE 0xB3050000 |
| 51 | #define CIM_BASE 0xB3060000 |
| 52 | #define IPU_BASE 0xB3080000 |
| 53 | #define ETH_BASE 0xB3100000 |
| 54 | |
| 55 | /************************************************************************* |
| 56 | * UART |
| 57 | *************************************************************************/ |
| 58 | |
| 59 | #define IRDA_BASE UART0_BASE |
| 60 | #define UART_BASE UART0_BASE |
| 61 | #define UART_OFF 0x1000 |
| 62 | |
| 63 | /* Register Offset */ |
| 64 | #define OFF_RDR (0x00) /* R 8b H'xx */ |
| 65 | #define OFF_TDR (0x00) /* W 8b H'xx */ |
| 66 | #define OFF_DLLR (0x00) /* RW 8b H'00 */ |
| 67 | #define OFF_DLHR (0x04) /* RW 8b H'00 */ |
| 68 | #define OFF_IER (0x04) /* RW 8b H'00 */ |
| 69 | #define OFF_ISR (0x08) /* R 8b H'01 */ |
| 70 | #define OFF_FCR (0x08) /* W 8b H'00 */ |
| 71 | #define OFF_LCR (0x0C) /* RW 8b H'00 */ |
| 72 | #define OFF_MCR (0x10) /* RW 8b H'00 */ |
| 73 | #define OFF_LSR (0x14) /* R 8b H'00 */ |
| 74 | #define OFF_MSR (0x18) /* R 8b H'00 */ |
| 75 | #define OFF_SPR (0x1C) /* RW 8b H'00 */ |
| 76 | #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ |
| 77 | #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ |
| 78 | #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ |
| 79 | |
| 80 | /* Register Address */ |
| 81 | #define UART0_RDR (UART0_BASE + OFF_RDR) |
| 82 | #define UART0_TDR (UART0_BASE + OFF_TDR) |
| 83 | #define UART0_DLLR (UART0_BASE + OFF_DLLR) |
| 84 | #define UART0_DLHR (UART0_BASE + OFF_DLHR) |
| 85 | #define UART0_IER (UART0_BASE + OFF_IER) |
| 86 | #define UART0_ISR (UART0_BASE + OFF_ISR) |
| 87 | #define UART0_FCR (UART0_BASE + OFF_FCR) |
| 88 | #define UART0_LCR (UART0_BASE + OFF_LCR) |
| 89 | #define UART0_MCR (UART0_BASE + OFF_MCR) |
| 90 | #define UART0_LSR (UART0_BASE + OFF_LSR) |
| 91 | #define UART0_MSR (UART0_BASE + OFF_MSR) |
| 92 | #define UART0_SPR (UART0_BASE + OFF_SPR) |
| 93 | #define UART0_SIRCR (UART0_BASE + OFF_SIRCR) |
| 94 | #define UART0_UMR (UART0_BASE + OFF_UMR) |
| 95 | #define UART0_UACR (UART0_BASE + OFF_UACR) |
| 96 | |
| 97 | /* |
| 98 | * Define macros for UARTIER |
| 99 | * UART Interrupt Enable Register |
| 100 | */ |
| 101 | #define UARTIER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */ |
| 102 | #define UARTIER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */ |
| 103 | #define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ |
| 104 | #define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */ |
| 105 | #define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ |
| 106 | |
| 107 | /* |
| 108 | * Define macros for UARTISR |
| 109 | * UART Interrupt Status Register |
| 110 | */ |
| 111 | #define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ |
| 112 | #define UARTISR_IID (7 << 1) /* Source of Interrupt */ |
| 113 | #define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */ |
| 114 | #define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ |
| 115 | #define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */ |
| 116 | #define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ |
| 117 | #define UARTISR_IID_RTO (6 << 1) /* Receive timeout */ |
| 118 | #define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */ |
| 119 | #define UARTISR_FFMS_NO_FIFO (0 << 6) |
| 120 | #define UARTISR_FFMS_FIFO_MODE (3 << 6) |
| 121 | |
| 122 | /* |
| 123 | * Define macros for UARTFCR |
| 124 | * UART FIFO Control Register |
| 125 | */ |
| 126 | #define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ |
| 127 | #define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ |
| 128 | #define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ |
| 129 | #define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */ |
| 130 | #define UARTFCR_UUE (1 << 4) /* 0: disable UART */ |
| 131 | #define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ |
| 132 | #define UARTFCR_RTRG_1 (0 << 6) |
| 133 | #define UARTFCR_RTRG_4 (1 << 6) |
| 134 | #define UARTFCR_RTRG_8 (2 << 6) |
| 135 | #define UARTFCR_RTRG_15 (3 << 6) |
| 136 | |
| 137 | /* |
| 138 | * Define macros for UARTLCR |
| 139 | * UART Line Control Register |
| 140 | */ |
| 141 | #define UARTLCR_WLEN (3 << 0) /* word length */ |
| 142 | #define UARTLCR_WLEN_5 (0 << 0) |
| 143 | #define UARTLCR_WLEN_6 (1 << 0) |
| 144 | #define UARTLCR_WLEN_7 (2 << 0) |
| 145 | #define UARTLCR_WLEN_8 (3 << 0) |
| 146 | #define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 |
| 147 | 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ |
| 148 | #define UARTLCR_STOP1 (0 << 2) |
| 149 | #define UARTLCR_STOP2 (1 << 2) |
| 150 | #define UARTLCR_PE (1 << 3) /* 0: parity disable */ |
| 151 | #define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ |
| 152 | #define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */ |
| 153 | #define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ |
| 154 | #define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */ |
| 155 | |
| 156 | /* |
| 157 | * Define macros for UARTLSR |
| 158 | * UART Line Status Register |
| 159 | */ |
| 160 | #define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ |
| 161 | #define UARTLSR_ORER (1 << 1) /* 0: no overrun error */ |
| 162 | #define UARTLSR_PER (1 << 2) /* 0: no parity error */ |
| 163 | #define UARTLSR_FER (1 << 3) /* 0; no framing error */ |
| 164 | #define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ |
| 165 | #define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ |
| 166 | #define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ |
| 167 | #define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ |
| 168 | |
| 169 | /* |
| 170 | * Define macros for UARTMCR |
| 171 | * UART Modem Control Register |
| 172 | */ |
| 173 | #define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high, 1: RTS_ output low */ |
| 174 | #define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ |
| 175 | #define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */ |
| 176 | |
| 177 | /* |
| 178 | * Define macros for UARTMSR |
| 179 | * UART Modem Status Register |
| 180 | */ |
| 181 | #define UARTMSR_CCTS (1 << 0) /* 1: a change on CTS_ pin */ |
| 182 | #define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */ |
| 183 | |
| 184 | /* |
| 185 | * Define macros for SIRCR |
| 186 | * Slow IrDA Control Register |
| 187 | */ |
| 188 | #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: SIR mode */ |
| 189 | #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: SIR mode */ |
| 190 | #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length |
| 191 | 1: 0 pulse width is 1.6us for 115.2Kbps */ |
| 192 | #define SIRCR_TDPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ |
| 193 | #define SIRCR_RDPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ |
| 194 | |
| 195 | |
| 196 | /************************************************************************* |
| 197 | * EMC (External Memory Controller) |
| 198 | *************************************************************************/ |
| 199 | #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ |
| 200 | #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ |
| 201 | #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ |
| 202 | #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ |
| 203 | #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ |
| 204 | #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ |
| 205 | #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ |
| 206 | #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ |
| 207 | #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ |
| 208 | #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ |
| 209 | |
| 210 | #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ |
| 211 | #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ |
| 212 | #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ |
| 213 | #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ |
| 214 | #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ |
| 215 | #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ |
| 216 | #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ |
| 217 | #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ |
| 218 | #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ |
| 219 | #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ |
| 220 | #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ |
| 221 | #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ |
| 222 | |
| 223 | #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ |
| 224 | #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ |
| 225 | #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ |
| 226 | #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ |
| 227 | #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ |
| 228 | #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ |
| 229 | |
| 230 | |
| 231 | #define REG_EMC_SMCR0 REG32(EMC_SMCR0) |
| 232 | #define REG_EMC_SMCR1 REG32(EMC_SMCR1) |
| 233 | #define REG_EMC_SMCR2 REG32(EMC_SMCR2) |
| 234 | #define REG_EMC_SMCR3 REG32(EMC_SMCR3) |
| 235 | #define REG_EMC_SMCR4 REG32(EMC_SMCR4) |
| 236 | #define REG_EMC_SACR0 REG32(EMC_SACR0) |
| 237 | #define REG_EMC_SACR1 REG32(EMC_SACR1) |
| 238 | #define REG_EMC_SACR2 REG32(EMC_SACR2) |
| 239 | #define REG_EMC_SACR3 REG32(EMC_SACR3) |
| 240 | #define REG_EMC_SACR4 REG32(EMC_SACR4) |
| 241 | |
| 242 | #define REG_EMC_NFCSR REG32(EMC_NFCSR) |
| 243 | #define REG_EMC_NFECR REG32(EMC_NFECR) |
| 244 | #define REG_EMC_NFECC REG32(EMC_NFECC) |
| 245 | #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) |
| 246 | #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) |
| 247 | #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) |
| 248 | #define REG_EMC_NFINTS REG32(EMC_NFINTS) |
| 249 | #define REG_EMC_NFINTE REG32(EMC_NFINTE) |
| 250 | #define REG_EMC_NFERR0 REG32(EMC_NFERR0) |
| 251 | #define REG_EMC_NFERR1 REG32(EMC_NFERR1) |
| 252 | #define REG_EMC_NFERR2 REG32(EMC_NFERR2) |
| 253 | #define REG_EMC_NFERR3 REG32(EMC_NFERR3) |
| 254 | |
| 255 | #define REG_EMC_DMCR REG32(EMC_DMCR) |
| 256 | #define REG_EMC_RTCSR REG16(EMC_RTCSR) |
| 257 | #define REG_EMC_RTCNT REG16(EMC_RTCNT) |
| 258 | #define REG_EMC_RTCOR REG16(EMC_RTCOR) |
| 259 | #define REG_EMC_DMAR0 REG32(EMC_DMAR0) |
| 260 | |
| 261 | /* Static Memory Control Register */ |
| 262 | #define EMC_SMCR_STRV_BIT 24 |
| 263 | #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) |
| 264 | #define EMC_SMCR_TAW_BIT 20 |
| 265 | #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) |
| 266 | #define EMC_SMCR_TBP_BIT 16 |
| 267 | #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) |
| 268 | #define EMC_SMCR_TAH_BIT 12 |
| 269 | #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) |
| 270 | #define EMC_SMCR_TAS_BIT 8 |
| 271 | #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) |
| 272 | #define EMC_SMCR_BW_BIT 6 |
| 273 | #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) |
| 274 | #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) |
| 275 | #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) |
| 276 | #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) |
| 277 | #define EMC_SMCR_BCM (1 << 3) |
| 278 | #define EMC_SMCR_BL_BIT 1 |
| 279 | #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) |
| 280 | #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) |
| 281 | #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) |
| 282 | #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) |
| 283 | #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) |
| 284 | #define EMC_SMCR_SMT (1 << 0) |
| 285 | |
| 286 | /* Static Memory Bank Addr Config Reg */ |
| 287 | #define EMC_SACR_BASE_BIT 8 |
| 288 | #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) |
| 289 | #define EMC_SACR_MASK_BIT 0 |
| 290 | #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) |
| 291 | |
| 292 | /* NAND Flash Control/Status Register */ |
| 293 | #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ |
| 294 | #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ |
| 295 | #define EMC_NFCSR_NFCE3 (1 << 5) |
| 296 | #define EMC_NFCSR_NFE3 (1 << 4) |
| 297 | #define EMC_NFCSR_NFCE2 (1 << 3) |
| 298 | #define EMC_NFCSR_NFE2 (1 << 2) |
| 299 | #define EMC_NFCSR_NFCE1 (1 << 1) |
| 300 | #define EMC_NFCSR_NFE1 (1 << 0) |
| 301 | |
| 302 | /* NAND Flash ECC Control Register */ |
| 303 | #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ |
| 304 | #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ |
| 305 | #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ |
| 306 | #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ |
| 307 | #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ |
| 308 | #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ |
| 309 | #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ |
| 310 | |
| 311 | /* NAND Flash ECC Data Register */ |
| 312 | #define EMC_NFECC_ECC2_BIT 16 |
| 313 | #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) |
| 314 | #define EMC_NFECC_ECC1_BIT 8 |
| 315 | #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) |
| 316 | #define EMC_NFECC_ECC0_BIT 0 |
| 317 | #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) |
| 318 | |
| 319 | /* NAND Flash Interrupt Status Register */ |
| 320 | #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ |
| 321 | #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) |
| 322 | #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ |
| 323 | #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ |
| 324 | #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ |
| 325 | #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ |
| 326 | #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ |
| 327 | |
| 328 | /* NAND Flash Interrupt Enable Register */ |
| 329 | #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ |
| 330 | #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ |
| 331 | #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ |
| 332 | #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ |
| 333 | #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ |
| 334 | |
| 335 | /* NAND Flash RS Error Report Register */ |
| 336 | #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ |
| 337 | #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) |
| 338 | #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ |
| 339 | #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) |
| 340 | |
| 341 | |
| 342 | /* DRAM Control Register */ |
| 343 | #define EMC_DMCR_BW_BIT 31 |
| 344 | #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) |
| 345 | #define EMC_DMCR_CA_BIT 26 |
| 346 | #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) |
| 347 | #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) |
| 348 | #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) |
| 349 | #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) |
| 350 | #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) |
| 351 | #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) |
| 352 | #define EMC_DMCR_RMODE (1 << 25) |
| 353 | #define EMC_DMCR_RFSH (1 << 24) |
| 354 | #define EMC_DMCR_MRSET (1 << 23) |
| 355 | #define EMC_DMCR_RA_BIT 20 |
| 356 | #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) |
| 357 | #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) |
| 358 | #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) |
| 359 | #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) |
| 360 | #define EMC_DMCR_BA_BIT 19 |
| 361 | #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) |
| 362 | #define EMC_DMCR_PDM (1 << 18) |
| 363 | #define EMC_DMCR_EPIN (1 << 17) |
| 364 | #define EMC_DMCR_TRAS_BIT 13 |
| 365 | #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) |
| 366 | #define EMC_DMCR_RCD_BIT 11 |
| 367 | #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) |
| 368 | #define EMC_DMCR_TPC_BIT 8 |
| 369 | #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) |
| 370 | #define EMC_DMCR_TRWL_BIT 5 |
| 371 | #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) |
| 372 | #define EMC_DMCR_TRC_BIT 2 |
| 373 | #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) |
| 374 | #define EMC_DMCR_TCL_BIT 0 |
| 375 | #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) |
| 376 | |
| 377 | /* Refresh Time Control/Status Register */ |
| 378 | #define EMC_RTCSR_CMF (1 << 7) |
| 379 | #define EMC_RTCSR_CKS_BIT 0 |
| 380 | #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) |
| 381 | #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) |
| 382 | #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) |
| 383 | #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) |
| 384 | #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) |
| 385 | #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) |
| 386 | #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) |
| 387 | #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) |
| 388 | #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) |
| 389 | |
| 390 | /* SDRAM Bank Address Configuration Register */ |
| 391 | #define EMC_DMAR_BASE_BIT 8 |
| 392 | #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) |
| 393 | #define EMC_DMAR_MASK_BIT 0 |
| 394 | #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) |
| 395 | |
| 396 | /* Mode Register of SDRAM bank 0 */ |
| 397 | #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ |
| 398 | #define EMC_SDMR_OM_BIT 7 /* Operating Mode */ |
| 399 | #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) |
| 400 | #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) |
| 401 | #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ |
| 402 | #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) |
| 403 | #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) |
| 404 | #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) |
| 405 | #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) |
| 406 | #define EMC_SDMR_BT_BIT 3 /* Burst Type */ |
| 407 | #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) |
| 408 | #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ |
| 409 | #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ |
| 410 | #define EMC_SDMR_BL_BIT 0 /* Burst Length */ |
| 411 | #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) |
| 412 | #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) |
| 413 | #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) |
| 414 | #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) |
| 415 | #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) |
| 416 | |
| 417 | #define EMC_SDMR_CAS2_16BIT \ |
| 418 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| 419 | #define EMC_SDMR_CAS2_32BIT \ |
| 420 | (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| 421 | #define EMC_SDMR_CAS3_16BIT \ |
| 422 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) |
| 423 | #define EMC_SDMR_CAS3_32BIT \ |
| 424 | (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) |
| 425 | |
| 426 | /************************************************************************* |
| 427 | * WDT (WatchDog Timer) |
| 428 | *************************************************************************/ |
| 429 | #define WDT_TDR (WDT_BASE + 0x00) |
| 430 | #define WDT_TCER (WDT_BASE + 0x04) |
| 431 | #define WDT_TCNT (WDT_BASE + 0x08) |
| 432 | #define WDT_TCSR (WDT_BASE + 0x0C) |
| 433 | |
| 434 | #define REG_WDT_TDR REG16(WDT_TDR) |
| 435 | #define REG_WDT_TCER REG8(WDT_TCER) |
| 436 | #define REG_WDT_TCNT REG16(WDT_TCNT) |
| 437 | #define REG_WDT_TCSR REG16(WDT_TCSR) |
| 438 | |
| 439 | // Register definition |
| 440 | #define WDT_TCSR_PRESCALE_BIT 3 |
| 441 | #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) |
| 442 | #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) |
| 443 | #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) |
| 444 | #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) |
| 445 | #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) |
| 446 | #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) |
| 447 | #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) |
| 448 | #define WDT_TCSR_EXT_EN (1 << 2) |
| 449 | #define WDT_TCSR_RTC_EN (1 << 1) |
| 450 | #define WDT_TCSR_PCK_EN (1 << 0) |
| 451 | |
| 452 | #define WDT_TCER_TCEN (1 << 0) |
| 453 | |
| 454 | /************************************************************************* |
| 455 | * RTC |
| 456 | *************************************************************************/ |
| 457 | #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ |
| 458 | #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ |
| 459 | #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ |
| 460 | #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ |
| 461 | |
| 462 | #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ |
| 463 | #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ |
| 464 | #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ |
| 465 | #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ |
| 466 | #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ |
| 467 | #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ |
| 468 | |
| 469 | #define REG_RTC_RCR REG32(RTC_RCR) |
| 470 | #define REG_RTC_RSR REG32(RTC_RSR) |
| 471 | #define REG_RTC_RSAR REG32(RTC_RSAR) |
| 472 | #define REG_RTC_RGR REG32(RTC_RGR) |
| 473 | #define REG_RTC_HCR REG32(RTC_HCR) |
| 474 | #define REG_RTC_HWFCR REG32(RTC_HWFCR) |
| 475 | #define REG_RTC_HRCR REG32(RTC_HRCR) |
| 476 | #define REG_RTC_HWCR REG32(RTC_HWCR) |
| 477 | #define REG_RTC_HWRSR REG32(RTC_HWRSR) |
| 478 | #define REG_RTC_HSPR REG32(RTC_HSPR) |
| 479 | |
| 480 | /* RTC Control Register */ |
| 481 | #define RTC_RCR_WRDY_BIT 7 |
| 482 | #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ |
| 483 | #define RTC_RCR_1HZ_BIT 6 |
| 484 | #define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */ |
| 485 | #define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */ |
| 486 | #define RTC_RCR_AF_BIT 4 |
| 487 | #define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */ |
| 488 | #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ |
| 489 | #define RTC_RCR_AE (1 << 2) /* Alarm Enable */ |
| 490 | #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ |
| 491 | |
| 492 | /* RTC Regulator Register */ |
| 493 | #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ |
| 494 | #define RTC_RGR_ADJC_BIT 16 |
| 495 | #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) |
| 496 | #define RTC_RGR_NC1HZ_BIT 0 |
| 497 | #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) |
| 498 | |
| 499 | /* Hibernate Control Register */ |
| 500 | #define RTC_HCR_PD (1 << 0) /* Power Down */ |
| 501 | |
| 502 | /* Hibernate Wakeup Filter Counter Register */ |
| 503 | #define RTC_HWFCR_BIT 5 |
| 504 | #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) |
| 505 | |
| 506 | /* Hibernate Reset Counter Register */ |
| 507 | #define RTC_HRCR_BIT 5 |
| 508 | #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) |
| 509 | |
| 510 | /* Hibernate Wakeup Control Register */ |
| 511 | #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ |
| 512 | |
| 513 | /* Hibernate Wakeup Status Register */ |
| 514 | #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ |
| 515 | #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ |
| 516 | #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ |
| 517 | #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ |
| 518 | |
| 519 | #endif /* __JZ4740_REGS_H__ */ |
| 520 | |
