| 1 | /* |
| 2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
| 3 | * JZ4740 platform IRQ support |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | * |
| 10 | * You should have received a copy of the GNU General Public License along |
| 11 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/types.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/ioport.h> |
| 21 | #include <linux/timex.h> |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/delay.h> |
| 24 | |
| 25 | #include <linux/debugfs.h> |
| 26 | #include <linux/seq_file.h> |
| 27 | |
| 28 | #include <asm/io.h> |
| 29 | #include <asm/mipsregs.h> |
| 30 | #include <asm/irq_cpu.h> |
| 31 | |
| 32 | static void __iomem *jz_intc_base; |
| 33 | static uint32_t jz_intc_wakeup; |
| 34 | static uint32_t jz_intc_saved; |
| 35 | |
| 36 | #define JZ_REG_BASE_INTC 0x10001000 |
| 37 | |
| 38 | #define JZ_REG_INTC_STATUS 0x00 |
| 39 | #define JZ_REG_INTC_MASK 0x04 |
| 40 | #define JZ_REG_INTC_SET_MASK 0x08 |
| 41 | #define JZ_REG_INTC_CLEAR_MASK 0x0c |
| 42 | #define JZ_REG_INTC_PENDING 0x10 |
| 43 | |
| 44 | #define IRQ_BIT(x) BIT((x) - JZ_IRQ_BASE) |
| 45 | |
| 46 | static void intc_irq_unmask(unsigned int irq) |
| 47 | { |
| 48 | writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); |
| 49 | } |
| 50 | |
| 51 | static void intc_irq_mask(unsigned int irq) |
| 52 | { |
| 53 | writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK); |
| 54 | } |
| 55 | |
| 56 | static void intc_irq_ack(unsigned int irq) |
| 57 | { |
| 58 | writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING); |
| 59 | } |
| 60 | |
| 61 | static int intc_irq_set_wake(unsigned int irq, unsigned int on) |
| 62 | { |
| 63 | if (on) |
| 64 | jz_intc_wakeup |= IRQ_BIT(irq); |
| 65 | else |
| 66 | jz_intc_wakeup &= ~IRQ_BIT(irq); |
| 67 | |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | static struct irq_chip intc_irq_type = { |
| 72 | .name = "INTC", |
| 73 | .mask = intc_irq_mask, |
| 74 | .unmask = intc_irq_unmask, |
| 75 | .ack = intc_irq_ack, |
| 76 | .set_wake = intc_irq_set_wake, |
| 77 | }; |
| 78 | |
| 79 | static irqreturn_t jz4740_cascade(int irq, void *data) |
| 80 | { |
| 81 | uint32_t irq_reg; |
| 82 | |
| 83 | irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING); |
| 84 | generic_handle_irq(ffs(irq_reg) - 1 + JZ_IRQ_BASE); |
| 85 | |
| 86 | return IRQ_HANDLED; |
| 87 | } |
| 88 | |
| 89 | static struct irqaction jz4740_cascade_action = { |
| 90 | .handler = jz4740_cascade, |
| 91 | .name = "JZ4740 cascade interrupt", |
| 92 | .flags = IRQF_DISABLED, |
| 93 | }; |
| 94 | |
| 95 | void __init arch_init_irq(void) |
| 96 | { |
| 97 | int i; |
| 98 | mips_cpu_irq_init(); |
| 99 | |
| 100 | jz_intc_base = ioremap(JZ_REG_BASE_INTC, 0x14); |
| 101 | |
| 102 | for (i = JZ_IRQ_BASE; i < JZ_IRQ_BASE + 32; i++) { |
| 103 | intc_irq_mask(i); |
| 104 | set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); |
| 105 | } |
| 106 | |
| 107 | setup_irq(2, &jz4740_cascade_action); |
| 108 | } |
| 109 | |
| 110 | asmlinkage void plat_irq_dispatch(void) |
| 111 | { |
| 112 | unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; |
| 113 | if (pending & STATUSF_IP2) |
| 114 | do_IRQ(2); |
| 115 | else if(pending & STATUSF_IP3) |
| 116 | do_IRQ(3); |
| 117 | else |
| 118 | spurious_interrupt(); |
| 119 | } |
| 120 | |
| 121 | /* TODO: Use sysdev */ |
| 122 | void jz4740_intc_suspend(void) |
| 123 | { |
| 124 | jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK); |
| 125 | writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK); |
| 126 | writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK); |
| 127 | } |
| 128 | |
| 129 | void jz4740_intc_resume(void) |
| 130 | { |
| 131 | writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK); |
| 132 | writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK); |
| 133 | } |
| 134 | |
| 135 | #ifdef CONFIG_DEBUG_FS |
| 136 | |
| 137 | static int intc_regs_show(struct seq_file *s, void *unused) |
| 138 | { |
| 139 | seq_printf(s, "Status:\t\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_STATUS)); |
| 140 | seq_printf(s, "Mask\t\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_MASK)); |
| 141 | seq_printf(s, "Pending:\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_PENDING)); |
| 142 | |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | static int intc_regs_open(struct inode *inode, struct file *file) |
| 147 | { |
| 148 | return single_open(file, intc_regs_show, NULL); |
| 149 | } |
| 150 | |
| 151 | static const struct file_operations intc_regs_operations = { |
| 152 | .open = intc_regs_open, |
| 153 | .read = seq_read, |
| 154 | .llseek = seq_lseek, |
| 155 | .release = single_release, |
| 156 | }; |
| 157 | |
| 158 | static int __init intc_debugfs_init(void) |
| 159 | { |
| 160 | (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO, |
| 161 | NULL, NULL, &intc_regs_operations); |
| 162 | return 0; |
| 163 | } |
| 164 | subsys_initcall(intc_debugfs_init); |
| 165 | |
| 166 | #endif |
| 167 | |
