| 1 | /* |
| 2 | * linux/arch/mips/jz4740/reset.c |
| 3 | * |
| 4 | * JZ4740 reset routines. |
| 5 | * |
| 6 | * Copyright (c) 2006-2007 Ingenic Semiconductor Inc. |
| 7 | * Author: <yliu@ingenic.cn> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | #include <linux/sched.h> |
| 14 | #include <linux/mm.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/pgtable.h> |
| 17 | #include <asm/processor.h> |
| 18 | #include <asm/reboot.h> |
| 19 | #include <asm/system.h> |
| 20 | #include <asm/mach-jz4740/regs.h> |
| 21 | #include <asm/mach-jz4740/timer.h> |
| 22 | #include <asm/mach-jz4740/jz4740.h> |
| 23 | |
| 24 | #include "clock.h" |
| 25 | |
| 26 | void jz_restart(char *command) |
| 27 | { |
| 28 | printk(KERN_NOTICE "Restarting after 4 ms\n"); |
| 29 | REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN; |
| 30 | REG_WDT_TCNT = 0; |
| 31 | REG_WDT_TDR = jz4740_clock_bdata.ext_rate / 1000; /* reset after 4ms */ |
| 32 | jz4740_timer_enable_watchdog(); |
| 33 | REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */ |
| 34 | while (1); |
| 35 | } |
| 36 | |
| 37 | void jz_halt(void) |
| 38 | { |
| 39 | /* Put CPU to power down mode */ |
| 40 | while (!(REG_RTC_RCR & RTC_RCR_WRDY)); |
| 41 | REG_RTC_HCR = RTC_HCR_PD; |
| 42 | |
| 43 | while (1) |
| 44 | __asm__(".set\tmips3\n\t" |
| 45 | "wait\n\t" |
| 46 | ".set\tmips0"); |
| 47 | } |
| 48 | |
| 49 | void jz_power_off(void) |
| 50 | { |
| 51 | jz_halt(); |
| 52 | } |
| 53 | |
