Root/target/linux/xburst/files-2.6.32/drivers/mmc/host/jz_mmc.c

1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 GPIO SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/mmc/host.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/scatterlist.h>
24#include <linux/clk.h>
25#include <linux/mmc/jz4740_mmc.h>
26
27#include <linux/gpio.h>
28#include <asm/mach-jz4740/gpio.h>
29#include <asm/cacheflush.h>
30#include <linux/dma-mapping.h>
31
32#define JZ_REG_MMC_STRPCL 0x00
33#define JZ_REG_MMC_STATUS 0x04
34#define JZ_REG_MMC_CLKRT 0x08
35#define JZ_REG_MMC_CMDAT 0x0C
36#define JZ_REG_MMC_RESTO 0x10
37#define JZ_REG_MMC_RDTO 0x14
38#define JZ_REG_MMC_BLKLEN 0x18
39#define JZ_REG_MMC_NOB 0x1C
40#define JZ_REG_MMC_SNOB 0x20
41#define JZ_REG_MMC_IMASK 0x24
42#define JZ_REG_MMC_IREG 0x28
43#define JZ_REG_MMC_CMD 0x2C
44#define JZ_REG_MMC_ARG 0x30
45#define JZ_REG_MMC_RESP_FIFO 0x34
46#define JZ_REG_MMC_RXFIFO 0x38
47#define JZ_REG_MMC_TXFIFO 0x3C
48
49#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
50#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
51#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
52#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
53#define JZ_MMC_STRPCL_RESET BIT(3)
54#define JZ_MMC_STRPCL_START_OP BIT(2)
55#define JZ_MMC_STRPCL_CLOCK_CONTROL BIT(1) | BIT(0)
56#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
57#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
58
59
60#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
61#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
62#define JZ_MMC_STATUS_PRG_DONE BIT(13)
63#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
64#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
65#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
66#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
67#define JZ_MMC_STATUS_CLK_EN BIT(8)
68#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
69#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
70#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
71#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
72#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
73#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
74#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
75#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
76
77#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
78#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
79
80
81#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
82#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
83#define JZ_MMC_CMDAT_DMA_EN BIT(8)
84#define JZ_MMC_CMDAT_INIT BIT(7)
85#define JZ_MMC_CMDAT_BUSY BIT(6)
86#define JZ_MMC_CMDAT_STREAM BIT(5)
87#define JZ_MMC_CMDAT_WRITE BIT(4)
88#define JZ_MMC_CMDAT_DATA_EN BIT(3)
89#define JZ_MMC_CMDAT_RESPONSE_FORMAT BIT(2) | BIT(1) | BIT(0)
90#define JZ_MMC_CMDAT_RSP_R1 1
91#define JZ_MMC_CMDAT_RSP_R2 2
92#define JZ_MMC_CMDAT_RSP_R3 3
93
94#define JZ_MMC_IRQ_SDIO BIT(7)
95#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
96#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
97#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
98#define JZ_MMC_IRQ_PRG_DONE BIT(1)
99#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
100
101
102#define JZ_MMC_CLK_RATE 24000000
103
104#define JZ4740_MMC_MAX_TIMEOUT 10000000
105
106struct jz4740_mmc_host {
107    struct mmc_host *mmc;
108    struct platform_device *pdev;
109    struct jz4740_mmc_platform_data *pdata;
110    struct clk *clk;
111
112    int irq;
113    int card_detect_irq;
114
115    struct resource *mem;
116    void __iomem *base;
117    struct mmc_request *req;
118    struct mmc_command *cmd;
119
120    int max_clock;
121    uint32_t cmdat;
122
123    uint16_t irq_mask;
124
125    spinlock_t lock;
126    struct timer_list clock_timer;
127    struct timer_list timeout_timer;
128    unsigned waiting:1;
129};
130
131static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
132
133static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
134{
135    unsigned long flags;
136    spin_lock_irqsave(&host->lock, flags);
137
138    host->irq_mask &= ~irq;
139    writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
140
141    spin_unlock_irqrestore(&host->lock, flags);
142}
143
144static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
145{
146    unsigned long flags;
147    spin_lock_irqsave(&host->lock, flags);
148
149    host->irq_mask |= irq;
150    writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
151
152    spin_unlock_irqrestore(&host->lock, flags);
153}
154
155static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
156{
157    uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
158
159    if (start_transfer)
160        val |= JZ_MMC_STRPCL_START_OP;
161
162    writew(val, host->base + JZ_REG_MMC_STRPCL);
163}
164
165static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
166{
167    uint16_t status;
168    writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
169    do {
170        status = readl(host->base + JZ_REG_MMC_STATUS);
171    } while (status & JZ_MMC_STATUS_CLK_EN);
172
173}
174
175static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
176{
177    writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
178    udelay(10);
179    while(readw(host->base + JZ_REG_MMC_STATUS) & JZ_MMC_STATUS_IS_RESETTING);
180}
181
182static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
183{
184    struct mmc_request *req;
185    unsigned long flags;
186
187    spin_lock_irqsave(&host->lock, flags);
188    req = host->req;
189    host->req = NULL;
190    host->waiting = 0;
191    spin_unlock_irqrestore(&host->lock, flags);
192
193    if (!unlikely(req))
194        return;
195
196/* if (req->cmd->error != 0) {
197        printk("error\n");
198        jz4740_mmc_reset(host);
199    }*/
200
201    mmc_request_done(host->mmc, req);
202}
203
204static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
205    struct scatterlist *sg;
206    uint32_t *sg_pointer;
207    int status;
208    unsigned int timeout;
209    size_t i, j;
210
211    for (sg = data->sg; sg; sg = sg_next(sg)) {
212        sg_pointer = sg_virt(sg);
213        i = sg->length / 4;
214        j = i >> 3;
215        i = i & 0x7;
216        while (j) {
217            timeout = JZ4740_MMC_MAX_TIMEOUT;
218            do {
219                status = readw(host->base + JZ_REG_MMC_IREG);
220            } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout);
221            if (unlikely(timeout == 0))
222                goto err_timeout;
223
224            writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
225
226            writel(sg_pointer[0], host->base + JZ_REG_MMC_TXFIFO);
227            writel(sg_pointer[1], host->base + JZ_REG_MMC_TXFIFO);
228            writel(sg_pointer[2], host->base + JZ_REG_MMC_TXFIFO);
229            writel(sg_pointer[3], host->base + JZ_REG_MMC_TXFIFO);
230            writel(sg_pointer[4], host->base + JZ_REG_MMC_TXFIFO);
231            writel(sg_pointer[5], host->base + JZ_REG_MMC_TXFIFO);
232            writel(sg_pointer[6], host->base + JZ_REG_MMC_TXFIFO);
233            writel(sg_pointer[7], host->base + JZ_REG_MMC_TXFIFO);
234            sg_pointer += 8;
235            --j;
236        }
237        if (i) {
238            timeout = JZ4740_MMC_MAX_TIMEOUT;
239            do {
240                status = readw(host->base + JZ_REG_MMC_IREG);
241            } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout);
242            if (unlikely(timeout == 0))
243                goto err_timeout;
244
245            writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
246
247            while (i) {
248                writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
249                ++sg_pointer;
250                --i;
251            }
252        }
253        data->bytes_xfered += sg->length;
254    }
255
256    status = readl(host->base + JZ_REG_MMC_STATUS);
257    if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
258        goto err;
259
260    writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
261    timeout = JZ4740_MMC_MAX_TIMEOUT;
262    do {
263        status = readl(host->base + JZ_REG_MMC_STATUS);
264    } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0 && --timeout);
265
266    if (unlikely(timeout == 0))
267        goto err_timeout;
268    writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
269
270    return;
271err_timeout:
272    host->req->cmd->error = -ETIMEDOUT;
273    data->error = -ETIMEDOUT;
274    return;
275err:
276    if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
277        host->req->cmd->error = -ETIMEDOUT;
278        data->error = -ETIMEDOUT;
279    } else {
280        host->req->cmd->error = -EILSEQ;
281        data->error = -EILSEQ;
282    }
283}
284
285static void jz4740_mmc_timeout(unsigned long data)
286{
287    struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)data;
288    unsigned long flags;
289
290    spin_lock_irqsave(&host->lock, flags);
291    if (!host->waiting) {
292        spin_unlock_irqrestore(&host->lock, flags);
293        return;
294    }
295
296    host->waiting = 0;
297
298    spin_unlock_irqrestore(&host->lock, flags);
299
300    host->req->cmd->error = -ETIMEDOUT;
301    jz4740_mmc_request_done(host);
302}
303
304static void jz4740_mmc_read_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
305    struct scatterlist *sg;
306    uint32_t *sg_pointer;
307    uint32_t d;
308    uint16_t status = 0;
309    size_t i, j;
310    unsigned int timeout;
311
312    for (sg = data->sg; sg; sg = sg_next(sg)) {
313        sg_pointer = sg_virt(sg);
314        i = sg->length;
315        j = i >> 5;
316        i = i & 0x1f;
317        while (j) {
318            timeout = JZ4740_MMC_MAX_TIMEOUT;
319            do {
320                status = readw(host->base + JZ_REG_MMC_IREG);
321            } while (!(status & JZ_MMC_IRQ_RXFIFO_RD_REQ) && --timeout);
322
323            if (unlikely(timeout == 0))
324                goto err_timeout;
325
326            writew(JZ_MMC_IRQ_RXFIFO_RD_REQ, host->base + JZ_REG_MMC_IREG);
327
328            sg_pointer[0] = readl(host->base + JZ_REG_MMC_RXFIFO);
329            sg_pointer[1] = readl(host->base + JZ_REG_MMC_RXFIFO);
330            sg_pointer[2] = readl(host->base + JZ_REG_MMC_RXFIFO);
331            sg_pointer[3] = readl(host->base + JZ_REG_MMC_RXFIFO);
332            sg_pointer[4] = readl(host->base + JZ_REG_MMC_RXFIFO);
333            sg_pointer[5] = readl(host->base + JZ_REG_MMC_RXFIFO);
334            sg_pointer[6] = readl(host->base + JZ_REG_MMC_RXFIFO);
335            sg_pointer[7] = readl(host->base + JZ_REG_MMC_RXFIFO);
336
337            sg_pointer += 8;
338            --j;
339        }
340
341        while (i >= 4) {
342            timeout = JZ4740_MMC_MAX_TIMEOUT;
343            do {
344                status = readl(host->base + JZ_REG_MMC_STATUS);
345            } while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout);
346
347            if (unlikely(timeout == 0))
348                goto err_timeout;
349
350            *sg_pointer = readl(host->base + JZ_REG_MMC_RXFIFO);
351            ++sg_pointer;
352            i -= 4;
353        }
354        if (i > 0) {
355            d = readl(host->base + JZ_REG_MMC_RXFIFO);
356            memcpy(sg_pointer, &d, i);
357        }
358        data->bytes_xfered += sg->length;
359
360        flush_dcache_page(sg_page(sg));
361    }
362
363    status = readl(host->base + JZ_REG_MMC_STATUS);
364    if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
365        goto err;
366
367    /* For whatever reason there is sometime one word more in the fifo then
368     * requested */
369    while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0 && --timeout) {
370        d = readl(host->base + JZ_REG_MMC_RXFIFO);
371        status = readl(host->base + JZ_REG_MMC_STATUS);
372    }
373    return;
374err_timeout:
375    host->req->cmd->error = -ETIMEDOUT;
376    data->error = -ETIMEDOUT;
377    return;
378err:
379    if(status & JZ_MMC_STATUS_TIMEOUT_READ) {
380        host->req->cmd->error = -ETIMEDOUT;
381        data->error = -ETIMEDOUT;
382    } else {
383        host->req->cmd->error = -EILSEQ;
384        data->error = -EILSEQ;
385    }
386}
387
388static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
389{
390    struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)devid;
391
392    if (host->cmd->error)
393        jz4740_mmc_request_done(host);
394    else
395        jz4740_mmc_cmd_done(host);
396
397    return IRQ_HANDLED;
398}
399
400static irqreturn_t jz_mmc_irq(int irq, void *devid)
401{
402    struct jz4740_mmc_host *host = devid;
403    uint16_t irq_reg, status, tmp;
404    unsigned long flags;
405    irqreturn_t ret = IRQ_HANDLED;
406
407    irq_reg = readw(host->base + JZ_REG_MMC_IREG);
408
409    tmp = irq_reg;
410    spin_lock_irqsave(&host->lock, flags);
411    irq_reg &= ~host->irq_mask;
412    spin_unlock_irqrestore(&host->lock, flags);
413
414    tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
415            JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
416
417    if (tmp != irq_reg)
418        writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
419
420    if (irq_reg & JZ_MMC_IRQ_SDIO) {
421        writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
422        mmc_signal_sdio_irq(host->mmc);
423    }
424
425    if (!host->req || !host->cmd) {
426        goto handled;
427    }
428
429
430    spin_lock_irqsave(&host->lock, flags);
431    if (!host->waiting) {
432        spin_unlock_irqrestore(&host->lock, flags);
433        goto handled;
434    }
435
436    host->waiting = 0;
437    spin_unlock_irqrestore(&host->lock, flags);
438
439    del_timer(&host->timeout_timer);
440
441    status = readl(host->base + JZ_REG_MMC_STATUS);
442
443    if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
444        host->cmd->error = -ETIMEDOUT;
445    } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
446        host->cmd->error = -EIO;
447    } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
448                        JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
449        host->cmd->data->error = -EIO;
450    } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
451                        JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
452        host->cmd->data->error = -EIO;
453    }
454
455    if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
456        jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
457        writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
458        ret = IRQ_WAKE_THREAD;
459    }
460
461    return ret;
462handled:
463
464    writew(0xff, host->base + JZ_REG_MMC_IREG);
465    return IRQ_HANDLED;
466}
467
468static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
469    int div = 0;
470    int real_rate;
471
472    jz4740_mmc_clock_disable(host);
473    clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
474
475    real_rate = clk_get_rate(host->clk);
476
477    while (real_rate > rate && div < 7) {
478        ++div;
479        real_rate >>= 1;
480    }
481
482    writew(div, host->base + JZ_REG_MMC_CLKRT);
483    return real_rate;
484}
485
486
487static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
488{
489    int i;
490    uint16_t tmp;
491    if (cmd->flags & MMC_RSP_136) {
492        tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
493        for (i = 0; i < 4; ++i) {
494            cmd->resp[i] = tmp << 24;
495            cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
496            tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
497            cmd->resp[i] |= tmp >> 8;
498        }
499    } else {
500        cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
501        cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
502        cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
503    }
504}
505
506static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
507{
508    uint32_t cmdat = host->cmdat;
509
510    host->cmdat &= ~JZ_MMC_CMDAT_INIT;
511    jz4740_mmc_clock_disable(host);
512
513    host->cmd = cmd;
514
515    if (cmd->flags & MMC_RSP_BUSY)
516        cmdat |= JZ_MMC_CMDAT_BUSY;
517
518    switch (mmc_resp_type(cmd)) {
519    case MMC_RSP_R1B:
520    case MMC_RSP_R1:
521        cmdat |= JZ_MMC_CMDAT_RSP_R1;
522        break;
523    case MMC_RSP_R2:
524        cmdat |= JZ_MMC_CMDAT_RSP_R2;
525        break;
526    case MMC_RSP_R3:
527        cmdat |= JZ_MMC_CMDAT_RSP_R3;
528        break;
529    default:
530        break;
531    }
532
533    if (cmd->data) {
534        cmdat |= JZ_MMC_CMDAT_DATA_EN;
535        if (cmd->data->flags & MMC_DATA_WRITE)
536            cmdat |= JZ_MMC_CMDAT_WRITE;
537        if (cmd->data->flags & MMC_DATA_STREAM)
538            cmdat |= JZ_MMC_CMDAT_STREAM;
539
540        writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
541        writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
542    }
543
544    writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
545    writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
546    writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
547
548    host->waiting = 1;
549    jz4740_mmc_clock_enable(host, 1);
550    mod_timer(&host->timeout_timer, jiffies + 5*HZ);
551}
552
553static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
554{
555    uint32_t status;
556    struct mmc_command *cmd = host->req->cmd;
557    struct mmc_request *req = host->req;
558    unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT;
559
560    if (cmd->flags & MMC_RSP_PRESENT)
561        jz4740_mmc_read_response(host, cmd);
562
563    if (cmd->data) {
564        if (cmd->data->flags & MMC_DATA_READ)
565            jz4740_mmc_read_data(host, cmd->data);
566        else
567            jz4740_mmc_write_data(host, cmd->data);
568    }
569
570    if (req->stop) {
571        jz4740_mmc_send_command(host, req->stop);
572        do {
573            status = readw(host->base + JZ_REG_MMC_IREG);
574        } while ((status & JZ_MMC_IRQ_PRG_DONE) == 0 && --timeout);
575        writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG);
576    }
577
578    if (unlikely(timeout == 0))
579        req->stop->error = -ETIMEDOUT;
580
581    jz4740_mmc_request_done(host);
582}
583
584static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
585{
586    struct jz4740_mmc_host *host = mmc_priv(mmc);
587
588    host->req = req;
589
590    writew(0xffff, host->base + JZ_REG_MMC_IREG);
591
592    writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
593    jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
594    jz4740_mmc_send_command(host, req->cmd);
595}
596
597
598static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
599{
600    struct jz4740_mmc_host *host = mmc_priv(mmc);
601    if (ios->clock)
602        jz4740_mmc_set_clock_rate(host, ios->clock);
603
604    switch(ios->power_mode) {
605    case MMC_POWER_UP:
606        jz4740_mmc_reset(host);
607        if (gpio_is_valid(host->pdata->gpio_power))
608            gpio_set_value(host->pdata->gpio_power,
609                    !host->pdata->power_active_low);
610        host->cmdat |= JZ_MMC_CMDAT_INIT;
611        clk_enable(host->clk);
612        break;
613    case MMC_POWER_ON:
614        break;
615    default:
616        if (gpio_is_valid(host->pdata->gpio_power))
617            gpio_set_value(host->pdata->gpio_power,
618                    host->pdata->power_active_low);
619        clk_disable(host->clk);
620        break;
621    }
622
623    switch(ios->bus_width) {
624    case MMC_BUS_WIDTH_1:
625        host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
626        break;
627    case MMC_BUS_WIDTH_4:
628        host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
629        break;
630    default:
631        dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
632    }
633}
634
635static int jz4740_mmc_get_ro(struct mmc_host *mmc)
636{
637    struct jz4740_mmc_host *host = mmc_priv(mmc);
638    if (!gpio_is_valid(host->pdata->gpio_read_only))
639        return -ENOSYS;
640
641    return gpio_get_value(host->pdata->gpio_read_only) ^
642        host->pdata->read_only_active_low;
643}
644
645static int jz4740_mmc_get_cd(struct mmc_host *mmc)
646{
647    struct jz4740_mmc_host *host = mmc_priv(mmc);
648    if (!gpio_is_valid(host->pdata->gpio_card_detect))
649        return -ENOSYS;
650
651    return gpio_get_value(host->pdata->gpio_card_detect) ^
652            host->pdata->card_detect_active_low;
653}
654
655static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
656{
657    struct jz4740_mmc_host *host = devid;
658
659    mmc_detect_change(host->mmc, HZ / 3);
660
661    return IRQ_HANDLED;
662}
663
664static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
665{
666    struct jz4740_mmc_host *host = mmc_priv(mmc);
667    if (enable)
668        jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
669    else
670        jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
671}
672
673static const struct mmc_host_ops jz4740_mmc_ops = {
674    .request = jz4740_mmc_request,
675    .set_ios = jz4740_mmc_set_ios,
676    .get_ro = jz4740_mmc_get_ro,
677    .get_cd = jz4740_mmc_get_cd,
678    .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
679};
680
681static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
682    JZ_GPIO_BULK_PIN(MSC_CMD),
683    JZ_GPIO_BULK_PIN(MSC_CLK),
684    JZ_GPIO_BULK_PIN(MSC_DATA0),
685    JZ_GPIO_BULK_PIN(MSC_DATA1),
686    JZ_GPIO_BULK_PIN(MSC_DATA2),
687    JZ_GPIO_BULK_PIN(MSC_DATA3),
688};
689
690static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
691{
692    int ret;
693    struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
694
695    if (!pdata)
696        return 0;
697
698    if (gpio_is_valid(pdata->gpio_card_detect)) {
699        ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
700        if (ret) {
701            dev_err(&pdev->dev, "Failed to request detect change gpio\n");
702            goto err;
703        }
704        gpio_direction_input(pdata->gpio_card_detect);
705    }
706
707    if (gpio_is_valid(pdata->gpio_read_only)) {
708        ret = gpio_request(pdata->gpio_read_only, "MMC read only");
709        if (ret) {
710            dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
711            goto err_free_gpio_card_detect;
712        }
713        gpio_direction_input(pdata->gpio_read_only);
714    }
715
716    if (gpio_is_valid(pdata->gpio_power)) {
717        ret = gpio_request(pdata->gpio_power, "MMC power");
718        if (ret) {
719            dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
720            goto err_free_gpio_read_only;
721        }
722        gpio_direction_output(pdata->gpio_power, pdata->power_active_low);
723    }
724
725    return 0;
726
727err_free_gpio_read_only:
728    if (gpio_is_valid(pdata->gpio_read_only))
729        gpio_free(pdata->gpio_read_only);
730err_free_gpio_card_detect:
731    if (gpio_is_valid(pdata->gpio_card_detect))
732        gpio_free(pdata->gpio_card_detect);
733err:
734    return ret;
735}
736
737static void jz4740_mmc_free_gpios(struct platform_device *pdev)
738{
739    struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
740
741    if (!pdata)
742        return;
743
744    if (gpio_is_valid(pdata->gpio_power))
745        gpio_free(pdata->gpio_power);
746    if (gpio_is_valid(pdata->gpio_read_only))
747        gpio_free(pdata->gpio_read_only);
748    if (gpio_is_valid(pdata->gpio_card_detect))
749        gpio_free(pdata->gpio_card_detect);
750}
751
752static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
753{
754    int ret;
755    struct mmc_host *mmc;
756    struct jz4740_mmc_host *host;
757    struct jz4740_mmc_platform_data *pdata;
758
759    pdata = pdev->dev.platform_data;
760
761    mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
762
763    if (!mmc) {
764        dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
765        return -ENOMEM;
766    }
767
768    host = mmc_priv(mmc);
769
770    host->irq = platform_get_irq(pdev, 0);
771
772    if (host->irq < 0) {
773        ret = host->irq;
774        dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
775        goto err_free_host;
776    }
777
778    host->clk = clk_get(&pdev->dev, "mmc");
779    if (!host->clk) {
780        ret = -ENOENT;
781        dev_err(&pdev->dev, "Failed to get mmc clock\n");
782        goto err_free_host;
783    }
784
785    host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
786
787    if (!host->mem) {
788        ret = -ENOENT;
789        dev_err(&pdev->dev, "Failed to get base platform memory\n");
790        goto err_clk_put;
791    }
792
793    host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
794                    pdev->name);
795
796    if (!host->mem) {
797        ret = -EBUSY;
798        dev_err(&pdev->dev, "Failed to request base memory region\n");
799        goto err_clk_put;
800    }
801
802    host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
803
804    if (!host->base) {
805        ret = -EBUSY;
806        dev_err(&pdev->dev, "Failed to ioremap base memory\n");
807        goto err_release_mem_region;
808    }
809
810    if (pdata && pdata->data_1bit)
811        ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
812    else
813        ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
814
815    if (ret) {
816        dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
817        goto err_iounmap;
818    }
819
820    ret = jz4740_mmc_request_gpios(pdev);
821    if (ret)
822        goto err_gpio_bulk_free;
823
824    mmc->ops = &jz4740_mmc_ops;
825    mmc->f_min = JZ_MMC_CLK_RATE / 128;
826    mmc->f_max = JZ_MMC_CLK_RATE;
827    mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
828    mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
829    mmc->caps |= MMC_CAP_SDIO_IRQ;
830    mmc->max_seg_size = 4096;
831    mmc->max_phys_segs = 128;
832
833    mmc->max_blk_size = (1 << 10) - 1;
834    mmc->max_blk_count = (1 << 15) - 1;
835    mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
836
837    host->mmc = mmc;
838    host->pdev = pdev;
839    host->pdata = pdata;
840    host->max_clock = JZ_MMC_CLK_RATE;
841    spin_lock_init(&host->lock);
842    host->irq_mask = 0xffff;
843
844    host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
845
846    if (host->card_detect_irq < 0) {
847        dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
848    } else {
849        ret = request_irq(host->card_detect_irq,
850                jz4740_mmc_card_detect_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC/SD detect changed", host);
851
852        if (ret) {
853            dev_err(&pdev->dev, "Failed to request card detect irq");
854            goto err_free_gpios;
855        }
856    }
857
858    ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, IRQF_DISABLED, "MMC/SD", host);
859    if (ret) {
860        dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
861        goto err_free_card_detect_irq;
862    }
863
864    jz4740_mmc_reset(host);
865    jz4740_mmc_clock_disable(host);
866    setup_timer(&host->timeout_timer, jz4740_mmc_timeout, (unsigned long)host);
867
868    platform_set_drvdata(pdev, host);
869    ret = mmc_add_host(mmc);
870
871    if (ret) {
872        dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
873        goto err_free_irq;
874    }
875    printk("JZ SD/MMC card driver registered\n");
876
877    return 0;
878
879err_free_irq:
880    free_irq(host->irq, host);
881err_free_card_detect_irq:
882    if (host->card_detect_irq >= 0)
883        free_irq(host->card_detect_irq, host);
884err_free_gpios:
885    jz4740_mmc_free_gpios(pdev);
886err_gpio_bulk_free:
887    if (pdata && pdata->data_1bit)
888        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
889    else
890        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
891err_iounmap:
892    iounmap(host->base);
893err_release_mem_region:
894    release_mem_region(host->mem->start, resource_size(host->mem));
895err_clk_put:
896    clk_put(host->clk);
897err_free_host:
898    platform_set_drvdata(pdev, NULL);
899    mmc_free_host(mmc);
900
901    return ret;
902}
903
904static int jz4740_mmc_remove(struct platform_device *pdev)
905{
906    struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
907    struct jz4740_mmc_platform_data *pdata = host->pdata;
908
909    del_timer_sync(&host->timeout_timer);
910    jz4740_mmc_disable_irq(host, 0xff);
911    jz4740_mmc_reset(host);
912
913    mmc_remove_host(host->mmc);
914
915    free_irq(host->irq, host);
916    if (host->card_detect_irq >= 0)
917        free_irq(host->card_detect_irq, host);
918
919    jz4740_mmc_free_gpios(pdev);
920    if (pdata && pdata->data_1bit)
921        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
922    else
923        jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
924
925    iounmap(host->base);
926    release_mem_region(host->mem->start, resource_size(host->mem));
927
928    clk_put(host->clk);
929
930    platform_set_drvdata(pdev, NULL);
931    mmc_free_host(host->mmc);
932
933    return 0;
934}
935
936#ifdef CONFIG_PM
937static int jz4740_mmc_suspend(struct device *dev)
938{
939    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
940    struct jz4740_mmc_platform_data *pdata = host->pdata;
941
942    mmc_suspend_host(host->mmc, PMSG_SUSPEND);
943
944    if (pdata && pdata->data_1bit)
945        jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
946    else
947        jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
948
949    return 0;
950}
951
952static int jz4740_mmc_resume(struct device *dev)
953{
954    struct jz4740_mmc_host *host = dev_get_drvdata(dev);
955    struct jz4740_mmc_platform_data *pdata = host->pdata;
956
957    if (pdata && pdata->data_1bit)
958        jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
959    else
960        jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
961
962    mmc_resume_host(host->mmc);
963
964    return 0;
965}
966
967struct dev_pm_ops jz4740_mmc_pm_ops = {
968    .suspend = jz4740_mmc_suspend,
969    .resume = jz4740_mmc_resume,
970    .poweroff = jz4740_mmc_suspend,
971    .restore = jz4740_mmc_resume,
972};
973
974#define jz4740_mmc_PM_OPS (&jz4740_mmc_pm_ops)
975#else
976#define jz4740_mmc_PM_OPS NULL
977#endif
978
979static struct platform_driver jz4740_mmc_driver = {
980    .probe = jz4740_mmc_probe,
981    .remove = jz4740_mmc_remove,
982    .driver = {
983        .name = "jz4740-mmc",
984        .owner = THIS_MODULE,
985        .pm = jz4740_mmc_PM_OPS,
986    },
987};
988
989static int __init jz4740_mmc_init(void) {
990    return platform_driver_register(&jz4740_mmc_driver);
991}
992module_init(jz4740_mmc_init);
993
994static void __exit jz4740_mmc_exit(void) {
995    platform_driver_unregister(&jz4740_mmc_driver);
996}
997module_exit(jz4740_mmc_exit);
998
999MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
1000MODULE_LICENSE("GPL");
1001MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1002

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