Root/target/linux/xburst/files-2.6.32/drivers/mtd/nand/jz4740_nand.c

1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC NAND controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
22
23#include <linux/mtd/jz4740_nand.h>
24#include <linux/gpio.h>
25
26#define JZ_REG_NAND_CTRL 0x50
27#define JZ_REG_NAND_ECC_CTRL 0x100
28#define JZ_REG_NAND_DATA 0x104
29#define JZ_REG_NAND_PAR0 0x108
30#define JZ_REG_NAND_PAR1 0x10C
31#define JZ_REG_NAND_PAR2 0x110
32#define JZ_REG_NAND_IRQ_STAT 0x114
33#define JZ_REG_NAND_IRQ_CTRL 0x118
34#define JZ_REG_NAND_ERR(x) (0x11C + (x << 2))
35
36#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
37#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
38#define JZ_NAND_ECC_CTRL_RS BIT(2)
39#define JZ_NAND_ECC_CTRL_RESET BIT(1)
40#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
41
42#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
43#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
44#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
45#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
46#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
47#define JZ_NAND_STATUS_ERROR BIT(0)
48
49#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT(x << 1)
50#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT((x << 1) + 1)
51
52#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
53#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
54#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
55
56struct jz_nand {
57    struct mtd_info mtd;
58    struct nand_chip chip;
59    void __iomem *base;
60    struct resource *mem;
61
62    struct jz_nand_platform_data *pdata;
63    bool is_reading;
64};
65
66static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
67{
68    return container_of(mtd, struct jz_nand, mtd);
69}
70
71static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
72{
73    struct jz_nand *nand = mtd_to_jz_nand(mtd);
74    struct nand_chip *chip = mtd->priv;
75    uint32_t reg;
76
77    if (ctrl & NAND_CTRL_CHANGE) {
78        BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
79        if (ctrl & NAND_ALE)
80            chip->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
81        else if (ctrl & NAND_CLE)
82            chip->IO_ADDR_W = JZ_NAND_CMD_ADDR;
83        else
84            chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
85
86        reg = readl(nand->base + JZ_REG_NAND_CTRL);
87        if ( ctrl & NAND_NCE )
88            reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
89        else
90            reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
91        writel(reg, nand->base + JZ_REG_NAND_CTRL);
92    }
93    if (dat != NAND_CMD_NONE)
94        writeb(dat, chip->IO_ADDR_W);
95}
96
97static int jz_nand_dev_ready(struct mtd_info *mtd)
98{
99    struct jz_nand *nand = mtd_to_jz_nand(mtd);
100    return gpio_get_value_cansleep(nand->pdata->busy_gpio);
101}
102
103static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
104{
105    struct jz_nand *nand = mtd_to_jz_nand(mtd);
106    uint32_t reg;
107
108
109    writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
110    reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
111
112    reg |= JZ_NAND_ECC_CTRL_RESET;
113    reg |= JZ_NAND_ECC_CTRL_ENABLE;
114    reg |= JZ_NAND_ECC_CTRL_RS;
115
116    switch(mode) {
117    case NAND_ECC_READ:
118        reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
119        nand->is_reading = true;
120        break;
121    case NAND_ECC_WRITE:
122        reg |= JZ_NAND_ECC_CTRL_ENCODING;
123        nand->is_reading = false;
124        break;
125    default:
126        break;
127    }
128
129    writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
130}
131
132
133static int jz_nand_calculate_ecc_rs(struct mtd_info* mtd, const uint8_t* dat,
134                    uint8_t *ecc_code)
135{
136    struct jz_nand *nand = mtd_to_jz_nand(mtd);
137    uint32_t reg, status;
138    int i;
139    static uint8_t all_ff_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f};
140
141    if (nand->is_reading)
142        return 0;
143
144    do {
145        status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
146    } while(!(status & JZ_NAND_STATUS_ENC_FINISH));
147
148    reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
149    reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
150    writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
151
152    for (i = 0; i < 9; ++i) {
153        ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
154    }
155
156    /* If the written data is completly 0xff, we also want to write 0xff as
157     * ecc, otherwise we will get in trouble when doing subpage writes. */
158    if (memcmp(ecc_code, all_ff_ecc, 9) == 0) {
159        memset(ecc_code, 0xff, 9);
160    }
161
162    return 0;
163}
164
165/*#define printkd printk*/
166#define printkd(...)
167
168static void correct_data(uint8_t *dat, int index, int mask)
169{
170    int offset = index & 0x7;
171    uint16_t data;
172    printkd("correct: ");
173
174    index += (index >> 3);
175
176    data = dat[index];
177    data |= dat[index+1] << 8;
178
179    printkd("0x%x -> ", data);
180
181    mask ^= (data >> offset) & 0x1ff;
182    data &= ~(0x1ff << offset);
183    data |= (mask << offset);
184
185    printkd("0x%x\n", data);
186
187    dat[index] = data & 0xff;
188    dat[index+1] = (data >> 8) & 0xff;
189}
190
191static int jz_nand_correct_ecc_rs(struct mtd_info* mtd, uint8_t *dat,
192                  uint8_t *read_ecc, uint8_t *calc_ecc)
193{
194    struct jz_nand *nand = mtd_to_jz_nand(mtd);
195    int i, error_count, index;
196    uint32_t reg, status, error;
197    uint32_t t;
198
199    t = read_ecc[0];
200
201    if (t == 0xff) {
202        for (i = 1; i < 9; ++i)
203            t &= read_ecc[i];
204
205        t &= dat[0];
206        t &= dat[nand->chip.ecc.size / 2];
207        t &= dat[nand->chip.ecc.size - 1];
208
209        if (t == 0xff) {
210            for (i = 1; i < nand->chip.ecc.size - 1; ++i)
211                t &= dat[i];
212            if (t == 0xff)
213                return 0;
214        }
215    }
216
217    for(i = 0; i < 9; ++i)
218        writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
219
220    reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
221    reg |= JZ_NAND_ECC_CTRL_PAR_READY;
222    writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
223
224    do {
225        status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
226    } while (!(status & JZ_NAND_STATUS_DEC_FINISH));
227
228    reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
229    reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
230    writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
231
232    if (status & JZ_NAND_STATUS_ERROR) {
233        if (status & JZ_NAND_STATUS_UNCOR_ERROR) {
234            printkd("uncorrectable ecc:");
235            for(i = 0; i < 9; ++i)
236                printkd(" 0x%x", read_ecc[i]);
237            printkd("\n");
238            printkd("uncorrectable data:");
239            for(i = 0; i < 32; ++i)
240                printkd(" 0x%x", dat[i]);
241            printkd("\n");
242            return -1;
243        }
244
245        error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
246
247        printkd("error_count: %d %x\n", error_count, status);
248
249        for(i = 0; i < error_count; ++i) {
250            error = readl(nand->base + JZ_REG_NAND_ERR(i));
251            index = ((error >> 16) & 0x1ff) - 1;
252            if (index >= 0 && index < 512) {
253                correct_data(dat, index, error & 0x1ff);
254            }
255        }
256
257        return error_count;
258    }
259
260    return 0;
261}
262
263
264
265#ifdef CONFIG_MTD_CMDLINE_PARTS
266static const char *part_probes[] = {"cmdline", NULL};
267#endif
268
269static int __devinit jz_nand_probe(struct platform_device *pdev)
270{
271    int ret;
272    struct jz_nand *nand;
273    struct nand_chip *chip;
274    struct mtd_info *mtd;
275    struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
276#ifdef CONFIG_MTD_PARTITIONS
277    struct mtd_partition *partition_info;
278    int num_partitions = 0;
279#endif
280
281    nand = kzalloc(sizeof(*nand), GFP_KERNEL);
282    if (!nand) {
283        dev_err(&pdev->dev, "Failed to allocate device structure.\n");
284        return -ENOMEM;
285    }
286
287    nand->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
288    if (!nand->mem) {
289        dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
290        ret = -ENOENT;
291        goto err_free;
292    }
293
294    nand->mem = request_mem_region(nand->mem->start, resource_size(nand->mem),
295                    pdev->name);
296
297    if (!nand->mem) {
298        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
299        ret = -EBUSY;
300        goto err_free;
301    }
302
303    nand->base = ioremap(nand->mem->start, resource_size(nand->mem));
304
305    if (!nand->base) {
306        dev_err(&pdev->dev, "Faild to ioremap mmio memory region\n");
307        ret = -EBUSY;
308        goto err_release_mem;
309    }
310
311    if (pdata && gpio_is_valid(pdata->busy_gpio)) {
312        ret = gpio_request(pdata->busy_gpio, "jz nand busy line");
313        if (ret) {
314            dev_err(&pdev->dev, "Failed to request busy gpio %d: %d\n",
315                    pdata->busy_gpio, ret);
316            goto err_iounmap;
317        }
318    }
319
320    mtd = &nand->mtd;
321    chip = &nand->chip;
322    mtd->priv = chip;
323    mtd->owner = THIS_MODULE;
324    mtd->name = "jz4740-nand";
325
326    chip->ecc.hwctl = jz_nand_hwctl;
327
328    chip->ecc.calculate = jz_nand_calculate_ecc_rs;
329    chip->ecc.correct = jz_nand_correct_ecc_rs;
330    chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
331    chip->ecc.size = 512;
332    chip->ecc.bytes = 9;
333    if (pdata)
334        chip->ecc.layout = pdata->ecc_layout;
335
336    chip->chip_delay = 50;
337    chip->cmd_ctrl = jz_nand_cmd_ctrl;
338
339    if (pdata && gpio_is_valid(pdata->busy_gpio))
340        chip->dev_ready = jz_nand_dev_ready;
341
342    chip->IO_ADDR_R = JZ_NAND_DATA_ADDR;
343    chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
344
345    nand->pdata = pdata;
346    platform_set_drvdata(pdev, nand);
347
348    ret = nand_scan_ident(mtd, 1);
349    if (ret) {
350        dev_err(&pdev->dev, "Failed to scan nand\n");
351        goto err_gpio_free;
352    }
353
354    if (pdata && pdata->ident_callback) {
355        pdata->ident_callback(pdev, chip, &pdata->partitions, &pdata->num_partitions);
356    }
357
358    ret = nand_scan_tail(mtd);
359    if (ret) {
360        dev_err(&pdev->dev, "Failed to scan nand\n");
361        goto err_gpio_free;
362    }
363
364#ifdef CONFIG_MTD_PARTITIONS
365#ifdef CONFIG_MTD_CMDLINE_PARTS
366    num_partitions = parse_mtd_partitions(mtd, part_probes,
367                        &partition_info, 0);
368#endif
369    if (num_partitions <= 0 && pdata) {
370        num_partitions = pdata->num_partitions;
371        partition_info = pdata->partitions;
372    }
373
374    if (num_partitions > 0)
375        ret = add_mtd_partitions(mtd, partition_info, num_partitions);
376    else
377#endif
378    ret = add_mtd_device(mtd);
379
380    if (ret) {
381        dev_err(&pdev->dev, "Failed to add mtd device\n");
382        goto err_nand_release;
383    }
384
385    dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
386
387    return 0;
388err_nand_release:
389    nand_release(&nand->mtd);
390err_gpio_free:
391    platform_set_drvdata(pdev, NULL);
392    gpio_free(pdata->busy_gpio);
393err_iounmap:
394    iounmap(nand->base);
395err_release_mem:
396    release_mem_region(nand->mem->start, resource_size(nand->mem));
397err_free:
398    kfree(nand);
399    return ret;
400}
401
402static void __devexit jz_nand_remove(struct platform_device *pdev)
403{
404    struct jz_nand *nand = platform_get_drvdata(pdev);
405
406    nand_release(&nand->mtd);
407
408    iounmap(nand->base);
409
410    release_mem_region(nand->mem->start, resource_size(nand->mem));
411
412    platform_set_drvdata(pdev, NULL);
413    kfree(nand);
414}
415
416struct platform_driver jz_nand_driver = {
417    .probe = jz_nand_probe,
418    .remove = __devexit_p(jz_nand_probe),
419    .driver = {
420        .name = "jz4740-nand",
421        .owner = THIS_MODULE,
422    },
423};
424
425static int __init jz_nand_init(void)
426{
427    return platform_driver_register(&jz_nand_driver);
428}
429module_init(jz_nand_init);
430
431static void __exit jz_nand_exit(void)
432{
433    platform_driver_unregister(&jz_nand_driver);
434}
435module_exit(jz_nand_exit);
436
437MODULE_LICENSE("GPL");
438MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
439MODULE_DESCRIPTION("NAND controller driver for JZ4720/JZ4740 SoC");
440MODULE_ALIAS("platform:jz4740-nand");
441MODULE_ALIAS("platform:jz4720-nand");
442

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