Root/target/linux/xburst/files-2.6.32/drivers/video/jz4740_fb.c

1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4720/JZ4740 SoC LCD framebuffer driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/types.h>
17#include <linux/platform_device.h>
18#include <linux/console.h>
19#include <linux/fb.h>
20#include <linux/module.h>
21#include <linux/dma-mapping.h>
22#include <linux/mutex.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25
26#include <linux/jz4740_fb.h>
27#include <asm/mach-jz4740/gpio.h>
28
29#define JZ_REG_LCD_CFG 0x00
30#define JZ_REG_LCD_VSYNC 0x04
31#define JZ_REG_LCD_HSYNC 0x08
32#define JZ_REG_LCD_VAT 0x0C
33#define JZ_REG_LCD_DAH 0x10
34#define JZ_REG_LCD_DAV 0x14
35#define JZ_REG_LCD_PS 0x18
36#define JZ_REG_LCD_CLS 0x1C
37#define JZ_REG_LCD_SPL 0x20
38#define JZ_REG_LCD_REV 0x24
39#define JZ_REG_LCD_CTRL 0x30
40#define JZ_REG_LCD_STATE 0x34
41#define JZ_REG_LCD_IID 0x38
42#define JZ_REG_LCD_DA0 0x40
43#define JZ_REG_LCD_SA0 0x44
44#define JZ_REG_LCD_FID0 0x48
45#define JZ_REG_LCD_CMD0 0x4C
46#define JZ_REG_LCD_DA1 0x50
47#define JZ_REG_LCD_SA1 0x54
48#define JZ_REG_LCD_FID1 0x58
49#define JZ_REG_LCD_CMD1 0x5C
50
51#define JZ_LCD_CFG_SLCD BIT(31)
52#define JZ_LCD_CFG_PS_DISABLE BIT(23)
53#define JZ_LCD_CFG_CLS_DISABLE BIT(22)
54#define JZ_LCD_CFG_SPL_DISABLE BIT(21)
55#define JZ_LCD_CFG_REV_DISABLE BIT(20)
56#define JZ_LCD_CFG_HSYNCM BIT(19)
57#define JZ_LCD_CFG_PCLKM BIT(18)
58#define JZ_LCD_CFG_INV BIT(17)
59#define JZ_LCD_CFG_SYNC_DIR BIT(16)
60#define JZ_LCD_CFG_PS_POLARITY BIT(15)
61#define JZ_LCD_CFG_CLS_POLARITY BIT(14)
62#define JZ_LCD_CFG_SPL_POLARITY BIT(13)
63#define JZ_LCD_CFG_REV_POLARITY BIT(12)
64#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
65#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
66#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
67#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
68#define JZ_LCD_CFG_18_BIT BIT(7)
69#define JZ_LCD_CFG_PDW BIT(5) | BIT(4)
70#define JZ_LCD_CFG_MODE_MASK 0xf
71
72#define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
73#define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
74#define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
75#define JZ_LCD_CTRL_RGB555 BIT(27)
76#define JZ_LCD_CTRL_OFUP BIT(26)
77#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
78#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
79#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
80#define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
81#define JZ_LCD_CTRL_EOF_IRQ BIT(13)
82#define JZ_LCD_CTRL_SOF_IRQ BIT(12)
83#define JZ_LCD_CTRL_OFU_IRQ BIT(11)
84#define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
85#define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
86#define JZ_LCD_CTRL_DD_IRQ BIT(8)
87#define JZ_LCD_CTRL_QDD_IRQ BIT(7)
88#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
89#define JZ_LCD_CTRL_LSB_FISRT BIT(5)
90#define JZ_LCD_CTRL_DISABLE BIT(4)
91#define JZ_LCD_CTRL_ENABLE BIT(3)
92#define JZ_LCD_CTRL_BPP_1 0x0
93#define JZ_LCD_CTRL_BPP_2 0x1
94#define JZ_LCD_CTRL_BPP_4 0x2
95#define JZ_LCD_CTRL_BPP_8 0x3
96#define JZ_LCD_CTRL_BPP_15_16 0x4
97#define JZ_LCD_CTRL_BPP_18_24 0x5
98
99#define JZ_LCD_CMD_SOF_IRQ BIT(15)
100#define JZ_LCD_CMD_EOF_IRQ BIT(16)
101#define JZ_LCD_CMD_ENABLE_PAL BIT(12)
102
103#define JZ_LCD_SYNC_MASK 0x3ff
104
105#define JZ_LCD_STATE_DISABLED BIT(0)
106
107struct jzfb_framedesc {
108    uint32_t next;
109    uint32_t addr;
110    uint32_t id;
111    uint32_t cmd;
112} __attribute__((packed));
113
114struct jzfb {
115    struct fb_info *fb;
116    struct platform_device *pdev;
117    void __iomem *base;
118    struct resource *mem;
119    struct jz4740_fb_platform_data *pdata;
120
121    size_t vidmem_size;
122    void *vidmem;
123    dma_addr_t vidmem_phys;
124    struct jzfb_framedesc *framedesc;
125    dma_addr_t framedesc_phys;
126
127    struct clk *ldclk;
128    struct clk *lpclk;
129
130    unsigned is_enabled:1;
131    struct mutex lock; /* Protecting against running enable/disable in paralell */
132
133    uint32_t pseudo_palette[256];
134};
135
136static struct fb_fix_screeninfo jzfb_fix __devinitdata = {
137    .id = "JZ4740 FB",
138    .type = FB_TYPE_PACKED_PIXELS,
139    .visual = FB_VISUAL_TRUECOLOR,
140    .xpanstep = 0,
141    .ypanstep = 0,
142    .ywrapstep = 0,
143    .accel = FB_ACCEL_NONE,
144};
145
146const static struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = {
147    JZ_GPIO_BULK_PIN(LCD_PCLK),
148    JZ_GPIO_BULK_PIN(LCD_HSYNC),
149    JZ_GPIO_BULK_PIN(LCD_VSYNC),
150    JZ_GPIO_BULK_PIN(LCD_DE),
151    JZ_GPIO_BULK_PIN(LCD_PS),
152    JZ_GPIO_BULK_PIN(LCD_REV),
153};
154
155const static struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
156    JZ_GPIO_BULK_PIN(LCD_DATA0),
157    JZ_GPIO_BULK_PIN(LCD_DATA1),
158    JZ_GPIO_BULK_PIN(LCD_DATA2),
159    JZ_GPIO_BULK_PIN(LCD_DATA3),
160    JZ_GPIO_BULK_PIN(LCD_DATA4),
161    JZ_GPIO_BULK_PIN(LCD_DATA5),
162    JZ_GPIO_BULK_PIN(LCD_DATA6),
163    JZ_GPIO_BULK_PIN(LCD_DATA7),
164    JZ_GPIO_BULK_PIN(LCD_DATA8),
165    JZ_GPIO_BULK_PIN(LCD_DATA9),
166    JZ_GPIO_BULK_PIN(LCD_DATA10),
167    JZ_GPIO_BULK_PIN(LCD_DATA11),
168    JZ_GPIO_BULK_PIN(LCD_DATA12),
169    JZ_GPIO_BULK_PIN(LCD_DATA13),
170    JZ_GPIO_BULK_PIN(LCD_DATA14),
171    JZ_GPIO_BULK_PIN(LCD_DATA15),
172    JZ_GPIO_BULK_PIN(LCD_DATA16),
173    JZ_GPIO_BULK_PIN(LCD_DATA17),
174};
175
176static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb)
177{
178    unsigned int num;
179
180    switch (jzfb->pdata->lcd_type) {
181    case JZ_LCD_TYPE_GENERIC_16_BIT:
182        num = 4;
183        break;
184    case JZ_LCD_TYPE_GENERIC_18_BIT:
185        num = 4;
186        break;
187    case JZ_LCD_TYPE_8BIT_SERIAL:
188        num = 3;
189        break;
190    default:
191        num = 0;
192        break;
193    }
194    return num;
195}
196
197static unsigned int jzfb_num_data_pins(struct jzfb *jzfb)
198{
199    unsigned int num;
200
201    switch (jzfb->pdata->lcd_type) {
202    case JZ_LCD_TYPE_GENERIC_16_BIT:
203        num = 16;
204        break;
205    case JZ_LCD_TYPE_GENERIC_18_BIT:
206        num = 19;
207        break;
208    case JZ_LCD_TYPE_8BIT_SERIAL:
209        num = 8;
210        break;
211    default:
212        num = 0;
213        break;
214    }
215    return num;
216}
217
218static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
219            unsigned transp, struct fb_info *fb)
220{
221    if (regno >= fb->cmap.len)
222        return -EINVAL;
223
224    red >>= 8;
225    green >>= 8;
226    blue >>= 8;
227
228    ((uint32_t*)fb->pseudo_palette)[regno] = red << 16 | green << 8 | blue;
229
230    return 0;
231}
232
233static int jzfb_get_controller_bpp(struct jzfb *jzfb)
234{
235    switch(jzfb->pdata->bpp) {
236    case 18:
237    case 24:
238        return 32;
239    case 15:
240        return 16;
241    default:
242        return jzfb->pdata->bpp;
243    }
244}
245
246static struct fb_videomode *jzfb_get_mode(struct jzfb* jzfb, struct fb_var_screeninfo *var)
247{
248    size_t i;
249    struct fb_videomode *mode = jzfb->pdata->modes;
250
251    for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) {
252        if (mode->xres == var->xres && mode->yres == var->yres)
253            return mode;
254    }
255
256    return NULL;
257}
258
259static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb)
260{
261    struct jzfb* jzfb = fb->par;
262    struct fb_videomode *mode;
263
264    if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) &&
265        var->bits_per_pixel != jzfb->pdata->bpp)
266        return -EINVAL;
267
268    mode = jzfb_get_mode(jzfb, var);
269    if (mode == NULL)
270        return -EINVAL;
271
272    fb_videomode_to_var(var, mode);
273
274    switch (jzfb->pdata->bpp) {
275    case 8:
276        break;
277    case 15:
278        var->red.offset = 10;
279        var->red.length = 5;
280        var->green.offset = 6;
281        var->green.length = 5;
282        var->blue.offset = 0;
283        var->blue.length = 5;
284        break;
285    case 16:
286        var->red.offset = 11;
287        var->red.length = 5;
288        var->green.offset = 6;
289        var->green.length = 6;
290        var->blue.offset = 0;
291        var->blue.length = 5;
292        break;
293    case 18:
294        var->red.offset = 16;
295        var->red.length = 6;
296        var->green.offset = 8;
297        var->green.length = 6;
298        var->blue.offset = 0;
299        var->blue.length = 6;
300        var->bits_per_pixel = 32;
301        break;
302    case 32:
303    case 24:
304        var->transp.offset = 24;
305        var->transp.length = 8;
306        var->red.offset = 16;
307        var->red.length = 8;
308        var->green.offset = 8;
309        var->green.length = 8;
310        var->blue.offset = 0;
311        var->blue.length = 8;
312        var->bits_per_pixel = 32;
313        break;
314    default:
315        break;
316    }
317
318    return 0;
319}
320
321static int jzfb_set_par(struct fb_info *info)
322{
323    struct jzfb* jzfb = info->par;
324    struct fb_var_screeninfo *var = &info->var;
325    struct fb_videomode *mode;
326    uint16_t hds, vds;
327    uint16_t hde, vde;
328    uint16_t ht, vt;
329    uint32_t ctrl;
330    uint32_t cfg;
331    unsigned long rate;
332
333    mode = jzfb_get_mode(jzfb, var);
334    if (mode == NULL)
335        return -EINVAL;
336
337    info->mode = mode;
338
339    hds = mode->hsync_len + mode->left_margin;
340    hde = hds + mode->xres;
341    ht = hde + mode->right_margin;
342
343    vds = mode->vsync_len + mode->upper_margin;
344    vde = vds + mode->yres;
345    vt = vde + mode->lower_margin;
346
347    ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
348
349    switch (jzfb->pdata->bpp) {
350    case 1:
351        ctrl |= JZ_LCD_CTRL_BPP_1;
352        break;
353    case 2:
354        ctrl |= JZ_LCD_CTRL_BPP_2;
355        break;
356    case 4:
357        ctrl |= JZ_LCD_CTRL_BPP_4;
358        break;
359    case 8:
360        ctrl |= JZ_LCD_CTRL_BPP_8;
361    break;
362    case 15:
363        ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */
364    case 16:
365        ctrl |= JZ_LCD_CTRL_BPP_15_16;
366        break;
367    case 18:
368    case 24:
369    case 32:
370        ctrl |= JZ_LCD_CTRL_BPP_18_24;
371        break;
372    default:
373        break;
374    }
375
376    cfg = 0;
377    cfg |= JZ_LCD_CFG_PS_DISABLE;
378    cfg |= JZ_LCD_CFG_CLS_DISABLE;
379    cfg |= JZ_LCD_CFG_SPL_DISABLE;
380    cfg |= JZ_LCD_CFG_REV_DISABLE;
381
382    if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
383        cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
384
385    if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
386        cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
387
388    if (jzfb->pdata->pixclk_falling_edge)
389        cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
390
391    if (jzfb->pdata->date_enable_active_low)
392        cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
393
394    if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT)
395        cfg |= JZ_LCD_CFG_18_BIT;
396
397    cfg |= jzfb->pdata->lcd_type & 0xf;
398
399    if (mode->pixclock) {
400        rate = PICOS2KHZ(mode->pixclock) * 1000;
401        mode->refresh = rate / vt / ht;
402    } else {
403        if (jzfb->pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL)
404            rate = mode->refresh * (vt + 2 * mode->xres) * ht;
405        else
406            rate = mode->refresh * vt * ht;
407
408        mode->pixclock = KHZ2PICOS(rate / 1000);
409    }
410
411    mutex_lock(&jzfb->lock);
412    if (!jzfb->is_enabled)
413        clk_enable(jzfb->ldclk);
414    else
415        ctrl |= JZ_LCD_CTRL_ENABLE;
416
417    writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC);
418    writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC);
419
420    writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT);
421
422    writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH);
423    writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV);
424
425    writel(cfg, jzfb->base + JZ_REG_LCD_CFG);
426
427    writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
428
429    if (!jzfb->is_enabled)
430        clk_disable(jzfb->ldclk);
431    mutex_unlock(&jzfb->lock);
432
433    clk_set_rate(jzfb->lpclk, rate);
434    clk_set_rate(jzfb->ldclk, rate * 3);
435
436    return 0;
437}
438
439static void jzfb_enable(struct jzfb *jzfb)
440{
441    uint32_t ctrl;
442
443    clk_enable(jzfb->ldclk);
444
445    jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
446    jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
447
448    writel(0, jzfb->base + JZ_REG_LCD_STATE);
449
450    writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
451
452    ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL);
453    ctrl |= JZ_LCD_CTRL_ENABLE;
454    ctrl &= ~JZ_LCD_CTRL_DISABLE;
455    writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
456}
457
458static void jzfb_disable(struct jzfb *jzfb)
459{
460    uint32_t ctrl;
461
462    ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL);
463    ctrl |= JZ_LCD_CTRL_DISABLE;
464    writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
465    do {
466        ctrl = readl(jzfb->base + JZ_REG_LCD_STATE);
467    } while (!(ctrl & JZ_LCD_STATE_DISABLED));
468
469    jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
470    jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
471
472    clk_disable(jzfb->ldclk);
473}
474
475static int jzfb_blank(int blank_mode, struct fb_info *info)
476{
477    struct jzfb* jzfb = info->par;
478
479    switch (blank_mode) {
480    case FB_BLANK_UNBLANK:
481        mutex_lock(&jzfb->lock);
482        if (jzfb->is_enabled) {
483            mutex_unlock(&jzfb->lock);
484            return 0;
485        }
486
487        jzfb_enable(jzfb);
488        jzfb->is_enabled = 1;
489
490        mutex_unlock(&jzfb->lock);
491
492        break;
493    default:
494        mutex_lock(&jzfb->lock);
495        if (!jzfb->is_enabled) {
496            mutex_unlock(&jzfb->lock);
497            return 0;
498        }
499
500        jzfb_disable(jzfb);
501
502        jzfb->is_enabled = 0;
503        mutex_unlock(&jzfb->lock);
504        break;
505    }
506
507    return 0;
508}
509
510static int jzfb_alloc_devmem(struct jzfb *jzfb)
511{
512    int max_videosize = 0;
513    struct fb_videomode *mode = jzfb->pdata->modes;
514    void *page;
515    int i;
516
517    for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) {
518        if (max_videosize < mode->xres * mode->yres)
519            max_videosize = mode->xres * mode->yres;
520    }
521
522    max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3;
523
524    jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev,
525                    sizeof(*jzfb->framedesc),
526                    &jzfb->framedesc_phys, GFP_KERNEL);
527
528    if (!jzfb->framedesc)
529        return -ENOMEM;
530
531    jzfb->vidmem_size = PAGE_ALIGN(max_videosize);
532    jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev,
533                        jzfb->vidmem_size,
534                        &jzfb->vidmem_phys, GFP_KERNEL);
535
536    if (!jzfb->vidmem) {
537        goto err_free_framedesc;
538    }
539
540    for (page = jzfb->vidmem;
541         page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size);
542         page += PAGE_SIZE) {
543        SetPageReserved(virt_to_page(page));
544    }
545
546
547    jzfb->framedesc->next = jzfb->framedesc_phys;
548    jzfb->framedesc->addr = jzfb->vidmem_phys;
549    jzfb->framedesc->id = 0xdeafbead;
550    jzfb->framedesc->cmd = 0;
551    jzfb->framedesc->cmd |= max_videosize / 4;
552
553    return 0;
554
555err_free_framedesc:
556        dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc),
557                jzfb->framedesc, jzfb->framedesc_phys);
558    return -ENOMEM;
559}
560
561static void jzfb_free_devmem(struct jzfb *jzfb)
562{
563    dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size,
564                jzfb->vidmem, jzfb->vidmem_phys);
565    dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc),
566                jzfb->framedesc, jzfb->framedesc_phys);
567}
568
569static struct fb_ops jzfb_ops = {
570    .owner = THIS_MODULE,
571    .fb_check_var = jzfb_check_var,
572    .fb_set_par = jzfb_set_par,
573    .fb_blank = jzfb_blank,
574    .fb_fillrect = sys_fillrect,
575    .fb_copyarea = sys_copyarea,
576    .fb_imageblit = sys_imageblit,
577    .fb_setcolreg = jzfb_setcolreg,
578};
579
580static int __devinit jzfb_probe(struct platform_device *pdev)
581{
582    int ret;
583    struct jzfb *jzfb;
584    struct fb_info *fb;
585    struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data;
586    struct resource *mem;
587
588    if (!pdata) {
589        dev_err(&pdev->dev, "Missing platform data\n");
590        return -ENOENT;
591    }
592
593    mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
594
595    if (!mem) {
596        dev_err(&pdev->dev, "Failed to get register memory resource\n");
597        return -ENOENT;
598    }
599
600    mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
601
602    if (!mem) {
603        dev_err(&pdev->dev, "Failed to request register memory region\n");
604        return -EBUSY;
605    }
606
607
608    fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev);
609
610    if (!fb) {
611        dev_err(&pdev->dev, "Failed to allocate framebuffer device\n");
612        ret = -ENOMEM;
613        goto err_release_mem_region;
614    }
615
616    fb->fbops = &jzfb_ops;
617    fb->flags = FBINFO_DEFAULT;
618
619    jzfb = fb->par;
620    jzfb->pdev = pdev;
621    jzfb->pdata = pdata;
622    jzfb->mem = mem;
623
624    jzfb->ldclk = clk_get(&pdev->dev, "lcd");
625    jzfb->lpclk = clk_get(&pdev->dev, "lcd_pclk");
626
627    if (IS_ERR(jzfb->ldclk)) {
628        ret = PTR_ERR(jzfb->ldclk);
629        dev_err(&pdev->dev, "Faild to get device clock: %d\n", ret);
630        goto err_framebuffer_release;
631    }
632
633    if (IS_ERR(jzfb->lpclk)) {
634        ret = PTR_ERR(jzfb->ldclk);
635        dev_err(&pdev->dev, "Faild to get pixel clock: %d\n", ret);
636        goto err_framebuffer_release;
637    }
638
639
640    jzfb->base = ioremap(mem->start, resource_size(mem));
641
642    if (!jzfb->base) {
643        dev_err(&pdev->dev, "Failed to ioremap register memory region\n");
644        ret = -EBUSY;
645        goto err_framebuffer_release;
646    }
647
648    platform_set_drvdata(pdev, jzfb);
649
650    fb_videomode_to_modelist(pdata->modes, pdata->num_modes,
651                 &fb->modelist);
652    fb->mode = pdata->modes;
653
654    fb_videomode_to_var(&fb->var, fb->mode);
655    fb->var.bits_per_pixel = pdata->bpp;
656    jzfb_check_var(&fb->var, fb);
657
658    ret = jzfb_alloc_devmem(jzfb);
659    if (ret) {
660        dev_err(&pdev->dev, "Failed to allocate video memory\n");
661        goto err_iounmap;
662    }
663
664    fb->fix = jzfb_fix;
665    fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8;
666    fb->fix.mmio_start = mem->start;
667    fb->fix.mmio_len = resource_size(mem);
668    fb->fix.smem_start = jzfb->vidmem_phys;
669    fb->fix.smem_len = fb->fix.line_length * fb->var.yres;
670    fb->screen_base = jzfb->vidmem;
671    fb->pseudo_palette = jzfb->pseudo_palette;
672
673    fb_alloc_cmap(&fb->cmap, 256, 0);
674
675    mutex_init(&jzfb->lock);
676
677    clk_enable(jzfb->ldclk);
678    jzfb->is_enabled = 1;
679
680    writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
681    jzfb_set_par(fb);
682
683    jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
684    jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
685
686    ret = register_framebuffer(fb);
687    if (ret) {
688        dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret);
689        goto err_free_devmem;
690    }
691
692    jzfb->fb = fb;
693
694    return 0;
695err_free_devmem:
696    jzfb_free_devmem(jzfb);
697err_iounmap:
698    iounmap(jzfb->base);
699err_framebuffer_release:
700    framebuffer_release(fb);
701err_release_mem_region:
702    release_mem_region(mem->start, resource_size(mem));
703    return ret;
704}
705
706static int __devexit jzfb_remove(struct platform_device *pdev)
707{
708    struct jzfb *jzfb = platform_get_drvdata(pdev);
709
710    jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
711    jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
712    iounmap(jzfb->base);
713    release_mem_region(jzfb->mem->start, resource_size(jzfb->mem));
714    jzfb_free_devmem(jzfb);
715    platform_set_drvdata(pdev, NULL);
716    framebuffer_release(jzfb->fb);
717    return 0;
718}
719
720#ifdef CONFIG_PM
721
722static int jzfb_suspend(struct device *dev)
723{
724    struct jzfb *jzfb = dev_get_drvdata(dev);
725
726    acquire_console_sem();
727    fb_set_suspend(jzfb->fb, 1);
728    release_console_sem();
729
730    mutex_lock(&jzfb->lock);
731    if (jzfb->is_enabled)
732        jzfb_disable(jzfb);
733    mutex_unlock(&jzfb->lock);
734
735    return 0;
736}
737
738static int jzfb_resume(struct device *dev)
739{
740    struct jzfb *jzfb = dev_get_drvdata(dev);
741    clk_enable(jzfb->ldclk);
742
743    mutex_lock(&jzfb->lock);
744    if (jzfb->is_enabled)
745        jzfb_enable(jzfb);
746    mutex_unlock(&jzfb->lock);
747
748    acquire_console_sem();
749    fb_set_suspend(jzfb->fb, 0);
750    release_console_sem();
751
752    return 0;
753}
754
755static const struct dev_pm_ops jzfb_pm_ops = {
756    .suspend = jzfb_suspend,
757    .resume = jzfb_resume,
758    .poweroff = jzfb_suspend,
759    .restore = jzfb_resume,
760};
761
762#define JZFB_PM_OPS (&jzfb_pm_ops)
763
764#else
765#define JZFB_PM_OPS NULL
766#endif
767
768static struct platform_driver jzfb_driver = {
769    .probe = jzfb_probe,
770    .remove = __devexit_p(jzfb_remove),
771
772    .driver = {
773        .name = "jz4740-fb",
774        .pm = JZFB_PM_OPS,
775    },
776};
777
778int __init jzfb_init(void)
779{
780    return platform_driver_register(&jzfb_driver);
781}
782module_init(jzfb_init);
783
784void __exit jzfb_exit(void)
785{
786    platform_driver_unregister(&jzfb_driver);
787}
788module_exit(jzfb_exit);
789
790MODULE_LICENSE("GPL");
791MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
792MODULE_DESCRIPTION("JZ4720/JZ4740 SoC LCD framebuffer driver");
793MODULE_ALIAS("platform:jz4740-fb");
794MODULE_ALIAS("platform:jz4720-fb");
795

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