Root/package/ltq-dsl/src/ifxmips_atm_core.h

1/******************************************************************************
2**
3** FILE NAME : ifxmips_atm_core.h
4** PROJECT : UEIP
5** MODULES : ATM
6**
7** DATE : 7 Jul 2009
8** AUTHOR : Xu Liang
9** DESCRIPTION : ATM driver header file (core functions)
10** COPYRIGHT : Copyright (c) 2006
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 17 JUN 2009 Xu Liang Init Version
22*******************************************************************************/
23
24#ifndef IFXMIPS_ATM_CORE_H
25#define IFXMIPS_ATM_CORE_H
26
27
28#include "ifxmips_compat.h"
29#include "ifx_atm.h"
30#include "ifxmips_atm_ppe_common.h"
31#include "ifxmips_atm_fw_regs_common.h"
32
33
34
35/*
36 * ####################################
37 * Definition
38 * ####################################
39 */
40
41/*
42 * Compile Options
43 */
44
45#define ENABLE_DEBUG 1
46
47#define ENABLE_ASSERT 1
48
49#define INLINE
50
51#define DEBUG_DUMP_SKB 1
52
53#define DEBUG_QOS 1
54
55#define ENABLE_DBG_PROC 1
56
57#define ENABLE_FW_PROC 1
58
59#ifdef CONFIG_IFX_ATM_TASKLET
60  #define ENABLE_TASKLET 1
61#endif
62
63
64/*
65 * Debug/Assert/Error Message
66 */
67
68#define DBG_ENABLE_MASK_ERR (1 << 0)
69#define DBG_ENABLE_MASK_DEBUG_PRINT (1 << 1)
70#define DBG_ENABLE_MASK_ASSERT (1 << 2)
71#define DBG_ENABLE_MASK_DUMP_SKB_RX (1 << 8)
72#define DBG_ENABLE_MASK_DUMP_SKB_TX (1 << 9)
73#define DBG_ENABLE_MASK_DUMP_QOS (1 << 10)
74#define DBG_ENABLE_MASK_DUMP_INIT (1 << 11)
75#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT)
76
77#define err(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
78
79#if defined(ENABLE_DEBUG) && ENABLE_DEBUG
80  #undef dbg
81  #define dbg(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
82#else
83  #if !defined(dbg)
84    #define dbg(format, arg...)
85  #endif
86#endif
87
88#if defined(ENABLE_ASSERT) && ENABLE_ASSERT
89  #define ASSERT(cond, format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
90#else
91  #define ASSERT(cond, format, arg...)
92#endif
93
94
95/*
96 * Constants
97 */
98#define DEFAULT_TX_LINK_RATE 3200 // in cells
99
100/*
101 * ATM Port, QSB Queue, DMA RX/TX Channel Parameters
102 */
103#define ATM_PORT_NUMBER 2
104#define MAX_QUEUE_NUMBER 16
105#define OAM_RX_QUEUE 15
106#define QSB_RESERVE_TX_QUEUE 0
107#define FIRST_QSB_QID 1
108#define MAX_PVC_NUMBER (MAX_QUEUE_NUMBER - FIRST_QSB_QID)
109#define MAX_RX_DMA_CHANNEL_NUMBER 8
110#define MAX_TX_DMA_CHANNEL_NUMBER 16
111#define DATA_BUFFER_ALIGNMENT EMA_ALIGNMENT
112#define DESC_ALIGNMENT 8
113#define DEFAULT_RX_HUNT_BITTH 4
114
115/*
116 * RX DMA Channel Allocation
117 */
118#define RX_DMA_CH_OAM 0
119#define RX_DMA_CH_AAL 1
120#define RX_DMA_CH_TOTAL 2
121#define RX_DMA_CH_OAM_DESC_LEN 32
122#define RX_DMA_CH_OAM_BUF_SIZE (CELL_SIZE & ~15)
123#define RX_DMA_CH_AAL_BUF_SIZE (2048 - 48)
124
125/*
126 * OAM Constants
127 */
128#define OAM_HTU_ENTRY_NUMBER 3
129#define OAM_F4_SEG_HTU_ENTRY 0
130#define OAM_F4_TOT_HTU_ENTRY 1
131#define OAM_F5_HTU_ENTRY 2
132#define OAM_F4_CELL_ID 0
133#define OAM_F5_CELL_ID 15
134//#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
135// #undef OAM_HTU_ENTRY_NUMBER
136// #define OAM_HTU_ENTRY_NUMBER 4
137// #define OAM_ARQ_HTU_ENTRY 3
138//#endif
139
140/*
141 * RX Frame Definitions
142 */
143#define MAX_RX_PACKET_ALIGN_BYTES 3
144#define MAX_RX_PACKET_PADDING_BYTES 3
145#define RX_INBAND_TRAILER_LENGTH 8
146#define MAX_RX_FRAME_EXTRA_BYTES (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
147
148/*
149 * TX Frame Definitions
150 */
151#define MAX_TX_HEADER_ALIGN_BYTES 12
152#define MAX_TX_PACKET_ALIGN_BYTES 3
153#define MAX_TX_PACKET_PADDING_BYTES 3
154#define TX_INBAND_HEADER_LENGTH 8
155#define MAX_TX_FRAME_EXTRA_BYTES (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
156
157/*
158 * Cell Constant
159 */
160#define CELL_SIZE ATM_AAL0_SDU
161
162
163
164/*
165 * ####################################
166 * Data Type
167 * ####################################
168 */
169
170typedef struct {
171    unsigned int h;
172    unsigned int l;
173} ppe_u64_t;
174
175struct port {
176    unsigned int tx_max_cell_rate;
177    unsigned int tx_current_cell_rate;
178
179    struct atm_dev *dev;
180};
181
182struct connection {
183    struct atm_vcc *vcc;
184
185    volatile struct tx_descriptor
186                           *tx_desc;
187    unsigned int tx_desc_pos;
188    struct sk_buff **tx_skb;
189
190    unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */
191    unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */
192
193    unsigned int port;
194};
195
196struct atm_priv_data {
197    unsigned long conn_table;
198    struct connection conn[MAX_PVC_NUMBER];
199
200    volatile struct rx_descriptor
201                           *aal_desc;
202    unsigned int aal_desc_pos;
203
204    volatile struct rx_descriptor
205                           *oam_desc;
206    unsigned char *oam_buf;
207    unsigned int oam_desc_pos;
208
209    struct port port[ATM_PORT_NUMBER];
210
211    unsigned int wrx_pdu; /* successfully received AAL5 packet */
212    unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */
213    unsigned int wtx_pdu; /* successfully tranmitted AAL5 packet */
214    unsigned int wtx_err_pdu; /* error AAL5 packet */
215    unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */
216
217    ppe_u64_t wrx_total_byte;
218    ppe_u64_t wtx_total_byte;
219    unsigned int prev_wrx_total_byte;
220    unsigned int prev_wtx_total_byte;
221
222    void *aal_desc_base;
223    void *oam_desc_base;
224    void *oam_buf_base;
225    void *tx_desc_base;
226    void *tx_skb_base;
227};
228
229
230
231/*
232 * ####################################
233 * Declaration
234 * ####################################
235 */
236
237extern unsigned int ifx_atm_dbg_enable;
238
239extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor);
240
241extern void ifx_atm_init_chip(void);
242extern void ifx_atm_uninit_chip(void);
243
244extern int ifx_pp32_start(int pp32);
245extern void ifx_pp32_stop(int pp32);
246
247
248
249#endif // IFXMIPS_ATM_CORE_H
250

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