| 1 | #ifndef IFXMIPS_ATM_PPE_COMMON_H |
| 2 | #define IFXMIPS_ATM_PPE_COMMON_H |
| 3 | |
| 4 | #if defined(CONFIG_LANTIQ) |
| 5 | #include "ifxmips_atm_ppe_danube.h" |
| 6 | #define CONFIG_DANUBE |
| 7 | #elif defined(CONFIG_DANUBE) |
| 8 | #include "ifxmips_atm_ppe_danube.h" |
| 9 | #elif defined(CONFIG_AMAZON_SE) |
| 10 | #include "ifxmips_atm_ppe_amazon_se.h" |
| 11 | #elif defined(CONFIG_AR9) |
| 12 | #include "ifxmips_atm_ppe_ar9.h" |
| 13 | #elif defined(CONFIG_VR9) |
| 14 | #include "ifxmips_atm_ppe_vr9.h" |
| 15 | #else |
| 16 | #error Platform is not specified! |
| 17 | #endif |
| 18 | |
| 19 | |
| 20 | /* |
| 21 | * Code/Data Memory (CDM) Interface Configuration Register |
| 22 | */ |
| 23 | #define CDM_CFG PPE_REG_ADDR(0x0100) |
| 24 | |
| 25 | #define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2) |
| 26 | #define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1)) |
| 27 | |
| 28 | #define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value) |
| 29 | #define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0) |
| 30 | |
| 31 | /* |
| 32 | * QSB Internal Cell Delay Variation Register |
| 33 | */ |
| 34 | #define QSB_ICDV QSB_CONF_REG_ADDR(0x0007) |
| 35 | |
| 36 | #define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0) |
| 37 | |
| 38 | #define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value) |
| 39 | |
| 40 | /* |
| 41 | * QSB Scheduler Burst Limit Register |
| 42 | */ |
| 43 | #define QSB_SBL QSB_CONF_REG_ADDR(0x0009) |
| 44 | |
| 45 | #define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0) |
| 46 | |
| 47 | #define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value) |
| 48 | |
| 49 | /* |
| 50 | * QSB Configuration Register |
| 51 | */ |
| 52 | #define QSB_CFG QSB_CONF_REG_ADDR(0x000A) |
| 53 | |
| 54 | #define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0) |
| 55 | |
| 56 | #define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value) |
| 57 | |
| 58 | /* |
| 59 | * QSB RAM Transfer Table Register |
| 60 | */ |
| 61 | #define QSB_RTM QSB_CONF_REG_ADDR(0x000B) |
| 62 | |
| 63 | #define QSB_RTM_DM (*QSB_RTM) |
| 64 | |
| 65 | #define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF) |
| 66 | |
| 67 | /* |
| 68 | * QSB RAM Transfer Data Register |
| 69 | */ |
| 70 | #define QSB_RTD QSB_CONF_REG_ADDR(0x000C) |
| 71 | |
| 72 | #define QSB_RTD_TTV (*QSB_RTD) |
| 73 | |
| 74 | #define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF) |
| 75 | |
| 76 | /* |
| 77 | * QSB RAM Access Register |
| 78 | */ |
| 79 | #define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D) |
| 80 | |
| 81 | #define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31)) |
| 82 | #define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24) |
| 83 | #define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16)) |
| 84 | #define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0) |
| 85 | |
| 86 | #define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0) |
| 87 | #define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value) |
| 88 | #define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0) |
| 89 | #define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value) |
| 90 | |
| 91 | /* |
| 92 | * QSB Queue Scheduling and Shaping Definitions |
| 93 | */ |
| 94 | #define QSB_WFQ_NONUBR_MAX 0x3f00 |
| 95 | #define QSB_WFQ_UBR_BYPASS 0x3fff |
| 96 | #define QSB_TP_TS_MAX 65472 |
| 97 | #define QSB_TAUS_MAX 64512 |
| 98 | #define QSB_GCR_MIN 18 |
| 99 | |
| 100 | /* |
| 101 | * QSB Constant |
| 102 | */ |
| 103 | #define QSB_RAMAC_RW_READ 0 |
| 104 | #define QSB_RAMAC_RW_WRITE 1 |
| 105 | |
| 106 | #define QSB_RAMAC_TSEL_QPT 0x01 |
| 107 | #define QSB_RAMAC_TSEL_SCT 0x02 |
| 108 | #define QSB_RAMAC_TSEL_SPT 0x03 |
| 109 | #define QSB_RAMAC_TSEL_VBR 0x08 |
| 110 | |
| 111 | #define QSB_RAMAC_LH_LOW 0 |
| 112 | #define QSB_RAMAC_LH_HIGH 1 |
| 113 | |
| 114 | #define QSB_QPT_SET_MASK 0x0 |
| 115 | #define QSB_QVPT_SET_MASK 0x0 |
| 116 | #define QSB_SET_SCT_MASK 0x0 |
| 117 | #define QSB_SET_SPT_MASK 0x0 |
| 118 | #define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF |
| 119 | |
| 120 | #define QSB_SPT_SBV_VALID (1 << 31) |
| 121 | #define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0) |
| 122 | #define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value) |
| 123 | |
| 124 | /* |
| 125 | * QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry |
| 126 | */ |
| 127 | #if defined(__BIG_ENDIAN) |
| 128 | union qsb_queue_parameter_table { |
| 129 | struct { |
| 130 | unsigned int res1 :1; |
| 131 | unsigned int vbr :1; |
| 132 | unsigned int wfqf :14; |
| 133 | unsigned int tp :16; |
| 134 | } bit; |
| 135 | u32 dword; |
| 136 | }; |
| 137 | |
| 138 | union qsb_queue_vbr_parameter_table { |
| 139 | struct { |
| 140 | unsigned int taus :16; |
| 141 | unsigned int ts :16; |
| 142 | } bit; |
| 143 | u32 dword; |
| 144 | }; |
| 145 | #else |
| 146 | union qsb_queue_parameter_table { |
| 147 | struct { |
| 148 | unsigned int tp :16; |
| 149 | unsigned int wfqf :14; |
| 150 | unsigned int vbr :1; |
| 151 | unsigned int res1 :1; |
| 152 | } bit; |
| 153 | u32 dword; |
| 154 | }; |
| 155 | |
| 156 | union qsb_queue_vbr_parameter_table { |
| 157 | struct { |
| 158 | unsigned int ts :16; |
| 159 | unsigned int taus :16; |
| 160 | } bit; |
| 161 | u32 dword; |
| 162 | }; |
| 163 | #endif // defined(__BIG_ENDIAN) |
| 164 | |
| 165 | /* |
| 166 | * Mailbox IGU0 Registers |
| 167 | */ |
| 168 | #define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200) |
| 169 | #define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201) |
| 170 | #define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202) |
| 171 | #define MBOX_IGU0_IER PPE_REG_ADDR(0x0203) |
| 172 | |
| 173 | #define MBOX_IGU0_ISRS_SET(n) (1 << (n)) |
| 174 | #define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n)) |
| 175 | #define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n))) |
| 176 | #define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n))) |
| 177 | #define MBOX_IGU0_IER_EN_SET(n) (1 << (n)) |
| 178 | |
| 179 | /* |
| 180 | * Mailbox IGU1 Registers |
| 181 | */ |
| 182 | #define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204) |
| 183 | #define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205) |
| 184 | #define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206) |
| 185 | #define MBOX_IGU1_IER PPE_REG_ADDR(0x0207) |
| 186 | |
| 187 | #define MBOX_IGU1_ISRS_SET(n) (1 << (n)) |
| 188 | #define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n)) |
| 189 | #define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n))) |
| 190 | #define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n))) |
| 191 | #define MBOX_IGU1_IER_EN_SET(n) (1 << (n)) |
| 192 | |
| 193 | /* |
| 194 | * Mailbox IGU3 Registers |
| 195 | */ |
| 196 | #define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214) |
| 197 | #define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215) |
| 198 | #define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216) |
| 199 | #define MBOX_IGU3_IER PPE_REG_ADDR(0x0217) |
| 200 | |
| 201 | #define MBOX_IGU3_ISRS_SET(n) (1 << (n)) |
| 202 | #define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n)) |
| 203 | #define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n))) |
| 204 | #define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n))) |
| 205 | #define MBOX_IGU3_IER_EN_SET(n) (1 << (n)) |
| 206 | |
| 207 | /* |
| 208 | * RTHA/TTHA Registers |
| 209 | */ |
| 210 | #define SFSM_STATE0 PPE_REG_ADDR(0x0410) |
| 211 | #define SFSM_STATE1 PPE_REG_ADDR(0x0411) |
| 212 | #define SFSM_DBA0 PPE_REG_ADDR(0x0412) |
| 213 | #define SFSM_DBA1 PPE_REG_ADDR(0x0413) |
| 214 | #define SFSM_CBA0 PPE_REG_ADDR(0x0414) |
| 215 | #define SFSM_CBA1 PPE_REG_ADDR(0x0415) |
| 216 | #define SFSM_CFG0 PPE_REG_ADDR(0x0416) |
| 217 | #define SFSM_CFG1 PPE_REG_ADDR(0x0417) |
| 218 | #define SFSM_PGCNT0 PPE_REG_ADDR(0x041C) |
| 219 | #define SFSM_PGCNT1 PPE_REG_ADDR(0x041D) |
| 220 | #define FFSM_DBA0 PPE_REG_ADDR(0x0508) |
| 221 | #define FFSM_DBA1 PPE_REG_ADDR(0x0509) |
| 222 | #define FFSM_CFG0 PPE_REG_ADDR(0x050A) |
| 223 | #define FFSM_CFG1 PPE_REG_ADDR(0x050B) |
| 224 | #define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E) |
| 225 | #define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F) |
| 226 | #define FFSM_PGCNT0 PPE_REG_ADDR(0x0514) |
| 227 | #define FFSM_PGCNT1 PPE_REG_ADDR(0x0515) |
| 228 | |
| 229 | |
| 230 | |
| 231 | #endif // IFXMIPS_ATM_PPE_COMMON_H |
| 232 | |
