Root/package/ltq-dsl/src/ifxmips_mei_interface.h

1/******************************************************************************
2
3                               Copyright (c) 2009
4                            Infineon Technologies AG
5                     Am Campeon 1-12; 81726 Munich, Germany
6
7  For licensing information, see the file 'LICENSE' in the root folder of
8  this software module.
9
10******************************************************************************/
11
12#ifndef IFXMIPS_MEI_H
13#define IFXMIPS_MEI_H
14
15#define CONFIG_DANUBE 1
16
17#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
18#error Platform undefined!!!
19#endif
20
21#ifdef IFX_MEI_BSP
22/** This is the character datatype. */
23typedef char DSL_char_t;
24/** This is the unsigned 8-bit datatype. */
25typedef unsigned char DSL_uint8_t;
26/** This is the signed 8-bit datatype. */
27typedef signed char DSL_int8_t;
28/** This is the unsigned 16-bit datatype. */
29typedef unsigned short DSL_uint16_t;
30/** This is the signed 16-bit datatype. */
31typedef signed short DSL_int16_t;
32/** This is the unsigned 32-bit datatype. */
33typedef unsigned long DSL_uint32_t;
34/** This is the signed 32-bit datatype. */
35typedef signed long DSL_int32_t;
36/** This is the float datatype. */
37typedef float DSL_float_t;
38/** This is the void datatype. */
39typedef void DSL_void_t;
40/** integer type, width is depending on processor arch */
41typedef int DSL_int_t;
42/** unsigned integer type, width is depending on processor arch */
43typedef unsigned int DSL_uint_t;
44typedef struct file DSL_DRV_file_t;
45typedef struct inode DSL_DRV_inode_t;
46
47/**
48 * Defines all possible CMV groups
49 * */
50typedef enum {
51   DSL_CMV_GROUP_CNTL = 1,
52   DSL_CMV_GROUP_STAT = 2,
53   DSL_CMV_GROUP_INFO = 3,
54   DSL_CMV_GROUP_TEST = 4,
55   DSL_CMV_GROUP_OPTN = 5,
56   DSL_CMV_GROUP_RATE = 6,
57   DSL_CMV_GROUP_PLAM = 7,
58   DSL_CMV_GROUP_CNFG = 8
59} DSL_CmvGroup_t;
60/**
61 * Defines all opcode types
62 * */
63typedef enum {
64   H2D_CMV_READ = 0x00,
65   H2D_CMV_WRITE = 0x04,
66   H2D_CMV_INDICATE_REPLY = 0x10,
67   H2D_ERROR_OPCODE_UNKNOWN =0x20,
68   H2D_ERROR_CMV_UNKNOWN =0x30,
69
70   D2H_CMV_READ_REPLY =0x01,
71   D2H_CMV_WRITE_REPLY = 0x05,
72   D2H_CMV_INDICATE = 0x11,
73   D2H_ERROR_OPCODE_UNKNOWN = 0x21,
74   D2H_ERROR_CMV_UNKNOWN = 0x31,
75   D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
76   D2H_ERROR_CMV_WRITE_ONLY = 0x51,
77   D2H_ERROR_CMV_READ_ONLY = 0x61,
78
79   H2D_DEBUG_READ_DM = 0x02,
80   H2D_DEBUG_READ_PM = 0x06,
81   H2D_DEBUG_WRITE_DM = 0x0a,
82   H2D_DEBUG_WRITE_PM = 0x0e,
83
84   D2H_DEBUG_READ_DM_REPLY = 0x03,
85   D2H_DEBUG_READ_FM_REPLY = 0x07,
86   D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
87   D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
88   D2H_ERROR_ADDR_UNKNOWN = 0x33,
89
90   D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
91} DSL_CmvOpcode_t;
92
93/* mutex macros */
94#define MEI_MUTEX_INIT(id,flag) \
95        sema_init(&id,flag)
96#define MEI_MUTEX_LOCK(id) \
97        down_interruptible(&id)
98#define MEI_MUTEX_UNLOCK(id) \
99        up(&id)
100#define MEI_WAIT(ms) \
101        {\
102                set_current_state(TASK_INTERRUPTIBLE);\
103                schedule_timeout(ms);\
104        }
105#define MEI_INIT_WAKELIST(name,queue) \
106        init_waitqueue_head(&queue)
107
108/* wait for an event, timeout is measured in ms */
109#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
110        interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)
111#define MEI_WAKEUP_EVENT(ev)\
112        wake_up_interruptible(&ev)
113#endif /* IFX_MEI_BSP */
114
115/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
116#define ME_DX_DATA (0x0000)
117#define ME_VERSION (0x0004)
118#define ME_ARC_GP_STAT (0x0008)
119#define ME_DX_STAT (0x000C)
120#define ME_DX_AD (0x0010)
121#define ME_DX_MWS (0x0014)
122#define ME_ME2ARC_INT (0x0018)
123#define ME_ARC2ME_STAT (0x001C)
124#define ME_ARC2ME_MASK (0x0020)
125#define ME_DBG_WR_AD (0x0024)
126#define ME_DBG_RD_AD (0x0028)
127#define ME_DBG_DATA (0x002C)
128#define ME_DBG_DECODE (0x0030)
129#define ME_CONFIG (0x0034)
130#define ME_RST_CTRL (0x0038)
131#define ME_DBG_MASTER (0x003C)
132#define ME_CLK_CTRL (0x0040)
133#define ME_BIST_CTRL (0x0044)
134#define ME_BIST_STAT (0x0048)
135#define ME_XDATA_BASE_SH (0x004c)
136#define ME_XDATA_BASE (0x0050)
137#define ME_XMEM_BAR_BASE (0x0054)
138#define ME_XMEM_BAR0 (0x0054)
139#define ME_XMEM_BAR1 (0x0058)
140#define ME_XMEM_BAR2 (0x005C)
141#define ME_XMEM_BAR3 (0x0060)
142#define ME_XMEM_BAR4 (0x0064)
143#define ME_XMEM_BAR5 (0x0068)
144#define ME_XMEM_BAR6 (0x006C)
145#define ME_XMEM_BAR7 (0x0070)
146#define ME_XMEM_BAR8 (0x0074)
147#define ME_XMEM_BAR9 (0x0078)
148#define ME_XMEM_BAR10 (0x007C)
149#define ME_XMEM_BAR11 (0x0080)
150#define ME_XMEM_BAR12 (0x0084)
151#define ME_XMEM_BAR13 (0x0088)
152#define ME_XMEM_BAR14 (0x008C)
153#define ME_XMEM_BAR15 (0x0090)
154#define ME_XMEM_BAR16 (0x0094)
155
156#define WHILE_DELAY 20000
157/*
158** Define where in ME Processor's memory map the Stratify chip lives
159*/
160
161#define MAXSWAPSIZE (8 * 1024) //8k *(32bits)
162
163// Mailboxes
164#define MSG_LENGTH 16 // x16 bits
165#define YES_REPLY 1
166#define NO_REPLY 0
167
168#define CMV_TIMEOUT 1000 //jiffies
169
170// Block size per BAR
171#define SDRAM_SEGMENT_SIZE (64*1024)
172// Number of Bar registers
173#define MAX_BAR_REGISTERS (17)
174
175#define XDATA_REGISTER (15)
176
177// ARC register addresss
178#define ARC_STATUS 0x0
179#define ARC_LP_START 0x2
180#define ARC_LP_END 0x3
181#define ARC_DEBUG 0x5
182#define ARC_INT_MASK 0x10A
183
184#define IRAM0_BASE (0x00000)
185#define IRAM1_BASE (0x04000)
186#if defined(CONFIG_DANUBE)
187#define BRAM_BASE (0x0A000)
188#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
189#define BRAM_BASE (0x08000)
190#endif
191#define XRAM_BASE (0x18000)
192#define YRAM_BASE (0x1A000)
193#define EXT_MEM_BASE (0x80000)
194#define ARC_GPIO_CTRL (0xC030)
195#define ARC_GPIO_DATA (0xC034)
196
197#define IRAM0_SIZE (16*1024)
198#define IRAM1_SIZE (16*1024)
199#define BRAM_SIZE (12*1024)
200#define XRAM_SIZE (8*1024)
201#define YRAM_SIZE (8*1024)
202#define EXT_MEM_SIZE (1536*1024)
203
204#define ADSL_BASE (0x20000)
205#define CRI_BASE (ADSL_BASE + 0x11F00)
206#define CRI_CCR0 (CRI_BASE + 0x00)
207#define CRI_RST (CRI_BASE + 0x04*4)
208#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
209
210//
211#define IRAM0_ADDR_BIT_MASK 0xFFF
212#define IRAM1_ADDR_BIT_MASK 0xFFF
213#define BRAM_ADDR_BIT_MASK 0xFFF
214#define RX_DILV_ADDR_BIT_MASK 0x1FFF
215
216/*** Bit definitions ***/
217#define ARC_AUX_HALT (1 << 25)
218#define ARC_DEBUG_HALT (1 << 1)
219#define FALSE 0
220#define TRUE 1
221#define BIT0 (1<<0)
222#define BIT1 (1<<1)
223#define BIT2 (1<<2)
224#define BIT3 (1<<3)
225#define BIT4 (1<<4)
226#define BIT5 (1<<5)
227#define BIT6 (1<<6)
228#define BIT7 (1<<7)
229#define BIT8 (1<<8)
230#define BIT9 (1<<9)
231#define BIT10 (1<<10)
232#define BIT11 (1<<11)
233#define BIT12 (1<<12)
234#define BIT13 (1<<13)
235#define BIT14 (1<<14)
236#define BIT15 (1<<15)
237#define BIT16 (1<<16)
238#define BIT17 (1<<17)
239#define BIT18 (1<<18)
240#define BIT19 (1<<19)
241#define BIT20 (1<<20)
242#define BIT21 (1<<21)
243#define BIT22 (1<<22)
244#define BIT23 (1<<23)
245#define BIT24 (1<<24)
246#define BIT25 (1<<25)
247#define BIT26 (1<<26)
248#define BIT27 (1<<27)
249#define BIT28 (1<<28)
250#define BIT29 (1<<29)
251#define BIT30 (1<<30)
252#define BIT31 (1<<31)
253
254// CRI_CCR0 Register definitions
255#define CLK_2M_MODE_ENABLE BIT6
256#define ACL_CLK_MODE_ENABLE BIT4
257#define FDF_CLK_MODE_ENABLE BIT2
258#define STM_CLK_MODE_ENABLE BIT0
259
260// CRI_RST Register definitions
261#define FDF_SRST BIT3
262#define MTE_SRST BIT2
263#define FCI_SRST BIT1
264#define AAI_SRST BIT0
265
266// MEI_TO_ARC_INTERRUPT Register definitions
267#define MEI_TO_ARC_INT1 BIT3
268#define MEI_TO_ARC_INT0 BIT2
269#define MEI_TO_ARC_CS_DONE BIT1 //need to check
270#define MEI_TO_ARC_MSGAV BIT0
271
272// ARC_TO_MEI_INTERRUPT Register definitions
273#define ARC_TO_MEI_INT1 BIT8
274#define ARC_TO_MEI_INT0 BIT7
275#define ARC_TO_MEI_CS_REQ BIT6
276#define ARC_TO_MEI_DBG_DONE BIT5
277#define ARC_TO_MEI_MSGACK BIT4
278#define ARC_TO_MEI_NO_ACCESS BIT3
279#define ARC_TO_MEI_CHECK_AAITX BIT2
280#define ARC_TO_MEI_CHECK_AAIRX BIT1
281#define ARC_TO_MEI_MSGAV BIT0
282
283// ARC_TO_MEI_INTERRUPT_MASK Register definitions
284#define GP_INT1_EN BIT8
285#define GP_INT0_EN BIT7
286#define CS_REQ_EN BIT6
287#define DBG_DONE_EN BIT5
288#define MSGACK_EN BIT4
289#define NO_ACC_EN BIT3
290#define AAITX_EN BIT2
291#define AAIRX_EN BIT1
292#define MSGAV_EN BIT0
293
294#define MEI_SOFT_RESET BIT0
295
296#define HOST_MSTR BIT0
297
298#define JTAG_MASTER_MODE 0x0
299#define MEI_MASTER_MODE HOST_MSTR
300
301// MEI_DEBUG_DECODE Register definitions
302#define MEI_DEBUG_DEC_MASK (0x3)
303#define MEI_DEBUG_DEC_AUX_MASK (0x0)
304#define ME_DBG_DECODE_DMP1_MASK (0x1)
305#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
306#define MEI_DEBUG_DEC_CORE_MASK (0x3)
307
308#define AUX_STATUS (0x0)
309#define AUX_ARC_GPIO_CTRL (0x10C)
310#define AUX_ARC_GPIO_DATA (0x10D)
311// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
312// page swap requests.
313#if defined(CONFIG_DANUBE)
314#define OMBOX_BASE 0xDF80
315#define ARC_TO_MEI_MAILBOX 0xDFA0
316#define IMBOX_BASE 0xDFC0
317#define MEI_TO_ARC_MAILBOX 0xDFD0
318#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
319#define OMBOX_BASE 0xAF80
320#define ARC_TO_MEI_MAILBOX 0xAFA0
321#define IMBOX_BASE 0xAFC0
322#define MEI_TO_ARC_MAILBOX 0xAFD0
323#endif
324
325#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
326#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
327#define OMBOX1 (OMBOX_BASE+0x4)
328
329// Codeswap request messages are indicated by setting BIT31
330#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
331
332// Clear Eoc messages received are indicated by setting BIT17
333#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
334#define OMB_REBOOT_INTERRUPT_CODE (1 << 18)
335
336/*
337** Swap page header
338*/
339// Page must be loaded at boot time if size field has BIT31 set
340#define BOOT_FLAG (BIT31)
341#define BOOT_FLAG_MASK ~BOOT_FLAG
342
343#define FREE_RELOAD 1
344#define FREE_SHOWTIME 2
345#define FREE_ALL 3
346
347// marcos
348#define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data)
349#define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
350#define SET_BIT(reg, mask) reg |= (mask)
351#define CLEAR_BIT(reg, mask) reg &= (~mask)
352#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
353//#define SET_BITS(reg, mask) SET_BIT(reg, mask)
354#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
355
356#define ALIGN_SIZE ( 1L<<10 ) //1K size align
357#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
358
359// swap marco
360#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
361#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
362
363
364#ifdef CONFIG_PROC_FS
365typedef struct reg_entry
366{
367   int *flag;
368   char name[30]; /* big enough to hold names */
369   char description[100]; /* big enough to hold description */
370   unsigned short low_ino;
371} reg_entry_t;
372#endif
373// Swap page header describes size in 32-bit words, load location, and image offset
374// for program and/or data segments
375typedef struct _arc_swp_page_hdr {
376    u32 p_offset; //Offset bytes of progseg from beginning of image
377    u32 p_dest; //Destination addr of progseg on processor
378    u32 p_size; //Size in 32-bitwords of program segment
379    u32 d_offset; //Offset bytes of dataseg from beginning of image
380    u32 d_dest; //Destination addr of dataseg on processor
381    u32 d_size; //Size in 32-bitwords of data segment
382} ARC_SWP_PAGE_HDR;
383
384/*
385** Swap image header
386*/
387#define GET_PROG 0 // Flag used for program mem segment
388#define GET_DATA 1 // Flag used for data mem segment
389
390// Image header contains size of image, checksum for image, and count of
391// page headers. Following that are 'count' page headers followed by
392// the code and/or data segments to be loaded
393typedef struct _arc_img_hdr {
394    u32 size; // Size of binary image in bytes
395    u32 checksum; // Checksum for image
396    u32 count; // Count of swp pages in image
397    ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
398} ARC_IMG_HDR;
399
400typedef struct smmu_mem_info {
401    int type;
402    int boot;
403    unsigned long nCopy;
404    unsigned long size;
405    unsigned char *address;
406    unsigned char *org_address;
407} smmu_mem_info_t;
408
409#ifdef __KERNEL__
410typedef struct ifx_mei_device_private {
411    int modem_ready;
412    int arcmsgav;
413    int cmv_reply;
414    int cmv_waiting;
415    // Mei to ARC CMV count, reply count, ARC Indicator count
416    int modem_ready_cnt;
417    int cmv_count;
418    int reply_count;
419    unsigned long image_size;
420    int nBar;
421    u16 Recent_indicator[MSG_LENGTH];
422
423    u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
424
425    smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
426    ARC_IMG_HDR *img_hdr;
427    // to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
428    wait_queue_head_t wait_queue_arcmsgav;
429    wait_queue_head_t wait_queue_modemready;
430    struct semaphore mei_cmv_sema;
431} ifx_mei_device_private_t;
432#endif
433typedef struct winhost_message {
434    union {
435        u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
436        u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
437    } msg;
438} DSL_DEV_WinHost_Message_t;
439/********************************************************************************************************
440 * DSL CPE API Driver Stack Interface Definitions
441 * *****************************************************************************************************/
442/** IOCTL codes for bsp driver */
443#define DSL_IOC_MEI_BSP_MAGIC 's'
444
445#define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0)
446#define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1)
447#define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2)
448#define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3)
449#define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4)
450#define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5)
451#define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6)
452#define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7)
453#define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8)
454#define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9)
455#define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
456#define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
457#define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
458#define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
459#define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
460#define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
461#define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
462#define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
463#define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
464#define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
465
466#define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512
467
468typedef struct DSL_DEV_MeiDebug
469{
470    DSL_uint32_t iAddress;
471    DSL_uint32_t iCount;
472    DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
473} DSL_DEV_MeiDebug_t; /* meidebug */
474
475/**
476 * Structure is used for debug access only.
477 * Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
478typedef struct struct_meireg
479{
480    /*
481    * Specifies that address for debug access */
482    unsigned long iAddress;
483    /*
484    * Specifies the pointer to the data that has to be written or returns a
485    * pointer to the data that has been read out*/
486    unsigned long iData;
487} DSL_DEV_MeiReg_t; /* meireg */
488
489typedef struct DSL_DEV_Device
490{
491    DSL_int_t nInUse; /* modem state, update by bsp driver, */
492    DSL_void_t *pPriv;
493    DSL_uint32_t base_address; /* mei base address */
494    DSL_int_t nIrq[2]; /* irq number */
495#define IFX_DFEIR 0
496#define IFX_DYING_GASP 1
497    DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */
498#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
499    struct module *owner;
500#endif
501} DSL_DEV_Device_t; /* ifx_adsl_device_t */
502
503#define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv))
504
505typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */
506{
507    unsigned long major;
508    unsigned long minor;
509    unsigned long revision;
510} DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */
511
512typedef struct DSL_DEV_ChipInfo
513{
514    unsigned long major;
515    unsigned long minor;
516} DSL_DEV_HwVersion_t;
517
518typedef struct
519{
520    DSL_uint8_t dummy;
521} DSL_DEV_DeviceConfig_t;
522
523/** error code definitions */
524typedef enum DSL_DEV_MeiError
525{
526    DSL_DEV_MEI_ERR_SUCCESS = 0,
527    DSL_DEV_MEI_ERR_FAILURE = -1,
528    DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
529    DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
530    DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
531} DSL_DEV_MeiError_t; /* MEI_ERROR */
532
533typedef enum {
534    DSL_BSP_MEMORY_READ=0,
535    DSL_BSP_MEMORY_WRITE,
536} DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */
537
538typedef enum
539{
540    DSL_LED_LINK_ID=0,
541    DSL_LED_DATA_ID
542} DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */
543
544typedef enum
545{
546    DSL_LED_LINK_TYPE=0,
547    DSL_LED_DATA_TYPE
548} DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */
549
550typedef enum
551{
552    DSL_LED_HD_CPU=0,
553    DSL_LED_HD_FW
554} DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */
555
556typedef enum {
557    DSL_LED_ON=0,
558    DSL_LED_OFF,
559    DSL_LED_FLASH,
560} DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */
561
562typedef enum {
563    DSL_CPU_HALT=0,
564    DSL_CPU_RUN,
565    DSL_CPU_RESET,
566} DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */
567
568#if 0
569typedef enum {
570    DSL_BSP_EVENT_DYING_GASP = 0,
571    DSL_BSP_EVENT_CEOC_IRQ,
572} DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */
573
574typedef union DSL_BSP_CB_Param
575{
576    DSL_uint32_t nIrqMessage;
577} DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */
578
579typedef struct DSL_BSP_CB_Event
580{
581    DSL_BSP_Event_id_t nID;
582    DSL_DEV_Device_t *pDev;
583    DSL_BSP_CB_Param_t *pParam;
584} DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */
585#endif
586
587/* external functions (from the BSP Driver) */
588extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
589extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
590extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
591extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
592extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
593extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
594extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
595extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
596extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
597extern volatile DSL_DEV_Device_t *adsl_dev;
598
599/**
600 * Dummy structure by now to show mechanism of extended data that will be
601 * provided within event callback itself.
602 * */
603typedef struct
604{
605    /**
606    * Dummy value */
607    DSL_uint32_t nDummy1;
608} DSL_BSP_CB_Event1DataDummy_t;
609
610/**
611 * Dummy structure by now to show mechanism of extended data that will be
612 * provided within event callback itself.
613 * */
614typedef struct
615{
616    /**
617    * Dummy value */
618    DSL_uint32_t nDummy2;
619} DSL_BSP_CB_Event2DataDummy_t;
620
621/**
622 * encapsulate all data structures that are necessary for status event
623 * callbacks.
624 * */
625typedef union
626{
627    DSL_BSP_CB_Event1DataDummy_t dataEvent1;
628    DSL_BSP_CB_Event2DataDummy_t dataEvent2;
629} DSL_BSP_CB_DATA_Union_t;
630
631
632typedef enum
633{
634    /**
635     * Informs the upper layer driver (DSL CPE API) about a reboot request from the
636     * firmware.
637     * \note This event does NOT include any additional data.
638     * More detailed information upon reboot reason has to be requested from
639     * upper layer software via CMV (INFO 109) if necessary. */
640    DSL_BSP_CB_FIRST = 0,
641        DSL_BSP_CB_DYING_GASP,
642    DSL_BSP_CB_CEOC_IRQ,
643    DSL_BSP_CB_FIRMWARE_REBOOT,
644    /**
645     * Delimiter only */
646    DSL_BSP_CB_LAST
647} DSL_BSP_CB_Type_t;
648
649/**
650 * Specifies the common event type that has to be used for registering and
651 * signalling of interrupts/autonomous status events from MEI BSP Driver.
652 *
653 * \param pDev
654 * Context pointer from MEI BSP Driver.
655 *
656 * \param IFX_ADSL_BSP_CallbackType_t
657 * Specifies the event callback type (reason of callback). Regrading to the
658 * setting of this value the data which is included in the following union
659 * might have different meanings.
660 * Please refer to the description of the union to get information about the
661 * meaning of the included data.
662 *
663 * \param pData
664 * Data according to \ref DSL_BSP_CB_DATA_Union_t.
665 * If this pointer is NULL there is no additional data available.
666 *
667 * \return depending on event
668 */
669typedef int (*DSL_BSP_EventCallback_t)
670(
671    DSL_DEV_Device_t *pDev,
672    DSL_BSP_CB_Type_t nCallbackType,
673    DSL_BSP_CB_DATA_Union_t *pData
674);
675
676typedef struct {
677        DSL_BSP_EventCallback_t function;
678        DSL_BSP_CB_Type_t event;
679        DSL_BSP_CB_DATA_Union_t *pData;
680} DSL_BSP_EventCallBack_t;
681
682extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
683extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
684
685/** Modem states */
686#define DSL_DEV_STAT_InitState 0x0000
687#define DSL_DEV_STAT_ReadyState 0x0001
688#define DSL_DEV_STAT_FailState 0x0002
689#define DSL_DEV_STAT_IdleState 0x0003
690#define DSL_DEV_STAT_QuietState 0x0004
691#define DSL_DEV_STAT_GhsState 0x0005
692#define DSL_DEV_STAT_FullInitState 0x0006
693#define DSL_DEV_STAT_ShowTimeState 0x0007
694#define DSL_DEV_STAT_FastRetrainState 0x0008
695#define DSL_DEV_STAT_LoopDiagMode 0x0009
696#define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */
697
698#define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002
699
700#endif //IFXMIPS_MEI_H
701

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