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Root/package/ubsec_ssb/src/ubsec_ssb.c

1
2	/*
3	* Copyright (c) 2008 Daniel Mueller (daniel@danm.de)
4	* Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com)
5	* Copyright (c) 2000 Jason L. Wright (jason@thought.net)
6	* Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
7	* Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
8	*
9	* Redistribution and use in source and binary forms, with or without
10	* modification, are permitted provided that the following conditions
11	* are met:
12	* 1. Redistributions of source code must retain the above copyright
13	* notice, this list of conditions and the following disclaimer.
14	* 2. Redistributions in binary form must reproduce the above copyright
15	* notice, this list of conditions and the following disclaimer in the
16	* documentation and/or other materials provided with the distribution.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21	* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
22	* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26	* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
27	* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28	* POSSIBILITY OF SUCH DAMAGE.
29	*
30	* Effort sponsored in part by the Defense Advanced Research Projects
31	* Agency (DARPA) and Air Force Research Laboratory, Air Force
32	* Materiel Command, USAF, under agreement number F30602-01-2-0537.
33	*
34	*/
35	#undef UBSEC_DEBUG
36	#undef UBSEC_VERBOSE_DEBUG
37
38	#ifdef UBSEC_VERBOSE_DEBUG
39	#define UBSEC_DEBUG
40	#endif
41
42	/*
43	* uBsec BCM5365 hardware crypto accelerator
44	*/
45
46	#include <linux/kernel.h>
47	#include <linux/module.h>
48	#include <linux/moduleparam.h>
49	#include <linux/proc_fs.h>
50	#include <linux/types.h>
51	#include <linux/init.h>
52	#include <linux/delay.h>
53	#include <linux/interrupt.h>
54	#include <linux/fs.h>
55	#include <linux/random.h>
56	#include <linux/skbuff.h>
57	#include <linux/stat.h>
58	#include <asm/io.h>
59
60	#include <linux/ssb/ssb.h>
61
62	/*
63	* BSD queue
64	*/
65	#include "bsdqueue.h"
66
67	/*
68	* OCF
69	*/
70	#include "cryptodev.h"
71	#include "uio.h"
72
73	#define HMAC_HACK 1
74
75	#ifdef HMAC_HACK
76	#include "hmachack.h"
77	#include "md5.h"
78	#include "md5.c"
79	#include "sha1.h"
80	#include "sha1.c"
81	#endif
82
83	#include "ubsecreg.h"
84	#include "ubsecvar.h"
85
86	#define DRV_MODULE_NAME "ubsec_ssb"
87	#define PFX DRV_MODULE_NAME ": "
88	#define DRV_MODULE_VERSION "0.02"
89	#define DRV_MODULE_RELDATE "Feb 21, 2009"
90
91	#if 1
92	#define DPRINTF(a...) \
93	if (debug) \
94	{ \
95	printk(DRV_MODULE_NAME ": " a); \
96	}
97	#else
98	#define DPRINTF(a...)
99	#endif
100
101	/*
102	* Prototypes
103	*/
104	static irqreturn_t ubsec_ssb_isr(int, void , struct pt_regs );
105	static int __devinit ubsec_ssb_probe(struct ssb_device *sdev,
106	const struct ssb_device_id *ent);
107	static void __devexit ubsec_ssb_remove(struct ssb_device *sdev);
108	int ubsec_attach(struct ssb_device sdev, const struct ssb_device_id ent,
109	struct device *self);
110	static void ubsec_setup_mackey(struct ubsec_session *ses, int algo,
111	caddr_t key, int klen);
112	static int dma_map_skb(struct ubsec_softc *sc,
113	struct ubsec_dma_alloc* q_map, struct sk_buff skb, int mlen);
114	static int dma_map_uio(struct ubsec_softc *sc,
115	struct ubsec_dma_alloc q_map, struct uio uio, int *mlen);
116	static void dma_unmap(struct ubsec_softc *sc,
117	struct ubsec_dma_alloc *q_map, int mlen);
118	static int ubsec_dmamap_aligned(struct ubsec_softc *sc,
119	const struct ubsec_dma_alloc *q_map, int mlen);
120
121	#ifdef UBSEC_DEBUG
122	static int proc_read(char buf, char *start, off_t offset,
123	int size, int peof, void data);
124	#endif
125
126	void ubsec_reset_board(struct ubsec_softc *);
127	void ubsec_init_board(struct ubsec_softc *);
128	void ubsec_cleanchip(struct ubsec_softc *);
129	void ubsec_totalreset(struct ubsec_softc *);
130	int ubsec_free_q(struct ubsec_softc, struct ubsec_q );
131
132	static int ubsec_newsession(device_t, u_int32_t , struct cryptoini );
133	static int ubsec_freesession(device_t, u_int64_t);
134	static int ubsec_process(device_t, struct cryptop *, int);
135
136	void ubsec_callback(struct ubsec_softc , struct ubsec_q );
137	void ubsec_feed(struct ubsec_softc *);
138	void ubsec_mcopy(struct sk_buff , struct sk_buff , int, int);
139	void ubsec_dma_free(struct ubsec_softc , struct ubsec_dma_alloc );
140	int ubsec_dma_malloc(struct ubsec_softc , struct ubsec_dma_alloc ,
141	size_t, int);
142
143	/* DEBUG crap... */
144	void ubsec_dump_pb(struct ubsec_pktbuf *);
145	void ubsec_dump_mcr(struct ubsec_mcr *);
146
147	#define READ_REG(sc,r) \
148	ssb_read32((sc)->sdev, (r));
149	#define WRITE_REG(sc,r,val) \
150	ssb_write32((sc)->sdev, (r), (val));
151	#define READ_REG_SDEV(sdev,r) \
152	ssb_read32((sdev), (r));
153	#define WRITE_REG_SDEV(sdev,r,val) \
154	ssb_write32((sdev), (r), (val));
155
156	#define SWAP32(x) (x) = htole32(ntohl((x)))
157	#define HTOLE32(x) (x) = htole32(x)
158
159	#ifdef __LITTLE_ENDIAN
160	#define letoh16(x) (x)
161	#define letoh32(x) (x)
162	#endif
163
164	static int debug;
165	module_param(debug, int, 0644);
166	MODULE_PARM_DESC(debug, "Enable debug output");
167
168	#define UBSEC_SSB_MAX_CHIPS 1
169	static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS];
170	static struct ubsec_stats ubsecstats;
171
172	#ifdef UBSEC_DEBUG
173	static struct proc_dir_entry *procdebug;
174	#endif
175
176	static struct ssb_device_id ubsec_ssb_tbl[] = {
177	/* Broadcom BCM5365P IPSec Core */
178	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV),
179	SSB_DEVTABLE_END
180	};
181
182	static struct ssb_driver ubsec_ssb_driver = {
183	.name = DRV_MODULE_NAME,
184	.id_table = ubsec_ssb_tbl,
185	.probe = ubsec_ssb_probe,
186	.remove = __devexit_p(ubsec_ssb_remove),
187	/*
188	.suspend = ubsec_ssb_suspend,
189	.resume = ubsec_ssb_resume
190	*/
191	};
192
193	static device_method_t ubsec_ssb_methods = {
194	/* crypto device methods */
195	DEVMETHOD(cryptodev_newsession, ubsec_newsession),
196	DEVMETHOD(cryptodev_freesession,ubsec_freesession),
197	DEVMETHOD(cryptodev_process, ubsec_process),
198	};
199
200	#ifdef UBSEC_DEBUG
201	static int
202	proc_read(char buf, char *start, off_t offset,
203	int size, int peof, void data)
204	{
205	int i = 0, byteswritten = 0, ret;
206	unsigned int stat, ctrl;
207	#ifdef UBSEC_VERBOSE_DEBUG
208	struct ubsec_q *q;
209	struct ubsec_dma *dmap;
210	#endif
211
212	while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL))
213	{
214	struct ubsec_softc *sc = ubsec_chip_idx[i];
215
216	stat = READ_REG(sc, BS_STAT);
217	ctrl = READ_REG(sc, BS_CTRL);
218	ret = snprintf((buf + byteswritten),
219	(size - byteswritten) ,
220	"DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl);
221
222	byteswritten += ret;
223
224	#ifdef UBSEC_VERBOSE_DEBUG
225	printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl);
226
227	/* Dump all queues MCRs */
228	if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
229	BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next)
230	{
231	dmap = q->q_dma;
232	ubsec_dump_mcr(&dmap->d_dma->d_mcr);
233	}
234	}
235	#endif
236
237	i++;
238	}
239
240	*peof = 1;
241
242	return byteswritten;
243	}
244	#endif
245
246	/*
247	* map in a given sk_buff
248	*/
249	static int
250	dma_map_skb(struct ubsec_softc sc, struct ubsec_dma_alloc q_map, struct sk_buff skb, int mlen)
251	{
252	int i = 0;
253	dma_addr_t tmp;
254
255	#ifdef UBSEC_DEBUG
256	DPRINTF("%s()\n", __FUNCTION__);
257	#endif
258
259	/*
260	* We support only a limited number of fragments.
261	*/
262	if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER))
263	{
264	printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER);
265	return (-ENOMEM);
266	}
267
268	#ifdef UBSEC_VERBOSE_DEBUG
269	DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb));
270	#endif
271
272	/* first data package */
273	tmp = dma_map_single(sc->sc_dv,
274	skb->data,
275	skb_headlen(skb),
276	DMA_BIDIRECTIONAL);
277
278	q_map[i].dma_paddr = tmp;
279	q_map[i].dma_vaddr = skb->data;
280	q_map[i].dma_size = skb_headlen(skb);
281
282	if (unlikely(tmp == 0))
283	{
284	printk(KERN_ERR "Could not map memory region for dma.\n");
285	return (-EINVAL);
286	}
287
288	#ifdef UBSEC_VERBOSE_DEBUG
289	DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp);
290	#endif
291
292
293	/* all other data packages */
294	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
295
296	#ifdef UBSEC_VERBOSE_DEBUG
297	DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1,
298	(unsigned int)page_address(skb_shinfo(skb)->frags[i].page) +
299	skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size);
300	#endif
301
302	tmp = dma_map_single(sc->sc_dv,
303	page_address(skb_shinfo(skb)->frags[i].page) +
304	skb_shinfo(skb)->frags[i].page_offset,
305	skb_shinfo(skb)->frags[i].size,
306	DMA_BIDIRECTIONAL);
307
308	q_map[i + 1].dma_paddr = tmp;
309	q_map[i + 1].dma_vaddr = (void*)(page_address(skb_shinfo(skb)->frags[i].page) +
310	skb_shinfo(skb)->frags[i].page_offset);
311	q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size;
312
313	if (unlikely(tmp == 0))
314	{
315	printk(KERN_ERR "Could not map memory region for dma.\n");
316	return (-EINVAL);
317	}
318
319	#ifdef UBSEC_VERBOSE_DEBUG
320	DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp);
321	#endif
322
323	}
324	*mlen = i + 1;
325
326	return(0);
327	}
328
329	/*
330	* map in a given uio buffer
331	*/
332
333	static int
334	dma_map_uio(struct ubsec_softc sc, struct ubsec_dma_alloc q_map, struct uio uio, int mlen)
335	{
336	struct iovec *iov = uio->uio_iov;
337	int n;
338	dma_addr_t tmp;
339
340	#ifdef UBSEC_DEBUG
341	DPRINTF("%s()\n", __FUNCTION__);
342	#endif
343
344	/*
345	* We support only a limited number of fragments.
346	*/
347	if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER))
348	{
349	printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER);
350	return (-ENOMEM);
351	}
352
353	for (n = 0; n < uio->uio_iovcnt; n++) {
354	#ifdef UBSEC_VERBOSE_DEBUG
355	DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len);
356	#endif
357	tmp = dma_map_single(sc->sc_dv,
358	iov->iov_base,
359	iov->iov_len,
360	DMA_BIDIRECTIONAL);
361
362	q_map[n].dma_paddr = tmp;
363	q_map[n].dma_vaddr = iov->iov_base;
364	q_map[n].dma_size = iov->iov_len;
365
366	if (unlikely(tmp == 0))
367	{
368	printk(KERN_ERR "Could not map memory region for dma.\n");
369	return (-EINVAL);
370	}
371
372	#ifdef UBSEC_VERBOSE_DEBUG
373	DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp);
374	#endif
375
376	iov++;
377	}
378	*mlen = n;
379
380	return(0);
381	}
382
383	static void
384	dma_unmap(struct ubsec_softc sc, struct ubsec_dma_alloc q_map, int mlen)
385	{
386	int i;
387
388	#ifdef UBSEC_DEBUG
389	DPRINTF("%s()\n", __FUNCTION__);
390	#endif
391
392	for(i = 0; i < mlen; i++)
393	{
394	#ifdef UBSEC_VERBOSE_DEBUG
395	DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size);
396	#endif
397	dma_unmap_single(sc->sc_dv,
398	q_map[i].dma_paddr,
399	q_map[i].dma_size,
400	DMA_BIDIRECTIONAL);
401	}
402	return;
403	}
404
405	/*
406	* Is the operand suitable aligned for direct DMA. Each
407	* segment must be aligned on a 32-bit boundary and all
408	* but the last segment must be a multiple of 4 bytes.
409	*/
410	static int
411	ubsec_dmamap_aligned(struct ubsec_softc sc, const struct ubsec_dma_alloc q_map, int mlen)
412	{
413	int i;
414
415	#ifdef UBSEC_DEBUG
416	DPRINTF("%s()\n", __FUNCTION__);
417	#endif
418
419	for (i = 0; i < mlen; i++) {
420	if (q_map[i].dma_paddr & 3)
421	return (0);
422	if (i != (mlen - 1) && (q_map[i].dma_size & 3))
423	return (0);
424	}
425	return (1);
426	}
427
428
429	#define N(a) (sizeof(a) / sizeof (a[0]))
430	static void
431	ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
432	{
433	#ifdef HMAC_HACK
434	MD5_CTX md5ctx;
435	SHA1_CTX sha1ctx;
436	int i;
437
438	#ifdef UBSEC_DEBUG
439	DPRINTF("%s()\n", __FUNCTION__);
440	#endif
441
442	for (i = 0; i < klen; i++)
443	key[i] ^= HMAC_IPAD_VAL;
444
445	if (algo == CRYPTO_MD5_HMAC) {
446	MD5Init(&md5ctx);
447	MD5Update(&md5ctx, key, klen);
448	MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
449	bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8));
450	} else {
451	SHA1Init(&sha1ctx);
452	SHA1Update(&sha1ctx, key, klen);
453	SHA1Update(&sha1ctx, hmac_ipad_buffer,
454	SHA1_HMAC_BLOCK_LEN - klen);
455	bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
456	}
457
458	for (i = 0; i < klen; i++)
459	key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
460
461	if (algo == CRYPTO_MD5_HMAC) {
462	MD5Init(&md5ctx);
463	MD5Update(&md5ctx, key, klen);
464	MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
465	bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8));
466	} else {
467	SHA1Init(&sha1ctx);
468	SHA1Update(&sha1ctx, key, klen);
469	SHA1Update(&sha1ctx, hmac_opad_buffer,
470	SHA1_HMAC_BLOCK_LEN - klen);
471	bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
472	}
473
474	for (i = 0; i < klen; i++)
475	key[i] ^= HMAC_OPAD_VAL;
476
477	#else /* HMAC_HACK */
478	DPRINTF("md5/sha not implemented\n");
479	#endif /* HMAC_HACK */
480	}
481	#undef N
482
483	static int
484	__devinit ubsec_ssb_probe(struct ssb_device *sdev,
485	const struct ssb_device_id *ent)
486	{
487	int err;
488
489	#ifdef UBSEC_DEBUG
490	DPRINTF("%s()\n", __FUNCTION__);
491	#endif
492
493	err = ssb_bus_powerup(sdev->bus, 0);
494	if (err) {
495	dev_err(sdev->dev, "Failed to powerup the bus\n");
496	goto err_out;
497	}
498
499	err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr,
500	IRQF_DISABLED \| IRQF_SHARED, DRV_MODULE_NAME, sdev);
501	if (err) {
502	dev_err(sdev->dev, "Could not request irq\n");
503	goto err_out_powerdown;
504	}
505
506	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34))
507	err = dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(32)) \|\|
508	dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(32));
509	#else
510	err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK);
511	#endif
512	if (err) {
513	dev_err(sdev->dev,
514	"Required 32BIT DMA mask unsupported by the system.\n");
515	goto err_out_free_irq;
516	}
517
518	printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n",
519	sdev->irq);
520
521	DPRINTF("Vendor: %x, core id: %x, revision: %x\n",
522	sdev->id.vendor, sdev->id.coreid, sdev->id.revision);
523
524	ssb_device_enable(sdev, 0);
525
526	if (ubsec_attach(sdev, ent, sdev->dev) != 0)
527	goto err_out_disable;
528
529	#ifdef UBSEC_DEBUG
530	procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL);
531	if (procdebug)
532	{
533	procdebug->read_proc = proc_read;
534	procdebug->data = NULL;
535	} else
536	DPRINTF("Unable to create proc file.\n");
537	#endif
538
539	return 0;
540
541	err_out_disable:
542	ssb_device_disable(sdev, 0);
543
544	err_out_free_irq:
545	free_irq(sdev->irq, sdev);
546
547	err_out_powerdown:
548	ssb_bus_may_powerdown(sdev->bus);
549
550	err_out:
551	return err;
552	}
553
554	static void __devexit ubsec_ssb_remove(struct ssb_device *sdev) {
555
556	struct ubsec_softc *sc;
557	unsigned int ctrlflgs;
558	struct ubsec_dma *dmap;
559	u_int32_t i;
560
561	#ifdef UBSEC_DEBUG
562	DPRINTF("%s()\n", __FUNCTION__);
563	#endif
564
565	ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL);
566	/* disable all IPSec Core interrupts globally */
567	ctrlflgs ^= (BS_CTRL_MCR1INT \| BS_CTRL_MCR2INT \|
568	BS_CTRL_DMAERR);
569	WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs);
570
571	free_irq(sdev->irq, sdev);
572
573	sc = (struct ubsec_softc *)ssb_get_drvdata(sdev);
574
575	/* unregister all crypto algorithms */
576	crypto_unregister_all(sc->sc_cid);
577
578	/* Free queue / dma memory */
579	for (i = 0; i < UBS_MAX_NQUEUE; i++) {
580	struct ubsec_q *q;
581
582	q = sc->sc_queuea[i];
583	if (q != NULL)
584	{
585	dmap = q->q_dma;
586	if (dmap != NULL)
587	{
588	ubsec_dma_free(sc, &dmap->d_alloc);
589	q->q_dma = NULL;
590	}
591	kfree(q);
592	}
593	sc->sc_queuea[i] = NULL;
594	}
595
596	ssb_device_disable(sdev, 0);
597	ssb_bus_may_powerdown(sdev->bus);
598	ssb_set_drvdata(sdev, NULL);
599
600	#ifdef UBSEC_DEBUG
601	if (procdebug)
602	remove_proc_entry(DRV_MODULE_NAME, NULL);
603	#endif
604
605	}
606
607
608	int
609	ubsec_attach(struct ssb_device sdev, const struct ssb_device_id ent,
610	struct device *self)
611	{
612	struct ubsec_softc *sc = NULL;
613	struct ubsec_dma *dmap;
614	u_int32_t i;
615	static int num_chips = 0;
616
617	#ifdef UBSEC_DEBUG
618	DPRINTF("%s()\n", __FUNCTION__);
619	#endif
620
621	sc = (struct ubsec_softc ) kmalloc(sizeof(sc), GFP_KERNEL);
622	if (!sc)
623	return(-ENOMEM);
624	memset(sc, 0, sizeof(*sc));
625
626	sc->sc_dv = sdev->dev;
627	sc->sdev = sdev;
628
629	spin_lock_init(&sc->sc_ringmtx);
630
631	softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods);
632
633	/* Maybe someday there are boards with more than one chip available */
634	if (num_chips < UBSEC_SSB_MAX_CHIPS) {
635	ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc;
636	num_chips++;
637	}
638
639	ssb_set_drvdata(sdev, sc);
640
641	BSD_SIMPLEQ_INIT(&sc->sc_queue);
642	BSD_SIMPLEQ_INIT(&sc->sc_qchip);
643	BSD_SIMPLEQ_INIT(&sc->sc_queue2);
644	BSD_SIMPLEQ_INIT(&sc->sc_qchip2);
645	BSD_SIMPLEQ_INIT(&sc->sc_q2free);
646
647	sc->sc_statmask = BS_STAT_MCR1_DONE \| BS_STAT_DMAERR;
648
649	sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE);
650	if (sc->sc_cid < 0) {
651	device_printf(sc->sc_dev, "could not get crypto driver id\n");
652	return -1;
653	}
654
655	BSD_SIMPLEQ_INIT(&sc->sc_freequeue);
656	dmap = sc->sc_dmaa;
657	for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
658	struct ubsec_q *q;
659
660	q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL);
661	if (q == NULL) {
662	printf(": can't allocate queue buffers\n");
663	break;
664	}
665
666	if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) {
667	printf(": can't allocate dma buffers\n");
668	kfree(q);
669	break;
670	}
671	dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
672
673	q->q_dma = dmap;
674	sc->sc_queuea[i] = q;
675
676	BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
677	}
678
679	/*
680	* Reset Broadcom chip
681	*/
682	ubsec_reset_board(sc);
683
684	/*
685	* Init Broadcom chip
686	*/
687	ubsec_init_board(sc);
688
689	/* supported crypto algorithms */
690	crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
691	crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
692
693	if (sc->sc_flags & UBS_FLAGS_AES) {
694	crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
695	printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n");
696	}
697	else
698	printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n");
699
700	crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
701	crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
702
703	return 0;
704	}
705
706	/*
707	* UBSEC Interrupt routine
708	*/
709	static irqreturn_t
710	ubsec_ssb_isr(int irq, void arg, struct pt_regs regs)
711	{
712	struct ubsec_softc *sc = NULL;
713	volatile u_int32_t stat;
714	struct ubsec_q *q;
715	struct ubsec_dma *dmap;
716	int npkts = 0, i;
717
718	#ifdef UBSEC_VERBOSE_DEBUG
719	DPRINTF("%s()\n", __FUNCTION__);
720	#endif
721
722	sc = (struct ubsec_softc *)ssb_get_drvdata(arg);
723
724	stat = READ_REG(sc, BS_STAT);
725
726	stat &= sc->sc_statmask;
727	if (stat == 0)
728	return IRQ_NONE;
729
730	WRITE_REG(sc, BS_STAT, stat); /* IACK */
731
732	/*
733	* Check to see if we have any packets waiting for us
734	*/
735	if ((stat & BS_STAT_MCR1_DONE)) {
736	while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
737	q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip);
738	dmap = q->q_dma;
739
740	if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
741	{
742	DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags);
743	break;
744	}
745
746	BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
747
748	npkts = q->q_nstacked_mcrs;
749	/*
750	* search for further sc_qchip ubsec_q's that share
751	* the same MCR, and complete them too, they must be
752	* at the top.
753	*/
754	for (i = 0; i < npkts; i++) {
755	if(q->q_stacked_mcr[i])
756	ubsec_callback(sc, q->q_stacked_mcr[i]);
757	else
758	break;
759	}
760	ubsec_callback(sc, q);
761	}
762
763	/*
764	* Don't send any more packet to chip if there has been
765	* a DMAERR.
766	*/
767	if (likely(!(stat & BS_STAT_DMAERR)))
768	ubsec_feed(sc);
769	else
770	DPRINTF("DMA error occurred. Stop feeding crypto chip.\n");
771	}
772
773	/*
774	* Check to see if we got any DMA Error
775	*/
776	if (stat & BS_STAT_DMAERR) {
777	volatile u_int32_t a = READ_REG(sc, BS_ERR);
778
779	printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME,
780	(a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR);
781
782	ubsecstats.hst_dmaerr++;
783	ubsec_totalreset(sc);
784	ubsec_feed(sc);
785	}
786
787	return IRQ_HANDLED;
788	}
789
790	/*
791	* ubsec_feed() - aggregate and post requests to chip
792	* It is assumed that the caller set splnet()
793	*/
794	void
795	ubsec_feed(struct ubsec_softc *sc)
796	{
797	#ifdef UBSEC_VERBOSE_DEBUG
798	static int max;
799	#endif
800	struct ubsec_q q, q2;
801	int npkts, i;
802	void *v;
803	u_int32_t stat;
804
805	npkts = sc->sc_nqueue;
806	if (npkts > UBS_MAX_AGGR)
807	npkts = UBS_MAX_AGGR;
808	if (npkts < 2)
809	goto feed1;
810
811	stat = READ_REG(sc, BS_STAT);
812
813	if (stat & (BS_STAT_MCR1_FULL \| BS_STAT_DMAERR)) {
814	if(stat & BS_STAT_DMAERR) {
815	ubsec_totalreset(sc);
816	ubsecstats.hst_dmaerr++;
817	}
818	return;
819	}
820
821	#ifdef UBSEC_VERBOSE_DEBUG
822	DPRINTF("merging %d records\n", npkts);
823
824	/* XXX temporary aggregation statistics reporting code */
825	if (max < npkts) {
826	max = npkts;
827	DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max);
828	}
829	#endif /* UBSEC_VERBOSE_DEBUG */
830
831	q = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
832	BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
833	--sc->sc_nqueue;
834
835	#if 0
836	/*
837	* XXX
838	* We use dma_map_single() - no sync required!
839	*/
840
841	bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
842	0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
843	if (q->q_dst_map != NULL)
844	bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
845	0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
846	#endif
847
848	q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
849
850	for (i = 0; i < q->q_nstacked_mcrs; i++) {
851	q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
852
853	#if 0
854	bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
855	0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
856	if (q2->q_dst_map != NULL)
857	bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
858	0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
859	#endif
860	BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
861	--sc->sc_nqueue;
862
863	v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
864	sizeof(struct ubsec_mcr_add);
865	bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
866	q->q_stacked_mcr[i] = q2;
867	}
868	q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
869	BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
870	#if 0
871	bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map,
872	0, q->q_dma->d_alloc.dma_map->dm_mapsize,
873	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
874	#endif
875	WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
876	offsetof(struct ubsec_dmachunk, d_mcr));
877	#ifdef UBSEC_VERBOSE_DEBUG
878	DPRINTF("feed (1): q->chip %p %08x %08x\n", q,
879	(u_int32_t)q->q_dma->d_alloc.dma_paddr,
880	(u_int32_t)(q->q_dma->d_alloc.dma_paddr +
881	offsetof(struct ubsec_dmachunk, d_mcr)));
882	#endif /* UBSEC_DEBUG */
883	return;
884
885	feed1:
886	while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) {
887	stat = READ_REG(sc, BS_STAT);
888
889	if (stat & (BS_STAT_MCR1_FULL \| BS_STAT_DMAERR)) {
890	if(stat & BS_STAT_DMAERR) {
891	ubsec_totalreset(sc);
892	ubsecstats.hst_dmaerr++;
893	}
894	break;
895	}
896
897	q = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
898
899	#if 0
900	bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
901	0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
902	if (q->q_dst_map != NULL)
903	bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
904	0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
905	bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map,
906	0, q->q_dma->d_alloc.dma_map->dm_mapsize,
907	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
908	#endif
909
910	WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
911	offsetof(struct ubsec_dmachunk, d_mcr));
912	#ifdef UBSEC_VERBOSE_DEBUG
913	DPRINTF("feed (2): q->chip %p %08x %08x\n", q,
914	(u_int32_t)q->q_dma->d_alloc.dma_paddr,
915	(u_int32_t)(q->q_dma->d_alloc.dma_paddr +
916	offsetof(struct ubsec_dmachunk, d_mcr)));
917	#endif /* UBSEC_DEBUG */
918	BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
919	--sc->sc_nqueue;
920	BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
921	}
922	}
923
924	/*
925	* Allocate a new 'session' and return an encoded session id. 'sidp'
926	* contains our registration id, and should contain an encoded session
927	* id on successful allocation.
928	*/
929	static int
930	ubsec_newsession(device_t dev, u_int32_t sidp, struct cryptoini cri)
931	{
932	struct cryptoini c, encini = NULL, *macini = NULL;
933	struct ubsec_softc *sc = NULL;
934	struct ubsec_session *ses = NULL;
935	int sesn, i;
936
937	#ifdef UBSEC_DEBUG
938	DPRINTF("%s()\n", __FUNCTION__);
939	#endif
940
941	if (sidp == NULL \|\| cri == NULL)
942	return (EINVAL);
943
944	sc = device_get_softc(dev);
945
946	if (sc == NULL)
947	return (EINVAL);
948
949	for (c = cri; c != NULL; c = c->cri_next) {
950	if (c->cri_alg == CRYPTO_MD5_HMAC \|\|
951	c->cri_alg == CRYPTO_SHA1_HMAC) {
952	if (macini)
953	return (EINVAL);
954	macini = c;
955	} else if (c->cri_alg == CRYPTO_DES_CBC \|\|
956	c->cri_alg == CRYPTO_3DES_CBC \|\|
957	c->cri_alg == CRYPTO_AES_CBC) {
958	if (encini)
959	return (EINVAL);
960	encini = c;
961	} else
962	return (EINVAL);
963	}
964	if (encini == NULL && macini == NULL)
965	return (EINVAL);
966
967	if (sc->sc_sessions == NULL) {
968	ses = sc->sc_sessions = (struct ubsec_session *)kmalloc(
969	sizeof(struct ubsec_session), SLAB_ATOMIC);
970	if (ses == NULL)
971	return (ENOMEM);
972	memset(ses, 0, sizeof(struct ubsec_session));
973	sesn = 0;
974	sc->sc_nsessions = 1;
975	} else {
976	for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
977	if (sc->sc_sessions[sesn].ses_used == 0) {
978	ses = &sc->sc_sessions[sesn];
979	break;
980	}
981	}
982
983	if (ses == NULL) {
984	sesn = sc->sc_nsessions;
985	ses = (struct ubsec_session )kmalloc((sesn + 1)
986	sizeof(struct ubsec_session), SLAB_ATOMIC);
987	if (ses == NULL)
988	return (ENOMEM);
989	memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session));
990	bcopy(sc->sc_sessions, ses, sesn *
991	sizeof(struct ubsec_session));
992	bzero(sc->sc_sessions, sesn *
993	sizeof(struct ubsec_session));
994	kfree(sc->sc_sessions);
995	sc->sc_sessions = ses;
996	ses = &sc->sc_sessions[sesn];
997	sc->sc_nsessions++;
998	}
999	}
1000
1001	bzero(ses, sizeof(struct ubsec_session));
1002	ses->ses_used = 1;
1003	if (encini) {
1004	/* get an IV */
1005	/* XXX may read fewer than requested */
1006	read_random(ses->ses_iv, sizeof(ses->ses_iv));
1007
1008	/* Go ahead and compute key in ubsec's byte order */
1009	if (encini->cri_alg == CRYPTO_DES_CBC) {
1010	/* DES uses the same key three times:
1011	* 1st encrypt -> 2nd decrypt -> 3nd encrypt */
1012	bcopy(encini->cri_key, &ses->ses_key[0], 8);
1013	bcopy(encini->cri_key, &ses->ses_key[2], 8);
1014	bcopy(encini->cri_key, &ses->ses_key[4], 8);
1015	ses->ses_keysize = 192; /* Fake! Actually its only 64bits ..
1016	oh no it is even less: 54bits. */
1017	} else if(encini->cri_alg == CRYPTO_3DES_CBC) {
1018	bcopy(encini->cri_key, ses->ses_key, 24);
1019	ses->ses_keysize = 192;
1020	} else if(encini->cri_alg == CRYPTO_AES_CBC) {
1021	ses->ses_keysize = encini->cri_klen;
1022
1023	if (ses->ses_keysize != 128 &&
1024	ses->ses_keysize != 192 &&
1025	ses->ses_keysize != 256)
1026	{
1027	DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize);
1028	return (EINVAL);
1029	}
1030	bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8));
1031	}
1032
1033	/* Hardware requires the keys in little endian byte order */
1034	for (i=0; i < (ses->ses_keysize / 32); i++)
1035	SWAP32(ses->ses_key[i]);
1036	}
1037
1038	if (macini) {
1039	ses->ses_mlen = macini->cri_mlen;
1040
1041	if (ses->ses_mlen == 0 \|\|
1042	ses->ses_mlen > SHA1_HASH_LEN) {
1043
1044	if (macini->cri_alg == CRYPTO_MD5_HMAC \|\|
1045	macini->cri_alg == CRYPTO_SHA1_HMAC)
1046	{
1047	ses->ses_mlen = DEFAULT_HMAC_LEN;
1048	} else
1049	{
1050	/*
1051	* Reserved for future usage. MD5/SHA1 calculations have
1052	* different hash sizes.
1053	*/
1054	printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen);
1055	return (EINVAL);
1056	}
1057
1058	}
1059
1060	if (macini->cri_key != NULL) {
1061	ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key,
1062	macini->cri_klen / 8);
1063	}
1064	}
1065
1066	*sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
1067	return (0);
1068	}
1069
1070	/*
1071	* Deallocate a session.
1072	*/
1073	static int
1074	ubsec_freesession(device_t dev, u_int64_t tid)
1075	{
1076	struct ubsec_softc *sc = device_get_softc(dev);
1077	int session;
1078	u_int32_t sid = ((u_int32_t)tid) & 0xffffffff;
1079
1080	#ifdef UBSEC_DEBUG
1081	DPRINTF("%s()\n", __FUNCTION__);
1082	#endif
1083
1084	if (sc == NULL)
1085	return (EINVAL);
1086
1087	session = UBSEC_SESSION(sid);
1088	if (session < sc->sc_nsessions) {
1089	bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
1090	return (0);
1091	} else
1092	return (EINVAL);
1093	}
1094
1095	static int
1096	ubsec_process(device_t dev, struct cryptop *crp, int hint)
1097	{
1098	struct ubsec_q *q = NULL;
1099	int err = 0, i, j, nicealign;
1100	struct ubsec_softc *sc = device_get_softc(dev);
1101	struct cryptodesc crd1, crd2, maccrd, enccrd;
1102	int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1103	int sskip, dskip, stheend, dtheend, ivsize = 8;
1104	int16_t coffset;
1105	struct ubsec_session *ses;
1106	struct ubsec_generic_ctx ctx;
1107	struct ubsec_dma *dmap = NULL;
1108	unsigned long flags;
1109
1110	#ifdef UBSEC_DEBUG
1111	DPRINTF("%s()\n", __FUNCTION__);
1112	#endif
1113
1114	if (unlikely(crp == NULL \|\| crp->crp_callback == NULL)) {
1115	ubsecstats.hst_invalid++;
1116	return (EINVAL);
1117	}
1118
1119	if (unlikely(sc == NULL))
1120	return (EINVAL);
1121
1122	#ifdef UBSEC_VERBOSE_DEBUG
1123	DPRINTF("spin_lock_irqsave\n");
1124	#endif
1125	spin_lock_irqsave(&sc->sc_ringmtx, flags);
1126	//spin_lock_irq(&sc->sc_ringmtx);
1127
1128	if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1129	ubsecstats.hst_queuefull++;
1130	#ifdef UBSEC_VERBOSE_DEBUG
1131	DPRINTF("spin_unlock_irqrestore\n");
1132	#endif
1133	spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1134	//spin_unlock_irq(&sc->sc_ringmtx);
1135	err = ENOMEM;
1136	goto errout2;
1137	}
1138
1139	q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue);
1140	BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1141	#ifdef UBSEC_VERBOSE_DEBUG
1142	DPRINTF("spin_unlock_irqrestore\n");
1143	#endif
1144	spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1145	//spin_unlock_irq(&sc->sc_ringmtx);
1146
1147	dmap = q->q_dma; /* Save dma pointer */
1148	bzero(q, sizeof(struct ubsec_q));
1149	bzero(&ctx, sizeof(ctx));
1150
1151	q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1152	q->q_dma = dmap;
1153	ses = &sc->sc_sessions[q->q_sesn];
1154
1155	if (crp->crp_flags & CRYPTO_F_SKBUF) {
1156	q->q_src_m = (struct sk_buff *)crp->crp_buf;
1157	q->q_dst_m = (struct sk_buff *)crp->crp_buf;
1158	} else if (crp->crp_flags & CRYPTO_F_IOV) {
1159	q->q_src_io = (struct uio *)crp->crp_buf;
1160	q->q_dst_io = (struct uio *)crp->crp_buf;
1161	} else {
1162	err = EINVAL;
1163	goto errout; /* XXX we don't handle contiguous blocks! */
1164	}
1165
1166	bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1167
1168	dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1169	dmap->d_dma->d_mcr.mcr_flags = 0;
1170	q->q_crp = crp;
1171
1172	crd1 = crp->crp_desc;
1173	if (crd1 == NULL) {
1174	err = EINVAL;
1175	goto errout;
1176	}
1177	crd2 = crd1->crd_next;
1178
1179	if (crd2 == NULL) {
1180	if (crd1->crd_alg == CRYPTO_MD5_HMAC \|\|
1181	crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1182	maccrd = crd1;
1183	enccrd = NULL;
1184	} else if (crd1->crd_alg == CRYPTO_DES_CBC \|\|
1185	crd1->crd_alg == CRYPTO_3DES_CBC \|\|
1186	crd1->crd_alg == CRYPTO_AES_CBC) {
1187	maccrd = NULL;
1188	enccrd = crd1;
1189	} else {
1190	err = EINVAL;
1191	goto errout;
1192	}
1193	} else {
1194	if ((crd1->crd_alg == CRYPTO_MD5_HMAC \|\|
1195	crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1196	(crd2->crd_alg == CRYPTO_DES_CBC \|\|
1197	crd2->crd_alg == CRYPTO_3DES_CBC \|\|
1198	crd2->crd_alg == CRYPTO_AES_CBC) &&
1199	((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1200	maccrd = crd1;
1201	enccrd = crd2;
1202	} else if ((crd1->crd_alg == CRYPTO_DES_CBC \|\|
1203	crd1->crd_alg == CRYPTO_3DES_CBC \|\|
1204	crd1->crd_alg == CRYPTO_AES_CBC) &&
1205	(crd2->crd_alg == CRYPTO_MD5_HMAC \|\|
1206	crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1207	(crd1->crd_flags & CRD_F_ENCRYPT)) {
1208	enccrd = crd1;
1209	maccrd = crd2;
1210	} else {
1211	/*
1212	* We cannot order the ubsec as requested
1213	*/
1214	printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n");
1215	err = EINVAL;
1216	goto errout;
1217	}
1218	}
1219
1220	/* Encryption/Decryption requested */
1221	if (enccrd) {
1222	encoffset = enccrd->crd_skip;
1223
1224	if (enccrd->crd_alg == CRYPTO_DES_CBC \|\|
1225	enccrd->crd_alg == CRYPTO_3DES_CBC)
1226	{
1227	ctx.pc_flags \|= htole16(UBS_PKTCTX_ENC_3DES);
1228	ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES);
1229	ivsize = 8; /* [3]DES uses 64bit IVs */
1230	} else {
1231	ctx.pc_flags \|= htole16(UBS_PKTCTX_ENC_AES);
1232	ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES);
1233	ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */
1234
1235	switch(ses->ses_keysize)
1236	{
1237	case 128:
1238	ctx.pc_flags \|= htole16(UBS_PKTCTX_AES128);
1239	break;
1240	case 192:
1241	ctx.pc_flags \|= htole16(UBS_PKTCTX_AES192);
1242	break;
1243	case 256:
1244	ctx.pc_flags \|= htole16(UBS_PKTCTX_AES256);
1245	break;
1246	default:
1247	DPRINTF("invalid AES key size: %d\n", ses->ses_keysize);
1248	err = EINVAL;
1249	goto errout;
1250	}
1251	}
1252
1253	if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1254	/* Direction: Outbound */
1255
1256	q->q_flags \|= UBSEC_QFLAGS_COPYOUTIV;
1257
1258	if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
1259	bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize);
1260	} else {
1261	for(i=0; i < (ivsize / 4); i++)
1262	ctx.pc_iv[i] = ses->ses_iv[i];
1263	}
1264
1265	/* If there is no IV in the buffer -> copy it here */
1266	if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1267	if (crp->crp_flags & CRYPTO_F_SKBUF)
1268	/*
1269	m_copyback(q->q_src_m,
1270	enccrd->crd_inject,
1271	8, ctx.pc_iv);
1272	*/
1273	crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m,
1274	enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv);
1275	else if (crp->crp_flags & CRYPTO_F_IOV)
1276	/*
1277	cuio_copyback(q->q_src_io,
1278	enccrd->crd_inject,
1279	8, ctx.pc_iv);
1280	*/
1281	crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io,
1282	enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv);
1283	}
1284	} else {
1285	/* Direction: Inbound */
1286
1287	ctx.pc_flags \|= htole16(UBS_PKTCTX_INBOUND);
1288
1289	if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1290	bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize);
1291	else if (crp->crp_flags & CRYPTO_F_SKBUF)
1292	/*
1293	m_copydata(q->q_src_m, enccrd->crd_inject,
1294	8, (caddr_t)ctx.pc_iv);
1295	*/
1296	crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m,
1297	enccrd->crd_inject, ivsize,
1298	(caddr_t)ctx.pc_iv);
1299	else if (crp->crp_flags & CRYPTO_F_IOV)
1300	/*
1301	cuio_copydata(q->q_src_io,
1302	enccrd->crd_inject, 8,
1303	(caddr_t)ctx.pc_iv);
1304	*/
1305	crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io,
1306	enccrd->crd_inject, ivsize,
1307	(caddr_t)ctx.pc_iv);
1308
1309	}
1310
1311	/* Even though key & IV sizes differ from cipher to cipher
1312	* copy / swap the full array lengths. Let the compiler unroll
1313	* the loop to increase the cpu pipeline performance... */
1314	for(i=0; i < 8; i++)
1315	ctx.pc_key[i] = ses->ses_key[i];
1316	for(i=0; i < 4; i++)
1317	SWAP32(ctx.pc_iv[i]);
1318	}
1319
1320	/* Authentication requested */
1321	if (maccrd) {
1322	macoffset = maccrd->crd_skip;
1323
1324	if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1325	ctx.pc_flags \|= htole16(UBS_PKTCTX_AUTH_MD5);
1326	else
1327	ctx.pc_flags \|= htole16(UBS_PKTCTX_AUTH_SHA1);
1328
1329	for (i = 0; i < 5; i++) {
1330	ctx.pc_hminner[i] = ses->ses_hminner[i];
1331	ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1332
1333	HTOLE32(ctx.pc_hminner[i]);
1334	HTOLE32(ctx.pc_hmouter[i]);
1335	}
1336	}
1337
1338	if (enccrd && maccrd) {
1339	/*
1340	* ubsec cannot handle packets where the end of encryption
1341	* and authentication are not the same, or where the
1342	* encrypted part begins before the authenticated part.
1343	*/
1344	if (((encoffset + enccrd->crd_len) !=
1345	(macoffset + maccrd->crd_len)) \|\|
1346	(enccrd->crd_skip < maccrd->crd_skip)) {
1347	err = EINVAL;
1348	goto errout;
1349	}
1350	sskip = maccrd->crd_skip;
1351	cpskip = dskip = enccrd->crd_skip;
1352	stheend = maccrd->crd_len;
1353	dtheend = enccrd->crd_len;
1354	coffset = enccrd->crd_skip - maccrd->crd_skip;
1355	cpoffset = cpskip + dtheend;
1356	#ifdef UBSEC_DEBUG
1357	DPRINTF("mac: skip %d, len %d, inject %d\n",
1358	maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1359	DPRINTF("enc: skip %d, len %d, inject %d\n",
1360	enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1361	DPRINTF("src: skip %d, len %d\n", sskip, stheend);
1362	DPRINTF("dst: skip %d, len %d\n", dskip, dtheend);
1363	DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1364	coffset, stheend, cpskip, cpoffset);
1365	#endif
1366	} else {
1367	cpskip = dskip = sskip = macoffset + encoffset;
1368	dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1369	cpoffset = cpskip + dtheend;
1370	coffset = 0;
1371	}
1372	ctx.pc_offset = htole16(coffset >> 2);
1373
1374	#if 0
1375	if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER,
1376	0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) {
1377	err = ENOMEM;
1378	goto errout;
1379	}
1380	#endif
1381
1382	if (crp->crp_flags & CRYPTO_F_SKBUF) {
1383	#if 0
1384	if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1385	q->q_src_m, BUS_DMA_NOWAIT) != 0) {
1386	bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1387	q->q_src_map = NULL;
1388	err = ENOMEM;
1389	goto errout;
1390	}
1391	#endif
1392	err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len);
1393	if (unlikely(err != 0))
1394	goto errout;
1395
1396	} else if (crp->crp_flags & CRYPTO_F_IOV) {
1397	#if 0
1398	if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1399	q->q_src_io, BUS_DMA_NOWAIT) != 0) {
1400	bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1401	q->q_src_map = NULL;
1402	err = ENOMEM;
1403	goto errout;
1404	}
1405	#endif
1406	err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len);
1407	if (unlikely(err != 0))
1408	goto errout;
1409	}
1410
1411	/*
1412	* Check alignment
1413	*/
1414	nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len);
1415
1416	dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1417
1418	#ifdef UBSEC_DEBUG
1419	DPRINTF("src skip: %d\n", sskip);
1420	#endif
1421	for (i = j = 0; i < q->q_src_len; i++) {
1422	struct ubsec_pktbuf *pb;
1423	size_t packl = q->q_src_map[i].dma_size;
1424	dma_addr_t packp = q->q_src_map[i].dma_paddr;
1425
1426	if (sskip >= packl) {
1427	sskip -= packl;
1428	continue;
1429	}
1430
1431	packl -= sskip;
1432	packp += sskip;
1433	sskip = 0;
1434
1435	/* maximum fragment size is 0xfffc */
1436	if (packl > 0xfffc) {
1437	DPRINTF("Error: fragment size is bigger than 0xfffc.\n");
1438	err = EIO;
1439	goto errout;
1440	}
1441
1442	if (j == 0)
1443	pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1444	else
1445	pb = &dmap->d_dma->d_sbuf[j - 1];
1446
1447	pb->pb_addr = htole32(packp);
1448
1449	if (stheend) {
1450	if (packl > stheend) {
1451	pb->pb_len = htole32(stheend);
1452	stheend = 0;
1453	} else {
1454	pb->pb_len = htole32(packl);
1455	stheend -= packl;
1456	}
1457	} else
1458	pb->pb_len = htole32(packl);
1459
1460	if ((i + 1) == q->q_src_len)
1461	pb->pb_next = 0;
1462	else
1463	pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1464	offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1465	j++;
1466	}
1467
1468	if (enccrd == NULL && maccrd != NULL) {
1469	/* Authentication only */
1470	dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1471	dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1472	dmap->d_dma->d_mcr.mcr_opktbuf.pb_next =
1473	htole32(dmap->d_alloc.dma_paddr +
1474	offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1475	#ifdef UBSEC_DEBUG
1476	DPRINTF("opkt: %x %x %x\n",
1477	dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1478	dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1479	dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1480	#endif
1481	} else {
1482	if (crp->crp_flags & CRYPTO_F_IOV) {
1483	if (!nicealign) {
1484	err = EINVAL;
1485	goto errout;
1486	}
1487	#if 0
1488	if (bus_dmamap_create(sc->sc_dmat, 0xfff0,
1489	UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT,
1490	&q->q_dst_map) != 0) {
1491	err = ENOMEM;
1492	goto errout;
1493	}
1494	if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1495	q->q_dst_io, BUS_DMA_NOWAIT) != 0) {
1496	bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1497	q->q_dst_map = NULL;
1498	goto errout;
1499	}
1500	#endif
1501
1502	/* HW shall copy the result into the source memory */
1503	for(i = 0; i < q->q_src_len; i++)
1504	q->q_dst_map[i] = q->q_src_map[i];
1505
1506	q->q_dst_len = q->q_src_len;
1507	q->q_has_dst = 0;
1508
1509	} else if (crp->crp_flags & CRYPTO_F_SKBUF) {
1510	if (nicealign) {
1511
1512	/* HW shall copy the result into the source memory */
1513	q->q_dst_m = q->q_src_m;
1514	for(i = 0; i < q->q_src_len; i++)
1515	q->q_dst_map[i] = q->q_src_map[i];
1516
1517	q->q_dst_len = q->q_src_len;
1518	q->q_has_dst = 0;
1519
1520	} else {
1521	#ifdef NOTYET
1522	int totlen, len;
1523	struct sk_buff m, top, **mp;
1524
1525	totlen = q->q_src_map->dm_mapsize;
1526	if (q->q_src_m->m_flags & M_PKTHDR) {
1527	len = MHLEN;
1528	MGETHDR(m, M_DONTWAIT, MT_DATA);
1529	} else {
1530	len = MLEN;
1531	MGET(m, M_DONTWAIT, MT_DATA);
1532	}
1533	if (m == NULL) {
1534	err = ENOMEM;
1535	goto errout;
1536	}
1537	if (len == MHLEN)
1538	M_DUP_PKTHDR(m, q->q_src_m);
1539	if (totlen >= MINCLSIZE) {
1540	MCLGET(m, M_DONTWAIT);
1541	if (m->m_flags & M_EXT)
1542	len = MCLBYTES;
1543	}
1544	m->m_len = len;
1545	top = NULL;
1546	mp = &top;
1547
1548	while (totlen > 0) {
1549	if (top) {
1550	MGET(m, M_DONTWAIT, MT_DATA);
1551	if (m == NULL) {
1552	m_freem(top);
1553	err = ENOMEM;
1554	goto errout;
1555	}
1556	len = MLEN;
1557	}
1558	if (top && totlen >= MINCLSIZE) {
1559	MCLGET(m, M_DONTWAIT);
1560	if (m->m_flags & M_EXT)
1561	len = MCLBYTES;
1562	}
1563	m->m_len = len = min(totlen, len);
1564	totlen -= len;
1565	*mp = m;
1566	mp = &m->m_next;
1567	}
1568	q->q_dst_m = top;
1569	ubsec_mcopy(q->q_src_m, q->q_dst_m,
1570	cpskip, cpoffset);
1571	if (bus_dmamap_create(sc->sc_dmat, 0xfff0,
1572	UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT,
1573	&q->q_dst_map) != 0) {
1574	err = ENOMEM;
1575	goto errout;
1576	}
1577	if (bus_dmamap_load_mbuf(sc->sc_dmat,
1578	q->q_dst_map, q->q_dst_m,
1579	BUS_DMA_NOWAIT) != 0) {
1580	bus_dmamap_destroy(sc->sc_dmat,
1581	q->q_dst_map);
1582	q->q_dst_map = NULL;
1583	err = ENOMEM;
1584	goto errout;
1585	}
1586	#else
1587	device_printf(sc->sc_dev,
1588	"%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n",
1589	__FILE__, __LINE__);
1590	err = EINVAL;
1591	goto errout;
1592	#endif
1593	}
1594	} else {
1595	err = EINVAL;
1596	goto errout;
1597	}
1598
1599	#ifdef UBSEC_DEBUG
1600	DPRINTF("dst skip: %d\n", dskip);
1601	#endif
1602	for (i = j = 0; i < q->q_dst_len; i++) {
1603	struct ubsec_pktbuf *pb;
1604	size_t packl = q->q_dst_map[i].dma_size;
1605	dma_addr_t packp = q->q_dst_map[i].dma_paddr;
1606
1607	if (dskip >= packl) {
1608	dskip -= packl;
1609	continue;
1610	}
1611
1612	packl -= dskip;
1613	packp += dskip;
1614	dskip = 0;
1615
1616	if (packl > 0xfffc) {
1617	DPRINTF("Error: fragment size is bigger than 0xfffc.\n");
1618	err = EIO;
1619	goto errout;
1620	}
1621
1622	if (j == 0)
1623	pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1624	else
1625	pb = &dmap->d_dma->d_dbuf[j - 1];
1626
1627	pb->pb_addr = htole32(packp);
1628
1629	if (dtheend) {
1630	if (packl > dtheend) {
1631	pb->pb_len = htole32(dtheend);
1632	dtheend = 0;
1633	} else {
1634	pb->pb_len = htole32(packl);
1635	dtheend -= packl;
1636	}
1637	} else
1638	pb->pb_len = htole32(packl);
1639
1640	if ((i + 1) == q->q_dst_len) {
1641	if (maccrd)
1642	/* Authentication:
1643	* The last fragment of the output buffer
1644	* contains the HMAC. */
1645	pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1646	offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1647	else
1648	pb->pb_next = 0;
1649	} else
1650	pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1651	offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1652	j++;
1653	}
1654	}
1655
1656	dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1657	offsetof(struct ubsec_dmachunk, d_ctx));
1658
1659	if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1660	/* new Broadcom cards with dynamic long command context structure */
1661
1662	if (enccrd != NULL &&
1663	enccrd->crd_alg == CRYPTO_AES_CBC)
1664	{
1665	struct ubsec_pktctx_aes128 *ctxaes128;
1666	struct ubsec_pktctx_aes192 *ctxaes192;
1667	struct ubsec_pktctx_aes256 *ctxaes256;
1668
1669	switch(ses->ses_keysize)
1670	{
1671	/* AES 128bit */
1672	case 128:
1673	ctxaes128 = (struct ubsec_pktctx_aes128 *)
1674	(dmap->d_alloc.dma_vaddr +
1675	offsetof(struct ubsec_dmachunk, d_ctx));
1676
1677	ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128));
1678	ctxaes128->pc_type = ctx.pc_type;
1679	ctxaes128->pc_flags = ctx.pc_flags;
1680	ctxaes128->pc_offset = ctx.pc_offset;
1681	for (i = 0; i < 4; i++)
1682	ctxaes128->pc_aeskey[i] = ctx.pc_key[i];
1683	for (i = 0; i < 5; i++)
1684	ctxaes128->pc_hminner[i] = ctx.pc_hminner[i];
1685	for (i = 0; i < 5; i++)
1686	ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i];
1687	for (i = 0; i < 4; i++)
1688	ctxaes128->pc_iv[i] = ctx.pc_iv[i];
1689	break;
1690
1691	/* AES 192bit */
1692	case 192:
1693	ctxaes192 = (struct ubsec_pktctx_aes192 *)
1694	(dmap->d_alloc.dma_vaddr +
1695	offsetof(struct ubsec_dmachunk, d_ctx));
1696
1697	ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192));
1698	ctxaes192->pc_type = ctx.pc_type;
1699	ctxaes192->pc_flags = ctx.pc_flags;
1700	ctxaes192->pc_offset = ctx.pc_offset;
1701	for (i = 0; i < 6; i++)
1702	ctxaes192->pc_aeskey[i] = ctx.pc_key[i];
1703	for (i = 0; i < 5; i++)
1704	ctxaes192->pc_hminner[i] = ctx.pc_hminner[i];
1705	for (i = 0; i < 5; i++)
1706	ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i];
1707	for (i = 0; i < 4; i++)
1708	ctxaes192->pc_iv[i] = ctx.pc_iv[i];
1709	break;
1710
1711	/* AES 256bit */
1712	case 256:
1713	ctxaes256 = (struct ubsec_pktctx_aes256 *)
1714	(dmap->d_alloc.dma_vaddr +
1715	offsetof(struct ubsec_dmachunk, d_ctx));
1716
1717	ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256));
1718	ctxaes256->pc_type = ctx.pc_type;
1719	ctxaes256->pc_flags = ctx.pc_flags;
1720	ctxaes256->pc_offset = ctx.pc_offset;
1721	for (i = 0; i < 8; i++)
1722	ctxaes256->pc_aeskey[i] = ctx.pc_key[i];
1723	for (i = 0; i < 5; i++)
1724	ctxaes256->pc_hminner[i] = ctx.pc_hminner[i];
1725	for (i = 0; i < 5; i++)
1726	ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i];
1727	for (i = 0; i < 4; i++)
1728	ctxaes256->pc_iv[i] = ctx.pc_iv[i];
1729	break;
1730
1731	}
1732	} else {
1733	/*
1734	* [3]DES / MD5_HMAC / SHA1_HMAC
1735	*
1736	* MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without
1737	* encryption.
1738	*/
1739	struct ubsec_pktctx_des *ctxdes;
1740
1741	ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr +
1742	offsetof(struct ubsec_dmachunk, d_ctx));
1743
1744	ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des));
1745	ctxdes->pc_type = ctx.pc_type;
1746	ctxdes->pc_flags = ctx.pc_flags;
1747	ctxdes->pc_offset = ctx.pc_offset;
1748	for (i = 0; i < 6; i++)
1749	ctxdes->pc_deskey[i] = ctx.pc_key[i];
1750	for (i = 0; i < 5; i++)
1751	ctxdes->pc_hminner[i] = ctx.pc_hminner[i];
1752	for (i = 0; i < 5; i++)
1753	ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i];
1754	ctxdes->pc_iv[0] = ctx.pc_iv[0];
1755	ctxdes->pc_iv[1] = ctx.pc_iv[1];
1756	}
1757	} else
1758	{
1759	/* old Broadcom card with fixed small command context structure */
1760
1761	/*
1762	* [3]DES / MD5_HMAC / SHA1_HMAC
1763	*/
1764	struct ubsec_pktctx *ctxs;
1765
1766	ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr +
1767	offsetof(struct ubsec_dmachunk, d_ctx));
1768
1769	/* transform generic context into small context */
1770	for (i = 0; i < 6; i++)
1771	ctxs->pc_deskey[i] = ctx.pc_key[i];
1772	for (i = 0; i < 5; i++)
1773	ctxs->pc_hminner[i] = ctx.pc_hminner[i];
1774	for (i = 0; i < 5; i++)
1775	ctxs->pc_hmouter[i] = ctx.pc_hmouter[i];
1776	ctxs->pc_iv[0] = ctx.pc_iv[0];
1777	ctxs->pc_iv[1] = ctx.pc_iv[1];
1778	ctxs->pc_flags = ctx.pc_flags;
1779	ctxs->pc_offset = ctx.pc_offset;
1780	}
1781
1782	#ifdef UBSEC_VERBOSE_DEBUG
1783	DPRINTF("spin_lock_irqsave\n");
1784	#endif
1785	spin_lock_irqsave(&sc->sc_ringmtx, flags);
1786	//spin_lock_irq(&sc->sc_ringmtx);
1787
1788	BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1789	sc->sc_nqueue++;
1790	ubsecstats.hst_ipackets++;
1791	ubsecstats.hst_ibytes += stheend;
1792	ubsec_feed(sc);
1793
1794	#ifdef UBSEC_VERBOSE_DEBUG
1795	DPRINTF("spin_unlock_irqrestore\n");
1796	#endif
1797	spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1798	//spin_unlock_irq(&sc->sc_ringmtx);
1799
1800	return (0);
1801
1802	errout:
1803	if (q != NULL) {
1804	#ifdef NOTYET
1805	if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1806	m_freem(q->q_dst_m);
1807	#endif
1808
1809	if ((q->q_has_dst == 1) && q->q_dst_len > 0) {
1810	#if 0
1811	bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1812	bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1813	#endif
1814	dma_unmap(sc, q->q_dst_map, q->q_dst_len);
1815	}
1816	if (q->q_src_len > 0) {
1817	#if 0
1818	bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1819	bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1820	#endif
1821	dma_unmap(sc, q->q_src_map, q->q_src_len);
1822	}
1823
1824	#ifdef UBSEC_VERBOSE_DEBUG
1825	DPRINTF("spin_lock_irqsave\n");
1826	#endif
1827	spin_lock_irqsave(&sc->sc_ringmtx, flags);
1828	//spin_lock_irq(&sc->sc_ringmtx);
1829
1830	BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1831
1832	#ifdef UBSEC_VERBOSE_DEBUG
1833	DPRINTF("spin_unlock_irqrestore\n");
1834	#endif
1835	spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1836	//spin_unlock_irq(&sc->sc_ringmtx);
1837
1838	}
1839	if (err == EINVAL)
1840	ubsecstats.hst_invalid++;
1841	else
1842	ubsecstats.hst_nomem++;
1843	errout2:
1844	crp->crp_etype = err;
1845	crypto_done(crp);
1846
1847	#ifdef UBSEC_DEBUG
1848	DPRINTF("%s() err = %x\n", __FUNCTION__, err);
1849	#endif
1850
1851	return (0);
1852	}
1853
1854	void
1855	ubsec_callback(struct ubsec_softc sc, struct ubsec_q q)
1856	{
1857	struct cryptop crp = (struct cryptop )q->q_crp;
1858	struct cryptodesc *crd;
1859	struct ubsec_dma *dmap = q->q_dma;
1860	int ivsize = 8;
1861
1862	#ifdef UBSEC_DEBUG
1863	DPRINTF("%s()\n", __FUNCTION__);
1864	#endif
1865
1866	ubsecstats.hst_opackets++;
1867	ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1868
1869	#if 0
1870	bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0,
1871	dmap->d_alloc.dma_map->dm_mapsize,
1872	BUS_DMASYNC_POSTREAD\|BUS_DMASYNC_POSTWRITE);
1873	if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1874	bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1875	0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1876	bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1877	bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1878	}
1879	bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
1880	0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1881	bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1882	bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1883	#endif
1884
1885	if ((q->q_has_dst == 1) && q->q_dst_len > 0)
1886	dma_unmap(sc, q->q_dst_map, q->q_dst_len);
1887
1888	dma_unmap(sc, q->q_src_map, q->q_src_len);
1889
1890	#ifdef NOTYET
1891	if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) {
1892	m_freem(q->q_src_m);
1893	crp->crp_buf = (caddr_t)q->q_dst_m;
1894	}
1895	#endif
1896
1897	/* copy out IV for future use */
1898	if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1899	for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1900	if (crd->crd_alg != CRYPTO_DES_CBC &&
1901	crd->crd_alg != CRYPTO_3DES_CBC &&
1902	crd->crd_alg != CRYPTO_AES_CBC)
1903	continue;
1904
1905	if (crd->crd_alg == CRYPTO_AES_CBC)
1906	ivsize = 16;
1907	else
1908	ivsize = 8;
1909
1910	if (crp->crp_flags & CRYPTO_F_SKBUF)
1911	#if 0
1912	m_copydata((struct sk_buff *)crp->crp_buf,
1913	crd->crd_skip + crd->crd_len - 8, 8,
1914	(caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1915	#endif
1916	crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf,
1917	crd->crd_skip + crd->crd_len - ivsize, ivsize,
1918	(caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1919
1920	else if (crp->crp_flags & CRYPTO_F_IOV) {
1921	#if 0
1922	cuio_copydata((struct uio *)crp->crp_buf,
1923	crd->crd_skip + crd->crd_len - 8, 8,
1924	(caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1925	#endif
1926	crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf,
1927	crd->crd_skip + crd->crd_len - ivsize, ivsize,
1928	(caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1929
1930	}
1931	break;
1932	}
1933	}
1934
1935	for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1936	if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1937	crd->crd_alg != CRYPTO_SHA1_HMAC)
1938	continue;
1939	#if 0
1940	if (crp->crp_flags & CRYPTO_F_SKBUF)
1941	m_copyback((struct sk_buff *)crp->crp_buf,
1942	crd->crd_inject, 12,
1943	dmap->d_dma->d_macbuf);
1944	#endif
1945	#if 0
1946	/* BUG? it does not honor the mac len.. */
1947	crypto_copyback(crp->crp_flags, crp->crp_buf,
1948	crd->crd_inject, 12,
1949	(caddr_t)dmap->d_dma->d_macbuf);
1950	#endif
1951	crypto_copyback(crp->crp_flags, crp->crp_buf,
1952	crd->crd_inject,
1953	sc->sc_sessions[q->q_sesn].ses_mlen,
1954	(caddr_t)dmap->d_dma->d_macbuf);
1955	#if 0
1956	else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1957	bcopy((caddr_t)dmap->d_dma->d_macbuf,
1958	crp->crp_mac, 12);
1959	#endif
1960	break;
1961	}
1962	BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1963	crypto_done(crp);
1964	}
1965
1966	void
1967	ubsec_mcopy(struct sk_buff srcm, struct sk_buff dstm, int hoffset, int toffset)
1968	{
1969	int i, j, dlen, slen;
1970	caddr_t dptr, sptr;
1971
1972	j = 0;
1973	sptr = srcm->data;
1974	slen = srcm->len;
1975	dptr = dstm->data;
1976	dlen = dstm->len;
1977
1978	while (1) {
1979	for (i = 0; i < min(slen, dlen); i++) {
1980	if (j < hoffset \|\| j >= toffset)
1981	dptr++ = sptr++;
1982	slen--;
1983	dlen--;
1984	j++;
1985	}
1986	if (slen == 0) {
1987	srcm = srcm->next;
1988	if (srcm == NULL)
1989	return;
1990	sptr = srcm->data;
1991	slen = srcm->len;
1992	}
1993	if (dlen == 0) {
1994	dstm = dstm->next;
1995	if (dstm == NULL)
1996	return;
1997	dptr = dstm->data;
1998	dlen = dstm->len;
1999	}
2000	}
2001	}
2002
2003	int
2004	ubsec_dma_malloc(struct ubsec_softc sc, struct ubsec_dma_alloc dma,
2005	size_t size, int mapflags)
2006	{
2007	dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv,
2008	size, &dma->dma_paddr, GFP_KERNEL);
2009
2010	if (likely(dma->dma_vaddr))
2011	{
2012	dma->dma_size = size;
2013	return (0);
2014	}
2015
2016	DPRINTF("could not allocate %d bytes of coherent memory.\n", size);
2017
2018	return (1);
2019	}
2020
2021	void
2022	ubsec_dma_free(struct ubsec_softc sc, struct ubsec_dma_alloc dma)
2023	{
2024	dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr,
2025	dma->dma_paddr);
2026	}
2027
2028	/*
2029	* Resets the board. Values in the regesters are left as is
2030	* from the reset (i.e. initial values are assigned elsewhere).
2031	*/
2032	void
2033	ubsec_reset_board(struct ubsec_softc *sc)
2034	{
2035	volatile u_int32_t ctrl;
2036
2037	#ifdef UBSEC_DEBUG
2038	DPRINTF("%s()\n", __FUNCTION__);
2039	#endif
2040	DPRINTF("Send reset signal to chip.\n");
2041
2042	ctrl = READ_REG(sc, BS_CTRL);
2043	ctrl \|= BS_CTRL_RESET;
2044	WRITE_REG(sc, BS_CTRL, ctrl);
2045
2046	/*
2047	* Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
2048	*/
2049	DELAY(10);
2050	}
2051
2052	/*
2053	* Init Broadcom registers
2054	*/
2055	void
2056	ubsec_init_board(struct ubsec_softc *sc)
2057	{
2058	u_int32_t ctrl;
2059
2060	#ifdef UBSEC_DEBUG
2061	DPRINTF("%s()\n", __FUNCTION__);
2062	#endif
2063	DPRINTF("Initialize chip.\n");
2064
2065	ctrl = READ_REG(sc, BS_CTRL);
2066	ctrl &= ~(BS_CTRL_BE32 \| BS_CTRL_BE64);
2067	ctrl \|= BS_CTRL_LITTLE_ENDIAN \| BS_CTRL_MCR1INT \| BS_CTRL_DMAERR;
2068
2069	WRITE_REG(sc, BS_CTRL, ctrl);
2070
2071	/* Set chip capabilities (BCM5365P) */
2072	sc->sc_flags \|= UBS_FLAGS_LONGCTX \| UBS_FLAGS_AES;
2073	}
2074
2075	/*
2076	* Clean up after a chip crash.
2077	* It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2078	*/
2079	void
2080	ubsec_cleanchip(struct ubsec_softc *sc)
2081	{
2082	struct ubsec_q *q;
2083
2084	#ifdef UBSEC_DEBUG
2085	DPRINTF("%s()\n", __FUNCTION__);
2086	#endif
2087	DPRINTF("Clean up queues after chip crash.\n");
2088
2089	while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2090	q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip);
2091	BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
2092	ubsec_free_q(sc, q);
2093	}
2094	}
2095
2096	/*
2097	* free a ubsec_q
2098	* It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2099	*/
2100	int
2101	ubsec_free_q(struct ubsec_softc sc, struct ubsec_q q)
2102	{
2103	struct ubsec_q *q2;
2104	struct cryptop *crp;
2105	int npkts;
2106	int i;
2107
2108	#ifdef UBSEC_DEBUG
2109	DPRINTF("%s()\n", __FUNCTION__);
2110	#endif
2111
2112	npkts = q->q_nstacked_mcrs;
2113
2114	for (i = 0; i < npkts; i++) {
2115	if(q->q_stacked_mcr[i]) {
2116	q2 = q->q_stacked_mcr[i];
2117
2118	if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2119	#ifdef NOTYET
2120	m_freem(q2->q_dst_m);
2121	#else
2122	printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__);
2123	#endif
2124
2125	crp = (struct cryptop *)q2->q_crp;
2126
2127	BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2128
2129	crp->crp_etype = EFAULT;
2130	crypto_done(crp);
2131	} else {
2132	break;
2133	}
2134	}
2135
2136	/*
2137	* Free header MCR
2138	*/
2139	if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2140	#ifdef NOTYET
2141	m_freem(q->q_dst_m);
2142	#else
2143	printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__);
2144	#endif
2145
2146	crp = (struct cryptop *)q->q_crp;
2147
2148	BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2149
2150	crp->crp_etype = EFAULT;
2151	crypto_done(crp);
2152	return(0);
2153	}
2154
2155	/*
2156	* Routine to reset the chip and clean up.
2157	* It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2158	*/
2159	void
2160	ubsec_totalreset(struct ubsec_softc *sc)
2161	{
2162
2163	#ifdef UBSEC_DEBUG
2164	DPRINTF("%s()\n", __FUNCTION__);
2165	#endif
2166	DPRINTF("initiate total chip reset.. \n");
2167	ubsec_reset_board(sc);
2168	ubsec_init_board(sc);
2169	ubsec_cleanchip(sc);
2170	}
2171
2172	void
2173	ubsec_dump_pb(struct ubsec_pktbuf *pb)
2174	{
2175	printf("addr 0x%x (0x%x) next 0x%x\n",
2176	pb->pb_addr, pb->pb_len, pb->pb_next);
2177	}
2178
2179	void
2180	ubsec_dump_mcr(struct ubsec_mcr *mcr)
2181	{
2182	struct ubsec_mcr_add *ma;
2183	int i;
2184
2185	printf("MCR:\n");
2186	printf(" pkts: %u, flags 0x%x\n",
2187	letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2188	ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2189	for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2190	printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2191	letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2192	letoh16(ma->mcr_reserved));
2193	printf(" %d: ipkt ", i);
2194	ubsec_dump_pb(&ma->mcr_ipktbuf);
2195	printf(" %d: opkt ", i);
2196	ubsec_dump_pb(&ma->mcr_opktbuf);
2197	ma++;
2198	}
2199	printf("END MCR\n");
2200	}
2201
2202	static int __init mod_init(void) {
2203	return ssb_driver_register(&ubsec_ssb_driver);
2204	}
2205
2206	static void __exit mod_exit(void) {
2207	ssb_driver_unregister(&ubsec_ssb_driver);
2208	}
2209
2210	module_init(mod_init);
2211	module_exit(mod_exit);
2212
2213	// Meta information
2214	MODULE_AUTHOR("Daniel Mueller <daniel@danm.de>");
2215	MODULE_LICENSE("BSD");
2216	MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core");
2217	MODULE_VERSION(DRV_MODULE_VERSION);
2218
2219

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