Root/target/linux/atheros/patches-2.6.38/105-ar2315_pci.patch

1--- a/arch/mips/ar231x/Makefile
2+++ b/arch/mips/ar231x/Makefile
3@@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
4 
5 obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
6 obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
7+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
8--- /dev/null
9+++ b/arch/mips/ar231x/pci.c
10@@ -0,0 +1,230 @@
11+/*
12+ * This program is free software; you can redistribute it and/or
13+ * modify it under the terms of the GNU General Public License
14+ * as published by the Free Software Foundation; either version 2
15+ * of the License, or (at your option) any later version.
16+ *
17+ * This program is distributed in the hope that it will be useful,
18+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
19+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20+ * GNU General Public License for more details.
21+ *
22+ * You should have received a copy of the GNU General Public License
23+ * along with this program; if not, write to the Free Software
24+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25+ */
26+
27+#include <linux/types.h>
28+#include <linux/pci.h>
29+#include <linux/kernel.h>
30+#include <linux/init.h>
31+#include <linux/mm.h>
32+#include <linux/spinlock.h>
33+#include <linux/delay.h>
34+#include <linux/irq.h>
35+#include <asm/bootinfo.h>
36+#include <asm/paccess.h>
37+#include <asm/irq_cpu.h>
38+#include <asm/io.h>
39+#include <ar231x_platform.h>
40+#include <ar231x.h>
41+#include <ar2315_regs.h>
42+#include "devices.h"
43+
44+#define AR531X_MEM_BASE 0x80800000UL
45+#define AR531X_MEM_SIZE 0x00ffffffUL
46+#define AR531X_IO_SIZE 0x00007fffUL
47+
48+static unsigned long configspace;
49+
50+static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
51+{
52+ unsigned long flags;
53+ int func = PCI_FUNC(devfn);
54+ int dev = PCI_SLOT(devfn);
55+ u32 value = 0;
56+ int err = 0;
57+ u32 addr;
58+
59+ if (((dev != 0) && (dev != 3)) || (func > 2))
60+ return PCIBIOS_DEVICE_NOT_FOUND;
61+
62+ /* Select Configuration access */
63+ local_irq_save(flags);
64+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
65+ mb();
66+
67+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
68+ if (size == 1)
69+ addr ^= 0x3;
70+ else if (size == 2)
71+ addr ^= 0x2;
72+
73+ if (write) {
74+ value = *ptr;
75+ if (size == 1)
76+ err = put_dbe(value, (u8 *) addr);
77+ else if (size == 2)
78+ err = put_dbe(value, (u16 *) addr);
79+ else if (size == 4)
80+ err = put_dbe(value, (u32 *) addr);
81+ } else {
82+ if (size == 1)
83+ err = get_dbe(value, (u8 *) addr);
84+ else if (size == 2)
85+ err = get_dbe(value, (u16 *) addr);
86+ else if (size == 4)
87+ err = get_dbe(value, (u32 *) addr);
88+ if (err)
89+ *ptr = 0xffffffff;
90+ else
91+ *ptr = value;
92+ }
93+
94+ /* Select Memory access */
95+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
96+ local_irq_restore(flags);
97+
98+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL);
99+}
100+
101+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
102+{
103+ return config_access(devfn, where, size, value, 0);
104+}
105+
106+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
107+{
108+ return config_access(devfn, where, size, &value, 1);
109+}
110+
111+struct pci_ops ar231x_pci_ops = {
112+ .read = ar231x_pci_read,
113+ .write = ar231x_pci_write,
114+};
115+
116+static struct resource ar231x_mem_resource = {
117+ .name = "AR531x PCI MEM",
118+ .start = AR531X_MEM_BASE,
119+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
120+ .flags = IORESOURCE_MEM,
121+};
122+
123+static struct resource ar231x_io_resource = {
124+ .name = "AR531x PCI I/O",
125+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
126+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
127+ .flags = IORESOURCE_IO,
128+};
129+
130+struct pci_controller ar231x_pci_controller = {
131+ .pci_ops = &ar231x_pci_ops,
132+ .mem_resource = &ar231x_mem_resource,
133+ .io_resource = &ar231x_io_resource,
134+ .mem_offset = 0x00000000UL,
135+ .io_offset = 0x00000000UL,
136+};
137+
138+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
139+{
140+ return AR2315_IRQ_LCBUS_PCI;
141+}
142+
143+int pcibios_plat_dev_init(struct pci_dev *dev)
144+{
145+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
146+ pci_write_config_word(dev, 0x40, 0);
147+
148+ /* Clear any pending Abort or external Interrupts
149+ * and enable interrupt processing */
150+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
151+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
152+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
153+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
154+
155+ return 0;
156+}
157+
158+static void
159+ar2315_pci_fixup(struct pci_dev *dev)
160+{
161+ unsigned int devfn = dev->devfn;
162+
163+ if (dev->bus->number != 0)
164+ return;
165+
166+ /* Only fix up the PCI host settings */
167+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
168+ return;
169+
170+ /* Fix up MBARs */
171+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
172+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
173+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
174+ pci_write_config_dword(dev, PCI_COMMAND,
175+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
176+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
177+ PCI_COMMAND_FAST_BACK);
178+}
179+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
180+
181+static int __init
182+ar2315_pci_init(void)
183+{
184+ u32 reg;
185+
186+ if (ar231x_devtype != DEV_TYPE_AR2315)
187+ return -ENODEV;
188+
189+ configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT, 1*1024*1024); /* Remap PCI config space */
190+ ar231x_pci_controller.io_map_base =
191+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
192+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
193+
194+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
195+ msleep(10);
196+
197+ reg &= ~AR2315_RESET_PCIDMA;
198+ ar231x_write_reg(AR2315_RESET, reg);
199+ msleep(10);
200+
201+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
202+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
203+
204+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
205+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
206+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
207+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
208+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
209+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
210+
211+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
212+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
213+ AR2315_PCIRST_LOW);
214+ msleep(100);
215+
216+ /* Bring the PCI out of reset */
217+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
218+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
219+
220+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
221+ 0x1E | /* 1GB uncached */
222+ (1 << 5) | /* Enable uncached */
223+ (0x2 << 30) /* Base: 0x80000000 */
224+ );
225+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
226+
227+ msleep(500);
228+
229+ /* dirty hack - anyone with a datasheet that knows the memory map ? */
230+ ioport_resource.start = 0x10000000;
231+ ioport_resource.end = 0xffffffff;
232+ iomem_resource.start = 0x10000000;
233+ iomem_resource.end = 0xffffffff;
234+
235+ register_pci_controller(&ar231x_pci_controller);
236+
237+ return 0;
238+}
239+
240+arch_initcall(ar2315_pci_init);
241--- a/arch/mips/ar231x/Kconfig
242+++ b/arch/mips/ar231x/Kconfig
243@@ -15,3 +15,13 @@ config ATHEROS_AR2315
244     select SYS_SUPPORTS_BIG_ENDIAN
245     select GENERIC_GPIO
246     default y
247+
248+config ATHEROS_AR2315_PCI
249+ bool "PCI support"
250+ depends on ATHEROS_AR2315
251+ select HW_HAS_PCI
252+ select PCI
253+ select USB_ARCH_HAS_HCD
254+ select USB_ARCH_HAS_OHCI
255+ select USB_ARCH_HAS_EHCI
256+ default y
257--- a/arch/mips/ar231x/ar2315.c
258+++ b/arch/mips/ar231x/ar2315.c
259@@ -63,6 +63,27 @@ static inline void ar2315_gpio_irq(void)
260         do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
261 }
262 
263+#ifdef CONFIG_ATHEROS_AR2315_PCI
264+static inline void pci_abort_irq(void)
265+{
266+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
267+}
268+
269+static inline void pci_ack_irq(void)
270+{
271+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
272+}
273+
274+void ar2315_pci_irq(int irq)
275+{
276+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
277+ pci_abort_irq();
278+ else {
279+ do_IRQ(irq);
280+ pci_ack_irq();
281+ }
282+}
283+#endif /* CONFIG_ATHEROS_AR2315_PCI */
284 
285 /*
286  * Called when an interrupt is received, this function
287@@ -81,6 +102,10 @@ ar2315_irq_dispatch(void)
288         do_IRQ(AR2315_IRQ_WLAN0_INTRS);
289     else if (pending & CAUSEF_IP4)
290         do_IRQ(AR2315_IRQ_ENET0_INTRS);
291+#ifdef CONFIG_ATHEROS_AR2315_PCI
292+ else if (pending & CAUSEF_IP5)
293+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
294+#endif
295     else if (pending & CAUSEF_IP2) {
296         unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
297 
298

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive