Root/target/linux/brcm47xx/patches-3.0/0011-bcm47xx-make-it-possible-to-build-bcm47xx-without-ss.patch

1From 82d03f33ba3e41511e56bd6ae5ae93b3b1bd0b63 Mon Sep 17 00:00:00 2001
2From: Hauke Mehrtens <hauke@hauke-m.de>
3Date: Wed, 22 Jun 2011 22:16:35 +0200
4Subject: [PATCH 11/14] bcm47xx: make it possible to build bcm47xx without ssb.
5
6
7Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
8---
9 arch/mips/Kconfig | 8 +-------
10 arch/mips/bcm47xx/Kconfig | 18 ++++++++++++++++++
11 arch/mips/bcm47xx/Makefile | 3 ++-
12 arch/mips/bcm47xx/gpio.c | 6 ++++++
13 arch/mips/bcm47xx/nvram.c | 4 ++++
14 arch/mips/bcm47xx/serial.c | 4 ++++
15 arch/mips/bcm47xx/setup.c | 8 ++++++++
16 arch/mips/bcm47xx/time.c | 2 ++
17 arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 4 ++++
18 arch/mips/include/asm/mach-bcm47xx/gpio.h | 12 ++++++++++++
19 arch/mips/pci/pci-bcm47xx.c | 6 ++++++
20 drivers/watchdog/bcm47xx_wdt.c | 4 ++++
21 12 files changed, 71 insertions(+), 8 deletions(-)
22 create mode 100644 arch/mips/bcm47xx/Kconfig
23
24--- a/arch/mips/Kconfig
25+++ b/arch/mips/Kconfig
26@@ -91,15 +91,8 @@ config BCM47XX
27     select DMA_NONCOHERENT
28     select HW_HAS_PCI
29     select IRQ_CPU
30- select SYS_HAS_CPU_MIPS32_R1
31     select SYS_SUPPORTS_32BIT_KERNEL
32     select SYS_SUPPORTS_LITTLE_ENDIAN
33- select SSB
34- select SSB_DRIVER_MIPS
35- select SSB_DRIVER_EXTIF
36- select SSB_EMBEDDED
37- select SSB_B43_PCI_BRIDGE if PCI
38- select SSB_PCICORE_HOSTMODE if PCI
39     select GENERIC_GPIO
40     select SYS_HAS_EARLY_PRINTK
41     select CFE
42@@ -785,6 +778,7 @@ endchoice
43 
44 source "arch/mips/alchemy/Kconfig"
45 source "arch/mips/ath79/Kconfig"
46+source "arch/mips/bcm47xx/Kconfig"
47 source "arch/mips/bcm63xx/Kconfig"
48 source "arch/mips/jazz/Kconfig"
49 source "arch/mips/jz4740/Kconfig"
50--- /dev/null
51+++ b/arch/mips/bcm47xx/Kconfig
52@@ -0,0 +1,18 @@
53+if BCM47XX
54+
55+config BCM47XX_SSB
56+ bool "SSB Support for Broadcom BCM47XX"
57+ select SYS_HAS_CPU_MIPS32_R1
58+ select SSB
59+ select SSB_DRIVER_MIPS
60+ select SSB_DRIVER_EXTIF
61+ select SSB_EMBEDDED
62+ select SSB_B43_PCI_BRIDGE if PCI
63+ select SSB_PCICORE_HOSTMODE if PCI
64+ default y
65+ help
66+ Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support bus.
67+
68+ This will generate an image with support for SSB and MIPS32 R2 instruction set.
69+
70+endif
71--- a/arch/mips/bcm47xx/Makefile
72+++ b/arch/mips/bcm47xx/Makefile
73@@ -3,4 +3,5 @@
74 # under Linux.
75 #
76 
77-obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
78+obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
79+obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
80--- a/arch/mips/bcm47xx/gpio.c
81+++ b/arch/mips/bcm47xx/gpio.c
82@@ -21,6 +21,7 @@ static DECLARE_BITMAP(gpio_in_use, BCM47
83 int gpio_request(unsigned gpio, const char *tag)
84 {
85     switch (bcm47xx_active_bus_type) {
86+#ifdef CONFIG_BCM47XX_SSB
87     case BCM47XX_BUS_TYPE_SSB:
88         if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
89             ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
90@@ -34,6 +35,7 @@ int gpio_request(unsigned gpio, const ch
91             return -EBUSY;
92 
93         return 0;
94+#endif
95     }
96     return -EINVAL;
97 }
98@@ -42,6 +44,7 @@ EXPORT_SYMBOL(gpio_request);
99 void gpio_free(unsigned gpio)
100 {
101     switch (bcm47xx_active_bus_type) {
102+#ifdef CONFIG_BCM47XX_SSB
103     case BCM47XX_BUS_TYPE_SSB:
104         if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
105             ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
106@@ -53,6 +56,7 @@ void gpio_free(unsigned gpio)
107 
108         clear_bit(gpio, gpio_in_use);
109         return;
110+#endif
111     }
112 }
113 EXPORT_SYMBOL(gpio_free);
114@@ -60,6 +64,7 @@ EXPORT_SYMBOL(gpio_free);
115 int gpio_to_irq(unsigned gpio)
116 {
117     switch (bcm47xx_active_bus_type) {
118+#ifdef CONFIG_BCM47XX_SSB
119     case BCM47XX_BUS_TYPE_SSB:
120         if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco))
121             return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2;
122@@ -67,6 +72,7 @@ int gpio_to_irq(unsigned gpio)
123             return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2;
124         else
125             return -EINVAL;
126+#endif
127     }
128     return -EINVAL;
129 }
130--- a/arch/mips/bcm47xx/nvram.c
131+++ b/arch/mips/bcm47xx/nvram.c
132@@ -26,7 +26,9 @@ static char nvram_buf[NVRAM_SPACE];
133 /* Probe for NVRAM header */
134 static void early_nvram_init(void)
135 {
136+#ifdef CONFIG_BCM47XX_SSB
137     struct ssb_mipscore *mcore_ssb;
138+#endif
139     struct nvram_header *header;
140     int i;
141     u32 base = 0;
142@@ -35,11 +37,13 @@ static void early_nvram_init(void)
143     u32 *src, *dst;
144 
145     switch (bcm47xx_active_bus_type) {
146+#ifdef CONFIG_BCM47XX_SSB
147     case BCM47XX_BUS_TYPE_SSB:
148         mcore_ssb = &bcm47xx_bus.ssb.mipscore;
149         base = mcore_ssb->flash_window;
150         lim = mcore_ssb->flash_window_size;
151         break;
152+#endif
153     }
154 
155     off = FLASH_MIN;
156--- a/arch/mips/bcm47xx/serial.c
157+++ b/arch/mips/bcm47xx/serial.c
158@@ -23,6 +23,7 @@ static struct platform_device uart8250_d
159     },
160 };
161 
162+#ifdef CONFIG_BCM47XX_SSB
163 static int __init uart8250_init_ssb(void)
164 {
165     int i;
166@@ -44,12 +45,15 @@ static int __init uart8250_init_ssb(void
167     }
168     return platform_device_register(&uart8250_device);
169 }
170+#endif
171 
172 static int __init uart8250_init(void)
173 {
174     switch (bcm47xx_active_bus_type) {
175+#ifdef CONFIG_BCM47XX_SSB
176     case BCM47XX_BUS_TYPE_SSB:
177         return uart8250_init_ssb();
178+#endif
179     }
180     return -EINVAL;
181 }
182--- a/arch/mips/bcm47xx/setup.c
183+++ b/arch/mips/bcm47xx/setup.c
184@@ -47,9 +47,11 @@ static void bcm47xx_machine_restart(char
185     local_irq_disable();
186     /* Set the watchdog timer to reset immediately */
187     switch (bcm47xx_active_bus_type) {
188+#ifdef CONFIG_BCM47XX_SSB
189     case BCM47XX_BUS_TYPE_SSB:
190         ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
191         break;
192+#endif
193     }
194     while (1)
195         cpu_relax();
196@@ -60,14 +62,17 @@ static void bcm47xx_machine_halt(void)
197     /* Disable interrupts and watchdog and spin forever */
198     local_irq_disable();
199     switch (bcm47xx_active_bus_type) {
200+#ifdef CONFIG_BCM47XX_SSB
201     case BCM47XX_BUS_TYPE_SSB:
202         ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
203         break;
204+#endif
205     }
206     while (1)
207         cpu_relax();
208 }
209 
210+#ifdef CONFIG_BCM47XX_SSB
211 #define READ_FROM_NVRAM(_outvar, name, buf) \
212     if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\
213         sprom->_outvar = simple_strtoul(buf, NULL, 0);
214@@ -288,13 +293,16 @@ static void __init bcm47xx_register_ssb(
215         }
216     }
217 }
218+#endif
219 
220 void __init plat_mem_setup(void)
221 {
222     struct cpuinfo_mips *c = &current_cpu_data;
223 
224+#ifdef CONFIG_BCM47XX_SSB
225     bcm47xx_active_bus_type = BCM47XX_BUS_TYPE_SSB;
226     bcm47xx_register_ssb();
227+#endif
228 
229     _machine_restart = bcm47xx_machine_restart;
230     _machine_halt = bcm47xx_machine_halt;
231--- a/arch/mips/bcm47xx/time.c
232+++ b/arch/mips/bcm47xx/time.c
233@@ -40,9 +40,11 @@ void __init plat_time_init(void)
234     write_c0_compare(0xffff);
235 
236     switch (bcm47xx_active_bus_type) {
237+#ifdef CONFIG_BCM47XX_SSB
238     case BCM47XX_BUS_TYPE_SSB:
239         hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
240         break;
241+#endif
242     }
243 
244     if (!hz)
245--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
246+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
247@@ -22,11 +22,15 @@
248 #include <linux/ssb/ssb.h>
249 
250 enum bcm47xx_bus_type {
251+#ifdef CONFIG_BCM47XX_SSB
252     BCM47XX_BUS_TYPE_SSB,
253+#endif
254 };
255 
256 union bcm47xx_bus {
257+#ifdef CONFIG_BCM47XX_SSB
258     struct ssb_bus ssb;
259+#endif
260 };
261 
262 extern union bcm47xx_bus bcm47xx_bus;
263--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
264+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
265@@ -22,8 +22,10 @@ extern int gpio_to_irq(unsigned gpio);
266 static inline int gpio_get_value(unsigned gpio)
267 {
268     switch (bcm47xx_active_bus_type) {
269+#ifdef CONFIG_BCM47XX_SSB
270     case BCM47XX_BUS_TYPE_SSB:
271         return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio);
272+#endif
273     }
274     return -EINVAL;
275 }
276@@ -31,18 +33,22 @@ static inline int gpio_get_value(unsigne
277 static inline void gpio_set_value(unsigned gpio, int value)
278 {
279     switch (bcm47xx_active_bus_type) {
280+#ifdef CONFIG_BCM47XX_SSB
281     case BCM47XX_BUS_TYPE_SSB:
282         ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
283                  value ? 1 << gpio : 0);
284+#endif
285     }
286 }
287 
288 static inline int gpio_direction_input(unsigned gpio)
289 {
290     switch (bcm47xx_active_bus_type) {
291+#ifdef CONFIG_BCM47XX_SSB
292     case BCM47XX_BUS_TYPE_SSB:
293         ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0);
294         return 0;
295+#endif
296     }
297     return -EINVAL;
298 }
299@@ -50,6 +56,7 @@ static inline int gpio_direction_input(u
300 static inline int gpio_direction_output(unsigned gpio, int value)
301 {
302     switch (bcm47xx_active_bus_type) {
303+#ifdef CONFIG_BCM47XX_SSB
304     case BCM47XX_BUS_TYPE_SSB:
305         /* first set the gpio out value */
306         ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
307@@ -57,6 +64,7 @@ static inline int gpio_direction_output(
308         /* then set the gpio mode */
309         ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio);
310         return 0;
311+#endif
312     }
313     return -EINVAL;
314 }
315@@ -64,10 +72,12 @@ static inline int gpio_direction_output(
316 static inline int gpio_intmask(unsigned gpio, int value)
317 {
318     switch (bcm47xx_active_bus_type) {
319+#ifdef CONFIG_BCM47XX_SSB
320     case BCM47XX_BUS_TYPE_SSB:
321         ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio,
322                  value ? 1 << gpio : 0);
323         return 0;
324+#endif
325     }
326     return -EINVAL;
327 }
328@@ -75,10 +85,12 @@ static inline int gpio_intmask(unsigned
329 static inline int gpio_polarity(unsigned gpio, int value)
330 {
331     switch (bcm47xx_active_bus_type) {
332+#ifdef CONFIG_BCM47XX_SSB
333     case BCM47XX_BUS_TYPE_SSB:
334         ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio,
335                   value ? 1 << gpio : 0);
336         return 0;
337+#endif
338     }
339     return -EINVAL;
340 }
341--- a/arch/mips/pci/pci-bcm47xx.c
342+++ b/arch/mips/pci/pci-bcm47xx.c
343@@ -25,6 +25,7 @@
344 #include <linux/types.h>
345 #include <linux/pci.h>
346 #include <linux/ssb/ssb.h>
347+#include <bcm47xx.h>
348 
349 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
350 {
351@@ -33,9 +34,13 @@ int __init pcibios_map_irq(const struct
352 
353 int pcibios_plat_dev_init(struct pci_dev *dev)
354 {
355+#ifdef CONFIG_BCM47XX_SSB
356     int res;
357     u8 slot, pin;
358 
359+ if (bcm47xx_active_bus_type != BCM47XX_BUS_TYPE_SSB)
360+ return 0;
361+
362     res = ssb_pcibios_plat_dev_init(dev);
363     if (res < 0) {
364         printk(KERN_ALERT "PCI: Failed to init device %s\n",
365@@ -55,5 +60,6 @@ int pcibios_plat_dev_init(struct pci_dev
366     }
367 
368     dev->irq = res;
369+#endif
370     return 0;
371 }
372--- a/drivers/watchdog/bcm47xx_wdt.c
373+++ b/drivers/watchdog/bcm47xx_wdt.c
374@@ -55,17 +55,21 @@ static inline void bcm47xx_wdt_hw_start(
375 {
376     /* this is 2,5s on 100Mhz clock and 2s on 133 Mhz */
377     switch (bcm47xx_active_bus_type) {
378+#ifdef CONFIG_BCM47XX_SSB
379     case BCM47XX_BUS_TYPE_SSB:
380         ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff);
381         break;
382+#endif
383     }
384 }
385 
386 static inline int bcm47xx_wdt_hw_stop(void)
387 {
388     switch (bcm47xx_active_bus_type) {
389+#ifdef CONFIG_BCM47XX_SSB
390     case BCM47XX_BUS_TYPE_SSB:
391         return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
392+#endif
393     }
394     return -EINVAL;
395 }
396

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive