| 1 | --- a/drivers/ssb/scan.c |
| 2 | +++ b/drivers/ssb/scan.c |
| 3 | @@ -90,6 +90,14 @@ const char *ssb_core_name(u16 coreid) |
| 4 | return "ARM 1176"; |
| 5 | case SSB_DEV_ARM_7TDMI: |
| 6 | return "ARM 7TDMI"; |
| 7 | + case SSB_DEV_ETHERNET_GBIT2: |
| 8 | + return "Gigabit MAC"; |
| 9 | + case SSB_DEV_MIPS_74K: |
| 10 | + return "MIPS 74k"; |
| 11 | + case SSB_DEV_DDR_CTRLR: |
| 12 | + return "DDR1/2 memory controller"; |
| 13 | + case SSB_DEV_I2S: |
| 14 | + return "I2S"; |
| 15 | } |
| 16 | return "UNKNOWN"; |
| 17 | } |
| 18 | @@ -148,6 +156,7 @@ static u8 chipid_to_nrcores(u16 chipid) |
| 19 | case 0x4710: |
| 20 | case 0x4610: |
| 21 | case 0x4704: |
| 22 | + case 0x4716: |
| 23 | return 9; |
| 24 | default: |
| 25 | ssb_printk(KERN_ERR PFX |
| 26 | --- a/include/linux/ssb/ssb.h |
| 27 | +++ b/include/linux/ssb/ssb.h |
| 28 | @@ -155,9 +155,16 @@ struct ssb_bus_ops { |
| 29 | #define SSB_DEV_MINI_MACPHY 0x823 |
| 30 | #define SSB_DEV_ARM_1176 0x824 |
| 31 | #define SSB_DEV_ARM_7TDMI 0x825 |
| 32 | +#define SSB_DEV_ETHERNET_GBIT2 0x82d |
| 33 | +#define SSB_DEV_MIPS_74K 0x82c |
| 34 | +#define SSB_DEV_DDR_CTRLR 0x82e |
| 35 | +#define SSB_DEV_I2S 0x834 |
| 36 | +#define SSB_DEV_DEFAULT 0xfff |
| 37 | |
| 38 | /* Vendor-ID values */ |
| 39 | #define SSB_VENDOR_BROADCOM 0x4243 |
| 40 | +#define SSB_VENDOR_BROADCOM2 0x04BF |
| 41 | +#define SSB_VENDOR_ARM 0x43b |
| 42 | |
| 43 | /* Some kernel subsystems poke with dev->drvdata, so we must use the |
| 44 | * following ugly workaround to get from struct device to struct ssb_device */ |
| 45 | --- a/include/linux/ssb/ssb_regs.h |
| 46 | +++ b/include/linux/ssb/ssb_regs.h |
| 47 | @@ -11,6 +11,7 @@ |
| 48 | #define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */ |
| 49 | #define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */ |
| 50 | #define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */ |
| 51 | +#define SSB_AI_BASE 0x18100000 /* base for AI registers */ |
| 52 | |
| 53 | #define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */ |
| 54 | #define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */ |
| 55 | @@ -26,6 +27,7 @@ |
| 56 | #define SSB_EUART (SSB_EXTIF_BASE + 0x00800000) |
| 57 | #define SSB_LED (SSB_EXTIF_BASE + 0x00900000) |
| 58 | |
| 59 | +#define SSB_EROM_ASD_SZ_BASE 0x00001000 |
| 60 | |
| 61 | /* Enumeration space constants */ |
| 62 | #define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */ |
| 63 | @@ -499,5 +501,41 @@ enum { |
| 64 | #define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */ |
| 65 | #define SSB_ADM_BASE2_SHIFT 16 |
| 66 | |
| 67 | +/***** EROM defines for AI type busses *****/ |
| 68 | +#define SSB_EROM_VALID 1 |
| 69 | +#define SSB_EROM_END 0xe |
| 70 | +#define SSB_EROM_TAG 0xe |
| 71 | +/* Adress Space Descriptor */ |
| 72 | +#define SSB_EROM_ASD 0x4 |
| 73 | +#define SSB_EROM_ASD_SP_MASK 0x00000f00 |
| 74 | +#define SSB_EROM_ASD_SP_SHIFT 8 |
| 75 | +#define SSB_EROM_ASD_ST_MASK 0x000000c0 |
| 76 | +#define SSB_EROM_ASD_ST_SLAVE 0x00000000 |
| 77 | +#define SSB_EROM_ASD_ST_BRIDGE 0x00000040 |
| 78 | +#define SSB_EROM_ASD_ST_MWRAP 0x000000c0 |
| 79 | +#define SSB_EROM_ASD_ST_SWRAP 0x00000080 |
| 80 | +#define SSB_EROM_ASD_ADDR_MASK 0xfffff000 |
| 81 | +#define SSB_EROM_ASD_AG32 0x00000008 |
| 82 | +#define SSB_EROM_ASD_SZ_MASK 0x00000030 |
| 83 | +#define SSB_EROM_ASD_SZ_SZD 0x00000030 |
| 84 | +#define SSB_EROM_ASD_SZ_SHIFT 4 |
| 85 | +#define SSB_EROM_CI 0 |
| 86 | +#define SSB_EROM_CIA_CID_MASK 0x000fff00 |
| 87 | +#define SSB_EROM_CIA_CID_SHIFT 8 |
| 88 | +#define SSB_EROM_CIA_MFG_MASK 0xfff00000 |
| 89 | +#define SSB_EROM_CIA_MFG_SHIFT 20 |
| 90 | +#define SSB_EROM_CIB_REV_MASK 0xff000000 |
| 91 | +#define SSB_EROM_CIB_REV_SHIFT 24 |
| 92 | +#define SSB_EROM_CIB_NMW_MASK 0x0007c000 |
| 93 | +#define SSB_EROM_CIB_NSW_MASK 0x00f80000 |
| 94 | +#define SSB_EROM_CIB_NSP_MASK 0x00003e00 |
| 95 | + |
| 96 | +/***** Registers of AI config space *****/ |
| 97 | +#define SSB_AI_RESETCTRL 0x800 /* maybe 0x804 for big endian */ |
| 98 | +#define SSB_AI_RESETCTRL_RESET 1 |
| 99 | +#define SSB_AI_IOCTRL 0x408 /* maybe 0x40c for big endian */ |
| 100 | +#define SSB_CF_FGC 0x0002 |
| 101 | +#define SSB_CF_CLOCK_EN 0x001 |
| 102 | +#define SSB_AI_oobselouta30 0x100 |
| 103 | |
| 104 | #endif /* LINUX_SSB_REGS_H_ */ |
| 105 | |
