Root/target/linux/cns21xx/patches-2.6.36/100-cns21xx-core.patch

1--- a/arch/arm/Kconfig
2+++ b/arch/arm/Kconfig
3@@ -179,6 +179,11 @@ config ARM_L1_CACHE_SHIFT_6
4     help
5       Setting ARM L1 cache line size to 64 Bytes.
6 
7+config ARM_L1_CACHE_SHIFT_4
8+ bool
9+ help
10+ Setting ARM L1 cache line size to 16 bytes.
11+
12 config VECTORS_BASE
13     hex
14     default 0xffff0000 if MMU || CPU_HIGH_VECTOR
15@@ -286,6 +291,15 @@ config ARCH_BCMRING
16     help
17       Support for Broadcom's BCMRing platform.
18 
19+config ARCH_CNS21XX
20+ bool "Cavium Networks CNS21xx family"
21+ select CPU_FA526
22+ select PLAT_FA
23+ select PLAT_FA_TIME
24+ select ARM_L1_CACHE_SHIFT_4
25+ help
26+ Support for Cavium Networks CNS21xx family.
27+
28 config ARCH_CLPS711X
29     bool "Cirrus Logic CLPS711x/EP721x-based"
30     select CPU_ARM720T
31@@ -845,6 +859,8 @@ source "arch/arm/mach-davinci/Kconfig"
32 
33 source "arch/arm/mach-dove/Kconfig"
34 
35+source "arch/arm/mach-cns21xx/Kconfig"
36+
37 source "arch/arm/mach-ep93xx/Kconfig"
38 
39 source "arch/arm/mach-footbridge/Kconfig"
40--- /dev/null
41+++ b/arch/arm/mach-cns21xx/Kconfig
42@@ -0,0 +1,6 @@
43+if ARCH_CNS21XX
44+
45+menu "Cavium Networks CNS21xx based machines"
46+endmenu
47+
48+endif
49--- /dev/null
50+++ b/arch/arm/mach-cns21xx/Makefile
51@@ -0,0 +1,10 @@
52+#
53+# Makefile for the linux kernel.
54+#
55+
56+# Object file lists.
57+
58+obj-y := core.o irq.o mm.o time.o
59+
60+# machine specific files
61+
62--- /dev/null
63+++ b/arch/arm/mach-cns21xx/Makefile.boot
64@@ -0,0 +1,3 @@
65+ zreladdr-y := 0x00008000
66+params_phys-y := 0x00000100
67+initrd_phys-y := 0x00C00000
68--- a/arch/arm/Makefile
69+++ b/arch/arm/Makefile
70@@ -129,6 +129,7 @@ endif
71 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
72 machine-$(CONFIG_ARCH_AT91) := at91
73 machine-$(CONFIG_ARCH_BCMRING) := bcmring
74+machine-$(CONFIG_ARCH_CNS21XX) := cns21xx
75 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
76 machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
77 machine-$(CONFIG_ARCH_DAVINCI) := davinci
78--- /dev/null
79+++ b/arch/arm/mach-cns21xx/common.h
80@@ -0,0 +1,18 @@
81+/*
82+ * Copyright (c) 2008 Cavium Networks
83+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
84+ *
85+ * This file is free software; you can redistribute it and/or modify
86+ * it under the terms of the GNU General Public License, Version 2, as
87+ * published by the Free Software Foundation.
88+ */
89+
90+#ifndef _MACH_CNS21XX_COMMON_H
91+#define _MACH_CNS21XX_COMMON_H
92+
93+void __init cns21xx_map_io(void);
94+void __init cns21xx_init_irq(void);
95+
96+extern struct sys_timer cns21xx_timer;
97+
98+#endif /* _MACH_CNS21XX_COMMON_H */
99--- /dev/null
100+++ b/arch/arm/mach-cns21xx/mm.c
101@@ -0,0 +1,170 @@
102+/*
103+ * Copyright (c) 2008 Cavium Networks
104+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
105+ *
106+ * This file is free software; you can redistribute it and/or modify
107+ * it under the terms of the GNU General Public License, Version 2, as
108+ * published by the Free Software Foundation.
109+ */
110+
111+#include <linux/mm.h>
112+#include <linux/init.h>
113+
114+#include <asm/mach/map.h>
115+
116+#include <mach/hardware.h>
117+#include <mach/cns21xx.h>
118+
119+#include "common.h"
120+
121+/*
122+ * Standard IO mapping
123+ */
124+static struct map_desc cns21xx_io_desc[] __initdata = {
125+ {
126+ .virtual = CNS21XX_FLASH_BANK0_BASE_VIRT,
127+ .pfn = __phys_to_pfn(CNS21XX_FLASH_BANK0_BASE),
128+ .length = SZ_256M,
129+ .type = MT_DEVICE
130+ }, {
131+ .virtual = CNS21XX_IDE_DEVICE_BASE_VIRT,
132+ .pfn = __phys_to_pfn(CNS21XX_IDE_DEVICE_BASE),
133+ .length = SZ_4K,
134+ .type = MT_DEVICE
135+ }, {
136+ .virtual = CNS21XX_GDMAC_BASE_VIRT,
137+ .pfn = __phys_to_pfn(CNS21XX_GDMAC_BASE),
138+ .length = SZ_4K,
139+ .type = MT_DEVICE
140+ }, {
141+ .virtual = CNS21XX_NIC_BASE_VIRT,
142+ .pfn = __phys_to_pfn(CNS21XX_NIC_BASE),
143+ .length = SZ_4K,
144+ .type = MT_DEVICE
145+ }, {
146+ .virtual = CNS21XX_SPI_BASE_VIRT,
147+ .pfn = __phys_to_pfn(CNS21XX_SPI_BASE),
148+ .length = SZ_4K,
149+ .type = MT_DEVICE
150+ }, {
151+ .virtual = CNS21XX_PCM_BASE_VIRT,
152+ .pfn = __phys_to_pfn(CNS21XX_PCM_BASE),
153+ .length = SZ_4K,
154+ .type = MT_DEVICE
155+ }, {
156+ .virtual = CNS21XX_I2C_BASE_VIRT,
157+ .pfn = __phys_to_pfn(CNS21XX_I2C_BASE),
158+ .length = SZ_4K,
159+ .type = MT_DEVICE
160+ }, {
161+ .virtual = CNS21XX_I2S_BASE_VIRT,
162+ .pfn = __phys_to_pfn(CNS21XX_I2S_BASE),
163+ .length = SZ_4K,
164+ .type = MT_DEVICE
165+ }, {
166+ .virtual = CNS21XX_DDRC_BASE_VIRT,
167+ .pfn = __phys_to_pfn(CNS21XX_DDRC_BASE),
168+ .length = SZ_4K,
169+ .type = MT_DEVICE
170+ }, {
171+ .virtual = CNS21XX_SMC_BASE_VIRT,
172+ .pfn = __phys_to_pfn(CNS21XX_SMC_BASE),
173+ .length = SZ_4K,
174+ .type = MT_DEVICE
175+ }, {
176+ .virtual = CNS21XX_IDE_CTRL_BASE_VIRT,
177+ .pfn = __phys_to_pfn(CNS21XX_IDE_CTRL_BASE),
178+ .length = SZ_4K,
179+ .type = MT_DEVICE
180+ }, {
181+ .virtual = CNS21XX_MISC_BASE_VIRT,
182+ .pfn = __phys_to_pfn(CNS21XX_MISC_BASE),
183+ .length = SZ_4K,
184+ .type = MT_DEVICE
185+ }, {
186+ .virtual = CNS21XX_CPM_BASE_VIRT,
187+ .pfn = __phys_to_pfn(CNS21XX_CPM_BASE),
188+ .length = SZ_4K,
189+ .type = MT_DEVICE
190+ }, {
191+ .virtual = CNS21XX_UART0_BASE_VIRT,
192+ .pfn = __phys_to_pfn(CNS21XX_UART0_BASE),
193+ .length = SZ_4K,
194+ .type = MT_DEVICE
195+ }, {
196+ .virtual = CNS21XX_UART1_BASE_VIRT,
197+ .pfn = __phys_to_pfn(CNS21XX_UART1_BASE),
198+ .length = SZ_4K,
199+ .type = MT_DEVICE
200+ }, {
201+ .virtual = CNS21XX_TIMER_BASE_VIRT,
202+ .pfn = __phys_to_pfn(CNS21XX_TIMER_BASE),
203+ .length = SZ_4K,
204+ .type = MT_DEVICE
205+ }, {
206+ .virtual = CNS21XX_WDT_BASE_VIRT,
207+ .pfn = __phys_to_pfn(CNS21XX_WDT_BASE),
208+ .length = SZ_4K,
209+ .type = MT_DEVICE
210+ }, {
211+ .virtual = CNS21XX_RTC_BASE_VIRT,
212+ .pfn = __phys_to_pfn(CNS21XX_RTC_BASE),
213+ .length = SZ_4K,
214+ .type = MT_DEVICE
215+ }, {
216+ .virtual = CNS21XX_GPIOA_BASE_VIRT,
217+ .pfn = __phys_to_pfn(CNS21XX_GPIOA_BASE),
218+ .length = SZ_4K,
219+ .type = MT_DEVICE
220+ }, {
221+ .virtual = CNS21XX_GPIOB_BASE_VIRT,
222+ .pfn = __phys_to_pfn(CNS21XX_GPIOB_BASE),
223+ .length = SZ_4K,
224+ .type = MT_DEVICE
225+ }, {
226+ .virtual = CNS21XX_PCI_CFGDATA_BASE_VIRT,
227+ .pfn = __phys_to_pfn(CNS21XX_PCI_CFGDATA_BASE),
228+ .length = SZ_4K,
229+ .type = MT_DEVICE
230+ }, {
231+ .virtual = CNS21XX_PCI_CFGADDR_BASE_VIRT,
232+ .pfn = __phys_to_pfn(CNS21XX_PCI_CFGADDR_BASE),
233+ .length = SZ_4K,
234+ .type = MT_DEVICE
235+ }, {
236+ .virtual = CNS21XX_OHCI_CONFIG_BASE_VIRT,
237+ .pfn = __phys_to_pfn(CNS21XX_OHCI_CONFIG_BASE),
238+ .length = SZ_4K,
239+ .type = MT_DEVICE
240+ }, {
241+ .virtual = CNS21XX_OHCI_CTRL_BASE_VIRT,
242+ .pfn = __phys_to_pfn(CNS21XX_OHCI_CTRL_BASE),
243+ .length = SZ_4K,
244+ .type = MT_DEVICE
245+ }, {
246+ .virtual = CNS21XX_EHCI_CONFIG_BASE_VIRT,
247+ .pfn = __phys_to_pfn(CNS21XX_EHCI_CONFIG_BASE),
248+ .length = SZ_4K,
249+ .type = MT_DEVICE
250+ }, {
251+ .virtual = CNS21XX_EHCI_CTRL_BASE_VIRT,
252+ .pfn = __phys_to_pfn(CNS21XX_EHCI_CTRL_BASE),
253+ .length = SZ_4K,
254+ .type = MT_DEVICE
255+ }, {
256+ .virtual = CNS21XX_USB_DEVICE_BASE_VIRT,
257+ .pfn = __phys_to_pfn(CNS21XX_USB_DEVICE_BASE),
258+ .length = SZ_4K,
259+ .type = MT_DEVICE
260+ }, {
261+ .virtual = CNS21XX_INTC_BASE_VIRT,
262+ .pfn = __phys_to_pfn(CNS21XX_INTC_BASE),
263+ .length = SZ_4K,
264+ .type = MT_DEVICE
265+ }
266+};
267+
268+void __init cns21xx_map_io(void)
269+{
270+ iotable_init(cns21xx_io_desc, ARRAY_SIZE(cns21xx_io_desc));
271+}
272--- /dev/null
273+++ b/arch/arm/mach-cns21xx/include/mach/hardware.h
274@@ -0,0 +1,23 @@
275+/*
276+ * Copyright (c) 2008 Cavium Networks
277+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
278+ *
279+ * This file is free software; you can redistribute it and/or modify
280+ * it under the terms of the GNU General Public License, Version 2, as
281+ * published by the Free Software Foundation.
282+ */
283+
284+#ifndef _CNS21XX_HARDWARE_H
285+#define _CNS21XX_HARDWARE_H
286+
287+#define PCIBIOS_MIN_IO 0x00000000
288+#define PCIBIOS_MIN_MEM 0x00000000
289+
290+#ifndef __ASSEMBLY__
291+extern unsigned long cns21xx_get_pll_freq(void);
292+extern unsigned long cns21xx_get_cpu_freq(void);
293+extern unsigned long cns21xx_get_ahb_freq(void);
294+extern unsigned long cns21xx_get_apb_freq(void);
295+#endif
296+
297+#endif /* _CNS21XX_HARDWARE_H */
298--- /dev/null
299+++ b/arch/arm/mach-cns21xx/include/mach/vmalloc.h
300@@ -0,0 +1,15 @@
301+/*
302+ * Copyright (c) 2008 Cavium Networks
303+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
304+ *
305+ * This file is free software; you can redistribute it and/or modify
306+ * it under the terms of the GNU General Public License, Version 2, as
307+ * published by the Free Software Foundation.
308+ */
309+
310+#ifndef _CNS21XX_VMALLOC_H
311+#define _CNS21XX_VMALLOC_H
312+
313+#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
314+
315+#endif /* _CNS21XX_VMALLOC_H */
316--- /dev/null
317+++ b/arch/arm/mach-cns21xx/include/mach/debug-macro.S
318@@ -0,0 +1,27 @@
319+/*
320+ * Copyright (c) 2008 Cavium Networks
321+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
322+ *
323+ * This file is free software; you can redistribute it and/or modify
324+ * it under the terms of the GNU General Public License, Version 2, as
325+ * published by the Free Software Foundation.
326+ */
327+
328+#include <mach/cns21xx.h>
329+
330+/* TODO: make it configurable */
331+#define CNS21XX_DEBUG_UART_BASE CNS21XX_UART0_BASE
332+#define CNS21XX_DEBUG_UART_BASE_VIRT CNS21XX_UART0_BASE_VIRT
333+
334+ .macro addruart, rx, tmp
335+ mrc p15, 0, \rx, c1, c0
336+ tst \rx, #1 @ MMU enabled ?
337+ moveq \rx, #(CNS21XX_DEBUG_UART_BASE) @ physical
338+ movne \rx, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0xff000000) @ virtual
339+ orrne \rx, \rx, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x00ff0000)
340+ orrne \rx, \rx, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x0000ff00)
341+ orrne \rx, \rx, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x000000ff)
342+ .endm
343+
344+#define UART_SHIFT 2
345+#include <asm/hardware/debug-8250.S>
346--- /dev/null
347+++ b/arch/arm/mach-cns21xx/include/mach/entry-macro.S
348@@ -0,0 +1,39 @@
349+/*
350+ * Copyright (c) 2008 Cavium Networks
351+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
352+ *
353+ * This file is free software; you can redistribute it and/or modify
354+ * it under the terms of the GNU General Public License, Version 2, as
355+ * published by the Free Software Foundation.
356+ */
357+
358+#include <mach/cns21xx.h>
359+#include <mach/irqs.h>
360+
361+#define INTC_IRQ_STATUS 0x1c
362+
363+ .macro disable_fiq
364+ .endm
365+
366+ .macro get_irqnr_preamble, base, tmp
367+ .endm
368+
369+ .macro arch_ret_to_user, tmp1, tmp2
370+ .endm
371+
372+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
373+ ldr \base, =(CNS21XX_INTC_BASE_VIRT + INTC_IRQ_STATUS)
374+ ldr \irqstat, [\base]
375+ mov \irqnr, #0
376+9001:
377+ tst \irqstat, #1
378+ bne 9002f
379+ add \irqnr, \irqnr, #1
380+ mov \irqstat, \irqstat, lsr #1
381+ cmp \irqnr, #CNS21XX_NR_INTC_IRQS
382+ bcc 9001b
383+9002:
384+ .endm
385+
386+ .macro irq_prio_table
387+ .endm
388--- /dev/null
389+++ b/arch/arm/mach-cns21xx/include/mach/io.h
390@@ -0,0 +1,18 @@
391+/*
392+ * Copyright (c) 2008 Cavium Networks
393+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
394+ *
395+ * This file is free software; you can redistribute it and/or modify
396+ * it under the terms of the GNU General Public License, Version 2, as
397+ * published by the Free Software Foundation.
398+ */
399+
400+#ifndef _CNS21XX_IO_H
401+#define _CNS21XX_IO_H
402+
403+#define IO_SPACE_LIMIT 0xffffffff
404+
405+#define __io(p) __typesafe_io(p)
406+#define __mem_pci(a) (a)
407+
408+#endif /* _CNS21XX_IO_H */
409--- /dev/null
410+++ b/arch/arm/mach-cns21xx/include/mach/irqs.h
411@@ -0,0 +1,53 @@
412+/*
413+ * Copyright (c) 2008 Cavium Networks
414+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
415+ *
416+ * This file is free software; you can redistribute it and/or modify
417+ * it under the terms of the GNU General Public License, Version 2, as
418+ * published by the Free Software Foundation.
419+ */
420+
421+#ifndef _CNS21XX_IRQS_H
422+#define _CNS21XX_IRQS_H
423+
424+#define CNS21XX_IRQ_TIMER1 0
425+#define CNS21XX_IRQ_TIMER2 1
426+#define CNS21XX_IRQ_CPM 2
427+#define CNS21XX_IRQ_WDT 3
428+#define CNS21XX_IRQ_GPIO 4
429+#define CNS21XX_IRQ_PCI_INTA 5
430+#define CNS21XX_IRQ_PCI_INTB 6
431+#define CNS21XX_IRQ_PCI_BROKEN 7
432+#define CNS21XX_IRQ_AHB2PCI 8
433+#define CNS21XX_IRQ_UART0 9
434+#define CNS21XX_IRQ_UART1 10
435+#define CNS21XX_IRQ_GDMAC_TC 11
436+#define CNS21XX_IRQ_GDMAC_ERR 12
437+#define CNS21XX_IRQ_PCMCIA 13
438+#define CNS21XX_IRQ_RTC 14
439+#define CNS21XX_IRQ_PCM 15
440+#define CNS21XX_IRQ_USB_DEVICE 16
441+#define CNS21XX_IRQ_IDE 17
442+#define CNS21XX_IRQ_NIC_STATUS 18
443+#define CNS21XX_IRQ_NIC_TXTC 19
444+#define CNS21XX_IRQ_NIC_RXRC 20
445+#define CNS21XX_IRQ_NIC_TXQE 21
446+#define CNS21XX_IRQ_NIC_RXQF 22
447+#define CNS21XX_IRQ_OHCI 23
448+#define CNS21XX_IRQ_EHCI 24
449+#define CNS21XX_IRQ_I2S 25
450+#define CNS21XX_IRQ_SPI 26
451+#define CNS21XX_IRQ_I2C 27
452+#define CNS21XX_IRQ_USB_VBUS 28
453+#define CNS21XX_IRQ_EXT_29 29
454+#define CNS21XX_IRQ_EXT_30 30
455+#define CNS21XX_IRQ_HSDMAC 31
456+
457+#define CNS21XX_GPIO_IRQ_BASE 32
458+
459+#define CNS21XX_NR_INTC_IRQS 32
460+#define CNS21XX_NR_GPIO_IRQS 64
461+
462+#define NR_IRQS 96
463+
464+#endif /* _CNS21XX_IRQS_H */
465--- /dev/null
466+++ b/arch/arm/mach-cns21xx/include/mach/timex.h
467@@ -0,0 +1,15 @@
468+/*
469+ * Copyright (c) 2008 Cavium Networks
470+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
471+ *
472+ * This file is free software; you can redistribute it and/or modify
473+ * it under the terms of the GNU General Public License, Version 2, as
474+ * published by the Free Software Foundation.
475+ */
476+
477+#ifndef _CNS21XX_TIMEX_H
478+#define _CNS21XX_TIMEX_H
479+
480+#define CLOCK_TICK_RATE 43750000
481+
482+#endif /* _CNS21XX_TIMEX_H */
483--- /dev/null
484+++ b/arch/arm/mach-cns21xx/include/mach/uncompress.h
485@@ -0,0 +1,40 @@
486+/*
487+ * Copyright (c) 2008 Cavium Networks
488+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
489+ *
490+ * This file is free software; you can redistribute it and/or modify
491+ * it under the terms of the GNU General Public License, Version 2, as
492+ * published by the Free Software Foundation.
493+ */
494+
495+#ifndef _CNS21XX_UNCOMPRESS_H
496+#define _CNS21XX_UNCOMPRESS_H
497+
498+#define UART_BASE 0x78000000
499+
500+#define UART_REG(offs) (*((volatile unsigned int *)(UART_BASE + offs)))
501+
502+#define UART_THR UART_REG(0x00)
503+#define UART_LSR UART_REG(0x14)
504+#define THR_EMPTY (1 << 5)
505+
506+#define UART_THR_EMPTY() (((UART_LSR) & THR_EMPTY) == (THR_EMPTY))
507+
508+static void putc(int c)
509+{
510+ if (c != 0) {
511+ while (!UART_THR_EMPTY())
512+ barrier();
513+
514+ UART_THR = (int)(c & 0xFF);
515+ }
516+}
517+
518+static inline void flush(void)
519+{
520+}
521+
522+#define arch_decomp_setup()
523+#define arch_decomp_wdog()
524+
525+#endif /* _CNS21XX_UNCOMPRESS_H */
526--- /dev/null
527+++ b/arch/arm/mach-cns21xx/include/mach/memory.h
528@@ -0,0 +1,15 @@
529+/*
530+ * Copyright (c) 2008 Cavium Networks
531+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
532+ *
533+ * This file is free software; you can redistribute it and/or modify
534+ * it under the terms of the GNU General Public License, Version 2, as
535+ * published by the Free Software Foundation.
536+ */
537+
538+#ifndef _CNS21XX_MEMORY_H
539+#define _CNS21XX_MEMORY_H
540+
541+#define PHYS_OFFSET UL(0x00000000)
542+
543+#endif /* _CNS21XX_MEMORY_H */
544--- /dev/null
545+++ b/arch/arm/mach-cns21xx/include/mach/system.h
546@@ -0,0 +1,38 @@
547+/*
548+ * Copyright (c) 2008 Cavium Networks
549+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
550+ *
551+ * This file is free software; you can redistribute it and/or modify
552+ * it under the terms of the GNU General Public License, Version 2, as
553+ * published by the Free Software Foundation.
554+ */
555+
556+#ifndef _CNS21XX_SYSTEM_H
557+#define _CNS21XX_SYSTEM_H
558+
559+#include <mach/cns21xx.h>
560+#include <mach/cns21xx_powermgmt.h>
561+
562+static inline void arch_idle(void)
563+{
564+ /*
565+ * Because of broken hardware we have to enable interrupts or the CPU
566+ * will never wakeup... Acctualy it is not very good to enable
567+ * interrupts here since scheduler can miss a tick, but there is
568+ * no other way around this. Platforms that needs it for power saving
569+ * should call enable_hlt() in init code, since by default it is
570+ * disabled.
571+ */
572+ local_irq_enable();
573+ cpu_do_idle();
574+}
575+
576+static inline void arch_reset(char mode, const char *cmd)
577+{
578+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |=
579+ (1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
580+ PWRMGT_SOFTWARE_RESET_CONTROL_REG &=
581+ ~(1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
582+}
583+
584+#endif /* _CNS21XX_SYSTEM_H */
585--- /dev/null
586+++ b/arch/arm/mach-cns21xx/irq.c
587@@ -0,0 +1,174 @@
588+/*
589+ * Copyright (c) 2008 Cavium Networks
590+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
591+ *
592+ * This file is free software; you can redistribute it and/or modify
593+ * it under the terms of the GNU General Public License, Version 2, as
594+ * published by the Free Software Foundation.
595+ */
596+
597+#include <linux/init.h>
598+#include <linux/interrupt.h>
599+#include <linux/irq.h>
600+#include <linux/io.h>
601+#include <linux/ioport.h>
602+
603+#include <mach/cns21xx.h>
604+
605+#define INTC_INTERRUPT_RAW_STATUS_REG 0x000
606+#define INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG 0x004
607+#define INTC_INTERRUPT_MASK_REG 0x008
608+#define INTC_INTERRUPT_MASK_CLEAR_REG 0x00c
609+#define INTC_INTERRUPT_TRIGGER_MODE_REG 0x010
610+#define INTC_INTERRUPT_TRIGGER_LEVEL_REG 0x014
611+#define INTC_FIQ_SELECT_REG 0x018
612+#define INTC_IRQ_STATUS_REG 0x01c
613+#define INTC_FIQ_STATUS_REG 0x020
614+#define INTC_SOFTWARE_INTERRUPT_REG 0x024
615+#define INTC_SOFTWARE_INTERRUPT_CLEAR_REG 0x028
616+#define INTC_SOFTWARE_PRIORITY_MASK_REG 0x02c
617+#define INTC_POWER_MANAGEMENT_INTERRUPT_REG 0x034
618+
619+#define INTC_VECTOR_ADDRESS_REG(_x) ((_x) + 0x040)
620+#define INTC_PRIORITY_REG(_x) ((_x) + 0x0c0)
621+#define INTC_IRQ_VECTOR_ADDRESS_REG 0x140
622+#define INTC_VECTOR_INTERRUPT_ENABLE_REG 0x144
623+
624+#define INTC_SIZE 0x148
625+
626+static unsigned int cns21xx_irq_types[CNS21XX_NR_INTC_IRQS] = {
627+ [CNS21XX_IRQ_TIMER1] = IRQ_TYPE_EDGE_RISING,
628+ [CNS21XX_IRQ_TIMER2] = IRQ_TYPE_EDGE_RISING,
629+ [CNS21XX_IRQ_CPM] = IRQ_TYPE_EDGE_FALLING,
630+ [CNS21XX_IRQ_WDT] = IRQ_TYPE_EDGE_RISING,
631+ [CNS21XX_IRQ_GPIO] = IRQ_TYPE_NONE,
632+ [CNS21XX_IRQ_PCI_INTA] = IRQ_TYPE_LEVEL_LOW,
633+ [CNS21XX_IRQ_PCI_INTB] = IRQ_TYPE_LEVEL_LOW,
634+ [CNS21XX_IRQ_PCI_BROKEN] = IRQ_TYPE_LEVEL_HIGH,
635+ [CNS21XX_IRQ_AHB2PCI] = IRQ_TYPE_LEVEL_HIGH,
636+ [CNS21XX_IRQ_UART0] = IRQ_TYPE_LEVEL_HIGH,
637+ [CNS21XX_IRQ_UART1] = IRQ_TYPE_LEVEL_HIGH,
638+ [CNS21XX_IRQ_GDMAC_TC] = IRQ_TYPE_LEVEL_HIGH,
639+ [CNS21XX_IRQ_GDMAC_ERR] = IRQ_TYPE_LEVEL_HIGH,
640+ [CNS21XX_IRQ_PCMCIA] = IRQ_TYPE_NONE,
641+ [CNS21XX_IRQ_RTC] = IRQ_TYPE_LEVEL_HIGH,
642+ [CNS21XX_IRQ_PCM] = IRQ_TYPE_LEVEL_LOW,
643+ [CNS21XX_IRQ_USB_DEVICE] = IRQ_TYPE_LEVEL_LOW,
644+ [CNS21XX_IRQ_IDE] = IRQ_TYPE_LEVEL_HIGH,
645+ [CNS21XX_IRQ_NIC_STATUS] = IRQ_TYPE_LEVEL_HIGH,
646+ [CNS21XX_IRQ_NIC_TXTC] = IRQ_TYPE_EDGE_RISING,
647+ [CNS21XX_IRQ_NIC_RXRC] = IRQ_TYPE_EDGE_RISING,
648+ [CNS21XX_IRQ_NIC_TXQE] = IRQ_TYPE_EDGE_RISING,
649+ [CNS21XX_IRQ_NIC_RXQF] = IRQ_TYPE_EDGE_RISING,
650+ [CNS21XX_IRQ_OHCI] = IRQ_TYPE_LEVEL_LOW,
651+ [CNS21XX_IRQ_EHCI] = IRQ_TYPE_LEVEL_LOW,
652+ [CNS21XX_IRQ_I2S] = IRQ_TYPE_LEVEL_LOW,
653+ [CNS21XX_IRQ_SPI] = IRQ_TYPE_LEVEL_LOW,
654+ [CNS21XX_IRQ_I2C] = IRQ_TYPE_LEVEL_LOW,
655+ [CNS21XX_IRQ_USB_VBUS] = IRQ_TYPE_EDGE_RISING,
656+ [CNS21XX_IRQ_EXT_29] = IRQ_TYPE_NONE,
657+ [CNS21XX_IRQ_EXT_30] = IRQ_TYPE_NONE,
658+ [CNS21XX_IRQ_HSDMAC] = IRQ_TYPE_EDGE_RISING,
659+};
660+
661+static void __iomem *cns21xx_intc_base;
662+
663+static inline void cns21xx_intc_writel(u32 val, unsigned int reg)
664+{
665+ __raw_writel(val, cns21xx_intc_base + reg);
666+}
667+
668+static inline u32 cns21xx_intc_readl(unsigned int reg)
669+{
670+ return __raw_readl(cns21xx_intc_base + reg);
671+}
672+
673+static void cns21xx_irq_ack(unsigned int irq)
674+{
675+ cns21xx_intc_writel(1 << irq, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
676+}
677+
678+static void cns21xx_irq_mask(unsigned int irq)
679+{
680+ cns21xx_intc_writel(1 << irq, INTC_INTERRUPT_MASK_REG);
681+}
682+
683+static void cns21xx_irq_unmask(unsigned int irq)
684+{
685+ cns21xx_intc_writel(1 << irq, INTC_INTERRUPT_MASK_CLEAR_REG);
686+}
687+
688+static struct irq_chip cns21xx_irq_chip = {
689+ .name = "INTC",
690+ .ack = cns21xx_irq_ack,
691+ .mask = cns21xx_irq_mask,
692+ .unmask = cns21xx_irq_unmask,
693+};
694+
695+static struct resource cns21xx_intc_resource = {
696+ .name = "INTC",
697+ .flags = IORESOURCE_MEM,
698+ .start = CNS21XX_INTC_BASE,
699+ .end = CNS21XX_INTC_BASE + INTC_SIZE - 1,
700+};
701+
702+void __init cns21xx_init_irq(void)
703+{
704+ unsigned int mode = 0;
705+ unsigned int level = 0;
706+ int i;
707+
708+ /*
709+ * Disable arch_idle() by default since it is buggy
710+ * For more info see arch/arm/mach-cns21xx/include/mach/system.h
711+ */
712+ disable_hlt();
713+
714+ request_resource(&iomem_resource, &cns21xx_intc_resource);
715+ cns21xx_intc_base = ioremap(cns21xx_intc_resource.start, INTC_SIZE);
716+
717+ cns21xx_intc_writel(0xffffffff, INTC_INTERRUPT_MASK_REG);
718+ cns21xx_intc_writel(0xffffffff, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
719+ cns21xx_intc_writel(0xffffffff, INTC_SOFTWARE_INTERRUPT_CLEAR_REG);
720+ cns21xx_intc_writel(0, INTC_SOFTWARE_PRIORITY_MASK_REG);
721+ cns21xx_intc_writel(0, INTC_FIQ_SELECT_REG);
722+ cns21xx_intc_writel(0, INTC_VECTOR_INTERRUPT_ENABLE_REG);
723+
724+ for (i = 0; i < ARRAY_SIZE(cns21xx_irq_types); i++) {
725+ irq_flow_handler_t handler;
726+
727+ switch (cns21xx_irq_types[i]) {
728+ case IRQ_TYPE_EDGE_RISING:
729+ handler = handle_edge_irq;
730+ mode |= (1 << i);
731+ break;
732+
733+ case IRQ_TYPE_EDGE_FALLING:
734+ handler = handle_edge_irq;
735+ mode |= (1 << i);
736+ level |= (1 << i);
737+ break;
738+
739+ case IRQ_TYPE_LEVEL_LOW:
740+ handler = handle_level_irq;
741+ level |= (1 << i);
742+ break;
743+
744+ case IRQ_TYPE_LEVEL_HIGH:
745+ case IRQ_TYPE_NONE:
746+ handler = handle_level_irq;
747+ break;
748+
749+ default:
750+ BUG();
751+ break;
752+ }
753+
754+ set_irq_chip(i, &cns21xx_irq_chip);
755+ set_irq_handler(i, handler);
756+ set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
757+ }
758+
759+ cns21xx_intc_writel(mode, INTC_INTERRUPT_TRIGGER_MODE_REG);
760+ cns21xx_intc_writel(level, INTC_INTERRUPT_TRIGGER_LEVEL_REG);
761+}
762--- /dev/null
763+++ b/arch/arm/mach-cns21xx/time.c
764@@ -0,0 +1,28 @@
765+/*
766+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
767+ *
768+ * This file is free software; you can redistribute it and/or modify
769+ * it under the terms of the GNU General Public License, Version 2, as
770+ * published by the Free Software Foundation.
771+ */
772+
773+#include <linux/init.h>
774+#include <linux/irq.h>
775+
776+#include <asm/mach/time.h>
777+
778+#include <plat/time.h>
779+#include <mach/hardware.h>
780+#include <mach/cns21xx.h>
781+
782+#include "common.h"
783+
784+static void __init cns21xx_timer_init(void)
785+{
786+ fa_timer_init(CNS21XX_TIMER_BASE, CNS21XX_IRQ_TIMER1, FA_TIMER1,
787+ cns21xx_get_apb_freq());
788+}
789+
790+struct sys_timer cns21xx_timer = {
791+ .init = cns21xx_timer_init,
792+};
793--- /dev/null
794+++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_powermgmt.h
795@@ -0,0 +1,591 @@
796+/*
797+ * Copyright (c) 2008 Cavium Networks
798+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
799+ *
800+ * This file is free software; you can redistribute it and/or modify
801+ * it under the terms of the GNU General Public License, Version 2, as
802+ * published by the Free Software Foundation.
803+ */
804+
805+#ifndef _CNS21XX_POWERMGMT_H
806+#define _CNS21XX_POWERMGMT_H
807+
808+#define PWRMGT_MEM_MAP_VALUE(reg_offset) \
809+ (*((u32 volatile *)(CNS21XX_CPM_BASE_VIRT + reg_offset)))
810+
811+/*
812+ * define access macros
813+ */
814+#define PWRMGT_CLOCK_GATE_CONTROL0_REG PWRMGT_MEM_MAP_VALUE(0x00)
815+#define PWRMGT_CLOCK_GATE_CONTROL1_REG PWRMGT_MEM_MAP_VALUE(0x04)
816+#define PWRMGT_SOFTWARE_RESET_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x08)
817+#define PWRMGT_SYSTEM_CLOCK_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x0C)
818+#define PWRMGT_PLL_POWER_DOWN_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x10)
819+#define PWRMGT_CPU_INITIALIZATION_REG PWRMGT_MEM_MAP_VALUE(0x14)
820+#define PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x1C)
821+#define PWRMGT_USB_DEVICE_POWERMGT_REG PWRMGT_MEM_MAP_VALUE(0x20)
822+#define PWRMGT_REGULATOR_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x24)
823+#define PWRMGT_RTC_XTAL_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x28)
824+#define PWRMGT_PLL250_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x2C)
825+
826+
827+/*
828+ * define constants macros
829+ */
830+#define PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX 0
831+#define PWRMGT_PCMCIA_SOFTWARE_RESET_BIT_INDEX 1
832+#define PWRMGT_IDE_SOFTWARE_RESET_BIT_INDEX 2
833+#define PWRMGT_VIC_SOFTWARE_RESET_BIT_INDEX 3
834+#define PWRMGT_DMA_SOFTWARE_RESET_BIT_INDEX 4
835+#define PWRMGT_NIC_SOFTWARE_RESET_BIT_INDEX 5
836+#define PWRMGT_USB_HOST_SOFTWARE_RESET_BIT_INDEX 6
837+#define PWRMGT_PCI_BRIDGE_SOFTWARE_RESET_BIT_INDEX 7
838+#define PWRMGT_P2S_SOFTWARE_RESET_BIT_INDEX 8
839+#define PWRMGT_UART0_SOFTWARE_RESET_BIT_INDEX 9
840+#define PWRMGT_UART1_SOFTWARE_RESET_BIT_INDEX 10
841+#define PWRMGT_TIMER_SOFTWARE_RESET_BIT_INDEX 11
842+#define PWRMGT_WDTIMER_SOFTWARE_RESET_BIT_INDEX 12
843+#define PWRMGT_GPIO_SOFTWARE_RESET_BIT_INDEX 13
844+#define PWRMGT_USB_DEVICE_SOFTWARE_RESET_BIT_INDEX 14
845+#define PWRMGT_FAST_ETHERNET_PHY_SOFTWARE_RESET_BIT_INDEX 15
846+#define PWRMGT_HSDMA_SOFTWARE_RESET_BIT_INDEX 16
847+
848+#define PWRMGT_PLL_FREQUENCY_175MHZ (0 << 0)
849+#define PWRMGT_PLL_FREQUENCY_200MHZ (1 << 0)
850+#define PWRMGT_PLL_FREQUENCY_225MHZ (2 << 0)
851+#define PWRMGT_PLL_FREQUENCY_250MHZ (3 << 0)
852+
853+#define PWRMGT_CPUCLK_DIVIDER_BY_1 (0 << 2)
854+#define PWRMGT_CPUCLK_DIVIDER_BY_2 (1 << 2)
855+#define PWRMGT_CPUCLK_DIVIDER_BY_3 (2 << 2)
856+#define PWRMGT_CPUCLK_DIVIDER_BY_4 (3 << 2)
857+
858+#define PWRMGT_HCLK_DIVIDER_BY_1 (0 << 4)
859+#define PWRMGT_HCLK_DIVIDER_BY_2 (1 << 4)
860+#define PWRMGT_HCLK_DIVIDER_BY_3 (2 << 4)
861+#define PWRMGT_HCLK_DIVIDER_BY_4 (3 << 4)
862+
863+#define PWRMGT_HCLK_SOURCE_FCLK (0 << 6)
864+#define PWRMGT_HCLK_SOURCE_125MHZ (1 << 6)
865+
866+#define PWRMGT_PCLK_DIVIDER_BY_1 (0 << 8)
867+#define PWRMGT_PCLK_DIVIDER_BY_2 (1 << 8)
868+#define PWRMGT_PCLK_DIVIDER_BY_3 (2 << 8)
869+#define PWRMGT_PCLK_DIVIDER_BY_4 (3 << 8)
870+
871+#define PWRMGT_PCICLK_DIVIDER_BY_1 (0 << 10)
872+#define PWRMGT_PCICLK_DIVIDER_BY_2 (1 << 10)
873+#define PWRMGT_PCICLK_DIVIDER_BY_3 (2 << 10)
874+#define PWRMGT_PCICLK_DIVIDER_BY_4 (3 << 10)
875+
876+
877+#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_1 1
878+#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_2 2
879+#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_3 3
880+#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_4 4
881+
882+#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_1 1
883+#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_2 2
884+#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_3 3
885+#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_4 4
886+
887+#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_1 1
888+#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_2 2
889+#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_3 3
890+#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_4 4
891+
892+/*
893+ * Macro defines for Clock Gate Control
894+ */
895+#define HAL_PWRMGT_DISABLE_DRAMC_CLOCK() \
896+{ \
897+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1); \
898+}
899+
900+
901+#define HAL_PWRMGT_ENABLE_NIC_CLOCK() \
902+{ \
903+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0); \
904+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x0F << 20); \
905+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 5); \
906+}
907+
908+#define HAL_PWRMGT_DISABLE_NIC_CLOCK() \
909+{ \
910+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x0F << 20); \
911+}
912+
913+
914+#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_33M_CLOCK() \
915+{ \
916+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
917+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
918+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 10); \
919+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
920+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
921+}
922+
923+#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_66M_CLOCK() \
924+{ \
925+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
926+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
927+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 10); \
928+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
929+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
930+}
931+
932+#define HAL_PWRMGT_DISABLE_PCI_CLOCK() \
933+{ \
934+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 28) | (0x1 << 30)); \
935+}
936+
937+
938+#define HAL_PWRMGT_ENABLE_USB_CLOCK() \
939+{ \
940+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0xF << 1); \
941+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 24); \
942+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 28); \
943+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 6) | (0x1 << 14); \
944+}
945+
946+#define HAL_PWRMGT_DISABLE_USB_CLOCK() \
947+{ \
948+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 24); \
949+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 28); \
950+}
951+
952+
953+#define HAL_PWRMGT_ENABLE_DMA_CLOCK() \
954+{ \
955+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 16); \
956+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 4); \
957+}
958+
959+#define HAL_PWRMGT_DISABLE_DMA_CLOCK() \
960+{ \
961+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 16); \
962+}
963+
964+
965+#define HAL_PWRMGT_ENABLE_IDE_CLOCK() \
966+{ \
967+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 8) | (0x1 << 9); \
968+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 2); \
969+}
970+
971+#define HAL_PWRMGT_DISABLE_IDE_CLOCK() \
972+{ \
973+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 8) | (0x1 << 9)); \
974+}
975+
976+
977+#define HAL_PWRMGT_ENABLE_UART0_CLOCK() \
978+{ \
979+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) | (0x1 << 2) | (0x1 << 5)); \
980+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 12); \
981+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 9); \
982+}
983+
984+#define HAL_PWRMGT_DISABLE_UART0_CLOCK() \
985+{ \
986+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 12); \
987+}
988+
989+
990+#define HAL_PWRMGT_ENABLE_UART1_CLOCK() \
991+{ \
992+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) | (0x1 << 2) | (0x1 << 5)); \
993+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 13); \
994+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 10); \
995+}
996+
997+#define HAL_PWRMGT_DISABLE_UART1_CLOCK() \
998+{ \
999+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 13); \
1000+}
1001+
1002+
1003+#define HAL_PWRMGT_ENABLE_PCMCIA_CLOCK() \
1004+{ \
1005+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
1006+}
1007+
1008+#define HAL_PWRMGT_DISABLE_PCMCIA_CLOCK() \
1009+{ \
1010+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
1011+}
1012+
1013+
1014+#define HAL_PWRMGT_ENABLE_GPIO_CLOCK() \
1015+{ \
1016+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 25); \
1017+}
1018+
1019+#define HAL_PWRMGT_DISABLE_GPIO_CLOCK() \
1020+{ \
1021+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 25); \
1022+}
1023+
1024+
1025+#define HAL_PWRMGT_ENABLE_WDTIMER_CLOCK() \
1026+{ \
1027+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 21) | (0x1 << 22); \
1028+}
1029+
1030+#define HAL_PWRMGT_DISABLE_WDTIMER_CLOCK() \
1031+{ \
1032+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 21) | (0x1 << 22)); \
1033+}
1034+
1035+
1036+#define HAL_PWRMGT_ENABLE_RTC_CLOCK() \
1037+{ \
1038+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 23); \
1039+}
1040+
1041+#define HAL_PWRMGT_DISABLE_RTC_CLOCK() \
1042+{ \
1043+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 23); \
1044+}
1045+
1046+
1047+#define HAL_PWRMGT_ENABLE_TIMER_CLOCK() \
1048+{ \
1049+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 17) | (0x1 << 18) | (0x1 << 19); \
1050+}
1051+
1052+#define HAL_PWRMGT_DISABLE_TIMER_CLOCK() \
1053+{ \
1054+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 17) | (0x1 << 18) | (0x1 << 19)); \
1055+}
1056+
1057+
1058+#define HAL_PWRMGT_ENABLE_I2C_CLOCK() \
1059+{ \
1060+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1); \
1061+}
1062+
1063+#define HAL_PWRMGT_DISABLE_I2C_CLOCK() \
1064+{ \
1065+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 1); \
1066+}
1067+
1068+
1069+#define HAL_PWRMGT_ENABLE_I2S_CLOCK() \
1070+{ \
1071+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 5) | (0x1 << 6)); \
1072+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 10); \
1073+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1074+}
1075+
1076+#define HAL_PWRMGT_DISABLE_I2S_CLOCK() \
1077+{ \
1078+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 10)); \
1079+}
1080+
1081+
1082+#define HAL_PWRMGT_ENABLE_PCM_CLOCK() \
1083+{ \
1084+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5); \
1085+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 6); \
1086+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1087+}
1088+
1089+#define HAL_PWRMGT_DISABLE_PCM_CLOCK() \
1090+{ \
1091+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 6)); \
1092+}
1093+
1094+
1095+#define HAL_PWRMGT_ENABLE_SPI_CLOCK() \
1096+{ \
1097+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 0) | (0x1 << 1); \
1098+}
1099+
1100+#define HAL_PWRMGT_DISABLE_SPI_CLOCK() \
1101+{ \
1102+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 0) | (0x1 << 1)); \
1103+}
1104+
1105+
1106+#define HAL_PWRMGT_ENABLE_VIC_CLOCK() \
1107+{ \
1108+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 12); \
1109+}
1110+
1111+#define HAL_PWRMGT_DISABLE_VIC_CLOCK() \
1112+{ \
1113+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 12); \
1114+}
1115+
1116+
1117+#define HAL_PWRMGT_ENABLE_SMC_CLOCK() \
1118+{ \
1119+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
1120+}
1121+
1122+#define HAL_PWRMGT_DISABLE_SMC_CLOCK() \
1123+{ \
1124+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
1125+}
1126+
1127+
1128+#define HAL_PWRMGT_ENABLE_HSDMA_CLOCK() \
1129+{ \
1130+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 29); \
1131+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 16); \
1132+}
1133+
1134+#define HAL_PWRMGT_DISABLE_HSDMA_CLOCK() \
1135+{ \
1136+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 29); \
1137+}
1138+
1139+
1140+
1141+/*
1142+ * Macro defines for Reset Control
1143+ */
1144+#define HAL_PWRMGT_GLOBAL_SOFTWARE_RESET() \
1145+{ \
1146+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1); \
1147+ PWRMGT_SOFTWARE_RESET_CONTROL_REG &= ~(0x1); \
1148+}
1149+
1150+
1151+/*
1152+ * Macro defines for System Clock Control
1153+ */
1154+#define HAL_PWRMGT_SET_PLL_FREQUENCY_175MHZ() \
1155+{ \
1156+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1157+}
1158+
1159+
1160+#define HAL_PWRMGT_SET_PLL_FREQUENCY_200MHZ() \
1161+{ \
1162+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1163+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x1; \
1164+}
1165+
1166+
1167+#define HAL_PWRMGT_SET_PLL_FREQUENCY_225MHZ() \
1168+{ \
1169+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1170+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x2; \
1171+}
1172+
1173+
1174+#define HAL_PWRMGT_SET_PLL_FREQUENCY_250MHZ() \
1175+{ \
1176+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1177+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x3; \
1178+}
1179+
1180+
1181+#define HAL_PWRMGT_CONFIG_PLLCLK_TO_CPUCLK_RATIO(ratio) \
1182+{ \
1183+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 2); \
1184+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 2); \
1185+}
1186+
1187+
1188+#define HAL_PWRMGT_CONFIG_CPUCLK_TO_HCLK_RATIO(ratio) \
1189+{ \
1190+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 4); \
1191+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 4); \
1192+}
1193+
1194+
1195+#define HAL_PWRMGT_HCLK_SOURCE_FCLK() \
1196+{ \
1197+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 6); \
1198+}
1199+
1200+
1201+#define HAL_PWRMGT_HCLK_SOURCE_125MHZ() \
1202+{ \
1203+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 6); \
1204+}
1205+
1206+
1207+#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_HCLK() \
1208+{ \
1209+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 7); \
1210+}
1211+
1212+
1213+#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_62_5MHZ() \
1214+{ \
1215+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 7); \
1216+}
1217+
1218+
1219+#define HAL_PWRMGT_CONFIG_HCLK_TO_PCLK_RATIO(ratio) \
1220+{ \
1221+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 8); \
1222+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 8); \
1223+}
1224+
1225+
1226+#define HAL_PWRMGT_I2S_CLOCK_SOURCE_8192000HZ() \
1227+{ \
1228+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1229+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 12); \
1230+}
1231+
1232+
1233+#define HAL_PWRMGT_I2S_CLOCK_SOURCE_11289600HZ() \
1234+{ \
1235+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1236+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 12); \
1237+}
1238+
1239+
1240+#define HAL_PWRMGT_I2S_CLOCK_SOURCE_12288000HZ() \
1241+{ \
1242+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1243+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x2 << 12); \
1244+}
1245+
1246+
1247+#define HAL_PWRMGT_CONFIGURE_MDC_CLOCK_DIVIDER(divided_value) \
1248+{ \
1249+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 14); \
1250+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 14); \
1251+}
1252+
1253+
1254+#define HAL_PWRMGT_CONFIGURE_CLOCK_OUT_PIN(pin_source_select, divided_value) \
1255+{ \
1256+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3F << 16); \
1257+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((pin_source_select & 0xF) << 16); \
1258+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 20); \
1259+}
1260+
1261+
1262+/*
1263+ * Macro defines for PLL Power Down Control
1264+ */
1265+#define HAL_PWRMGT_POWER_DOWN_SYSTEM_XTAL_PAD() \
1266+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 7)
1267+
1268+#define HAL_PWRMGT_POWER_ON_SYSTEM_XTAL_PAD() \
1269+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 7)
1270+
1271+
1272+#define HAL_PWRMGT_POWER_DOWN_PLL_X5() \
1273+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 0)
1274+
1275+#define HAL_PWRMGT_POWER_ON_PLL_X5() \
1276+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0)
1277+
1278+
1279+#define HAL_PWRMGT_POWER_DOWN_PLL_X8() \
1280+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 1)
1281+
1282+#define HAL_PWRMGT_POWER_ON_PLL_X8() \
1283+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1)
1284+
1285+
1286+#define HAL_PWRMGT_POWER_DOWN_PLL_X3() \
1287+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 2)
1288+
1289+#define HAL_PWRMGT_POWER_ON_PLL_X3() \
1290+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 2)
1291+
1292+
1293+#define HAL_PWRMGT_POWER_DOWN_USBH_PHY_PLL() \
1294+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 3)
1295+
1296+#define HAL_PWRMGT_POWER_ON_USBH_PHY_PLL() \
1297+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 3)
1298+
1299+
1300+#define HAL_PWRMGT_POWER_DOWN_USBD_PHY_PLL() \
1301+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 4)
1302+
1303+#define HAL_PWRMGT_POWER_ON_USBD_PHY_PLL() \
1304+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 4)
1305+
1306+
1307+#define HAL_PWRMGT_POWER_DOWN_PLL_X2250() \
1308+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 5)
1309+
1310+#define HAL_PWRMGT_POWER_ON_PLL_X2250() \
1311+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5)
1312+
1313+
1314+#define HAL_PWRMGT_POWER_DOWN_PLL_X7() \
1315+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 6)
1316+
1317+#define HAL_PWRMGT_POWER_ON_PLL_X7() \
1318+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 6)
1319+
1320+
1321+#define HAL_PWRMGT_POWER_DOWN_ALL_PLL() \
1322+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG = 0x7F;
1323+
1324+#define HAL_PWRMGT_POWER_ON_ALL_PLL() \
1325+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG = 0;
1326+
1327+
1328+/*
1329+ * Macro defines for Pad Drive Strength Control
1330+ */
1331+#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCMCIA_CARDBUS_MODE() \
1332+{ \
1333+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1334+}
1335+
1336+#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCI_MODE() \
1337+{ \
1338+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1339+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 0); \
1340+}
1341+
1342+#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_MII_MODE() \
1343+{ \
1344+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 2); \
1345+}
1346+
1347+#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_RGMII_MODE() \
1348+{ \
1349+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 2); \
1350+}
1351+
1352+#define HAL_PWRMGT_ENABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1353+{ \
1354+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 3); \
1355+}
1356+
1357+#define HAL_PWRMGT_DISABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1358+{ \
1359+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 3); \
1360+}
1361+
1362+
1363+/*
1364+ * Macro defines for USB Device Power Management
1365+ */
1366+#define HAL_PWRMGT_REMOTE_WAKEUP_USB_HOST() \
1367+{ \
1368+ PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 4); \
1369+}
1370+
1371+#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_EXTERNAL_12MHZ() \
1372+{ \
1373+ PWRMGT_USB_DEVICE_POWERMGT_REG &= ~(0x1 << 5); \
1374+}
1375+
1376+#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_INTERNAL_12MHZ() \
1377+{ \
1378+ PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 5); \
1379+}
1380+
1381+
1382+/*
1383+ * Macro defines for Regulator Control
1384+ */
1385+
1386+#endif /* _CNS21XX_POWERMGMT_H */
1387--- /dev/null
1388+++ b/arch/arm/mach-cns21xx/include/mach/cns21xx.h
1389@@ -0,0 +1,88 @@
1390+/*
1391+ * Copyright (c) 2008 Cavium Networks
1392+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
1393+ *
1394+ * This file is free software; you can redistribute it and/or modify
1395+ * it under the terms of the GNU General Public License, Version 2, as
1396+ * published by the Free Software Foundation.
1397+ */
1398+
1399+#ifndef _CNS21XX_H
1400+#define _CNS21XX_H
1401+
1402+#define CNS21XX_FLASH_BANK0_BASE 0x10000000
1403+#define CNS21XX_FLASH_BANK1_BASE 0x11000000
1404+#define CNS21XX_FLASH_BANK2_BASE 0x12000000
1405+#define CNS21XX_FLASH_BANK3_BASE 0x13000000
1406+#define CNS21XX_PCMCIA_ATTR_BASE 0x14000000
1407+#define CNS21XX_PCMCIA_MEM_BASE 0x15000000
1408+#define CNS21XX_PCMCIA_IO_BASE 0x16000000
1409+#define CNS21XX_IDE_DEVICE_BASE 0x18000000
1410+#define CNS21XX_SDRAM_MEMORY_BASE 0x20000000
1411+#define CNS21XX_GDMAC_BASE 0x60000000
1412+#define CNS21XX_NIC_BASE 0x70000000
1413+#define CNS21XX_SPI_BASE 0x71000000
1414+#define CNS21XX_PCM_BASE 0x71000000
1415+#define CNS21XX_I2C_BASE 0x71000000
1416+#define CNS21XX_I2S_BASE 0x71000000
1417+#define CNS21XX_DDRC_BASE 0x72000000
1418+#define CNS21XX_SMC_BASE 0x73000000
1419+#define CNS21XX_PCMCIA_CTRL_BASE 0x73000000
1420+#define CNS21XX_IDE_CTRL_BASE 0x74000000
1421+#define CNS21XX_MISC_BASE 0x76000000
1422+#define CNS21XX_CPM_BASE 0x77000000
1423+#define CNS21XX_UART0_BASE 0x78000000
1424+#define CNS21XX_UART1_BASE 0x78800000
1425+#define CNS21XX_TIMER_BASE 0x79000000
1426+#define CNS21XX_WDT_BASE 0x7a000000
1427+#define CNS21XX_RTC_BASE 0x7b000000
1428+#define CNS21XX_GPIOA_BASE 0x7c000000
1429+#define CNS21XX_GPIOB_BASE 0x7c800000
1430+#define CNS21XX_PCI_CFGDATA_BASE 0xa0000000
1431+#define CNS21XX_PCI_CFGADDR_BASE 0xa4000000
1432+#define CNS21XX_PCI_IO_BASE 0xa8000000
1433+#define CNS21XX_PCI_MEMORY_BASE 0xb0000000
1434+#define CNS21XX_OHCI_CONFIG_BASE 0xc0000000
1435+#define CNS21XX_OHCI_CTRL_BASE 0xc4000000
1436+#define CNS21XX_EHCI_CONFIG_BASE 0xc8000000
1437+#define CNS21XX_EHCI_CTRL_BASE 0xcc000000
1438+#define CNS21XX_USB_DEVICE_BASE 0xd0000000
1439+#define CNS21XX_INTC_BASE 0xfffff000
1440+
1441+#define CNS21XX_FLASH_BANK0_BASE_VIRT 0xe0000000
1442+#define CNS21XX_FLASH_BANK1_BASE_VIRT 0xe2000000
1443+#define CNS21XX_FLASH_BANK2_BASE_VIRT 0xe4000000
1444+#define CNS21XX_FLASH_BANK3_BASE_VIRT 0xe8000000
1445+#define CNS21XX_IDE_DEVICE_BASE_VIRT 0xfff00000
1446+#define CNS21XX_GDMAC_BASE_VIRT 0xfff01000
1447+#define CNS21XX_NIC_BASE_VIRT 0xfff02000
1448+#define CNS21XX_SPI_BASE_VIRT 0xfff03000
1449+#define CNS21XX_PCM_BASE_VIRT 0xfff04000
1450+#define CNS21XX_I2C_BASE_VIRT 0xfff05000
1451+#define CNS21XX_I2S_BASE_VIRT 0xfff06000
1452+#define CNS21XX_DDRC_BASE_VIRT 0xfff07000
1453+#define CNS21XX_SMC_BASE_VIRT 0xfff08000
1454+#define CNS21XX_PCMCIA_CTRL_BASE_VIRT 0xfff09000
1455+#define CNS21XX_IDE_CTRL_BASE_VIRT 0xfff0A000
1456+#define CNS21XX_MISC_BASE_VIRT 0xfff0B000
1457+#define CNS21XX_CPM_BASE_VIRT 0xfff0C000
1458+#define CNS21XX_UART0_BASE_VIRT 0xfff0D000
1459+#define CNS21XX_UART1_BASE_VIRT 0xfff0E000
1460+#define CNS21XX_TIMER_BASE_VIRT 0xfff0F000
1461+#define CNS21XX_WDT_BASE_VIRT 0xfff10000
1462+#define CNS21XX_RTC_BASE_VIRT 0xfff11000
1463+#define CNS21XX_GPIOA_BASE_VIRT 0xfff12000
1464+#define CNS21XX_GPIOB_BASE_VIRT 0xfff13000
1465+#define CNS21XX_PCI_CFGDATA_BASE_VIRT 0xfff14000
1466+#define CNS21XX_PCI_CFGADDR_BASE_VIRT 0xfff15000
1467+#define CNS21XX_OHCI_CONFIG_BASE_VIRT 0xfff16000
1468+#define CNS21XX_OHCI_CTRL_BASE_VIRT 0xfff17000
1469+#define CNS21XX_EHCI_CONFIG_BASE_VIRT 0xfff18000
1470+#define CNS21XX_EHCI_CTRL_BASE_VIRT 0xfff19000
1471+#define CNS21XX_USB_DEVICE_BASE_VIRT 0xfff1a000
1472+#define CNS21XX_INTC_BASE_VIRT 0xfff1b000
1473+
1474+#define CNS21XX_PHYS_IO CNS21XX_UART0_BASE
1475+#define CNS21XX_IO_PAGE_OFFSET ((CNS21XX_UART0_BASE_VIRT) >> 18) & 0xfffc
1476+
1477+#endif /* _CNS21XX_H */
1478--- /dev/null
1479+++ b/arch/arm/mach-cns21xx/core.c
1480@@ -0,0 +1,77 @@
1481+/*
1482+ * Copyright (c) 2008 Cavium Networks
1483+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
1484+ *
1485+ * This file is free software; you can redistribute it and/or modify
1486+ * it under the terms of the GNU General Public License, Version 2, as
1487+ * published by the Free Software Foundation.
1488+ */
1489+
1490+#include <linux/kernel.h>
1491+
1492+#include <mach/hardware.h>
1493+#include <mach/cns21xx.h>
1494+#include <mach/cns21xx_powermgmt.h>
1495+
1496+static unsigned long cns21xx_pll_freq;
1497+static unsigned long cns21xx_cpu_freq;
1498+static unsigned long cns21xx_ahb_freq;
1499+static unsigned long cns21xx_apb_freq;
1500+
1501+static void cns21xx_init_freq(void)
1502+{
1503+ static int freq_init_done;
1504+ unsigned int t;
1505+
1506+ if (freq_init_done)
1507+ return;
1508+
1509+ t = PWRMGT_SYSTEM_CLOCK_CONTROL_REG;
1510+ switch (t & 0x3) {
1511+ case 0x00:
1512+ cns21xx_pll_freq = 175000000;
1513+ break;
1514+
1515+ case 0x01:
1516+ cns21xx_pll_freq = 200000000;
1517+ break;
1518+
1519+ case 0x02:
1520+ cns21xx_pll_freq = 225000000;
1521+ break;
1522+
1523+ case 0x03:
1524+ cns21xx_pll_freq = 250000000;
1525+ break;
1526+ }
1527+
1528+ cns21xx_cpu_freq = cns21xx_pll_freq / (((t >> 2) & 0x3) + 1);
1529+ cns21xx_ahb_freq = cns21xx_cpu_freq / (((t >> 4) & 0x3) + 1);
1530+ cns21xx_apb_freq = cns21xx_ahb_freq / (((t >> 8) & 0x3) + 1);
1531+
1532+ freq_init_done = 1;
1533+}
1534+
1535+unsigned long cns21xx_get_pll_freq(void)
1536+{
1537+ cns21xx_init_freq();
1538+ return cns21xx_pll_freq;
1539+}
1540+
1541+unsigned long cns21xx_get_cpu_freq(void)
1542+{
1543+ cns21xx_init_freq();
1544+ return cns21xx_cpu_freq;
1545+}
1546+
1547+unsigned long cns21xx_get_ahb_freq(void)
1548+{
1549+ cns21xx_init_freq();
1550+ return cns21xx_ahb_freq;
1551+}
1552+
1553+unsigned long cns21xx_get_apb_freq(void)
1554+{
1555+ cns21xx_init_freq();
1556+ return cns21xx_apb_freq;
1557+}
1558--- a/arch/arm/mm/Kconfig
1559+++ b/arch/arm/mm/Kconfig
1560@@ -799,6 +799,7 @@ config CACHE_XSC3L2
1561 config ARM_L1_CACHE_SHIFT
1562     int
1563     default 6 if ARM_L1_CACHE_SHIFT_6
1564+ default 4 if ARM_L1_CACHE_SHIFT_4
1565     default 5
1566 
1567 config ARM_DMA_MEM_BUFFERABLE
1568--- a/arch/arm/mm/cache-fa.S
1569+++ b/arch/arm/mm/cache-fa.S
1570@@ -28,7 +28,7 @@
1571 /*
1572  * The total size of the data cache.
1573  */
1574-#ifdef CONFIG_ARCH_GEMINI
1575+#if (defined(CONFIG_ARCH_GEMINI) || defined(CONFIG_ARCH_CNS21XX))
1576 #define CACHE_DSIZE 8192
1577 #else
1578 #define CACHE_DSIZE 16384
1579--- /dev/null
1580+++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_misc.h
1581@@ -0,0 +1,507 @@
1582+/*******************************************************************************
1583+ *
1584+ * Copyright (c) 2008 Cavium Networks
1585+ *
1586+ * This file is free software; you can redistribute it and/or modify
1587+ * it under the terms of the GNU General Public License, Version 2, as
1588+ * published by the Free Software Foundation.
1589+ *
1590+ * This file is distributed in the hope that it will be useful,
1591+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
1592+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1593+ * NONINFRINGEMENT. See the GNU General Public License for more details.
1594+ *
1595+ * You should have received a copy of the GNU General Public License
1596+ * along with this file; if not, write to the Free Software
1597+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
1598+ * visit http://www.gnu.org/licenses/.
1599+ *
1600+ * This file may also be available under a different license from Cavium.
1601+ * Contact Cavium Networks for more information
1602+ *
1603+ ******************************************************************************/
1604+
1605+#ifndef _STAR_MISC_H_
1606+#define _STAR_MISC_H_
1607+
1608+#include <mach/cns21xx.h>
1609+
1610+#define MISC_MEM_MAP_VALUE(reg_offset) \
1611+ (*((u32 volatile *)(CNS21XX_MISC_BASE_VIRT + reg_offset)))
1612+
1613+/*
1614+ * define access macros
1615+ */
1616+#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
1617+#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
1618+#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
1619+#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
1620+#define MISC_PCI_CONTROL_BROKEN_MASK_REG MISC_MEM_MAP_VALUE(0x10)
1621+#define MISC_PCI_BROKEN_STATUS_REG MISC_MEM_MAP_VALUE(0x14)
1622+#define MISC_PCI_DEVICE_VENDOR_ID_REG MISC_MEM_MAP_VALUE(0x18)
1623+#define MISC_USB_HOST_PHY_CONTROL_TEST_REG MISC_MEM_MAP_VALUE(0x1C)
1624+#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x20)
1625+#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x24)
1626+#define MISC_GPIOA_RESISTOR_CONFIG_REG MISC_MEM_MAP_VALUE(0x28)
1627+#define MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG MISC_MEM_MAP_VALUE(0x2C)
1628+#define MISC_FAST_ETHERNET_PHY_CONFIG_REG MISC_MEM_MAP_VALUE(0x30)
1629+#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x38)
1630+#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x3C)
1631+
1632+#define MISC_E_FUSE_0_REG MISC_MEM_MAP_VALUE(0x60)
1633+#define MISC_E_FUSE_1_REG MISC_MEM_MAP_VALUE(0x64)
1634+
1635+
1636+/*
1637+ * define constants macros
1638+ */
1639+#define MISC_PARALLEL_FLASH_BOOT 0
1640+#define MISC_SPI_SERIAL_FLASH_BOOT 1
1641+
1642+#define MISC_LITTLE_ENDIAN 0
1643+#define MISC_BIG_ENDIAN 1
1644+
1645+#define MISC_FARADAY_ICE 0
1646+#define MISC_ARM_ICE 1
1647+
1648+#define MISC_EXT_INT29_PINS ((0x1 << 0))
1649+#define MISC_EXT_INT30_PINS ((0x1 << 1))
1650+#define MISC_EXT_INT31_PINS ((0x1 << 2))
1651+#define MISC_I2C_PINS ((0x1 << 13) | (0x1 << 14))
1652+#define MISC_I2S_PINS ((0x1 << 15) | (0x1 << 16) | (0x1 << 17))
1653+#define MISC_I2SSD_PINS (1 << 15)
1654+#define MISC_I2SWS_PINS (1 << 16)
1655+#define MISC_I2SCLK_PINS (1 << 17)
1656+#define MISC_PCM_PINS ((0x1 << 18) | (0x1 << 19) | (0x1 << 20) | (0x1 << 21))
1657+#define MISC_PCMDR_PINS (1 << 18)
1658+#define MISC_PCMDT_PINS (1 << 19)
1659+#define MISC_PCMFS_PINS (1 << 20)
1660+#define MISC_PCMCLK_PINS (1 << 21)
1661+#define MISC_LED0_PINS ((0x1 << 22))
1662+#define MISC_LED1_PINS ((0x1 << 23))
1663+#define MISC_LED2_PINS ((0x1 << 24))
1664+#define MISC_LED012_PINS ((0x1 << 22) | (0x1 << 23) | (0x1 << 24))
1665+#define MISC_WDTIMER_RESET_PINS ((0x1 << 25))
1666+#define MISC_SPIDR_PINS (0x1 << 26)
1667+#define MISC_SPICLK_PINS (0x1 << 27)
1668+#define MISC_SPICSN0_PINS (0x1 << 28)
1669+#define MISC_SPICSN1_PINS (0x1 << 29)
1670+#define MISC_SPICSN2_PINS (0x1 << 30)
1671+#define MISC_SPICSN3_PINS (0x1 << 31)
1672+#define MISC_SPI_PINS ((0x1 << 26) | (0x1 << 27) | (0x1 << 28) | (0x1 << 29) | (0x1 << 30) | (0x1 << 31))
1673+#define MISC_MDC_MDIO_PINS ((0x1 << 0) | (0x1 << 1))
1674+#define MISC_NIC_COL_PINS ((0x1 << 2))
1675+#define MISC_IDE_PINS ((0xFF << 3))
1676+#define MISC_SRAM_BANK1_PINS ((0x1 << 11) | (0x1 << 14))
1677+#define MISC_SRAM_BANK2_PINS ((0x1 << 12) | (0x1 << 15))
1678+#define MISC_SRAM_BANK3_PINS ((0x1 << 13) | (0x1 << 16))
1679+#define MISC_PCMCIA_PINS ((0x1 << 17) | (0x1 << 18) | (0x1 << 19) | (0x1 << 20))
1680+#define MISC_UART1_PINS ((0x1 << 21) | (0x1 << 22))
1681+#define MISC_PCI_PINS (((u32)0x1FF << 23))
1682+
1683+#define MISC_UART0_ACT0_Pin (0x1 << 2)
1684+#define MISC_UART1_ACT1_Pin (0x1 << 3)
1685+
1686+#define MISC_GPIOA_PIN_0 0
1687+#define MISC_GPIOA_PIN_1 1
1688+#define MISC_GPIOA_PIN_2 2
1689+#define MISC_GPIOA_PIN_3 3
1690+#define MISC_GPIOA_PIN_4 4
1691+#define MISC_GPIOA_PIN_5 5
1692+#define MISC_GPIOA_PIN_6 6
1693+#define MISC_GPIOA_PIN_7 7
1694+#define MISC_GPIOA_PIN_8 8
1695+#define MISC_GPIOA_PIN_9 9
1696+#define MISC_GPIOA_PIN_10 10
1697+
1698+#define MISC_GPIOA_75K_RESISTOR_PULL_DOWN 1
1699+#define MISC_GPIOA_75K_RESISTOR_PULL_UP 2
1700+#define MISC_GPIOA_75K_RESISTOR_PULL_KEEPER 3
1701+
1702+#define MISC_GPIOA_DRIVE_STRENGTH_4MA 0
1703+#define MISC_GPIOA_DRIVE_STRENGTH_8MA 1
1704+
1705+
1706+/*
1707+ * macro declarations
1708+ */
1709+#define HAL_MISC_ENABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1710+{ \
1711+ (MISC_CHIP_CONFIG_REG) |= (0x1 << 4); \
1712+}
1713+
1714+#define HAL_MISC_DISABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1715+{ \
1716+ (MISC_CHIP_CONFIG_REG) &= ~(0x1 << 4); \
1717+}
1718+
1719+
1720+/*
1721+ * Macro defines for GPIOA and GPIOB Pin Enable Register
1722+ */
1723+#define HAL_MISC_ENABLE_EXT_INT29_PINS() \
1724+{ \
1725+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_EXT_INT29_PINS); \
1726+}
1727+
1728+#define HAL_MISC_DISABLE_EXT_INT29_PINS() \
1729+{ \
1730+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_EXT_INT29_PINS); \
1731+}
1732+
1733+#define HAL_MISC_ENABLE_EXT_INT30_PINS() \
1734+{ \
1735+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_EXT_INT30_PINS); \
1736+}
1737+
1738+#define HAL_MISC_DISABLE_EXT_INT30_PINS() \
1739+{ \
1740+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_EXT_INT30_PINS); \
1741+}
1742+
1743+#define HAL_MISC_ENABLE_I2C_PINS() \
1744+{ \
1745+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2C_PINS); \
1746+}
1747+
1748+#define HAL_MISC_DISABLE_I2C_PINS() \
1749+{ \
1750+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2C_PINS); \
1751+}
1752+
1753+#define HAL_MISC_ENABLE_I2S_PINS() \
1754+{ \
1755+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2S_PINS); \
1756+}
1757+
1758+#define HAL_MISC_DISABLE_I2S_PINS() \
1759+{ \
1760+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2S_PINS); \
1761+}
1762+
1763+#define HAL_MISC_DISABLE_I2SSD_PINS() \
1764+{ \
1765+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SSD_PINS); \
1766+}
1767+
1768+#define HAL_MISC_DISABLE_I2SWS_PINS() \
1769+{ \
1770+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SWS_PINS); \
1771+}
1772+
1773+#define HAL_MISC_DISABLE_I2SCLK_PINS() \
1774+{ \
1775+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SCLK_PINS); \
1776+}
1777+
1778+#define HAL_MISC_ENABLE_PCM_PINS() \
1779+{ \
1780+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_PCM_PINS); \
1781+}
1782+
1783+#define HAL_MISC_DISABLE_PCM_PINS() \
1784+{ \
1785+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCM_PINS); \
1786+}
1787+
1788+#define HAL_MISC_DISABLE_PCMDR_PINS() \
1789+{ \
1790+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMDR_PINS); \
1791+}
1792+
1793+#define HAL_MISC_DISABLE_PCMDT_PINS() \
1794+{ \
1795+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMDT_PINS); \
1796+}
1797+
1798+#define HAL_MISC_DISABLE_PCMFS_PINS() \
1799+{ \
1800+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMFS_PINS); \
1801+}
1802+
1803+#define HAL_MISC_DISABLE_PCMCLK_PINS() \
1804+{ \
1805+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMCLK_PINS); \
1806+}
1807+
1808+#define HAL_MISC_ENABLE_LED0_PINS() \
1809+{ \
1810+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED0_PINS); \
1811+}
1812+
1813+#define HAL_MISC_DISABLE_LED0_PINS() \
1814+{ \
1815+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED0_PINS); \
1816+}
1817+
1818+#define HAL_MISC_ENABLE_LED1_PINS() \
1819+{ \
1820+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED1_PINS); \
1821+}
1822+
1823+#define HAL_MISC_DISABLE_LED1_PINS() \
1824+{ \
1825+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED1_PINS); \
1826+}
1827+
1828+#define HAL_MISC_ENABLE_LED2_PINS() \
1829+{ \
1830+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED2_PINS); \
1831+}
1832+
1833+#define HAL_MISC_DISABLE_LED2_PINS() \
1834+{ \
1835+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED2_PINS); \
1836+}
1837+
1838+#define HAL_MISC_ENABLE_LED012_PINS() \
1839+{ \
1840+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED012_PINS); \
1841+}
1842+
1843+#define HAL_MISC_DISABLE_LED012_PINS() \
1844+{ \
1845+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED012_PINS); \
1846+}
1847+
1848+#define HAL_MISC_ENABLE_WDTIMER_RESET_PINS() \
1849+{ \
1850+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_WDTIMER_RESET_PINS); \
1851+}
1852+
1853+#define HAL_MISC_DISABLE_WDTIMER_RESET_PINS() \
1854+{ \
1855+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_WDTIMER_RESET_PINS); \
1856+}
1857+
1858+#define HAL_MISC_ENABLE_SPI_PINS() \
1859+{ \
1860+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPI_PINS); \
1861+}
1862+
1863+#define HAL_MISC_ENABLE_SPIDR_PINS() \
1864+{ \
1865+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPIDR_PINS); \
1866+}
1867+
1868+#define HAL_MISC_ENABLE_SPICLK_PINS() \
1869+{ \
1870+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICLK_PINS); \
1871+}
1872+
1873+#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1874+{ \
1875+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN0_PINS); \
1876+}
1877+
1878+#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1879+{ \
1880+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN0_PINS); \
1881+}
1882+
1883+#define HAL_MISC_ENABLE_SPICSN1_PINS() \
1884+{ \
1885+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN1_PINS); \
1886+}
1887+
1888+#define HAL_MISC_ENABLE_SPICSN2_PINS() \
1889+{ \
1890+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN2_PINS); \
1891+}
1892+
1893+#define HAL_MISC_ENABLE_SPICSN3_PINS() \
1894+{ \
1895+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN3_PINS); \
1896+}
1897+
1898+#define HAL_MISC_DISABLE_SPI_PINS() \
1899+{ \
1900+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPI_PINS); \
1901+}
1902+
1903+#define HAL_MISC_DISABLE_SPIDR_PINS() \
1904+{ \
1905+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPIDR_PINS); \
1906+}
1907+
1908+#define HAL_MISC_DISABLE_SPICLK_PINS() \
1909+{ \
1910+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICLK_PINS); \
1911+}
1912+
1913+#define HAL_MISC_DISABLE_SPICSN0_PINS() \
1914+{ \
1915+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN0_PINS); \
1916+}
1917+
1918+#define HAL_MISC_DISABLE_SPICSN1_PINS() \
1919+{ \
1920+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN1_PINS); \
1921+}
1922+
1923+#define HAL_MISC_DISABLE_SPICSN2_PINS() \
1924+{ \
1925+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN2_PINS); \
1926+}
1927+
1928+#define HAL_MISC_DISABLE_SPICSN3_PINS() \
1929+{ \
1930+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN3_PINS); \
1931+}
1932+
1933+#define HAL_MISC_ENABLE_UART0_ACT0_PIN() \
1934+{ \
1935+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART0_ACT0_Pin); \
1936+}
1937+
1938+#define HAL_MISC_DISABLE_UART0_ACT0_PIN() \
1939+{ \
1940+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART0_ACT0_Pin); \
1941+}
1942+
1943+#define HAL_MISC_ENABLE_UART1_ACT1_PIN() \
1944+{ \
1945+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART1_ACT1_Pin); \
1946+}
1947+
1948+#define HAL_MISC_DISABLE_UART1_ACT1_PIN() \
1949+{ \
1950+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART1_ACT1_Pin); \
1951+}
1952+
1953+#define HAL_MISC_ENABLE_MDC_MDIO_PINS() \
1954+{ \
1955+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_MDC_MDIO_PINS); \
1956+}
1957+
1958+#define HAL_MISC_DISABLE_MDC_MDIO_PINS() \
1959+{ \
1960+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_MDC_MDIO_PINS); \
1961+}
1962+
1963+#define HAL_MISC_ENABLE_NIC_COL_PINS() \
1964+{ \
1965+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_NIC_COL_PINS); \
1966+}
1967+
1968+#define HAL_MISC_DISABLE_NIC_COL_PINS() \
1969+{ \
1970+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_NIC_COL_PINS); \
1971+}
1972+
1973+#define HAL_MISC_ENABLE_IDE_PINS() \
1974+{ \
1975+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_IDE_PINS); \
1976+}
1977+
1978+#define HAL_MISC_DISABLE_IDE_PINS() \
1979+{ \
1980+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_IDE_PINS); \
1981+}
1982+
1983+#define HAL_MISC_ENABLE_SRAM_BANK1_PINS() \
1984+{ \
1985+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK1_PINS); \
1986+}
1987+
1988+#define HAL_MISC_DISABLE_SRAM_BANK1_PINS() \
1989+{ \
1990+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK1_PINS); \
1991+}
1992+
1993+#define HAL_MISC_ENABLE_SRAM_BANK2_PINS() \
1994+{ \
1995+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK2_PINS); \
1996+}
1997+
1998+#define HAL_MISC_DISABLE_SRAM_BANK2_PINS() \
1999+{ \
2000+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK2_PINS); \
2001+}
2002+
2003+#define HAL_MISC_ENABLE_SRAM_BANK3_PINS() \
2004+{ \
2005+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK3_PINS); \
2006+}
2007+
2008+#define HAL_MISC_DISABLE_SRAM_BANK3_PINS() \
2009+{ \
2010+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK3_PINS); \
2011+}
2012+
2013+#define HAL_MISC_ENABLE_PCMCIA_PINS() \
2014+{ \
2015+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCMCIA_PINS); \
2016+}
2017+
2018+#define HAL_MISC_DISABLE_PCMCIA_PINS() \
2019+{ \
2020+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCMCIA_PINS); \
2021+}
2022+
2023+#define HAL_MISC_ENABLE_UART1_PINS() \
2024+{ \
2025+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_UART1_PINS); \
2026+}
2027+
2028+#define HAL_MISC_DISABLE_UART1_PINS() \
2029+{ \
2030+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_UART1_PINS); \
2031+}
2032+
2033+#define HAL_MISC_ENABLE_PCI_PINS() \
2034+{ \
2035+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCI_PINS); \
2036+}
2037+
2038+#define HAL_MISC_DISABLE_PCI_PINS() \
2039+{ \
2040+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCI_PINS); \
2041+}
2042+
2043+#define HAL_MISC_ENABLE_ALL_SHARED_GPIO_PINS() \
2044+{ \
2045+ (MISC_GPIOA_PIN_ENABLE_REG) = (0x0); \
2046+ (MISC_GPIOB_PIN_ENABLE_REG) = (0x0); \
2047+}
2048+
2049+#define HAL_MISC_DISABLE_ALL_SHARED_GPIO_PINS() \
2050+{ \
2051+ (MISC_GPIOA_PIN_ENABLE_REG) = (0xFFFFFFFF); \
2052+ (MISC_GPIOB_PIN_ENABLE_REG) = (0xFFFFFFFF); \
2053+}
2054+
2055+#define HAL_MISC_CONFIGURE_GPIOA_RESISTOR(pin_index, value) \
2056+{ \
2057+ (MISC_GPIOA_RESISTOR_CONFIG_REG) &= ~(0x3 << (2 * pin_index)); \
2058+ (MISC_GPIOA_RESISTOR_CONFIG_REG) |= ((value & 0x3) << (2 * pin_index)); \
2059+}
2060+
2061+#define HAL_MISC_CONFIGURE_GPIOA_DRIVE_STRENGTH(pin_index, value) \
2062+{ \
2063+ (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) &= ~(0x1 << pin_index); \
2064+ (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) |= (value << pin_index); \
2065+}
2066+
2067+#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE0() \
2068+{ \
2069+ (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x0); \
2070+}
2071+
2072+#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE1() \
2073+{ \
2074+ (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x1); \
2075+}
2076+
2077+#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE2() \
2078+{ \
2079+ (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x2); \
2080+}
2081+
2082+#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE3() \
2083+{ \
2084+ (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x3); \
2085+}
2086+
2087+
2088+#endif // end of #ifndef _STAR_MISC_H_
2089

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