Root/target/linux/cns3xxx/patches-2.6.31/100-cns3xxx_support.patch

1--- a/arch/arm/common/gic.c
2+++ b/arch/arm/common/gic.c
3@@ -32,6 +32,8 @@
4 #include <asm/irq.h>
5 #include <asm/mach/irq.h>
6 #include <asm/hardware/gic.h>
7+#include <linux/module.h>
8+
9 
10 static DEFINE_SPINLOCK(irq_controller_lock);
11 
12@@ -90,7 +92,7 @@ static void gic_ack_irq(unsigned int irq
13     spin_unlock(&irq_controller_lock);
14 }
15 
16-static void gic_mask_irq(unsigned int irq)
17+void gic_mask_irq(unsigned int irq)
18 {
19     u32 mask = 1 << (irq % 32);
20 
21@@ -175,6 +177,109 @@ void __init gic_cascade_irq(unsigned int
22     set_irq_chained_handler(irq, gic_handle_cascade_irq);
23 }
24 
25+
26+// type: level or edge
27+// 0 - level high active, 1 - rising edge sensitive
28+void set_interrupt_type_by_base(void __iomem *base, int id, u32 type)
29+{
30+ unsigned char int_type_bit=0;
31+ u32 gic_v=0;
32+
33+ // judge gic offset
34+ //printk("gic addr: %#x\n", id/16*4 + 0xc00);
35+ //printk("gic addr bits: %#x\n", id%16*2);
36+ int_type_bit=(id%16*2+1);
37+
38+ gic_v = readl(base + GIC_DIST_CONFIG + id/16*4);
39+
40+ gic_v &= (~(1 << int_type_bit));
41+ gic_v |= ( type << int_type_bit);
42+
43+ writel(gic_v, base + GIC_DIST_CONFIG + id/16*4);
44+}
45+
46+// type: level or edge
47+// 0 - level high active, 1 - rising edge sensitive
48+void set_interrupt_type(int id, u32 type)
49+{
50+ set_interrupt_type_by_base((void __iomem *) CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, id, type);
51+}
52+
53+void get_interrupt_type_by_base(void __iomem *base, u32 id, u32 *type)
54+{
55+ unsigned char int_type_bit=0;
56+ u32 gic_v=0;
57+
58+ // judge gic offset
59+ int_type_bit=(id%16*2+1);
60+
61+ //gic_v = readl(base + GIC_DIST_CONFIG + 4);
62+ gic_v = readl(base + GIC_DIST_CONFIG + id/16*4);
63+
64+ *type = ((gic_v >> int_type_bit) & 0x1);
65+
66+ //writel(0, base + GIC_DIST_CONFIG + id/16*4);
67+}
68+
69+void get_interrupt_type(u32 id, u32 *type)
70+{
71+ get_interrupt_type_by_base((void __iomem *) CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, id, type);
72+}
73+
74+
75+
76+// set interrupt priority
77+void set_interrupt_pri_by_base(void __iomem *base, u32 id, u32 pri)
78+{
79+ unsigned char int_type_bit=0;
80+ u32 gic_v=0;
81+
82+
83+ // judge gic offset
84+ int_type_bit=(id%4*8+4);
85+
86+ gic_v = readl(base + GIC_DIST_PRI + id/4*4);
87+
88+ gic_v &= (~(0xf << int_type_bit));
89+ gic_v |= (pri << int_type_bit);
90+
91+ writel(gic_v, base + GIC_DIST_PRI + id/4*4);
92+
93+ gic_v = 0;
94+ gic_v = readl(base + GIC_DIST_PRI + id/4*4);
95+ //printk("read gic_v: %x\n", gic_v);
96+}
97+
98+void set_interrupt_pri(u32 id, u32 pri)
99+{
100+ set_interrupt_pri_by_base((void __iomem *) CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, id, pri);
101+}
102+
103+void get_interrupt_pri_by_base(void __iomem *base, int id, u32 *type)
104+{
105+ unsigned char int_type_bit=0;
106+ u32 gic_v=0;
107+
108+ // judge gic offset
109+ int_type_bit=(id%4*8+4);
110+
111+ gic_v = readl(base + GIC_DIST_PRI + id/4*4);
112+
113+ //printk("int_type_bit: %d\n", int_type_bit);
114+ //printk("gic_v: %#x\n", gic_v);
115+ *type = ((gic_v >> int_type_bit) & 0xf);
116+ //gic_v &= (~(1 << int_type_bit));
117+ //gic_v |= ( type << int_type_bit);
118+
119+ //writel(0, base + GIC_DIST_CONFIG + id/16*4);
120+}
121+
122+void get_interrupt_pri(int id, u32 *pri)
123+{
124+ get_interrupt_pri_by_base((void __iomem *) CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, id, pri);
125+}
126+
127+
128 void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
129               unsigned int irq_start)
130 {
131@@ -254,6 +359,12 @@ void __cpuinit gic_cpu_init(unsigned int
132     writel(1, base + GIC_CPU_CTRL);
133 }
134 
135+void cns3xxx_write_pri_mask(u8 pri_mask)
136+{
137+ writel(pri_mask, (void __iomem *) CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT + GIC_CPU_PRIMASK);
138+}
139+
140+
141 #ifdef CONFIG_SMP
142 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
143 {
144--- a/arch/arm/include/asm/cacheflush.h
145+++ b/arch/arm/include/asm/cacheflush.h
146@@ -280,6 +280,35 @@ extern void dmac_flush_range(const void
147 
148 #endif
149 
150+#ifdef CONFIG_CPU_NO_CACHE_BCAST
151+enum smp_dma_cache_type {
152+ SMP_DMA_CACHE_INV,
153+ SMP_DMA_CACHE_CLEAN,
154+ SMP_DMA_CACHE_FLUSH,
155+};
156+
157+extern void smp_dma_cache_op(int type, const void *start, const void *end);
158+
159+static inline void smp_dma_inv_range(const void *start, const void *end)
160+{
161+ smp_dma_cache_op(SMP_DMA_CACHE_INV, start, end);
162+}
163+
164+static inline void smp_dma_clean_range(const void *start, const void *end)
165+{
166+ smp_dma_cache_op(SMP_DMA_CACHE_CLEAN, start, end);
167+}
168+
169+static inline void smp_dma_flush_range(const void *start, const void *end)
170+{
171+ smp_dma_cache_op(SMP_DMA_CACHE_FLUSH, start, end);
172+}
173+#else
174+#define smp_dma_inv_range dmac_inv_range
175+#define smp_dma_clean_range dmac_clean_range
176+#define smp_dma_flush_range dmac_flush_range
177+#endif
178+
179 #ifdef CONFIG_OUTER_CACHE
180 
181 extern struct outer_cache_fns outer_cache;
182--- /dev/null
183+++ b/arch/arm/include/asm/hardware/arm_twd.h
184@@ -0,0 +1,21 @@
185+#ifndef __ASM_HARDWARE_TWD_H
186+#define __ASM_HARDWARE_TWD_H
187+
188+#define TWD_TIMER_LOAD 0x00
189+#define TWD_TIMER_COUNTER 0x04
190+#define TWD_TIMER_CONTROL 0x08
191+#define TWD_TIMER_INTSTAT 0x0C
192+
193+#define TWD_WDOG_LOAD 0x20
194+#define TWD_WDOG_COUNTER 0x24
195+#define TWD_WDOG_CONTROL 0x28
196+#define TWD_WDOG_INTSTAT 0x2C
197+#define TWD_WDOG_RESETSTAT 0x30
198+#define TWD_WDOG_DISABLE 0x34
199+
200+#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
201+#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
202+#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
203+#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
204+
205+#endif
206--- /dev/null
207+++ b/arch/arm/include/asm/hardware/cache-l2cc.h
208@@ -0,0 +1,79 @@
209+/*******************************************************************************
210+ *
211+ * arch/arm/include/asm/hardware/cache-l2cc.h
212+ *
213+ * Copyright (c) 2008 Cavium Networks
214+ *
215+ * This file is free software; you can redistribute it and/or modify
216+ * it under the terms of the GNU General Public License, Version 2, as
217+ * published by the Free Software Foundation.
218+ *
219+ * This file is distributed in the hope that it will be useful,
220+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
221+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
222+ * NONINFRINGEMENT. See the GNU General Public License for more details.
223+ *
224+ * You should have received a copy of the GNU General Public License
225+ * along with this file; if not, write to the Free Software
226+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
227+ * visit http://www.gnu.org/licenses/.
228+ *
229+ * This file may also be available under a different license from Cavium.
230+ * Contact Cavium Networks for more information
231+ *
232+ ******************************************************************************/
233+
234+#ifndef __ASM_ARM_HARDWARE_L2_H
235+#define __ASM_ARM_HARDWARE_L2_H
236+
237+#define L2CC_CACHE_ID 0x000
238+#define L2CC_CACHE_TYPE 0x004
239+#define L2CC_CTRL 0x100
240+#define L2CC_AUX_CTRL 0x104
241+#define L2CC_TAG_RAM_LATENCY_CTRL 0x108
242+#define L2CC_DATA_RAM_LATENCY_CTRL 0x10C
243+#define L2CC_EVENT_CNT_CTRL 0x200
244+#define L2CC_EVENT_CNT1_CFG 0x204
245+#define L2CC_EVENT_CNT0_CFG 0x208
246+#define L2CC_EVENT_CNT1_VAL 0x20C
247+#define L2CC_EVENT_CNT0_VAL 0x210
248+#define L2CC_INTR_MASK 0x214
249+#define L2CC_MASKED_INTR_STAT 0x218
250+#define L2CC_RAW_INTR_STAT 0x21C
251+#define L2CC_INTR_CLEAR 0x220
252+#define L2CC_CACHE_SYNC 0x730
253+#define L2CC_INV_LINE_PA 0x770
254+#define L2CC_INV_WAY 0x77C
255+#define L2CC_CLEAN_LINE_PA 0x7B0
256+#define L2CC_CLEAN_LINE_IDX 0x7B8
257+#define L2CC_CLEAN_WAY 0x7BC
258+#define L2CC_CLEAN_INV_LINE_PA 0x7F0
259+#define L2CC_CLEAN_INV_LINE_IDX 0x7F8
260+#define L2CC_CLEAN_INV_WAY 0x7FC
261+#define L2CC_LOCKDOWN_0_WAY_D 0x900
262+#define L2CC_LOCKDOWN_0_WAY_I 0x904
263+#define L2CC_LOCKDOWN_1_WAY_D 0x908
264+#define L2CC_LOCKDOWN_1_WAY_I 0x90C
265+#define L2CC_LOCKDOWN_2_WAY_D 0x910
266+#define L2CC_LOCKDOWN_2_WAY_I 0x914
267+#define L2CC_LOCKDOWN_3_WAY_D 0x918
268+#define L2CC_LOCKDOWN_3_WAY_I 0x91C
269+#define L2CC_LOCKDOWN_4_WAY_D 0x920
270+#define L2CC_LOCKDOWN_4_WAY_I 0x924
271+#define L2CC_LOCKDOWN_5_WAY_D 0x928
272+#define L2CC_LOCKDOWN_5_WAY_I 0x92C
273+#define L2CC_LOCKDOWN_6_WAY_D 0x930
274+#define L2CC_LOCKDOWN_6_WAY_I 0x934
275+#define L2CC_LOCKDOWN_7_WAY_D 0x938
276+#define L2CC_LOCKDOWN_7_WAY_I 0x93C
277+#define L2CC_LOCKDOWN_LINE_EN 0x950
278+#define L2CC_UNLOCK_ALL_LINE_WAY 0x954
279+#define L2CC_ADDR_FILTER_START 0xC00
280+#define L2CC_ADDR_FILTER_END 0xC04
281+#define L2CC_DEBUG_CTRL 0xF40
282+
283+#ifndef __ASSEMBLY__
284+extern void __init l2cc_init(void __iomem *base);
285+#endif
286+
287+#endif
288--- a/arch/arm/include/asm/hardware/gic.h
289+++ b/arch/arm/include/asm/hardware/gic.h
290@@ -37,6 +37,13 @@ void gic_dist_init(unsigned int gic_nr,
291 void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
292 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
293 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
294+
295+void cns3xxx_write_pri_mask(u8 pri_mask);
296+void set_interrupt_type(int id, u32 type);
297+void get_interrupt_type(u32 id, u32 *type);
298+void set_interrupt_pri(u32 id, u32 pri);
299+void get_interrupt_pri(int id, u32 *pri);
300+
301 #endif
302 
303 #endif
304--- a/arch/arm/include/asm/mach/pci.h
305+++ b/arch/arm/include/asm/mach/pci.h
306@@ -20,6 +20,9 @@ struct hw_pci {
307     void (*postinit)(void);
308     u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
309     int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
310+#ifdef CONFIG_PCI_DOMAINS
311+ int nr_domains;
312+#endif
313 };
314 
315 /*
316@@ -37,8 +40,12 @@ struct pci_sys_data {
317                     /* IRQ mapping */
318     int (*map_irq)(struct pci_dev *, u8, u8);
319     struct hw_pci *hw;
320+#ifdef CONFIG_PCI_DOMAINS
321+ int domain;
322+#endif
323 };
324 
325+
326 /*
327  * This is the standard PCI-PCI bridge swizzling algorithm.
328  */
329--- a/arch/arm/include/asm/pci.h
330+++ b/arch/arm/include/asm/pci.h
331@@ -25,6 +25,11 @@ static inline void pcibios_penalize_isa_
332     /* We don't do dynamic PCI IRQ allocation */
333 }
334 
335+#ifdef CONFIG_PCI_DOMAINS
336+int pci_domain_nr(struct pci_bus *bus);
337+int pci_proc_domain(struct pci_bus *bus);
338+#endif
339+
340 /*
341  * The PCI address space does equal the physical memory address space.
342  * The networking and block device layers use this boolean for bounce
343--- a/arch/arm/include/asm/xor.h
344+++ b/arch/arm/include/asm/xor.h
345@@ -132,10 +132,43 @@ static struct xor_block_template xor_blo
346     .do_5 = xor_arm4regs_5,
347 };
348 
349+#ifdef CONFIG_CNS3XXX_RAID
350+extern void do_cns_rdma_xorgen(unsigned int src_no, unsigned int bytes,
351+ void **bh_ptr, void *dst_ptr);
352+/*
353+ * We create these funcs/template just for benchmark reference.
354+ */
355+static void xor_cns_raid_2(unsigned long bytes, unsigned long *p1,
356+ unsigned long *p2)
357+{
358+ void *src[2];
359+
360+ src[0] = p2;
361+ src[1] = p1;
362+ do_cns_rdma_xorgen(2, bytes, src, (void *)p2);
363+}
364+
365+static struct xor_block_template xor_block_cnsraid = {
366+ .name = "CNS-RAID",
367+ .do_2 = xor_cns_raid_2,
368+};
369+#endif /* CONFIG_CNS3XXX_RAID */
370+
371 #undef XOR_TRY_TEMPLATES
372+
373+#ifdef CONFIG_CNS3XXX_RAID
374+#define XOR_TRY_TEMPLATES \
375+ do { \
376+ xor_speed(&xor_block_arm4regs); \
377+ xor_speed(&xor_block_8regs); \
378+ xor_speed(&xor_block_32regs); \
379+ xor_speed(&xor_block_cnsraid); \
380+ } while (0)
381+#else
382 #define XOR_TRY_TEMPLATES \
383     do { \
384         xor_speed(&xor_block_arm4regs); \
385         xor_speed(&xor_block_8regs); \
386         xor_speed(&xor_block_32regs); \
387     } while (0)
388+#endif /* CONFIG_CNS3XXX_RAID */
389--- a/arch/arm/Kconfig
390+++ b/arch/arm/Kconfig
391@@ -193,7 +193,7 @@ menu "System Type"
392 
393 choice
394     prompt "ARM system type"
395- default ARCH_VERSATILE
396+ default ARCH_CNS3XXX
397 
398 config ARCH_AAEC2000
399     bool "Agilent AAEC-2000 based"
400@@ -235,6 +235,17 @@ config ARCH_VERSATILE
401     help
402       This enables support for ARM Ltd Versatile board.
403 
404+config ARCH_CNS3XXX
405+ bool "Cavium Networks CNS3XXX family"
406+ select ARM_AMBA
407+ select HAVE_CLK
408+ select COMMON_CLKDEV
409+ select GENERIC_TIME
410+ select GENERIC_CLOCKEVENTS
411+ select ARCH_REQUIRE_GPIOLIB
412+ help
413+ This enables support for Cavium Networks CNS3XXX boards.
414+
415 config ARCH_AT91
416     bool "Atmel AT91"
417     select GENERIC_GPIO
418@@ -715,6 +726,8 @@ source "arch/arm/mach-aaec2000/Kconfig"
419 
420 source "arch/arm/mach-realview/Kconfig"
421 
422+source "arch/arm/mach-cns3xxx/Kconfig"
423+
424 source "arch/arm/mach-at91/Kconfig"
425 
426 source "arch/arm/plat-mxc/Kconfig"
427@@ -768,7 +781,7 @@ endif
428 
429 config ARM_ERRATA_411920
430     bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
431- depends on CPU_V6 && !SMP
432+ depends on CPU_V6 && !SMP && !ARCH_CNS3XXX
433     help
434       Invalidation of the Instruction Cache operation can
435       fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
436@@ -849,13 +862,17 @@ config ISA_DMA_API
437     bool
438 
439 config PCI
440- bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
441+ bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_CNS3XXX || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
442     help
443       Find out whether you have a PCI motherboard. PCI is the name of a
444       bus system, i.e. the way the CPU talks to the other stuff inside
445       your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
446       VESA. If you have PCI, say Y, otherwise N.
447 
448+config PCI_DOMAINS
449+ def_bool y
450+ depends on PCI && ARCH_CNS3XXX
451+
452 config PCI_SYSCALL
453     def_bool PCI
454 
455@@ -873,6 +890,8 @@ config PCI_HOST_ITE8152
456 
457 source "drivers/pci/Kconfig"
458 
459+source "drivers/pci/pcie/Kconfig"
460+
461 source "drivers/pcmcia/Kconfig"
462 
463 endmenu
464@@ -884,10 +903,10 @@ source "kernel/time/Kconfig"
465 config SMP
466     bool "Symmetric Multi-Processing (EXPERIMENTAL)"
467     depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
468- MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
469+ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_CNS3XXX || ARCH_OMAP4)
470     depends on GENERIC_CLOCKEVENTS
471     select USE_GENERIC_SMP_HELPERS
472- select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4)
473+ select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_CNS3XXX || ARCH_OMAP4)
474     help
475       This enables support for systems with more than one CPU. If you have
476       a system with only one CPU, like most personal computers, say N. If
477@@ -944,7 +963,7 @@ config NR_CPUS
478     int "Maximum number of CPUs (2-32)"
479     range 2 32
480     depends on SMP
481- default "4"
482+ default "2"
483 
484 config HOTPLUG_CPU
485     bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
486@@ -955,10 +974,10 @@ config HOTPLUG_CPU
487 
488 config LOCAL_TIMERS
489     bool "Use local timer interrupts"
490- depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
491+ depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || ARCH_CNS3XXX || \
492         REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
493     default y
494- select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4)
495+ select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_CNS3XXX || ARCH_OMAP4)
496     help
497       Enable support for local timers on SMP platforms, rather then the
498       legacy IPI broadcast method. Local timers allows the system
499--- a/arch/arm/kernel/bios32.c
500+++ b/arch/arm/kernel/bios32.c
501@@ -531,6 +531,7 @@ static void __init pcibios_init_hw(struc
502         sys->busnr = busnr;
503         sys->swizzle = hw->swizzle;
504         sys->map_irq = hw->map_irq;
505+ sys->domain = hw->nr_domains;
506         sys->resource[0] = &ioport_resource;
507         sys->resource[1] = &iomem_resource;
508 
509@@ -694,3 +695,20 @@ int pci_mmap_page_range(struct pci_dev *
510 
511     return 0;
512 }
513+#ifdef CONFIG_PCI_DOMAINS
514+int pci_domain_nr(struct pci_bus *bus)
515+{
516+
517+ //struct pci_sysdata *sd = bus->sysdata;
518+ struct pci_sys_data *sd = bus->sysdata;
519+ return sd->domain;
520+
521+}
522+EXPORT_SYMBOL(pci_domain_nr);
523+
524+int pci_proc_domain(struct pci_bus *bus)
525+{
526+ return pci_domain_nr(bus);
527+}
528+EXPORT_SYMBOL(pci_proc_domain);
529+#endif
530--- a/arch/arm/kernel/entry-armv.S
531+++ b/arch/arm/kernel/entry-armv.S
532@@ -38,6 +38,12 @@
533     bne asm_do_IRQ
534 
535 #ifdef CONFIG_SMP
536+
537+ test_for_cache_ipi r0, r6, r5, lr
538+ movne r0, sp
539+ adrne lr, 1b
540+ bne do_cache_IPI
541+
542     /*
543      * XXX
544      *
545--- a/arch/arm/kernel/smp.c
546+++ b/arch/arm/kernel/smp.c
547@@ -58,12 +58,20 @@ static DEFINE_PER_CPU(struct ipi_data, i
548     .lock = SPIN_LOCK_UNLOCKED,
549 };
550 
551+#ifdef CONFIG_CPU_NO_CACHE_BCAST_DEBUG
552+static DEFINE_PER_CPU(unsigned long,dma_cache_counter) = 0;
553+unsigned long bcache_bitmap = 0;
554+#endif
555+
556 enum ipi_msg_type {
557     IPI_TIMER,
558     IPI_RESCHEDULE,
559     IPI_CALL_FUNC,
560     IPI_CALL_FUNC_SINGLE,
561     IPI_CPU_STOP,
562+#ifdef CONFIG_CPU_NO_CACHE_BCAST
563+ IPI_DMA_CACHE,
564+#endif
565 };
566 
567 int __cpuinit __cpu_up(unsigned int cpu)
568@@ -349,10 +357,17 @@ static void send_ipi_message(const struc
569      * Call the platform specific cross-CPU call function.
570      */
571     smp_cross_call(mask);
572-
573     local_irq_restore(flags);
574 }
575 
576+static void send_ipi_message_cache(const struct cpumask *mask)
577+{
578+ unsigned long flags;
579+
580+ local_irq_save(flags);
581+ smp_cross_call_cache(mask);
582+ local_irq_restore(flags);
583+}
584 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
585 {
586     send_ipi_message(mask, IPI_CALL_FUNC);
587@@ -373,6 +388,13 @@ void show_ipi_list(struct seq_file *p)
588         seq_printf(p, " %10lu", per_cpu(ipi_data, cpu).ipi_count);
589 
590     seq_putc(p, '\n');
591+
592+#ifdef CONFIG_CPU_NO_CACHE_BCAST_DEBUG
593+ seq_puts(p, " dc: ");
594+ for_each_present_cpu(cpu)
595+ seq_printf(p, " %10lu", per_cpu(dma_cache_counter, cpu));
596+ seq_putc(p, '\n');
597+#endif
598 }
599 
600 void show_local_irqs(struct seq_file *p)
601@@ -472,6 +494,10 @@ static void ipi_cpu_stop(unsigned int cp
602         cpu_relax();
603 }
604 
605+#ifdef CONFIG_CPU_NO_CACHE_BCAST
606+static void ipi_dma_cache_op(unsigned int cpu);
607+#endif
608+
609 /*
610  * Main handler for inter-processor interrupts
611  *
612@@ -531,6 +557,16 @@ asmlinkage void __exception do_IPI(struc
613                 ipi_cpu_stop(cpu);
614                 break;
615 
616+#ifdef CONFIG_CPU_NO_CACHE_BCAST
617+ case IPI_DMA_CACHE:
618+#ifdef CONFIG_CPU_NO_CACHE_BCAST_DEBUG
619+ //get_cpu_var(dma_cache_counter)++;
620+ //put_cpu_var(dma_cache_counter);
621+#endif
622+ ipi_dma_cache_op(cpu);
623+ break;
624+#endif
625+
626             default:
627                 printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n",
628                        cpu, nextmsg);
629@@ -542,6 +578,19 @@ asmlinkage void __exception do_IPI(struc
630     set_irq_regs(old_regs);
631 }
632 
633+asmlinkage void __exception do_cache_IPI(struct pt_regs *regs)
634+{
635+ unsigned int cpu = smp_processor_id();
636+ struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
637+ struct pt_regs *old_regs = set_irq_regs(regs);
638+
639+ ipi->ipi_count++;
640+
641+ ipi_dma_cache_op(cpu);
642+
643+ set_irq_regs(old_regs);
644+}
645+
646 void smp_send_reschedule(int cpu)
647 {
648     send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
649@@ -692,3 +741,115 @@ void flush_tlb_kernel_range(unsigned lon
650     } else
651         local_flush_tlb_kernel_range(start, end);
652 }
653+
654+#ifdef CONFIG_CPU_NO_CACHE_BCAST
655+/*
656+ * DMA cache maintenance operations on SMP if the automatic hardware
657+ * broadcasting is not available
658+ */
659+struct smp_dma_cache_struct {
660+ int type;
661+ const void *start;
662+ const void *end;
663+ char unfinished;
664+};
665+
666+static struct smp_dma_cache_struct smp_dma_cache_data[3];
667+static DEFINE_SPINLOCK(smp_dma_cache_lock);
668+
669+static void local_dma_cache_op(int type, const void *start, const void *end)
670+{
671+ switch (type) {
672+ case SMP_DMA_CACHE_INV:
673+ dmac_inv_range(start, end);
674+ break;
675+ case SMP_DMA_CACHE_CLEAN:
676+ dmac_clean_range(start, end);
677+ break;
678+ case SMP_DMA_CACHE_FLUSH:
679+ dmac_flush_range(start, end);
680+ break;
681+ default:
682+ printk(KERN_CRIT "CPU%u: Unknown SMP DMA cache type %d\n",
683+ smp_processor_id(), type);
684+ }
685+}
686+
687+/*
688+ * This function must be executed with interrupts disabled.
689+ */
690+static void ipi_dma_cache_op(unsigned int cpu)
691+{
692+ unsigned long flags;
693+ int type;
694+ const void *start;
695+ const void *end;
696+
697+ /* check for spurious IPI */
698+ spin_lock_irqsave(&smp_dma_cache_lock, flags);
699+ if (!test_bit(cpu, &bcache_bitmap))
700+ goto out;
701+
702+ type = smp_dma_cache_data[cpu].type;
703+ start = smp_dma_cache_data[cpu].start;
704+ end = smp_dma_cache_data[cpu].end;
705+ spin_unlock_irqrestore(&smp_dma_cache_lock, flags);
706+
707+
708+ local_dma_cache_op(type, start, end);
709+
710+ spin_lock_irqsave(&smp_dma_cache_lock, flags);
711+ clear_bit(cpu, &bcache_bitmap);
712+ smp_dma_cache_data[cpu].type = 0;
713+ smp_dma_cache_data[cpu].start = 0;
714+ smp_dma_cache_data[cpu].end = 0;
715+ smp_dma_cache_data[cpu].unfinished = 0;
716+out:
717+ spin_unlock_irqrestore(&smp_dma_cache_lock, flags);
718+}
719+
720+/*
721+ * Execute the DMA cache operations on all online CPUs. This function
722+ * can be called with interrupts disabled or from interrupt context.
723+ */
724+static void __smp_dma_cache_op(int type, const void *start, const void *end)
725+{
726+ cpumask_t callmap = cpu_online_map;
727+ unsigned int cpu = get_cpu();
728+ unsigned long flags;
729+ unsigned long cpu_check;
730+ cpu_clear(cpu, callmap);
731+ cpu_check = *cpus_addr(callmap) >> 1;
732+
733+ while (test_bit(cpu, &bcache_bitmap))
734+ ipi_dma_cache_op(cpu);
735+
736+ while (test_bit(cpu_check, &bcache_bitmap))
737+ barrier();
738+
739+ spin_lock_irqsave(&smp_dma_cache_lock, flags);
740+ smp_dma_cache_data[cpu_check].type = type;
741+ smp_dma_cache_data[cpu_check].start = start;
742+ smp_dma_cache_data[cpu_check].end = end;
743+ smp_dma_cache_data[cpu_check].unfinished = 1;
744+ set_bit(cpu_check, &bcache_bitmap);
745+ send_ipi_message_cache(&callmap);
746+ spin_unlock_irqrestore(&smp_dma_cache_lock, flags);
747+
748+ /* run the local operation in parallel with the other CPUs */
749+ local_dma_cache_op(type, start, end);
750+ put_cpu();
751+}
752+
753+#define DMA_MAX_RANGE SZ_4K
754+
755+/*
756+ * Split the cache range in smaller pieces if interrupts are enabled
757+ * to reduce the latency caused by disabling the interrupts during the
758+ * broadcast.
759+ */
760+void smp_dma_cache_op(int type, const void *start, const void *end)
761+{
762+ __smp_dma_cache_op(type, start, end);
763+}
764+#endif
765--- a/arch/arm/kernel/smp_twd.c
766+++ b/arch/arm/kernel/smp_twd.c
767@@ -41,7 +41,8 @@
768 /* set up by the platform code */
769 void __iomem *twd_base;
770 
771-static unsigned long twd_timer_rate;
772+unsigned long twd_timer_rate;
773+EXPORT_SYMBOL(twd_timer_rate);
774 
775 static void twd_set_mode(enum clock_event_mode mode,
776             struct clock_event_device *clk)
777--- /dev/null
778+++ b/arch/arm/mach-cns3xxx/core.c
779@@ -0,0 +1,629 @@
780+/*
781+ * linux/arch/arm/mach-cns3xxx/cns3xxx.c
782+ *
783+ * Copyright (c) 2008 Cavium Networks
784+ * Copyright (C) 1999 - 2003 ARM Limited
785+ * Copyright (C) 2000 Deep Blue Solutions Ltd
786+ *
787+ * This file is free software; you can redistribute it and/or modify
788+ * it under the terms of the GNU General Public License, Version 2, as
789+ * published by the Free Software Foundation.
790+ *
791+ * This file is distributed in the hope that it will be useful,
792+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
793+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
794+ * NONINFRINGEMENT. See the GNU General Public License for more details.
795+ *
796+ * You should have received a copy of the GNU General Public License
797+ * along with this file; if not, write to the Free Software
798+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
799+ * visit http://www.gnu.org/licenses/.
800+ *
801+ * This file may also be available under a different license from Cavium.
802+ * Contact Cavium Networks for more information
803+ */
804+
805+#include <linux/init.h>
806+#include <linux/platform_device.h>
807+#include <linux/dma-mapping.h>
808+#include <linux/sysdev.h>
809+#include <linux/interrupt.h>
810+#include <linux/amba/bus.h>
811+#include <linux/delay.h>
812+#include <linux/clocksource.h>
813+#include <linux/clockchips.h>
814+#include <linux/io.h>
815+#include <linux/ata_platform.h>
816+#include <linux/serial.h>
817+#include <linux/tty.h>
818+#include <linux/serial_8250.h>
819+
820+#include <asm/clkdev.h>
821+#include <asm/system.h>
822+#include <mach/hardware.h>
823+#include <asm/irq.h>
824+#include <asm/leds.h>
825+#include <asm/mach-types.h>
826+#include <asm/hardware/arm_timer.h>
827+#include <asm/hardware/cache-l2cc.h>
828+#include <asm/smp_twd.h>
829+#include <asm/gpio.h>
830+
831+#include <asm/mach/arch.h>
832+#include <asm/mach/flash.h>
833+#include <asm/mach/irq.h>
834+#include <asm/mach/map.h>
835+#include <asm/mach/time.h>
836+
837+#include <asm/hardware/gic.h>
838+
839+#include <mach/platform.h>
840+#include <mach/irqs.h>
841+#include <mach/pm.h>
842+#include <asm/dma.h>
843+#include <mach/dmac.h>
844+
845+#include "core.h"
846+#include "rdma.h"
847+
848+static struct map_desc cns3xxx_io_desc[] __initdata = {
849+ {
850+ .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
851+ .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
852+ .length = SZ_4K,
853+ .type = MT_DEVICE,
854+ }, {
855+ .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
856+ .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
857+ .length = SZ_4K,
858+ .type = MT_DEVICE,
859+ }, {
860+ .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
861+ .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
862+ .length = SZ_4K,
863+ .type = MT_DEVICE,
864+ }, {
865+ .virtual = CNS3XXX_I2S_BASE_VIRT,
866+ .pfn = __phys_to_pfn(CNS3XXX_I2S_BASE),
867+ .length = SZ_4K,
868+ .type = MT_DEVICE,
869+ }, {
870+ .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
871+ .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
872+ .length = SZ_4K,
873+ .type = MT_DEVICE,
874+ }, {
875+ .virtual = CNS3XXX_TC11MP_L220_BASE_VIRT,
876+ .pfn = __phys_to_pfn(CNS3XXX_TC11MP_L220_BASE),
877+ .length = SZ_8K,
878+ .type = MT_DEVICE,
879+ }, {
880+ .virtual = CNS3XXX_SWITCH_BASE_VIRT,
881+ .pfn = __phys_to_pfn(CNS3XXX_SWITCH_BASE),
882+ .length = SZ_4K,
883+ .type = MT_DEVICE,
884+ }, {
885+ .virtual = CNS3XXX_SSP_BASE_VIRT,
886+ .pfn = __phys_to_pfn(CNS3XXX_SSP_BASE),
887+ .length = SZ_4K,
888+ .type = MT_DEVICE,
889+ }, {
890+ .virtual = CNS3XXX_DMC_BASE_VIRT,
891+ .pfn = __phys_to_pfn(CNS3XXX_DMC_BASE),
892+ .length = SZ_4K,
893+ .type = MT_DEVICE,
894+ }, {
895+ .virtual = CNS3XXX_SMC_BASE_VIRT,
896+ .pfn = __phys_to_pfn(CNS3XXX_SMC_BASE),
897+ .length = SZ_4K,
898+ .type = MT_DEVICE,
899+ }, {
900+ .virtual = CNS3XXX_GPIOA_BASE_VIRT,
901+ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
902+ .length = SZ_4K,
903+ .type = MT_DEVICE,
904+ }, {
905+ .virtual = CNS3XXX_GPIOB_BASE_VIRT,
906+ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
907+ .length = SZ_4K,
908+ .type = MT_DEVICE,
909+ }, {
910+ .virtual = CNS3XXX_RTC_BASE_VIRT,
911+ .pfn = __phys_to_pfn(CNS3XXX_RTC_BASE),
912+ .length = SZ_4K,
913+ .type = MT_DEVICE,
914+ }, {
915+ .virtual = CNS3XXX_MISC_BASE_VIRT,
916+ .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
917+ .length = SZ_4K,
918+ .type = MT_DEVICE,
919+ }, {
920+ .virtual = CNS3XXX_PM_BASE_VIRT,
921+ .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
922+ .length = SZ_4K,
923+ .type = MT_DEVICE,
924+ }, {
925+ .virtual = CNS3XXX_UART0_BASE_VIRT,
926+ .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
927+ .length = SZ_4K,
928+ .type = MT_DEVICE,
929+ }, {
930+ .virtual = CNS3XXX_UART1_BASE_VIRT,
931+ .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
932+ .length = SZ_4K,
933+ .type = MT_DEVICE,
934+ }, {
935+ .virtual = CNS3XXX_UART2_BASE_VIRT,
936+ .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
937+ .length = SZ_4K,
938+ .type = MT_DEVICE,
939+ }, {
940+ .virtual = CNS3XXX_UART3_BASE_VIRT,
941+ .pfn = __phys_to_pfn(CNS3XXX_UART3_BASE),
942+ .length = SZ_4K,
943+ .type = MT_DEVICE,
944+ }, {
945+ .virtual = CNS3XXX_DMAC_BASE_VIRT,
946+ .pfn = __phys_to_pfn(CNS3XXX_DMAC_BASE),
947+ .length = SZ_4K,
948+ .type = MT_DEVICE,
949+ }, {
950+ .virtual = CNS3XXX_CRYPTO_BASE_VIRT,
951+ .pfn = __phys_to_pfn(CNS3XXX_CRYPTO_BASE),
952+ .length = SZ_4K,
953+ .type = MT_DEVICE,
954+ }, {
955+ .virtual = CNS3XXX_HCIE_BASE_VIRT,
956+ .pfn = __phys_to_pfn(CNS3XXX_HCIE_BASE),
957+ .length = SZ_32K,
958+ .type = MT_DEVICE,
959+ }, {
960+ .virtual = CNS3XXX_RAID_BASE_VIRT,
961+ .pfn = __phys_to_pfn(CNS3XXX_RAID_BASE),
962+ .length = SZ_4K,
963+ .type = MT_DEVICE,
964+ }, {
965+ .virtual = CNS3XXX_AXI_IXC_BASE_VIRT,
966+ .pfn = __phys_to_pfn(CNS3XXX_AXI_IXC_BASE),
967+ .length = SZ_4K,
968+ .type = MT_DEVICE,
969+ }, {
970+ .virtual = CNS3XXX_CLCD_BASE_VIRT,
971+ .pfn = __phys_to_pfn( CNS3XXX_CLCD_BASE),
972+ .length = SZ_4K,
973+ .type = MT_DEVICE,
974+ }, {
975+ .virtual = CNS3XXX_USBOTG_BASE_VIRT,
976+ .pfn = __phys_to_pfn(CNS3XXX_USBOTG_BASE),
977+ .length = SZ_4K,
978+ .type = MT_DEVICE,
979+ }, {
980+ .virtual = CNS3XXX_USB_BASE_VIRT,
981+ .pfn = __phys_to_pfn(CNS3XXX_USB_BASE),
982+ .length = SZ_4K,
983+ .type = MT_DEVICE,
984+ }, {
985+ .virtual = CNS3XXX_SATA2_BASE_VIRT,
986+ .pfn = __phys_to_pfn(CNS3XXX_SATA2_BASE),
987+ .length = SZ_4K,
988+ .type = MT_DEVICE,
989+ }, {
990+ .virtual = CNS3XXX_CAMERA_BASE_VIRT,
991+ .pfn = __phys_to_pfn(CNS3XXX_CAMERA_BASE),
992+ .length = SZ_4K,
993+ .type = MT_DEVICE,
994+ }, {
995+ .virtual = CNS3XXX_I2S_TDM_BASE_VIRT,
996+ .pfn = __phys_to_pfn(CNS3XXX_I2S_TDM_BASE),
997+ .length = SZ_4K,
998+ .type = MT_DEVICE,
999+ }, {
1000+ .virtual = CNS3XXX_2DG_BASE_VIRT,
1001+ .pfn = __phys_to_pfn(CNS3XXX_2DG_BASE),
1002+ .length = SZ_4K,
1003+ .type = MT_DEVICE,
1004+ }, {
1005+ .virtual = CNS3XXX_USB_OHCI_BASE_VIRT,
1006+ .pfn = __phys_to_pfn(CNS3XXX_USB_OHCI_BASE),
1007+ .length = SZ_4K,
1008+ .type = MT_DEVICE,
1009+ }, {
1010+ .virtual = CNS3XXX_PCIE0_MEM_BASE_VIRT,
1011+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_MEM_BASE),
1012+ .length = SZ_16M, // 176MB
1013+ .type = MT_DEVICE,
1014+ }, {
1015+ .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
1016+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
1017+ .length = SZ_16M,
1018+ .type = MT_DEVICE,
1019+ }, {
1020+ .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
1021+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
1022+ .length = SZ_16M,
1023+ .type = MT_DEVICE,
1024+ }, {
1025+ .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
1026+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
1027+ .length = SZ_16M,
1028+ .type = MT_DEVICE,
1029+ }, {
1030+ .virtual = CNS3XXX_PCIE0_MSG_BASE_VIRT,
1031+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_MSG_BASE),
1032+ .length = SZ_16M,
1033+ .type = MT_DEVICE,
1034+ }, {
1035+ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT,
1036+ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE),
1037+ .length = SZ_16M,
1038+ .type = MT_DEVICE,
1039+ }, {
1040+ .virtual = CNS3XXX_PCIE1_MEM_BASE_VIRT,
1041+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_MEM_BASE),
1042+ .length = SZ_16M,
1043+ .type = MT_DEVICE,
1044+ }, {
1045+ .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
1046+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
1047+ .length = SZ_16M,
1048+ .type = MT_DEVICE,
1049+ }, {
1050+ .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
1051+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
1052+ .length = SZ_16M,
1053+ .type = MT_DEVICE,
1054+ }, {
1055+ .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
1056+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
1057+ .length = SZ_16M,
1058+ .type = MT_DEVICE,
1059+ }, {
1060+ .virtual = CNS3XXX_PCIE1_MSG_BASE_VIRT,
1061+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_MSG_BASE),
1062+ .length = SZ_4K,
1063+ .type = MT_DEVICE,
1064+ }, {
1065+ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT,
1066+ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE),
1067+ .length = SZ_16M,
1068+ .type = MT_DEVICE,
1069+ }, {
1070+ .virtual = CNS3XXX_L2C_BASE_VIRT,
1071+ .pfn = __phys_to_pfn(CNS3XXX_L2C_BASE),
1072+ .length = SZ_4K,
1073+ .type = MT_DEVICE,
1074+ }, {
1075+ .virtual = CNS3XXX_PPE_BASE_VIRT,
1076+ .pfn = __phys_to_pfn(CNS3XXX_PPE_BASE),
1077+ .length = SZ_4K,
1078+ .type = MT_DEVICE,
1079+ }, {
1080+ .virtual = CNS3XXX_EMBEDDED_SRAM_BASE_VIRT,
1081+ .pfn = __phys_to_pfn(CNS3XXX_EMBEDDED_SRAM_BASE),
1082+ .length = SZ_8K,
1083+ .type = MT_DEVICE,
1084+ },
1085+};
1086+
1087+void __init cns3xxx_map_io(void)
1088+{
1089+ iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
1090+}
1091+
1092+/* used by entry-macro.S */
1093+void __iomem *gic_cpu_base_addr;
1094+
1095+void __init cns3xxx_init_irq(void)
1096+{
1097+ /* ARM11 MPCore test chip GIC */
1098+ gic_cpu_base_addr = (void __iomem *) CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT;
1099+ gic_dist_init(0, (void __iomem *) CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, 29);
1100+ gic_cpu_init(0, gic_cpu_base_addr);
1101+ set_interrupt_pri(1, 0); // Set cache broadcast priority to the highest priority
1102+}
1103+
1104+int gpio_to_irq(int gpio)
1105+{
1106+ if (gpio > 63)
1107+ return -EINVAL;
1108+
1109+ if (gpio < 32)
1110+ return IRQ_CNS3XXX_GPIOA;
1111+ else
1112+ return IRQ_CNS3XXX_GPIOB;
1113+}
1114+
1115+int irq2gpio(int irq)
1116+{
1117+ if (irq == IRQ_CNS3XXX_GPIOA)
1118+ return 0;
1119+ else if (irq == IRQ_CNS3XXX_GPIOB)
1120+ return 32;
1121+ else
1122+ return -EINVAL;
1123+}
1124+
1125+static inline void gpio_line_config(u8 line, u32 direction)
1126+{
1127+ u32 reg;
1128+ if (direction) {
1129+ if (line < 32) {
1130+ reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
1131+ reg |= (1 << line);
1132+ __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
1133+ } else {
1134+ reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
1135+ reg |= (1 << (line - 32));
1136+ __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
1137+ }
1138+ } else {
1139+ if (line < 32) {
1140+ reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
1141+ reg &= ~(1 << line);
1142+ __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
1143+ } else {
1144+ reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
1145+ reg &= ~(1 << (line - 32));
1146+ __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
1147+ }
1148+ }
1149+}
1150+
1151+static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1152+{
1153+ gpio_line_config(gpio, CNS3XXX_GPIO_IN);
1154+ return 0;
1155+}
1156+
1157+static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
1158+{
1159+ gpio_line_set(gpio, level);
1160+ gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
1161+ return 0;
1162+}
1163+
1164+static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1165+{
1166+ return gpio_get_value(gpio);
1167+}
1168+
1169+static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1170+{
1171+ gpio_set_value(gpio, value);
1172+}
1173+
1174+static struct gpio_chip cns3xxx_gpio_chip = {
1175+ .label = "CNS3XXX_GPIO_CHIP",
1176+ .direction_input = cns3xxx_gpio_direction_input,
1177+ .direction_output = cns3xxx_gpio_direction_output,
1178+ .get = cns3xxx_gpio_get_value,
1179+ .set = cns3xxx_gpio_set_value,
1180+ .base = 0,
1181+ .ngpio = 64,
1182+};
1183+
1184+/* Watchdog */
1185+static struct resource cns3xxx_watchdog_resources[] = {
1186+ {
1187+ .start = CNS3XXX_TC11MP_TWD_BASE,
1188+ .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
1189+ .flags = IORESOURCE_MEM,
1190+ },{
1191+ .start = IRQ_LOCALWDOG,
1192+ .end = IRQ_LOCALWDOG,
1193+ .flags = IORESOURCE_IRQ,
1194+ }
1195+};
1196+
1197+static struct platform_device cns3xxx_watchdog_device = {
1198+ .name = "cns3xxx-wdt",
1199+ .id = -1,
1200+ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources),
1201+ .resource = cns3xxx_watchdog_resources,
1202+};
1203+
1204+static struct resource cns3xxx_gpio_resources[] = {
1205+ {
1206+ .name = "gpio",
1207+ .start = 0xFFFFFFFF,
1208+ .end = 0xFFFFFFFF,
1209+ .flags = 0,
1210+ },
1211+};
1212+
1213+static struct platform_device cns3xxx_gpio = {
1214+ .name = "GPIODEV",
1215+ .id = -1,
1216+ .num_resources = ARRAY_SIZE(cns3xxx_gpio_resources),
1217+ .resource = cns3xxx_gpio_resources,
1218+};
1219+
1220+void __init cns3xxx_sys_init(void)
1221+{
1222+ l2cc_init((void __iomem *) CNS3XXX_L2C_BASE_VIRT);
1223+
1224+ dmac_init();
1225+ cns_rdma_init();
1226+
1227+ platform_device_register(&cns3xxx_gpio);
1228+ platform_device_register(&cns3xxx_watchdog_device);
1229+ gpiochip_add(&cns3xxx_gpio_chip);
1230+}
1231+
1232+void __iomem *timer1_va_base;
1233+
1234+static void timer_set_mode(enum clock_event_mode mode,
1235+ struct clock_event_device *clk)
1236+{
1237+ unsigned long ctrl = readl(timer1_va_base + TIMER1_2_CONTROL_OFFSET);
1238+ int reload;
1239+ int pclk = (cns3xxx_cpu_clock() >> 3);
1240+
1241+ switch(mode) {
1242+ case CLOCK_EVT_MODE_PERIODIC:
1243+ /* pclk is cpu clock/8 */
1244+ reload=pclk*1000000/HZ;
1245+ writel(reload, timer1_va_base + TIMER1_AUTO_RELOAD_OFFSET);
1246+ ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
1247+ break;
1248+ case CLOCK_EVT_MODE_ONESHOT:
1249+ /* period set, and timer enabled in 'next_event' hook */
1250+ writel(0, timer1_va_base + TIMER1_AUTO_RELOAD_OFFSET);
1251+ ctrl |= (1 << 2) | (1 << 9);
1252+ break;
1253+ case CLOCK_EVT_MODE_UNUSED:
1254+ case CLOCK_EVT_MODE_SHUTDOWN:
1255+ default:
1256+ ctrl = 0;
1257+ }
1258+
1259+ writel(ctrl, timer1_va_base + TIMER1_2_CONTROL_OFFSET);
1260+}
1261+
1262+static int timer_set_next_event(unsigned long evt,
1263+ struct clock_event_device *unused)
1264+{
1265+ unsigned long ctrl = readl(timer1_va_base + TIMER1_2_CONTROL_OFFSET);
1266+
1267+ writel(evt, timer1_va_base + TIMER1_COUNTER_OFFSET);
1268+ writel(ctrl | (1 << 0), timer1_va_base + TIMER1_2_CONTROL_OFFSET);
1269+
1270+ return 0;
1271+}
1272+
1273+static struct clock_event_device timer1_clockevent = {
1274+ .name = "timer1",
1275+ .shift = 32,
1276+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
1277+ .set_mode = timer_set_mode,
1278+ .set_next_event = timer_set_next_event,
1279+ .rating = 300,
1280+ .cpumask = cpu_all_mask,
1281+};
1282+
1283+static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
1284+{
1285+ timer1_clockevent.irq = timer_irq;
1286+ timer1_clockevent.mult =
1287+ div_sc( (cns3xxx_cpu_clock() >> 3)*1000000, NSEC_PER_SEC, timer1_clockevent.shift);
1288+ timer1_clockevent.max_delta_ns =
1289+ clockevent_delta2ns(0xffffffff, &timer1_clockevent);
1290+ timer1_clockevent.min_delta_ns =
1291+ clockevent_delta2ns(0xf, &timer1_clockevent);
1292+
1293+ clockevents_register_device(&timer1_clockevent);
1294+}
1295+
1296+/*
1297+ * IRQ handler for the timer
1298+ */
1299+static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
1300+{
1301+ u32 val;
1302+ struct clock_event_device *evt = &timer1_clockevent;
1303+
1304+ /* Clear the interrupt */
1305+ val = readl(timer1_va_base + TIMER1_2_INTERRUPT_STATUS_OFFSET);
1306+ writel(val & ~(1 << 2), timer1_va_base + TIMER1_2_INTERRUPT_STATUS_OFFSET);
1307+
1308+ evt->event_handler(evt);
1309+
1310+ return IRQ_HANDLED;
1311+}
1312+
1313+static struct irqaction cns3xxx_timer_irq = {
1314+ .name = "timer",
1315+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
1316+ .handler = cns3xxx_timer_interrupt,
1317+};
1318+
1319+static cycle_t cns3xxx_get_cycles(struct clocksource *cs)
1320+{
1321+ u64 val;
1322+
1323+ val = readl(timer1_va_base + TIMER_FREERUN_CONTROL_OFFSET);
1324+ val &= 0xffff;
1325+
1326+ return ((val << 32) | readl(timer1_va_base + TIMER_FREERUN_OFFSET));
1327+}
1328+
1329+static struct clocksource clocksource_cns3xxx = {
1330+ .name = "freerun",
1331+ .rating = 200,
1332+ .read = cns3xxx_get_cycles,
1333+ .mask = CLOCKSOURCE_MASK(48),
1334+ .shift = 16,
1335+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
1336+};
1337+
1338+
1339+static void __init cns3xxx_clocksource_init(void)
1340+{
1341+ /* Reset the FreeRunning counter */
1342+ writel((1 << 16), timer1_va_base + TIMER_FREERUN_CONTROL_OFFSET);
1343+
1344+ clocksource_cns3xxx.mult =
1345+ clocksource_khz2mult(100, clocksource_cns3xxx.shift);
1346+ clocksource_register(&clocksource_cns3xxx);
1347+}
1348+
1349+/*
1350+ * Set up the clock source and clock events devices
1351+ */
1352+void __init __cns3xxx_timer_init(unsigned int timer_irq)
1353+{
1354+ unsigned long val, irq_mask;
1355+
1356+ /*
1357+ * Initialise to a known state (all timers off)
1358+ */
1359+ writel(0, timer1_va_base + TIMER1_2_CONTROL_OFFSET); /* disable timer1 and timer2 */
1360+ writel(0, timer1_va_base + TIMER_FREERUN_CONTROL_OFFSET); /* stop free running timer3 */
1361+ writel(0, timer1_va_base + TIMER1_MATCH_V1_OFFSET);
1362+ writel(0, timer1_va_base + TIMER1_MATCH_V2_OFFSET);
1363+
1364+ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ;
1365+ writel(val, timer1_va_base + TIMER1_COUNTER_OFFSET);
1366+
1367+ /* mask irq, non-mask timer1 overflow */
1368+ irq_mask = readl(timer1_va_base + TIMER1_2_INTERRUPT_MASK_OFFSET);
1369+ irq_mask &= ~(1 << 2);
1370+ irq_mask |= 0x03;
1371+ writel(irq_mask, timer1_va_base + TIMER1_2_INTERRUPT_MASK_OFFSET);
1372+ /* down counter */
1373+ val = readl(timer1_va_base + TIMER1_2_CONTROL_OFFSET);
1374+ val |= (1 << 9);
1375+ writel(val, timer1_va_base + TIMER1_2_CONTROL_OFFSET);
1376+
1377+ /*
1378+ * Make irqs happen for the system timer
1379+ */
1380+ setup_irq(timer_irq, &cns3xxx_timer_irq);
1381+
1382+ cns3xxx_clocksource_init();
1383+ cns3xxx_clockevents_init(timer_irq);
1384+}
1385+
1386+void __init cns3xxx_timer_init(void)
1387+{
1388+ timer1_va_base = (void __iomem *) CNS3XXX_TIMER1_2_3_BASE_VIRT;
1389+ twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
1390+ __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
1391+}
1392+
1393+struct sys_timer cns3xxx_timer = {
1394+ .init = cns3xxx_timer_init,
1395+};
1396+
1397+
1398+void cns3xxx_power_off(void)
1399+{
1400+ __u32 clkctrl;
1401+
1402+ printk(KERN_INFO "powering system down...\n");
1403+
1404+ clkctrl = readl(CNS3XXX_PM_BASE_VIRT + PM_SYS_CLK_CTRL_OFFSET);
1405+ clkctrl &= 0xfffff1ff;
1406+ clkctrl |= (0x5 << 9); /* Hibernate */
1407+ writel(clkctrl, CNS3XXX_PM_BASE_VIRT + PM_SYS_CLK_CTRL_OFFSET);
1408+}
1409--- /dev/null
1410+++ b/arch/arm/mach-cns3xxx/core.h
1411@@ -0,0 +1,34 @@
1412+/*
1413+ * linux/arch/arm/mach-cns3xxx/core.h
1414+ *
1415+ * Copyright (c) 2008 Cavium Networks
1416+ * Copyright (C) 2004 ARM Limited
1417+ * Copyright (C) 2000 Deep Blue Solutions Ltd
1418+ *
1419+ * This file is free software; you can redistribute it and/or modify
1420+ * it under the terms of the GNU General Public License, Version 2, as
1421+ * published by the Free Software Foundation.
1422+ *
1423+ * This file is distributed in the hope that it will be useful,
1424+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
1425+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1426+ * NONINFRINGEMENT. See the GNU General Public License for more details.
1427+ *
1428+ * You should have received a copy of the GNU General Public License
1429+ * along with this file; if not, write to the Free Software
1430+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
1431+ * visit http://www.gnu.org/licenses/.
1432+ *
1433+ * This file may also be available under a different license from Cavium.
1434+ * Contact Cavium Networks for more information
1435+ */
1436+
1437+#ifndef __ASM_ARCH_CNS3XXX_H
1438+#define __ASM_ARCH_CNS3XXX_H
1439+
1440+void __init cns3xxx_map_io(void);
1441+void cns3xxx_power_off(void);
1442+void __init cns3xxx_init_irq(void);
1443+
1444+extern struct sys_timer cns3xxx_timer;
1445+#endif
1446--- /dev/null
1447+++ b/arch/arm/mach-cns3xxx/dmac.c
1448@@ -0,0 +1,1464 @@
1449+/*******************************************************************************
1450+ *
1451+ * Copyright (c) 2008 Cavium Networks
1452+ *
1453+ * This file is free software; you can redistribute it and/or modify
1454+ * it under the terms of the GNU General Public License, Version 2, as
1455+ * published by the Free Software Foundation.
1456+ *
1457+ * This file is distributed in the hope that it will be useful,
1458+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
1459+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1460+ * NONINFRINGEMENT. See the GNU General Public License for more details.
1461+ *
1462+ * You should have received a copy of the GNU General Public License
1463+ * along with this file; if not, write to the Free Software
1464+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
1465+ * visit http://www.gnu.org/licenses/.
1466+ *
1467+ * This file may also be available under a different license from Cavium.
1468+ * Contact Cavium Networks for more information
1469+ *
1470+ ******************************************************************************/
1471+
1472+#include <linux/module.h>
1473+#include <linux/kernel.h>
1474+#include <linux/types.h>
1475+#include <linux/string.h>
1476+#include <linux/mm.h>
1477+#include <linux/spinlock.h>
1478+#include <linux/interrupt.h>
1479+#include <linux/irq.h>
1480+#include <linux/dma-mapping.h>
1481+#include <asm/memory.h>
1482+#include <asm/dma.h>
1483+#include <mach/hardware.h>
1484+#include <mach/pm.h>
1485+
1486+
1487+#include <mach/dmac.h>
1488+
1489+//#define DEBUG_GDMA
1490+
1491+#define DMAC_MEM_MAP_VALUE(reg_offset) (*((uint32_t volatile *)(CNS3XXX_DMAC_BASE_VIRT + reg_offset)))
1492+
1493+#define DMAC_INTEN DMAC_MEM_MAP_VALUE(0x020)
1494+#define DMAC_INTSTATUS DMAC_MEM_MAP_VALUE(0x028)
1495+#define DMAC_INTCLR DMAC_MEM_MAP_VALUE(0x02C)
1496+
1497+/* DMAC Debug registers */
1498+#define DMAC_DBGSTATUS DMAC_MEM_MAP_VALUE(0xD00) /* Debug Status Register */
1499+#define DMAC_DBGCMD DMAC_MEM_MAP_VALUE(0xD04) /* Debug Command Register */
1500+#define DMAC_DBGINST0 DMAC_MEM_MAP_VALUE(0xD08) /* Debug Instrucion-0 Register */
1501+#define DMAC_DBGINST1 DMAC_MEM_MAP_VALUE(0xD0C) /* Debug Instrucion-1 Register */
1502+
1503+#define CHANNEL_AND_MANAGER 0x1ff
1504+#define CHANNEL_ONLY 0xff
1505+#define MANAGER_ONLY 0x100
1506+
1507+#define MAX_MICROCODE_SIZE 2048
1508+
1509+#if 0
1510+#define ERROR_INTR 45
1511+#define DMAC_IRQNO_BASE 46
1512+#else
1513+#define ERROR_INTR 68
1514+#define DMAC_IRQNO_BASE 69
1515+#endif
1516+
1517+#define MAX_INTR_EVENTS 32
1518+
1519+#define MIN_EVENT_NUM 8 //2
1520+
1521+/* Debug Status Register */
1522+#define DMAC_DBG_BUSY_BIT (1<<0)
1523+#define DMAC_DBG_INSTR_0_SHIFT 16
1524+#define DMAC_DBG_INSTR_2_SHIFT 0
1525+#define DMAC_DBG_THREAD_BIT (1<<0)
1526+#define DMAC_DBG_CH_NUM_SHIFT 8
1527+#define DMAC_DBG_CH_NUM_BIT_MASK 0x7
1528+#define DMAC_CHMGR 8
1529+
1530+spinlock_t dma_mgr_lock;
1531+
1532+typedef enum {
1533+// DMAC_INSTR_DMAADDH = 0, /* Add Halfword */ /*** No implement ***/
1534+ DMAC_INSTR_DMAEND = 0, /* End */
1535+ DMAC_INSTR_DMAFLUSHP, /* Flash and notify Peripheral */
1536+ DMAC_INSTR_DMAGO, /* Go */
1537+ DMAC_INSTR_DMALD, /* Load */
1538+ DMAC_INSTR_DMALDP, /* Load aPeripheral */
1539+ DMAC_INSTR_DMALP, /* Loop */
1540+ DMAC_INSTR_DMALPEND, /* Loop End */
1541+// DMAC_INSTR_DMALPFE, /* Loop Forever */
1542+ DMAC_INSTR_DMAKILL, /* kill */
1543+ DMAC_INSTR_DMAMOV, /* Move */
1544+ DMAC_INSTR_DMANOP, /* No operation */
1545+// DMAC_INSTR_DMARMB, /* Read Memory Barrier */
1546+ DMAC_INSTR_DMASEV, /* Send Event */
1547+ DMAC_INSTR_DMAST, /* Store */
1548+ DMAC_INSTR_DMASTP, /* Store and notify Peripheral */
1549+ DMAC_INSTR_DMASTZ, /* Store Zero */
1550+ DMAC_INSTR_DMAWFE, /* Wait For Event */
1551+ DMAC_INSTR_DMAWFP, /* Wait For Peripheral */
1552+ DMAC_INSTR_DMAWMB /* Wait For Barrier */
1553+} dmac_instr_t;
1554+
1555+typedef struct {
1556+ const char *enc_buf;
1557+ int enc_buf_len;
1558+ int chan_or_mgr; /* 0xff for DMA manager and DMA channel,
1559+ 0x7f for DMA channel,
1560+ 0x80 for DMA manager */
1561+} dmac_instr_encode_t;
1562+
1563+typedef struct {
1564+ uint32_t sa:1; /* source address increment: 0 - FIXED / 1 - INCR */
1565+ uint32_t ss:3; /* source burst size in bytes: mapping value TBD with designer */
1566+ uint32_t sb:4; /* source burst length */
1567+ uint32_t sp:3; /* source protection */
1568+ uint32_t sc:3; /* source cache */
1569+ uint32_t da:1; /* destination address increment: 0 - FIXED / 1 - INCR */
1570+ uint32_t ds:3; /* destination burst size in bytes: mapping value TBD with designer */
1571+ uint32_t db:4; /* destination burst length */
1572+ uint32_t dp:3; /* destination protection */
1573+ uint32_t dc:3; /* destination cache */
1574+ uint32_t es:3; /* endian swap size, in bits */
1575+ uint32_t padding:1;
1576+} dmac_ch_ctrl_t;
1577+
1578+typedef struct {
1579+ union {
1580+ dmac_ch_ctrl_t ccr;
1581+ uint32_t val;
1582+ } i;
1583+} dmac_cmd_imm32_t;
1584+
1585+typedef struct {
1586+ uint16_t bs:1; /* burst/single bit */
1587+ uint16_t x:1; /* x bit */
1588+ uint16_t ns:1; /* not secure bit */
1589+ uint16_t lc:1; /* loop counter bit */
1590+ uint16_t p:1; /* p bit */
1591+ uint16_t nf:1; /* no-finite bit */
1592+ uint16_t i:1; /* invalid bit */
1593+ uint16_t padding:9;
1594+} dmac_cmd_bits_t;
1595+
1596+typedef struct {
1597+ uint8_t periph; /* peripheral ID */
1598+ uint8_t cn; /* Channel Number */
1599+ uint8_t iter; /* iteration count */
1600+ uint8_t backwards_jump; /* backwards jump length */
1601+ uint8_t rd; /* destination register, <SAR=b000, CCR=b001, DAR=b010> */
1602+ uint8_t event_num; /* event number */
1603+
1604+ union {
1605+ dmac_cmd_bits_t b;
1606+ uint16_t val;
1607+ } bits;
1608+
1609+ dmac_cmd_imm32_t imm32; /* immediate 32bit value */
1610+} dmac_instr_param_t;
1611+
1612+typedef struct {
1613+ int in_use; /* Channel in use or not */
1614+ int channel; /* Channel number */
1615+ int microcode_size; /* Microcode size */
1616+ uint8_t *microcode; /* TODO */
1617+ dma_addr_t microcode_dma;
1618+ int (*intr_handler) (void *);
1619+ void *handler_args;
1620+ int notifications_used; /* 32 bits for every interrupt/event */
1621+} dmac_channel_t;
1622+
1623+/* TODO: Not protected as of now */
1624+dmac_channel_t *dmac_channels[MAX_DMA_CHANNELS];
1625+
1626+int dmac_events[MAX_INTR_EVENTS];
1627+
1628+static int dmac_create_instr(int chan, dmac_instr_t instr,
1629+ dmac_instr_param_t * param);
1630+static int dmac_exec_ucode(int ucode_channel, int ch);
1631+void pl330_dump_regs(void);
1632+
1633+/******************************************************************************
1634+ *
1635+ * Instruction: DMAEND
1636+ * Description:
1637+ * | 7 6 5 4 | 3 2 1 0 |
1638+ * 0 0 0 0 0 0 0 0
1639+ * Example:
1640+ * DMAEND
1641+ * 00
1642+ ******************************************************************************/
1643+const char dmac_code_DMAEND[] = { 0x00 };
1644+
1645+int DMAC_DMAEND(int ch_num)
1646+{
1647+ dmac_instr_param_t param;
1648+ int instr_len;
1649+ memset(&param, 0, sizeof(dmac_instr_param_t));
1650+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAEND, &param);
1651+ if (instr_len < 0) {
1652+ printk("dmac_create_instr failed \n");
1653+ return -1;
1654+ }
1655+
1656+ return 0;
1657+}
1658+
1659+EXPORT_SYMBOL(DMAC_DMAEND);
1660+
1661+/******************************************************************************
1662+ *
1663+ * Instruction: DMAFLUSHP
1664+ * Description:
1665+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
1666+ * <periph[4:0] > 0 0 0 0 0 1 1 0 1 0 1
1667+ * Example:
1668+ * DMAFLUSHP P0
1669+ * 35 00
1670+ ******************************************************************************/
1671+const char dmac_code_DMAFLUSHP[] = { 0x35, 0x00 };
1672+
1673+int DMAC_DMAFLUSHP(int ch_num, int periph)
1674+{
1675+ dmac_instr_param_t param;
1676+ int instr_len;
1677+ memset(&param, 0, sizeof(dmac_instr_param_t));
1678+ param.periph = periph;
1679+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAFLUSHP, &param);
1680+ if (instr_len < 0) {
1681+ printk("dmac_create_instr failed \n");
1682+ return -1;
1683+ }
1684+
1685+ return 0;
1686+}
1687+
1688+EXPORT_SYMBOL(DMAC_DMAFLUSHP);
1689+
1690+/******************************************************************************
1691+ *
1692+ * Instruction: DMAGO
1693+ * Description:
1694+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
1695+ * 0 0 0 0 0 <cn[2:0]> 1 0 1 0 0 0 ns 0
1696+ *
1697+ * | 47 16 |
1698+ * < imm[31:0] >
1699+ * Example:
1700+ * DMAGO C0, 0x40000000
1701+ * A0 00 00 00 00 40
1702+ ******************************************************************************/
1703+const char dmac_code_DMAGO[] = { 0xA0, 0x00, 0x00, 0x00, 0x00, 0x40 };
1704+
1705+int DMAC_DMAGO(int ch_num)
1706+{
1707+ dmac_instr_param_t param;
1708+ int instr_len;
1709+ dmac_channel_t *dma_ch = dmac_channels[ch_num];
1710+
1711+ if(!dma_ch->in_use) {
1712+ printk("DMAC_DMAGO an unused channel\n");
1713+ return -1;
1714+ }
1715+
1716+ memset(&param, 0, sizeof(dmac_instr_param_t));
1717+ param.bits.b.ns = 1;
1718+ param.cn = ch_num;
1719+ param.imm32.i.val = dma_ch->microcode_dma;
1720+#ifdef DEBUG_GDMA
1721+ printk("%s:%d: microcode Physical Address *(%x)==[%x]\n", __FUNCTION__,
1722+ __LINE__, param.imm32.i.val,
1723+ *((uint32_t *) phys_to_virt(dma_ch->microcode_dma)));
1724+#endif
1725+ instr_len = dmac_create_instr(DMAC_CHMGR, DMAC_INSTR_DMAGO, &param);
1726+ if (instr_len < 0) {
1727+ printk("dmac_create_instr failed \n");
1728+ return -1;
1729+ }
1730+
1731+ dmac_exec_ucode(DMAC_CHMGR, DMAC_CHMGR); // DMAC_CHMGR);
1732+ if (dmac_channels[DMAC_CHMGR])
1733+ dmac_channels[DMAC_CHMGR]->microcode_size = 0;
1734+ else
1735+ printk("BUG HERE !! DEBUG .. \n");
1736+
1737+ return 0;
1738+}
1739+
1740+EXPORT_SYMBOL(DMAC_DMAGO);
1741+
1742+/******************************************************************************
1743+ *
1744+ * Instruction: DMALD
1745+ * Description:
1746+ * | 7 6 5 4 | 3 2 1 0 |
1747+ * 0 0 0 0 0 1 bs x
1748+ * Example:
1749+ * DMALD
1750+ * 04
1751+ ******************************************************************************/
1752+const char dmac_code_DMALD[] = { 0x04 };
1753+
1754+int DMAC_DMALD(int ch_num)
1755+{
1756+ dmac_instr_param_t param;
1757+ int instr_len;
1758+ memset(&param, 0, sizeof(dmac_instr_param_t));
1759+ /* param.bits.b.x = param.bits.b.bs = 0; */
1760+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMALD, &param);
1761+ if (instr_len < 0) {
1762+ printk("dmac_create_instr failed \n");
1763+ return -1;
1764+ }
1765+
1766+ return 0;
1767+}
1768+
1769+EXPORT_SYMBOL(DMAC_DMALD);
1770+
1771+int DMAC_DMALDB(int ch_num)
1772+{
1773+ dmac_instr_param_t param;
1774+ int instr_len;
1775+ memset(&param, 0, sizeof(dmac_instr_param_t));
1776+ /* param.bits.b.x = param.bits.b.bs = 0; */
1777+ param.bits.b.x = 1;
1778+ param.bits.b.bs = 1;
1779+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMALD, &param);
1780+ if (instr_len < 0) {
1781+ printk("dmac_create_instr failed \n");
1782+ return -1;
1783+ }
1784+
1785+ return 0;
1786+}
1787+
1788+EXPORT_SYMBOL(DMAC_DMALDB);
1789+
1790+int DMAC_DMALDS(int ch_num)
1791+{
1792+ dmac_instr_param_t param;
1793+ int instr_len;
1794+ memset(&param, 0, sizeof(dmac_instr_param_t));
1795+ /* param.bits.b.x = param.bits.b.bs = 0; */
1796+ param.bits.b.x = 1;
1797+ param.bits.b.bs = 0;
1798+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMALD, &param);
1799+ if (instr_len < 0) {
1800+ printk("dmac_create_instr failed \n");
1801+ return -1;
1802+ }
1803+
1804+ return 0;
1805+}
1806+
1807+EXPORT_SYMBOL(DMAC_DMALDS);
1808+
1809+/******************************************************************************
1810+ *
1811+ * Instruction: DMALP
1812+ * Description:
1813+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
1814+ * < iter[7:0] > 0 0 1 0 0 0 lc 0
1815+ * Example:
1816+ * DMALP 8
1817+ * 20 07
1818+ ******************************************************************************/
1819+const char dmac_code_DMALP[] = { 0x20, 0x07 };
1820+
1821+int DMAC_DMALP(int ch_num, int loop_reg_idx, int iter)
1822+{
1823+ dmac_instr_param_t param;
1824+ int instr_len;
1825+ memset(&param, 0, sizeof(dmac_instr_param_t));
1826+ param.bits.b.lc = loop_reg_idx;
1827+ param.iter = (uint8_t) (iter - 1);
1828+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMALP, &param);
1829+ if (instr_len < 0) {
1830+ printk("dmac_create_instr failed \n");
1831+ return -1;
1832+ }
1833+ return 0;
1834+}
1835+
1836+EXPORT_SYMBOL(DMAC_DMALP);
1837+
1838+/******************************************************************************
1839+ *
1840+ * Instruction: DMALPEND
1841+ * Description:
1842+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
1843+ * < backwards_jump[7:0] > 0 0 1 nf 1 lc bs x
1844+ * Example:
1845+ * DMALPEND
1846+ * 38 04
1847+ ******************************************************************************/
1848+const char dmac_code_DMALPEND[] = { 0x38, 0x04 };
1849+
1850+int DMAC_DMALPEND(int ch_num, int loop_reg_idx, int jump, int lpfe)
1851+{
1852+ dmac_instr_param_t param;
1853+ int instr_len;
1854+ memset(&param, 0, sizeof(dmac_instr_param_t));
1855+ /* param.bits.b.x = param.bits.b.bs = 0; */
1856+ param.bits.b.lc = loop_reg_idx;
1857+ param.bits.b.nf = lpfe;
1858+ param.backwards_jump = jump;
1859+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMALPEND, &param);
1860+ if (instr_len < 0) {
1861+ printk("dmac_create_instr failed \n");
1862+ return -1;
1863+ }
1864+ return 0;
1865+}
1866+
1867+EXPORT_SYMBOL(DMAC_DMALPEND);
1868+
1869+/******************************************************************************
1870+ *
1871+ * Instruction: DMAMOV
1872+ * Description:
1873+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
1874+ * 0 0 0 0 0 <rd[2:0]> 1 0 1 1 1 1 0 0
1875+ *
1876+ * | 47 16 |
1877+ * < imm[31:0] >
1878+ *
1879+ * # CCR Description
1880+ * # [30:28] Endian swap size
1881+ * # [27:25] AWCACHE[3,1:0] value
1882+ * # [24:22] AWPROT value
1883+ * # [21:18] AWLEN value
1884+ * # [17:15] AWSIZE value
1885+ * # [14] AWBURST[0] value
1886+ * 0 - FIXED / 1 - INCR
1887+ * # [13:11] ARCACHE[2:0] value
1888+ * # [10:8] ARPROT value
1889+ * # [7:4] ARLEN value
1890+ * # [3:1] ARSIZE value
1891+ * # [0] ARBURST[0] value
1892+ * 0 - FIXED / 1 - INCR
1893+ * Example:
1894+ * DMAMOV CCR, SB1 SS32 DB1 DS32
1895+ * BC 01 05 40 01 00
1896+ ******************************************************************************/
1897+const char dmac_code_DMAMOV[] = { 0xBC, 0x01, 0x05, 0x40, 0x01, 0x00 };
1898+
1899+/* ccr_sar_dar: 0 for SAR, 1, for CCR, 2 for DAR */
1900+//typedef enum { SAR = 0, CCR = 1, DAR = 2} dmamov_arg_t;
1901+int DMAC_DMAMOV(int ch_num, dmamov_arg_t ccr_sar_dar, uint32_t value)
1902+{
1903+ dmac_instr_param_t param;
1904+ int instr_len;
1905+ memset(&param, 0, sizeof(dmac_instr_param_t));
1906+ param.rd = ccr_sar_dar;
1907+ param.imm32.i.val = value;
1908+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAMOV, &param);
1909+ if (instr_len < 0) {
1910+ printk("dmac_create_instr failed \n");
1911+ return -1;
1912+ }
1913+ return 0;
1914+}
1915+
1916+EXPORT_SYMBOL(DMAC_DMAMOV);
1917+
1918+/******************************************************************************
1919+ *
1920+ * Instruction: DMAST
1921+ * Description:
1922+ * | 7 6 5 4 | 3 2 1 0 |
1923+ * 0 0 0 0 1 0 bs x
1924+ * Example:
1925+ * DMAST
1926+ * 08
1927+ ******************************************************************************/
1928+const char dmac_code_DMAST[] = { 0x08 };
1929+
1930+int DMAC_DMAST(int ch_num)
1931+{
1932+ dmac_instr_param_t param;
1933+ int instr_len;
1934+ memset(&param, 0, sizeof(dmac_instr_param_t));
1935+ /* param.bits.b.x = param.bits.b.bs = 0; */
1936+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAST, &param);
1937+ if (instr_len < 0) {
1938+ printk("dmac_create_instr failed \n");
1939+ return -1;
1940+ }
1941+
1942+ return 0;
1943+}
1944+
1945+EXPORT_SYMBOL(DMAC_DMAST);
1946+
1947+const char dmac_code_DMAWMB[] = { 0x13 };
1948+
1949+int DMAC_DMAWMB(int ch_num)
1950+{
1951+ dmac_instr_param_t param;
1952+ int instr_len;
1953+ memset(&param, 0, sizeof(dmac_instr_param_t));
1954+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAWMB, &param);
1955+ if (instr_len < 0) {
1956+ printk("dmac_create_instr failed\n");
1957+ return -1;
1958+ }
1959+ return 0;
1960+}
1961+
1962+EXPORT_SYMBOL(DMAC_DMAWMB);
1963+
1964+const char dmac_code_DMANOP[] = { 0x18 };
1965+
1966+int DMAC_DMANOP(int ch_num)
1967+{
1968+ dmac_instr_param_t param;
1969+ int instr_len;
1970+ memset(&param, 0, sizeof(dmac_instr_param_t));
1971+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMANOP, &param);
1972+ if (instr_len < 0) {
1973+ printk("dmac_create_instr failed\n");
1974+ return -1;
1975+ }
1976+ return 0;
1977+}
1978+
1979+EXPORT_SYMBOL(DMAC_DMANOP);
1980+
1981+int DMAC_DMASTB(int ch_num)
1982+{
1983+ dmac_instr_param_t param;
1984+ int instr_len;
1985+ memset(&param, 0, sizeof(dmac_instr_param_t));
1986+ param.bits.b.x = 1;
1987+ param.bits.b.bs = 1;
1988+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAST, &param);
1989+ if (instr_len < 0) {
1990+ printk("dmac_create_instr failed \n");
1991+ return -1;
1992+ }
1993+
1994+ return 0;
1995+}
1996+
1997+EXPORT_SYMBOL(DMAC_DMASTB);
1998+
1999+int DMAC_DMASTS(int ch_num)
2000+{
2001+ dmac_instr_param_t param;
2002+ int instr_len;
2003+ memset(&param, 0, sizeof(dmac_instr_param_t));
2004+ param.bits.b.x = 1;
2005+ param.bits.b.bs = 0;
2006+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAST, &param);
2007+ if (instr_len < 0) {
2008+ printk("dmac_create_instr failed \n");
2009+ return -1;
2010+ }
2011+
2012+ return 0;
2013+}
2014+
2015+EXPORT_SYMBOL(DMAC_DMASTS);
2016+
2017+/******************************************************************************
2018+ *
2019+ * Instruction: DMASTZ
2020+ * Description:
2021+ * | 7 6 5 4 | 3 2 1 0 |
2022+ * 0 0 0 0 1 1 0 0
2023+ * Example:
2024+ * DMASTZ
2025+ * 08
2026+ ******************************************************************************/
2027+const char dmac_code_DMASTZ[] = { 0x0C };
2028+
2029+/******************************************************************************
2030+ *
2031+ * Instruction: DMAWFE
2032+ * Description:
2033+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
2034+ * <event_num[4:0]> 0 i 0 0 0 1 1 0 1 1 0
2035+ * Example:
2036+ * DMAWFE E0
2037+ * 36 00
2038+ ******************************************************************************/
2039+const char dmac_code_DMAWFE[] = { 0x36, 0x00 };
2040+
2041+int DMAC_WFE(int chan, int event_num)
2042+{
2043+ dmac_instr_param_t param;
2044+ int instr_len;
2045+ memset(&param, 0, sizeof(dmac_instr_param_t));
2046+ /* param.bits.b.x = param.bits.b.bs = 0; */
2047+//#warning "to set bits"
2048+ param.event_num = event_num;
2049+ instr_len = dmac_create_instr(chan, DMAC_INSTR_DMAWFE, &param);
2050+ if (instr_len < 0) {
2051+ printk("dmac_create_instr failed \n");
2052+ return -1;
2053+ }
2054+
2055+ return 0;
2056+}
2057+
2058+EXPORT_SYMBOL(DMAC_WFE);
2059+
2060+/******************************************************************************
2061+ *
2062+ * Instruction: DMAWFP
2063+ * Description:
2064+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
2065+ * < periph[4:0] > 0 0 0 0 0 1 1 0 0 bs p
2066+ * Example:
2067+ * DMAWFP P0, periph
2068+ * 31 00
2069+ ******************************************************************************/
2070+const char dmac_code_DMAWFP[] = { 0x31, 0x00 };
2071+
2072+int DMAC_DMAWFP(int ch_num, int periph_id, dmawfp_burst_type s)
2073+{
2074+ dmac_instr_param_t param;
2075+ int instr_len;
2076+ memset(&param, 0, sizeof(dmac_instr_param_t));
2077+ if (s == SINGLE) {
2078+ param.bits.b.bs = 0;
2079+ param.bits.b.p = 0;
2080+ }
2081+ if (s == BURST) {
2082+ param.bits.b.bs = 1;
2083+ param.bits.b.p = 0;
2084+ }
2085+ if (s == PERIPHERAL) {
2086+ param.bits.b.bs = 0;
2087+ param.bits.b.p = 1;
2088+ }
2089+ param.periph = periph_id;
2090+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAWFP, &param);
2091+ if (instr_len < 0) {
2092+ printk("dmac_create_instr failed \n");
2093+ return -1;
2094+ }
2095+
2096+ return 0;
2097+}
2098+
2099+EXPORT_SYMBOL(DMAC_DMAWFP);
2100+
2101+/******************************************************************************
2102+ *
2103+ * Instruction: DMAKILL
2104+ * Description:
2105+ * | 7 6 5 4 | 3 2 1 0 |
2106+ * 0 0 0 0 0 0 0 1
2107+ * Example:
2108+ * DMAKILL
2109+ * 01
2110+ ******************************************************************************/
2111+const char dmac_code_DMAKILL[] = { 0x01 };
2112+
2113+/******************************************************************************
2114+ *
2115+ * Instruction: DMASEV
2116+ * Description:
2117+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
2118+ * <event_num[4:0]> 0 i 0 0 0 1 1 0 1 0 0
2119+ * Example:
2120+ * DMASEV E0
2121+ * 34 00
2122+ ******************************************************************************/
2123+const char dmac_code_DMASEV[] = { 0x34, 0x00 };
2124+
2125+int DMAC_DMASEV(int ch_num, int event_num)
2126+{
2127+ dmac_instr_param_t param;
2128+ int instr_len;
2129+ dmac_channel_t *dma_ch = dmac_channels[ch_num];
2130+ if ((event_num >= MIN_EVENT_NUM)
2131+ && !(dma_ch->notifications_used & (1 << event_num))) {
2132+ printk("DMAC_DMASEV failed event number request not done\n");
2133+ return -1;
2134+ } else if ((event_num < MIN_EVENT_NUM) && (event_num != ch_num)) {
2135+ printk
2136+ ("%s:%d - Presently, we have this hard restriction that each channel can signal irq event == channel_no\n",
2137+ __FUNCTION__, __LINE__);
2138+ return -1;
2139+ }
2140+ memset(&param, 0, sizeof(dmac_instr_param_t));
2141+ param.event_num = event_num;
2142+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMASEV, &param);
2143+ if (instr_len < 0) {
2144+ printk("dmac_create_instr failed \n");
2145+ return -1;
2146+ }
2147+
2148+ return 0;
2149+}
2150+
2151+EXPORT_SYMBOL(DMAC_DMASEV);
2152+
2153+/******************************************************************************
2154+ *
2155+ * Instruction: DMALDP<S|B>
2156+ * Description:
2157+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
2158+ * < periph[4:0] > 0 0 0 0 0 1 0 0 1 bs 1
2159+ * Example:
2160+ * DMALDPS P0
2161+ * 25 00
2162+ ******************************************************************************/
2163+const char dmac_code_DMALDP[] = { 0x25, 0x00 };
2164+
2165+int DMAC_DMALDP(int ch_num, int periph_id, int burst)
2166+{
2167+ dmac_instr_param_t param;
2168+ int instr_len;
2169+ memset(&param, 0, sizeof(dmac_instr_param_t));
2170+ /* param.bits.b.x = param.bits.b.bs = 0; */
2171+ param.periph = periph_id;
2172+ param.bits.b.bs = burst;
2173+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMALDP, &param);
2174+ if (instr_len < 0) {
2175+ printk("dmac_create_instr failed \n");
2176+ return -1;
2177+ }
2178+
2179+ return 0;
2180+}
2181+
2182+EXPORT_SYMBOL(DMAC_DMALDP);
2183+
2184+/******************************************************************************
2185+ *
2186+ * Instruction: DMASTP<S|B>
2187+ * Description:
2188+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
2189+ * < periph[4:0] > 0 0 0 0 0 1 0 1 0 bs 1
2190+ * Example:
2191+ * DMASTPS P0
2192+ * 29 00
2193+ ******************************************************************************/
2194+const char dmac_code_DMASTP[] = { 0x29, 0x00 };
2195+
2196+int DMAC_DMASTP(int ch_num, int periph_id, int burst)
2197+{
2198+ dmac_instr_param_t param;
2199+ int instr_len;
2200+ memset(&param, 0, sizeof(dmac_instr_param_t));
2201+ /* param.bits.b.x = param.bits.b.bs = 0; */
2202+ param.periph = periph_id;
2203+ param.bits.b.bs = burst;
2204+ instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMASTP, &param);
2205+ if (instr_len < 0) {
2206+ printk("dmac_create_instr failed \n");
2207+ return -1;
2208+ }
2209+
2210+ return 0;
2211+}
2212+
2213+EXPORT_SYMBOL(DMAC_DMASTP);
2214+
2215+dmac_instr_encode_t dmac_codes[] = {
2216+ {dmac_code_DMAEND, sizeof(dmac_code_DMAEND), CHANNEL_AND_MANAGER}
2217+ ,
2218+ {dmac_code_DMAFLUSHP, sizeof(dmac_code_DMAFLUSHP), CHANNEL_ONLY}
2219+ ,
2220+ {dmac_code_DMAGO, sizeof(dmac_code_DMAGO), MANAGER_ONLY}
2221+ ,
2222+ {dmac_code_DMALD, sizeof(dmac_code_DMALD), CHANNEL_ONLY}
2223+ ,
2224+ {dmac_code_DMALDP, sizeof(dmac_code_DMALDP), CHANNEL_ONLY}
2225+ ,
2226+ {dmac_code_DMALP, sizeof(dmac_code_DMALP), CHANNEL_ONLY}
2227+ ,
2228+ {dmac_code_DMALPEND, sizeof(dmac_code_DMALPEND), CHANNEL_ONLY}
2229+ ,
2230+ {dmac_code_DMAKILL, sizeof(dmac_code_DMAKILL), CHANNEL_AND_MANAGER}
2231+ ,
2232+ {dmac_code_DMAMOV, sizeof(dmac_code_DMAMOV), CHANNEL_ONLY}
2233+ ,
2234+ {dmac_code_DMANOP, sizeof(dmac_code_DMANOP), CHANNEL_AND_MANAGER}
2235+ ,
2236+ {dmac_code_DMASEV, sizeof(dmac_code_DMASEV), CHANNEL_AND_MANAGER}
2237+ ,
2238+ {dmac_code_DMAST, sizeof(dmac_code_DMAST), CHANNEL_ONLY}
2239+ ,
2240+ {dmac_code_DMASTP, sizeof(dmac_code_DMASTP), CHANNEL_ONLY}
2241+ ,
2242+ {dmac_code_DMASTZ, sizeof(dmac_code_DMASTZ), CHANNEL_ONLY}
2243+ ,
2244+ {dmac_code_DMAWFE, sizeof(dmac_code_DMAWFE), CHANNEL_AND_MANAGER}
2245+ ,
2246+ {dmac_code_DMAWFP, sizeof(dmac_code_DMAWFP), CHANNEL_ONLY}
2247+ ,
2248+ {dmac_code_DMAWMB, sizeof(dmac_code_DMAWMB), CHANNEL_ONLY}
2249+ ,
2250+};
2251+
2252+static void Dmac_Cmd_Write32(uint8_t * buf, uint32_t val)
2253+{
2254+ buf[0] = (uint8_t) (val);
2255+ buf[1] = (uint8_t) (val >> 8);
2256+ buf[2] = (uint8_t) (val >> 16);
2257+ buf[3] = (uint8_t) (val >> 24);
2258+
2259+ return;
2260+}
2261+
2262+static int
2263+dmac_create_instr(int chan, dmac_instr_t instr, dmac_instr_param_t * param)
2264+{
2265+ int len = 0;
2266+ dmac_channel_t *dma_ch = dmac_channels[chan];
2267+ uint8_t *buf = NULL;
2268+#ifdef DEBUG_GDMA
2269+ printk("%s:%d: In with channel no %d\n", __FUNCTION__, __LINE__, chan);
2270+#endif
2271+
2272+ if (!((0x1 << chan) & dmac_codes[instr].chan_or_mgr)) {
2273+ printk("Channel %d does not support this instruction %d\n",
2274+ chan, instr);
2275+ return -1;
2276+ }
2277+#ifdef DEBUG_GDMA
2278+ if (!dma_ch)
2279+ printk("%s:%d: Bug here !!\n", __FUNCTION__, __LINE__);
2280+#endif
2281+
2282+ if (dma_ch->microcode == NULL) {
2283+ buf = dma_ch->microcode =
2284+ dma_alloc_coherent(NULL, MAX_MICROCODE_SIZE,
2285+ &dma_ch->microcode_dma, GFP_KERNEL);
2286+ printk
2287+ ("First time microcode alloc for channel %d done @phy:%x\n",
2288+ chan, dma_ch->microcode_dma);
2289+ dma_ch->microcode_size = 0;
2290+ } else {
2291+ if ((dmac_codes[instr].enc_buf_len + dma_ch->microcode_size) >
2292+ MAX_MICROCODE_SIZE) {
2293+ printk
2294+ ("We have a buffer overflow [%d]issue here ... BUG !!\n",
2295+ dma_ch->microcode_size);
2296+ return -1;
2297+ }
2298+ buf = dma_ch->microcode + dma_ch->microcode_size;
2299+ }
2300+#ifdef DEBUG_GDMA
2301+ printk("%s:%d: Microcode alloc for channel %d\n", __FUNCTION__,
2302+ __LINE__, chan);
2303+#endif
2304+
2305+ if (buf == NULL) {
2306+ printk("%s: Unable to allocate memory for microocode space\n",
2307+ __FUNCTION__);
2308+ return -1;
2309+ }
2310+#ifdef DEBUG_GDMA
2311+ printk("%s:%d: allocated microcode buffer%p [@phy: %x]\n", __FUNCTION__,
2312+ __LINE__, buf, dma_ch->microcode_dma + dma_ch->microcode_size);
2313+#endif
2314+ /* TODO: buf_space checking */
2315+ memcpy(buf, dmac_codes[instr].enc_buf, dmac_codes[instr].enc_buf_len);
2316+ len += dmac_codes[instr].enc_buf_len;
2317+
2318+ /* TODO: Parameter checking */
2319+ switch (instr) {
2320+ case DMAC_INSTR_DMAEND:
2321+ case DMAC_INSTR_DMASTZ:
2322+ case DMAC_INSTR_DMAKILL:
2323+ case DMAC_INSTR_DMAWMB:
2324+ case DMAC_INSTR_DMANOP:
2325+ /* no parameter needed */
2326+ break;
2327+
2328+ case DMAC_INSTR_DMAFLUSHP:
2329+ /* Fill additional parameters */
2330+ buf[1] |= (param->periph) << 3; // shift to bit 11
2331+ break;
2332+
2333+ case DMAC_INSTR_DMAGO:
2334+ // Fill additional parameters
2335+ if (param->bits.b.ns)
2336+ buf[0] |= 0x2;
2337+ else
2338+ buf[0] &= ~0x2;
2339+ buf[1] = param->cn & 0x7;
2340+//#warning "rewrite this"
2341+ Dmac_Cmd_Write32(&buf[2], param->imm32.i.val);
2342+ //memcpy (&buf[2],&(param->imm32.i.val),4);
2343+ break;
2344+
2345+ case DMAC_INSTR_DMALD:
2346+ case DMAC_INSTR_DMAST:
2347+ // Fill additional parameters
2348+ buf[0] &= 0xFC;
2349+ if (param->bits.b.x)
2350+ buf[0] |= 0x1;
2351+ else
2352+ buf[0] &= ~0x1;
2353+ if (param->bits.b.bs)
2354+ buf[0] |= 0x2;
2355+ else
2356+ buf[0] &= ~0x2;
2357+ break;
2358+
2359+ case DMAC_INSTR_DMALP:
2360+ buf[0] &= (~0x2);
2361+ if (param->bits.b.lc)
2362+ buf[0] |= 0x2;
2363+ buf[1] = param->iter;
2364+ break;
2365+
2366+ case DMAC_INSTR_DMALPEND:
2367+ // Fill additional parameters
2368+ buf[0] = 0x28;
2369+ if (param->bits.b.x)
2370+ buf[0] |= 0x1;
2371+ if (param->bits.b.bs)
2372+ buf[0] |= 0x2;
2373+ if (param->bits.b.lc)
2374+ buf[0] |= 0x4;
2375+ if (param->bits.b.nf)
2376+ buf[0] |= 0x10;
2377+ buf[1] = param->backwards_jump;
2378+ break;
2379+
2380+ case DMAC_INSTR_DMAMOV:
2381+ // Fill additional parameters
2382+ buf[1] = (param->rd) & 0x7;
2383+//#warning "rewrite this"
2384+ Dmac_Cmd_Write32(&buf[2], param->imm32.i.val);
2385+ //memcpy (&buf[2],&(param->imm32.i.val),4);
2386+ break;
2387+
2388+ case DMAC_INSTR_DMAWFE:
2389+ buf[1] = 0x0;
2390+ if (param->bits.b.i)
2391+ buf[1] |= 0x2;
2392+ buf[1] |= (param->event_num) << 3; // shift to bit 11
2393+ break;
2394+
2395+ case DMAC_INSTR_DMASEV:
2396+ buf[1] |= (param->event_num) << 3; // shift to bit 11
2397+ break;
2398+
2399+ case DMAC_INSTR_DMAWFP:
2400+ if (param->bits.b.p)
2401+ buf[0] |= 0x1;
2402+ else
2403+ buf[0] &= ~0x1;
2404+ if (param->bits.b.bs)
2405+ buf[0] |= 0x2;
2406+ else
2407+ buf[0] &= ~0x2;
2408+ buf[1] |= (param->periph) << 3; // shift to bit 11
2409+ break;
2410+
2411+ case DMAC_INSTR_DMALDP:
2412+ case DMAC_INSTR_DMASTP:
2413+ // Fill additional parameters
2414+ if (param->bits.b.bs)
2415+ buf[0] |= 0x2;
2416+ else
2417+ buf[0] &= ~0x2;
2418+ buf[1] |= (param->periph) << 3; // shift to bit 11
2419+ break;
2420+
2421+ default:
2422+ printk("%s: unknown instr (%d)\r\n", __FUNCTION__, instr);
2423+ break;
2424+ }
2425+ dma_ch->microcode_size += len;
2426+#ifdef DEBUG_GDMA
2427+ printk("%s:%d: out with length %d\n", __FUNCTION__, __LINE__,
2428+ dma_ch->microcode_size);
2429+ {
2430+ int foo = 0;
2431+ uint8_t *foop = dma_ch->microcode;
2432+ printk("Dumping the buffer -- ");
2433+ for (foo = 0; foo < dma_ch->microcode_size; foo++)
2434+ printk("%x ", *(foop + foo));
2435+ printk(" -- done.\n");
2436+ }
2437+#endif
2438+ return len;
2439+}
2440+
2441+static int dmac_exec_ucode(int ucode_channel, int ch)
2442+{
2443+ uint8_t i, dbg_instr_0_shift_base, dbg_instr_2_shift_base, dbg_cmd_len,
2444+ *dbg_cmd_buf;
2445+ uint32_t dbg1_val, dbg2_val;
2446+ dmac_channel_t *dma_ch = dmac_channels[ucode_channel];
2447+
2448+ if (!dma_ch->microcode_size) {
2449+ printk("%s: No instructions have been created\n", __FUNCTION__);
2450+ return -1;
2451+ }
2452+
2453+ dbg_cmd_buf = dma_ch->microcode;
2454+ dbg_cmd_len = dma_ch->microcode_size;
2455+#ifdef DEBUG_GDMA
2456+ {
2457+ int tmp;
2458+ uint8_t *tmpp = dbg_cmd_buf;
2459+ printk
2460+ ("Executing the code for channel %d, with instrn len %d\n",
2461+ ch, dma_ch->microcode_size);
2462+ printk("Dumping microcode : ");
2463+ for (tmp = 0; tmp < dbg_cmd_len; tmp++)
2464+ printk("%x ", *tmpp++);
2465+ printk("\n");
2466+ }
2467+#endif
2468+
2469+ spin_lock(&dma_mgr_lock);
2470+
2471+ /* 3. Poll the Debug Status Register */
2472+ while (DMAC_DBGSTATUS & DMAC_DBG_BUSY_BIT) ;
2473+
2474+ /* 4. Write to the Debug Instrution-X Register */
2475+ dbg1_val = 0;
2476+ dbg2_val = 0;
2477+
2478+ dbg_instr_0_shift_base = DMAC_DBG_INSTR_0_SHIFT;
2479+ dbg_instr_2_shift_base = DMAC_DBG_INSTR_2_SHIFT;
2480+ for (i = 0; i < dbg_cmd_len; i++) {
2481+ uint8_t tmp_val = dbg_cmd_buf[i];
2482+ switch (i) {
2483+ case 0:
2484+ case 1:
2485+ dbg1_val |= (tmp_val << dbg_instr_0_shift_base);
2486+ dbg_instr_0_shift_base += 8;
2487+ break;
2488+ case 2:
2489+ case 3:
2490+ case 4:
2491+ case 5:
2492+ tmp_val = dbg_cmd_buf[i];
2493+ dbg2_val |= (tmp_val << dbg_instr_2_shift_base);
2494+ dbg_instr_2_shift_base += 8;
2495+ break;
2496+ default:
2497+ printk("BUG here ... DEBUG\n");
2498+ break;
2499+ }
2500+ }
2501+
2502+ // Fill channel field
2503+ if (ch == DMAC_CHMGR) {
2504+ dbg1_val &= (~DMAC_DBG_THREAD_BIT);
2505+ } else {
2506+ dbg1_val |= DMAC_DBG_THREAD_BIT;
2507+ dbg1_val |=
2508+ ((ch & DMAC_DBG_CH_NUM_BIT_MASK) << DMAC_DBG_CH_NUM_SHIFT);
2509+ }
2510+
2511+#ifdef DEBUG_GDMA
2512+ {
2513+ printk("dbg1_val: %x, dbg2_val: %x\n", dbg1_val, dbg2_val);
2514+ }
2515+#endif
2516+
2517+ DMAC_DBGINST0 = dbg1_val;
2518+ DMAC_DBGINST1 = dbg2_val;
2519+
2520+ /* 5. Writing zero to the Debug Command Register */
2521+ DMAC_DBGCMD = 0x0;
2522+
2523+ spin_unlock(&dma_mgr_lock);
2524+ return 0;
2525+}
2526+
2527+#define MAX_SINGLE_INSTR_LEN 8 /* TODO */
2528+
2529+static int dmac_channel_state_init(int ch_num)
2530+{
2531+ int instr_len = dmac_create_instr(ch_num, DMAC_INSTR_DMAKILL, NULL);
2532+
2533+ if (instr_len < 0) {
2534+ printk("dmac_create_instr failed \n");
2535+ return -1;
2536+ }
2537+
2538+ dmac_exec_ucode(ch_num, ch_num);
2539+
2540+ if (dmac_channels[ch_num])
2541+ dmac_channels[ch_num]->microcode_size = 0;
2542+ else
2543+ printk("BUG HERE !! DEBUG .. \n");
2544+
2545+ return 0;
2546+}
2547+
2548+static irqreturn_t dmac_irq_handler(int irq, void *dev_id)
2549+{
2550+ uint32_t irq_status = 0;
2551+ uint8_t event_status = 0, channel_no = 0;
2552+ dmac_channel_t *chan = NULL;
2553+
2554+ irq_status = DMAC_INTSTATUS; /* TODO: Get Interrupt status */
2555+#ifdef DEBUG_GDMA
2556+ printk("Dumping the interrupt status register %x\n", irq_status);
2557+#endif
2558+
2559+ if (!irq_status) {
2560+#ifdef DEBUG_GDMA
2561+ printk("%s: Probably a DMAC Fault !!%x\n", __FUNCTION__,
2562+ irq_status);
2563+ pl330_dump_regs();
2564+#endif
2565+ return IRQ_NONE;
2566+ }
2567+
2568+// if (irq_status >= MIN_EVENT_NUM) {
2569+// printk(KERN_CRIT
2570+// "Event interrupt handler..(%d) Not implemented\n",
2571+// irq_status);
2572+// return IRQ_NONE;
2573+// }
2574+
2575+ event_status = irq_status & 0xff;
2576+ /* Clear Interrupt */
2577+ DMAC_INTCLR |= (irq_status & 0xff);
2578+
2579+ while (event_status) {
2580+ if (event_status & 0x1) {
2581+ chan = dmac_channels[channel_no];
2582+ if (chan->intr_handler && chan->in_use)
2583+ chan->intr_handler(chan->handler_args);
2584+ }
2585+ event_status >>= 1;
2586+ channel_no++;
2587+ }
2588+ return IRQ_HANDLED;
2589+}
2590+
2591+static void cns3xxx_dmac_hw_init(void)
2592+{
2593+#ifdef CONFIG_CNS3XXX_PM_API
2594+ /* enable GDMA clock*/
2595+ cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(GDMA));
2596+ /* check clok status and power status */
2597+ #if 0
2598+ PM_PWR_STA_REG & (0x1 << PM_PWR_STA_REG_REG_OFFSET_GDMA)
2599+ PM_CACTIVE_STA_REG & (0x1 << PM_CACTIVE_STA_REG_OFFSET_GDMA)
2600+ #endif
2601+ /* do software reset*/
2602+ cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GDMA));
2603+#else
2604+#error "CNS3XXX PM API support should be enabled in Linux kernel"
2605+#endif
2606+}
2607+
2608+/*
2609+ * dmac_init
2610+ */
2611+int __init dmac_init(void)
2612+{
2613+ int i, irqno = DMAC_IRQNO_BASE;
2614+
2615+ printk(KERN_INFO "Initializing CNS3XXX DMA controller \n");
2616+
2617+ cns3xxx_dmac_hw_init();
2618+
2619+ memset(dmac_channels, 0, sizeof(dmac_channel_t *) * MAX_DMA_CHANNELS);
2620+
2621+ spin_lock_init(&dma_mgr_lock);
2622+
2623+ for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2624+ dmac_channels[i] = kmalloc(sizeof(dmac_channel_t), GFP_KERNEL);
2625+
2626+ if (dmac_channels[i] == NULL) {
2627+ printk("Unable to allocate memory for channel %d \n",
2628+ i);
2629+ return -ENOMEM;
2630+ }
2631+
2632+ memset(dmac_channels[i], 0, sizeof(dmac_channel_t));
2633+ }
2634+
2635+ /* Moves all the DMA channels to the Stopped state */
2636+ for (i = 0; i < MAX_DMA_CHANNELS; i++)
2637+ dmac_channel_state_init(i);
2638+
2639+ for (i = 0; i < MAX_INTR_EVENTS; i++)
2640+ dmac_events[i] = -1;
2641+
2642+ /* Clear spurious interrupts */
2643+ DMAC_INTCLR = 0xffffffff;
2644+ DMAC_INTEN = 0xff; //Enable 8 interrupt 0x03; /* Enabling interrupts IRQ[0], IRQ[1] */
2645+
2646+ /* TODO: error interrupt Right now using the same irq handler,
2647+ * and reporting error inside the handler
2648+ */
2649+ if (request_irq(ERROR_INTR, dmac_irq_handler, 0, "DMAC-ERR", NULL)) {
2650+ printk(KERN_CRIT "failed to request DMAC-ERR interrupt.\n");
2651+ return -ENOENT;
2652+ }
2653+
2654+ do {
2655+ if (request_irq(irqno, dmac_irq_handler, 0, "DMAC", NULL)) {
2656+ printk(KERN_CRIT "failed to request DMAC interrupt.\n");
2657+ return -ENOENT;
2658+ }
2659+ } while (++irqno < (DMAC_IRQNO_BASE + MIN_EVENT_NUM));
2660+
2661+ return 0;
2662+}
2663+
2664+/*
2665+ * dmac_get_channel
2666+ */
2667+int dmac_get_channel(int (*handler) (void *), void *handler_args)
2668+{
2669+ int i;
2670+
2671+ for (i = 0; i < MAX_DMA_CHANNELS; i++)
2672+ if (dmac_channels[i]->in_use == 0) {
2673+ dmac_channel_t *dmac_ch = dmac_channels[i];
2674+
2675+ dmac_ch->microcode_size = 0;
2676+ dmac_ch->in_use = 1;
2677+ dmac_ch->intr_handler = handler;
2678+ dmac_ch->handler_args = handler_args;
2679+
2680+ /* TODO enable interrupts for that channel */
2681+// dmac_channel_state_init(i);
2682+ return i;
2683+ }
2684+
2685+ return -1;
2686+}
2687+
2688+int dmac_get_channel_ex(int channel, int (*handler) (void *), void *handler_args)
2689+{
2690+ if((channel >= 0) && (channel < MAX_DMA_CHANNELS) && (dmac_channels[channel]->in_use == 0)) {
2691+ dmac_channel_t *dmac_ch = dmac_channels[channel];
2692+
2693+ dmac_ch->microcode_size = 0;
2694+ dmac_ch->in_use = 1;
2695+ dmac_ch->intr_handler = handler;
2696+ dmac_ch->handler_args = handler_args;
2697+
2698+ /* TODO enable interrupts for that channel */
2699+// dmac_channel_state_init(channel);
2700+ return channel;
2701+ }
2702+
2703+ return -1;
2704+}
2705+
2706+EXPORT_SYMBOL(dmac_get_channel);
2707+EXPORT_SYMBOL(dmac_get_channel_ex);
2708+
2709+/*
2710+ * dmac_release_channel
2711+ */
2712+int dmac_release_channel(int chan)
2713+{
2714+ dmac_channel_t *dma_ch;
2715+
2716+ if (chan < 0 || chan > 7)
2717+ return -1;
2718+
2719+ dma_ch = dmac_channels[chan];
2720+ if (!dma_ch->in_use)
2721+ return -1;
2722+
2723+ dma_ch->in_use = 0;
2724+ dma_ch->microcode_size = 0;
2725+ dma_ch->intr_handler = 0;
2726+ dma_ch->handler_args = 0;
2727+
2728+ /* TODO enable interrupts for that channel */
2729+ dmac_channel_state_init(chan);
2730+
2731+ return 0;
2732+}
2733+
2734+EXPORT_SYMBOL(dmac_release_channel);
2735+
2736+/*
2737+ *
2738+ */
2739+int dmac_get_event(int chan, int event_num)
2740+{
2741+ if ((event_num < MIN_EVENT_NUM) || (event_num > MAX_INTR_EVENTS)) {
2742+ return -1;
2743+ }
2744+
2745+ if (dmac_events[event_num] == -1) {
2746+ dmac_channel_t *dmac_ch = dmac_channels[chan];
2747+ dmac_events[event_num] = chan;
2748+ dmac_ch->notifications_used |= (1 << event_num);
2749+ return 0;
2750+ }
2751+ return -1;
2752+}
2753+
2754+EXPORT_SYMBOL(dmac_get_event);
2755+
2756+/*
2757+ *
2758+ */
2759+int dmac_release_event(int chan, int event_num)
2760+{
2761+ if (dmac_events[event_num] != chan)
2762+ return -1;
2763+
2764+ dmac_events[event_num] = -1;
2765+ dmac_channels[chan]->notifications_used ^= (1 << event_num);
2766+ return 0;
2767+}
2768+
2769+EXPORT_SYMBOL(dmac_release_event);
2770+
2771+static int get_bpb_val(int bpb)
2772+{
2773+ int i = bpb;
2774+ int retval = -1;
2775+ while (i) {
2776+ retval += 0x1;
2777+ i /= 2;
2778+ }
2779+ return retval;
2780+}
2781+
2782+/* @src_inc - src address auto increment
2783+ * @s_bpb - src bytes per burst
2784+ * @s_dt - src num of data transfers
2785+ * @dst_inc - dst address auto increment
2786+ * @d_bpb - dst bytes per burst
2787+ * @d_dt - dst data transfers
2788+ * @swap - swapping bytes
2789+ */
2790+uint32_t dmac_create_ctrlval(int src_inc, int s_bpb, int s_dt, int dst_inc,
2791+ int d_bpb, int d_dt, int swap)
2792+{
2793+ if (!
2794+ ((s_bpb == 1) || (s_bpb == 2) || (s_bpb == 4) || (s_bpb == 8)
2795+ || (s_bpb == 16)
2796+ || (s_bpb == 32) || (s_bpb == 64) || (s_bpb == 128))) {
2797+ printk
2798+ ("INVALID s_bpb parameter ... setting default and proceeding\n");
2799+ s_bpb = 4;
2800+ }
2801+ if (!
2802+ ((d_bpb == 1) || (d_bpb == 2) || (d_bpb == 4) || (d_bpb == 8)
2803+ || (d_bpb == 16)
2804+ || (d_bpb == 32) || (d_bpb == 64) || (d_bpb == 128))) {
2805+ printk
2806+ ("INVALID d_bpb parameter ... setting default and proceeding\n");
2807+ d_bpb = 4;
2808+ }
2809+
2810+ if ((s_dt < 1) || (s_dt > 16)) {
2811+ printk
2812+ ("INVALID s_dt parameter ... setting default and proceeding\n");
2813+ s_dt = 1;
2814+ }
2815+ if ((d_dt < 1) || (d_dt > 16)) {
2816+ printk
2817+ ("INVALID d_dt parameter ... setting default and proceeding\n");
2818+ d_dt = 1;
2819+ }
2820+ return (((src_inc & 0x1) << 0) |
2821+ ((get_bpb_val(s_bpb) & 0x7) << 1) |
2822+ ((s_dt - 1) << 4) |
2823+ (0x2 << 8) |
2824+ (0x0 << 11) |
2825+ ((dst_inc & 0x1) << 14) |
2826+ ((get_bpb_val(d_bpb) & 0x7) << 15) |
2827+ ((d_dt - 1) << 18) | (0x2 << 22) | (0x0 << 25) | (swap << 28)
2828+ );
2829+}
2830+
2831+EXPORT_SYMBOL(dmac_create_ctrlval);
2832+
2833+void pl330_dump_regs(void)
2834+{
2835+ printk("Read Periph Id 0 for GDMAC is %x\n", DMAC_MEM_MAP_VALUE(0xFE0));
2836+ printk("DS Register: %x\n", DMAC_MEM_MAP_VALUE(0x0));
2837+ printk("Conf Reg 0 : %x\n", DMAC_MEM_MAP_VALUE(0xE00));
2838+ printk("Conf Reg 1 : %x\n", DMAC_MEM_MAP_VALUE(0xE04));
2839+ printk("Conf Reg 2 : %x\n", DMAC_MEM_MAP_VALUE(0xE08));
2840+ printk("Conf Reg 3 : %x\n", DMAC_MEM_MAP_VALUE(0xE0C));
2841+ printk("Conf Reg 4 : %x\n", DMAC_MEM_MAP_VALUE(0xE10));
2842+ printk("Conf Reg d : %x\n", DMAC_MEM_MAP_VALUE(0xE14));
2843+
2844+ printk("Dumping the status registers \n");
2845+ printk("INTEN Register: %x\n", DMAC_MEM_MAP_VALUE(0x20));
2846+ printk("ES Register: %x\n", DMAC_MEM_MAP_VALUE(0x24));
2847+ printk("INTSTAT Register: %x\n", DMAC_MEM_MAP_VALUE(0x28));
2848+ printk("FSDM Register: %x\n", DMAC_MEM_MAP_VALUE(0x30));
2849+ printk("FSC Register: %x\n", DMAC_MEM_MAP_VALUE(0x34));
2850+ printk("FTM Register: %x\n", DMAC_MEM_MAP_VALUE(0x38));
2851+ printk("FTC0 Register: %x\n", DMAC_MEM_MAP_VALUE(0x40));
2852+ printk("FTC1 Register: %x\n", DMAC_MEM_MAP_VALUE(0x44));
2853+ printk("CS0 Register: %x\n", DMAC_MEM_MAP_VALUE(0x100));
2854+ printk("CPC0 Register: %x\n", DMAC_MEM_MAP_VALUE(0x104));
2855+ printk("CS1 Register: %x\n", DMAC_MEM_MAP_VALUE(0x108));
2856+ printk("CPC1 Register: %x\n", DMAC_MEM_MAP_VALUE(0x10C));
2857+ printk("SA0 Register: %x\n", DMAC_MEM_MAP_VALUE(0x400));
2858+ printk("SA1 Register: %x\n", DMAC_MEM_MAP_VALUE(0x420));
2859+ printk("DA0 Register: %x\n", DMAC_MEM_MAP_VALUE(0x404));
2860+ printk("DA1 Register: %x\n", DMAC_MEM_MAP_VALUE(0x424));
2861+ return;
2862+}
2863+
2864+EXPORT_SYMBOL(pl330_dump_regs);
2865+
2866+/*
2867+ *
2868+ */
2869+uint32_t DMAC_READ_CHREGS(int chan, chregs_t reg)
2870+{
2871+ int step = 0, base = 0;
2872+
2873+ switch (reg) {
2874+ case PL330_FTC:
2875+ base = 0x40;
2876+ step = chan * 0x4;
2877+ break;
2878+ case PL330_CS:
2879+ base = 0x100;
2880+ step = chan * 0x8;
2881+ break;
2882+ case PL330_CPC:
2883+ base = 0x104;
2884+ step = chan * 0x8;
2885+ break;
2886+ case PL330_SA:
2887+ base = 0x400;
2888+ step = chan * 0x20;
2889+ break;
2890+ case PL330_DA:
2891+ base = 0x404;
2892+ step = chan * 0x20;
2893+ break;
2894+ case PL330_CC:
2895+ base = 0x408;
2896+ step = chan * 0x20;
2897+ break;
2898+ case PL330_LC0:
2899+ base = 0x40C;
2900+ step = chan * 0x20;
2901+ break;
2902+ case PL330_LC1:
2903+ base = 0x410;
2904+ step = chan * 0x20;
2905+ break;
2906+ default:
2907+ printk("Wrong argument to function %s\n", __FUNCTION__);
2908+ }
2909+ return DMAC_MEM_MAP_VALUE(base + step);
2910+}
2911+
2912+EXPORT_SYMBOL(DMAC_READ_CHREGS);
2913--- /dev/null
2914+++ b/arch/arm/mach-cns3xxx/headsmp.S
2915@@ -0,0 +1,54 @@
2916+/*
2917+ * linux/arch/arm/mach-cns3xxx/headsmp.S
2918+ *
2919+ * Copyright (c) 2008 Cavium Networks
2920+ * Copyright (c) 2003 ARM Limited
2921+ * All Rights Reserved
2922+ *
2923+ * This file is free software; you can redistribute it and/or modify
2924+ * it under the terms of the GNU General Public License, Version 2, as
2925+ * published by the Free Software Foundation.
2926+ *
2927+ * This file is distributed in the hope that it will be useful,
2928+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
2929+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
2930+ * NONINFRINGEMENT. See the GNU General Public License for more details.
2931+ *
2932+ * You should have received a copy of the GNU General Public License
2933+ * along with this file; if not, write to the Free Software
2934+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
2935+ * visit http://www.gnu.org/licenses/.
2936+ *
2937+ * This file may also be available under a different license from Cavium.
2938+ * Contact Cavium Networks for more information
2939+ */
2940+
2941+#include <linux/linkage.h>
2942+#include <linux/init.h>
2943+
2944+ __INIT
2945+
2946+/*
2947+ * CNS3XXX specific entry point for secondary CPUs. This provides
2948+ * a "holding pen" into which all secondary cores are held until we're
2949+ * ready for them to initialise.
2950+ */
2951+ENTRY(cns3xxx_secondary_startup)
2952+ mrc p15, 0, r0, c0, c0, 5
2953+ and r0, r0, #15
2954+ adr r4, 1f
2955+ ldmia r4, {r5, r6}
2956+ sub r4, r4, r5
2957+ add r6, r6, r4
2958+pen: ldr r7, [r6]
2959+ cmp r7, r0
2960+ bne pen
2961+
2962+ /*
2963+ * we've been released from the holding pen: secondary_stack
2964+ * should now contain the SVC stack for this core
2965+ */
2966+ b secondary_startup
2967+
2968+1: .long .
2969+ .long pen_release
2970--- /dev/null
2971+++ b/arch/arm/mach-cns3xxx/hotplug.c
2972@@ -0,0 +1,155 @@
2973+/*
2974+ * linux/arch/arm/mach-cns3xxx/hotplug.c
2975+ *
2976+ * Copyright (c) 2008 Cavium Networks
2977+ * Copyright (C) 2002 ARM Ltd.
2978+ * All Rights Reserved
2979+ *
2980+ * This file is free software; you can redistribute it and/or modify
2981+ * it under the terms of the GNU General Public License, Version 2, as
2982+ * published by the Free Software Foundation.
2983+ *
2984+ * This file is distributed in the hope that it will be useful,
2985+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
2986+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
2987+ * NONINFRINGEMENT. See the GNU General Public License for more details.
2988+ *
2989+ * You should have received a copy of the GNU General Public License
2990+ * along with this file; if not, write to the Free Software
2991+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
2992+ * visit http://www.gnu.org/licenses/.
2993+ *
2994+ * This file may also be available under a different license from Cavium.
2995+ * Contact Cavium Networks for more information
2996+ */
2997+#include <linux/kernel.h>
2998+#include <linux/errno.h>
2999+#include <linux/smp.h>
3000+#include <linux/completion.h>
3001+
3002+#include <asm/cacheflush.h>
3003+
3004+extern volatile int pen_release;
3005+
3006+static DECLARE_COMPLETION(cpu_killed);
3007+
3008+static inline void cpu_enter_lowpower(void)
3009+{
3010+ unsigned int v;
3011+
3012+ flush_cache_all();
3013+ asm volatile(
3014+ " mcr p15, 0, %1, c7, c5, 0\n"
3015+ " mcr p15, 0, %1, c7, c10, 4\n"
3016+ /*
3017+ * Turn off coherency
3018+ */
3019+ " mrc p15, 0, %0, c1, c0, 1\n"
3020+ " bic %0, %0, #0x20\n"
3021+ " mcr p15, 0, %0, c1, c0, 1\n"
3022+ " mrc p15, 0, %0, c1, c0, 0\n"
3023+ " bic %0, %0, #0x04\n"
3024+ " mcr p15, 0, %0, c1, c0, 0\n"
3025+ : "=&r" (v)
3026+ : "r" (0)
3027+ : "cc");
3028+}
3029+
3030+static inline void cpu_leave_lowpower(void)
3031+{
3032+ unsigned int v;
3033+
3034+ asm volatile( "mrc p15, 0, %0, c1, c0, 0\n"
3035+ " orr %0, %0, #0x04\n"
3036+ " mcr p15, 0, %0, c1, c0, 0\n"
3037+ " mrc p15, 0, %0, c1, c0, 1\n"
3038+ " orr %0, %0, #0x20\n"
3039+ " mcr p15, 0, %0, c1, c0, 1\n"
3040+ : "=&r" (v)
3041+ :
3042+ : "cc");
3043+}
3044+
3045+static inline void platform_do_lowpower(unsigned int cpu)
3046+{
3047+ /*
3048+ * there is no power-control hardware on this platform, so all
3049+ * we can do is put the core into WFI; this is safe as the calling
3050+ * code will have already disabled interrupts
3051+ */
3052+ for (;;) {
3053+ /*
3054+ * here's the WFI
3055+ */
3056+ asm(".word 0xe320f003\n"
3057+ :
3058+ :
3059+ : "memory", "cc");
3060+
3061+ if (pen_release == cpu) {
3062+ /*
3063+ * OK, proper wakeup, we're done
3064+ */
3065+ break;
3066+ }
3067+
3068+ /*
3069+ * getting here, means that we have come out of WFI without
3070+ * having been woken up - this shouldn't happen
3071+ *
3072+ * The trouble is, letting people know about this is not really
3073+ * possible, since we are currently running incoherently, and
3074+ * therefore cannot safely call printk() or anything else
3075+ */
3076+#ifdef DEBUG
3077+ printk("CPU%u: spurious wakeup call\n", cpu);
3078+#endif
3079+ }
3080+}
3081+
3082+int platform_cpu_kill(unsigned int cpu)
3083+{
3084+ return wait_for_completion_timeout(&cpu_killed, 5000);
3085+}
3086+
3087+/*
3088+ * platform-specific code to shutdown a CPU
3089+ *
3090+ * Called with IRQs disabled
3091+ */
3092+void platform_cpu_die(unsigned int cpu)
3093+{
3094+#ifdef DEBUG
3095+ unsigned int this_cpu = hard_smp_processor_id();
3096+
3097+ if (cpu != this_cpu) {
3098+ printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
3099+ this_cpu, cpu);
3100+ BUG();
3101+ }
3102+#endif
3103+
3104+ printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
3105+ complete(&cpu_killed);
3106+
3107+ /*
3108+ * we're ready for shutdown now, so do it
3109+ */
3110+ cpu_enter_lowpower();
3111+ platform_do_lowpower(cpu);
3112+
3113+ /*
3114+ * bring this CPU back into the world of cache
3115+ * coherency, and then restore interrupts
3116+ */
3117+ cpu_leave_lowpower();
3118+}
3119+
3120+int mach_cpu_disable(unsigned int cpu)
3121+{
3122+ /*
3123+ * we don't allow CPU 0 to be shutdown (it is still too special
3124+ * e.g. clock tick interrupts)
3125+ */
3126+ return cpu == 0 ? -EPERM : 0;
3127+}
3128--- /dev/null
3129+++ b/arch/arm/mach-cns3xxx/include/mach/board.h
3130@@ -0,0 +1,386 @@
3131+/*
3132+ * arch/arm/mach-cns3xxx/include/mach/board.h
3133+ *
3134+ * Copyright (c) 2008 Cavium Networks
3135+ *
3136+ * This file is free software; you can redistribute it and/or modify
3137+ * it under the terms of the GNU General Public License, Version 2, as
3138+ * published by the Free Software Foundation.
3139+ *
3140+ * This file is distributed in the hope that it will be useful,
3141+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
3142+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
3143+ * NONINFRINGEMENT. See the GNU General Public License for more details.
3144+ *
3145+ * You should have received a copy of the GNU General Public License
3146+ * along with this file; if not, write to the Free Software
3147+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
3148+ * visit http://www.gnu.org/licenses/.
3149+ *
3150+ * This file may also be available under a different license from Cavium.
3151+ * Contact Cavium Networks for more information
3152+ */
3153+
3154+#ifndef __ASM_ARCH_BOARD_CNS3XXXH
3155+#define __ASM_ARCH_BOARD_CNS3XXXH
3156+
3157+/*
3158+ * Cavium Networks CNS3XXX Linux Memory Map:
3159+ *
3160+ * Phy Size Virt Description
3161+ * =========================================================================
3162+ *
3163+ * 0x00000000 0x10000000(max) PAGE_OFFSET Alien RAM (??)
3164+ *
3165+ * 0x78000000 0x00400000 0xFFF09000 UART0
3166+ *
3167+ */
3168+
3169+/*
3170+ * Peripheral addresses
3171+ */
3172+#define CNS3XXX_FLASH0_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
3173+#define CNS3XXX_FLASH0_SIZE SZ_128M
3174+
3175+#define CNS3XXX_FLASH1_BASE 0x11000000 /* Flash/SRAM Memory Bank 1 */
3176+#define CNS3XXX_FLASH1_SIZE SZ_16M
3177+#define CNS3XXX_FLASH2_BASE 0x12000000 /* Flash/SRAM Memory Bank 2 */
3178+#define CNS3XXX_FLASH2_SIZE SZ_16M
3179+#define CNS3XXX_FLASH3_BASE 0x13000000 /* Flash/SRAM Memory Bank 3 */
3180+#define CNS3XXX_FLASH3_SIZE SZ_16M
3181+
3182+#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
3183+
3184+#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
3185+
3186+#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
3187+#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
3188+
3189+#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
3190+#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
3191+
3192+#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
3193+#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
3194+
3195+#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
3196+#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
3197+
3198+#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
3199+#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
3200+
3201+#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
3202+#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
3203+
3204+#define SMC_MEMC_STATUS_OFFSET 0x000
3205+#define SMC_MEMIF_CFG_OFFSET 0x004
3206+#define SMC_MEMC_CFG_SET_OFFSET 0x008
3207+#define SMC_MEMC_CFG_CLR_OFFSET 0x00C
3208+#define SMC_DIRECT_CMD_OFFSET 0x010
3209+#define SMC_SET_CYCLES_OFFSET 0x014
3210+#define SMC_SET_OPMODE_OFFSET 0x018
3211+#define SMC_REFRESH_PERIOD_0_OFFSET 0x020
3212+#define SMC_REFRESH_PERIOD_1_OFFSET 0x024
3213+#define SMC_SRAM_CYCLES0_0_OFFSET 0x100
3214+#define SMC_NAND_CYCLES0_0_OFFSET 0x100
3215+#define SMC_OPMODE0_0_OFFSET 0x104
3216+#define SMC_SRAM_CYCLES0_1_OFFSET 0x120
3217+#define SMC_NAND_CYCLES0_1_OFFSET 0x120
3218+#define SMC_OPMODE0_1_OFFSET 0x124
3219+#define SMC_USER_STATUS_OFFSET 0x200
3220+#define SMC_USER_CONFIG_OFFSET 0x204
3221+#define SMC_ECC_STATUS_OFFSET 0x300
3222+#define SMC_ECC_MEMCFG_OFFSET 0x304
3223+#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
3224+#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
3225+#define SMC_ECC_ADDR0_OFFSET 0x310
3226+#define SMC_ECC_ADDR1_OFFSET 0x314
3227+#define SMC_ECC_VALUE0_OFFSET 0x318
3228+#define SMC_ECC_VALUE1_OFFSET 0x31C
3229+#define SMC_ECC_VALUE2_OFFSET 0x320
3230+#define SMC_ECC_VALUE3_OFFSET 0x324
3231+#define SMC_PERIPH_ID_0_OFFSET 0xFE0
3232+#define SMC_PERIPH_ID_1_OFFSET 0xFE4
3233+#define SMC_PERIPH_ID_2_OFFSET 0xFE8
3234+#define SMC_PERIPH_ID_3_OFFSET 0xFEC
3235+#define SMC_PCELL_ID_0_OFFSET 0xFF0
3236+#define SMC_PCELL_ID_1_OFFSET 0xFF4
3237+#define SMC_PCELL_ID_2_OFFSET 0xFF8
3238+#define SMC_PCELL_ID_3_OFFSET 0xFFC
3239+
3240+#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
3241+#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
3242+
3243+#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
3244+#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
3245+
3246+#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
3247+#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
3248+
3249+#define RTC_SEC_OFFSET 0x00
3250+#define RTC_MIN_OFFSET 0x04
3251+#define RTC_HOUR_OFFSET 0x08
3252+#define RTC_DAY_OFFSET 0x0C
3253+#define RTC_SEC_ALM_OFFSET 0x10
3254+#define RTC_MIN_ALM_OFFSET 0x14
3255+#define RTC_HOUR_ALM_OFFSET 0x18
3256+#define RTC_REC_OFFSET 0x1C
3257+#define RTC_CTRL_OFFSET 0x20
3258+#define RTC_INTR_STS_OFFSET 0x34
3259+
3260+#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
3261+#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */
3262+
3263+#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
3264+#define CNS3XXX_PM_BASE_VIRT 0xFFF08000
3265+
3266+#define PM_CLK_GATE_OFFSET 0x00
3267+#define PM_SOFT_RST_OFFSET 0x04
3268+#define PM_HS_CFG_OFFSET 0x08
3269+#define PM_CACTIVE_STA_OFFSET 0x0C
3270+#define PM_PWR_STA_OFFSET 0x10
3271+#define PM_SYS_CLK_CTRL_OFFSET 0x14
3272+#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
3273+#define PM_PLL_HM_PD_OFFSET 0x1C
3274+
3275+#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
3276+#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000
3277+
3278+#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
3279+#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
3280+
3281+#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
3282+#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
3283+
3284+#define CNS3XXX_UART3_BASE 0x78C00000 /* UART 3 */
3285+#define CNS3XXX_UART3_BASE_VIRT 0xFFF0C000
3286+
3287+#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
3288+#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
3289+
3290+#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
3291+#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
3292+
3293+#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
3294+#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
3295+
3296+#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
3297+#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
3298+
3299+#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
3300+#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800
3301+
3302+#define TIMER1_COUNTER_OFFSET 0x00
3303+#define TIMER1_AUTO_RELOAD_OFFSET 0x04
3304+#define TIMER1_MATCH_V1_OFFSET 0x08
3305+#define TIMER1_MATCH_V2_OFFSET 0x0C
3306+
3307+#define TIMER2_COUNTER_OFFSET 0x10
3308+#define TIMER2_AUTO_RELOAD_OFFSET 0x14
3309+#define TIMER2_MATCH_V1_OFFSET 0x18
3310+#define TIMER2_MATCH_V2_OFFSET 0x1C
3311+
3312+#define TIMER1_2_CONTROL_OFFSET 0x30
3313+#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
3314+#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
3315+
3316+#define TIMER_FREERUN_OFFSET 0x40
3317+#define TIMER_FREERUN_CONTROL_OFFSET 0x44
3318+
3319+#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
3320+#if 0
3321+#define CNS3XXX_HCIE_BASE_VIRT 0xFFF11000
3322+#else
3323+#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
3324+#endif
3325+
3326+#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
3327+#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
3328+
3329+#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
3330+#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
3331+
3332+#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
3333+#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
3334+
3335+#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
3336+#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
3337+
3338+#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
3339+#define CNS3XXX_USB_BASE_VIRT 0xFFF16000
3340+
3341+#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
3342+#define CNS3XXX_SATA2_SIZE SZ_16M
3343+#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
3344+
3345+#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
3346+#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
3347+
3348+#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
3349+#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
3350+
3351+#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
3352+#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
3353+
3354+#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
3355+#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
3356+
3357+#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
3358+#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000
3359+
3360+#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
3361+#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
3362+
3363+#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
3364+#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
3365+
3366+#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
3367+#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
3368+
3369+#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
3370+#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000
3371+
3372+#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
3373+#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
3374+
3375+#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
3376+#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
3377+
3378+#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
3379+#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000
3380+
3381+#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
3382+#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000
3383+
3384+#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
3385+#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
3386+
3387+#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
3388+#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000
3389+
3390+#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
3391+#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
3392+
3393+#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
3394+#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
3395+
3396+#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
3397+#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000
3398+
3399+/*
3400+ * Testchip peripheral and fpga gic regions
3401+ */
3402+//#define CNS3XXX_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
3403+#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
3404+#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000
3405+
3406+//#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
3407+#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
3408+#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100
3409+
3410+//#define CNS3XXX_TC11MP_TWD_BASE 0x1F000600
3411+#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
3412+#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600
3413+
3414+//#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
3415+#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
3416+#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000
3417+
3418+//#define CNS3XXX_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
3419+#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
3420+#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
3421+
3422+/*
3423+ * Irqs
3424+ */
3425+#define IRQ_TC11MP_GIC_START 32
3426+
3427+/*
3428+ * ARM11 MPCore test chip interrupt sources (primary GIC on the test chip)
3429+ */
3430+#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
3431+#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
3432+#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
3433+#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)
3434+#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)
3435+#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)
3436+#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)
3437+#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)
3438+#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)
3439+#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)
3440+#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)
3441+#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)
3442+#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)
3443+#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)
3444+#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)
3445+#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)
3446+#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)
3447+
3448+#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)
3449+#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)
3450+#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)
3451+#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)
3452+#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)
3453+#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)
3454+#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)
3455+#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)
3456+#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)
3457+#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)
3458+
3459+#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)
3460+#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)
3461+#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)
3462+#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)
3463+#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)
3464+#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)
3465+#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)
3466+#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)
3467+#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)
3468+
3469+#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)
3470+#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)
3471+#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)
3472+#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)
3473+#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)
3474+#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)
3475+#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)
3476+#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)
3477+#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)
3478+#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)
3479+#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)
3480+#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)
3481+#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)
3482+#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)
3483+#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)
3484+#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)
3485+#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)
3486+#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)
3487+#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)
3488+
3489+#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)
3490+#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)
3491+#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)
3492+#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)
3493+#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)
3494+#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)
3495+#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)
3496+#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)
3497+#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)
3498+
3499+#define NR_GIC_CNS3XXX 1
3500+
3501+/*
3502+ * Only define NR_IRQS if less than NR_IRQS_CNS3XXX
3503+ */
3504+#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
3505+
3506+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
3507+#undef NR_IRQS
3508+#define NR_IRQS NR_IRQS_CNS3XXX
3509+#endif
3510+
3511+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_CNS3XXX)
3512+#undef MAX_GIC_NR
3513+#define MAX_GIC_NR NR_GIC_CNS3XXX
3514+#endif
3515+
3516+#endif /* __ASM_ARCH_BOARD_CNS3XXX_H */
3517--- /dev/null
3518+++ b/arch/arm/mach-cns3xxx/include/mach/camera.h
3519@@ -0,0 +1,97 @@
3520+/*
3521+ camera.h - CNS3XXX camera driver header file
3522+
3523+ Copyright (C) 2003, Intel Corporation
3524+ Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
3525+
3526+ This program is free software; you can redistribute it and/or modify
3527+ it under the terms of the GNU General Public License as published by
3528+ the Free Software Foundation; either version 2 of the License, or
3529+ (at your option) any later version.
3530+
3531+ This program is distributed in the hope that it will be useful,
3532+ but WITHOUT ANY WARRANTY; without even the implied warranty of
3533+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3534+ GNU General Public License for more details.
3535+
3536+ You should have received a copy of the GNU General Public License
3537+ along with this program; if not, write to the Free Software
3538+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
3539+*/
3540+
3541+#ifndef __ASM_ARCH_CAMERA_H_
3542+#define __ASM_ARCH_CAMERA_H_
3543+
3544+#define CNS3XXX_CAMERA_MASTER 0x01
3545+#define CNS3XXX_CAMERA_DATAWIDTH_4 0x02
3546+#define CNS3XXX_CAMERA_DATAWIDTH_5 0x04
3547+#define CNS3XXX_CAMERA_DATAWIDTH_8 0x08
3548+#define CNS3XXX_CAMERA_DATAWIDTH_9 0x10
3549+#define CNS3XXX_CAMERA_DATAWIDTH_10 0x20
3550+#define CNS3XXX_CAMERA_PCLK_EN 0x40
3551+#define CNS3XXX_CAMERA_MCLK_EN 0x80
3552+#define CNS3XXX_CAMERA_PCP 0x100
3553+#define CNS3XXX_CAMERA_HSP 0x200
3554+#define CNS3XXX_CAMERA_VSP 0x400
3555+
3556+/* Camera Interface */
3557+#define CIM_GLOBAL_REG 0x00 /* CIM control*/
3558+#define CIM_TIMING_V_REG 0x04 /* Vertical capture range setting */
3559+#define CIM_TIMING_H_REG 0x08 /* Horizontal capture range setting */
3560+#define CIM_CCIR656_0_REG 0x0C /* CCIR656 detect and control setting*/
3561+#define CIM_CCIR656_1_REG 0x10 /* CCIR656 self test setting */
3562+#define CIM_SERIAL_SRC_REG 0x14 /* Serial pix capture module control settings */
3563+#define CIM_INT_MASK_REG 0x28 /* CIM interrupt mask register. */
3564+#define CIM_INT_STATUS_REG 0x2C /* CIM interrupt status register. */
3565+#define CIM_INT_CLEAR_REG 0x30 /* CIM interrupt clear register. */
3566+#define CIM_DATAPATH_CTL_REG 0x34 /* CIM data path options and control settings */
3567+#define CIM_VIDEO_PORT_REG 0x100 /* CIM¡¦s video port */
3568+#define CIM_CORRECTION_R_REG 0x200 /* Internal programmable table for R component. */
3569+#define CIM_CORRECTION_G_REG 0x600 /* Internal programmable table for G component. */
3570+#define CIM_CORRECTION_B_REG 0xA00 /* Internal programmable table for B component. */
3571+
3572+#define SRC_DATA_FMT_CCIR656 0x00
3573+#define SRC_DATA_FMT_YCBCR_A 0x01
3574+#define SRC_DATA_FMT_YCBCR_B 0x02
3575+#define SRC_DATA_FMT_RGB565 0x03
3576+#define SRC_DATA_FMT_RGB555 0x04
3577+#define SRC_DATA_FMT_BAYER_82 0x05
3578+#define SRC_DATA_FMT_BAYER_10 0x06
3579+
3580+#define DST_DATA_FMT_RGB888 0x00
3581+#define DST_DATA_FMT_RGB565 0x01
3582+#define DST_DATA_FMT_RGB1555 0x02
3583+#define DST_DATA_FMT_RGB444 0x03
3584+
3585+#define CISR_LAST_LINE (1 << 0) /* Last line */
3586+#define CISR_FIRST_LINE (1 << 1) /* First line */
3587+#define CISR_LINE_END (1 << 2) /* Line end */
3588+#define CISR_LINE_START (1 << 3) /* Line start */
3589+#define CISR_FIELD_CHG (1 << 4) /* Field Change */
3590+#define CISR_FIFO_OVERRUN (1 << 5) /* FIFO overrun */
3591+
3592+
3593+#define CIMR_LAST_LINE_M (1 << 0) /* Last line mask*/
3594+#define CIMR_FIRST_LINE_M (1 << 1) /* First line mask*/
3595+#define CIMR_LINE_END_M (1 << 2) /* Line end mask*/
3596+#define CIMR_LINE_START_M (1 << 3) /* Line start mask*/
3597+#define CIMR_FIELD_CHG_M (1 << 4) /* Field Change mask*/
3598+#define CIMR_FIFO_OVERRUN_M (1 << 5) /* FIFO overrun mask*/
3599+
3600+
3601+struct cns3xxx_camera_platform_data {
3602+#if 0
3603+ int (*init)(struct device *);
3604+ int (*power)(struct device *, int);
3605+ int (*reset)(struct device *, int);
3606+#endif
3607+
3608+ unsigned long flags;
3609+ unsigned long mclk_10khz;
3610+ unsigned long lcd_base;
3611+ unsigned long misc_base;
3612+};
3613+
3614+//extern void cns3xxx_set_camera_info(struct pxacamera_platform_data *);
3615+
3616+#endif /* __ASM_ARCH_CAMERA_H_ */
3617--- /dev/null
3618+++ b/arch/arm/mach-cns3xxx/include/mach/clkdev.h
3619@@ -0,0 +1,7 @@
3620+#ifndef __ASM_MACH_CLKDEV_H
3621+#define __ASM_MACH_CLKDEV_H
3622+
3623+#define __clk_get(clk) ({ 1; })
3624+#define __clk_put(clk) do { } while (0)
3625+
3626+#endif
3627--- /dev/null
3628+++ b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
3629@@ -0,0 +1,35 @@
3630+/* arch/arm/mach-cns3xxx/include/mach/debug-macro.S
3631+ *
3632+ * Debugging macro include header
3633+ *
3634+ * Copyright (c) 2008 Cavium Networks
3635+ * Copyright (C) 1994-1999 Russell King
3636+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
3637+ *
3638+ * This file is free software; you can redistribute it and/or modify
3639+ * it under the terms of the GNU General Public License, Version 2, as
3640+ * published by the Free Software Foundation.
3641+ *
3642+ * This file is distributed in the hope that it will be useful,
3643+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
3644+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
3645+ * NONINFRINGEMENT. See the GNU General Public License for more details.
3646+ *
3647+ * You should have received a copy of the GNU General Public License
3648+ * along with this file; if not, write to the Free Software
3649+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
3650+ * visit http://www.gnu.org/licenses/.
3651+ *
3652+ * This file may also be available under a different license from Cavium.
3653+ * Contact Cavium Networks for more information
3654+ */
3655+
3656+ .macro addruart,rx
3657+ mrc p15, 0, \rx, c1, c0
3658+ tst \rx, #1 @ MMU enabled?
3659+ moveq \rx, #0x10000000
3660+ movne \rx, #0xf0000000 @ virtual base
3661+ orr \rx, \rx, #0x00009000
3662+ .endm
3663+
3664+#include <asm/hardware/debug-pl01x.S>
3665--- /dev/null
3666+++ b/arch/arm/mach-cns3xxx/include/mach/dmac.h
3667@@ -0,0 +1,295 @@
3668+/*******************************************************************************
3669+ *
3670+ * arch/arm/mach-cns3xxx/dmac.h
3671+ *
3672+ * Copyright (c) 2008 Cavium Networks
3673+ *
3674+ * This file is free software; you can redistribute it and/or modify
3675+ * it under the terms of the GNU General Public License, Version 2, as
3676+ * published by the Free Software Foundation.
3677+ *
3678+ * This file is distributed in the hope that it will be useful,
3679+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
3680+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
3681+ * NONINFRINGEMENT. See the GNU General Public License for more details.
3682+ *
3683+ * You should have received a copy of the GNU General Public License
3684+ * along with this file; if not, write to the Free Software
3685+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
3686+ * visit http://www.gnu.org/licenses/.
3687+ *
3688+ * This file may also be available under a different license from Cavium.
3689+ * Contact Cavium Networks for more information
3690+ *
3691+ ******************************************************************************/
3692+
3693+#ifndef _CNS3XXX_DMAC_H_
3694+#define _CNS3XXX_DMAC_H_
3695+
3696+#define MAX_DMA_CHANNELS 9
3697+#define DMAC_PCM1_PERIPH_ID_0 4
3698+#define DMAC_SPI_PERIPH_ID 8
3699+#define DMAC_PCM_PERIPH_ID_0 9
3700+#define CNS3XXX_DMAC_I2STX_PID 12
3701+#define CNS3XXX_DMAC_I2SRX_PID 13
3702+
3703+/* APIs */
3704+int __init dmac_init(void);
3705+extern int dmac_get_channel (int (*handler)(void*), void *handler_args);
3706+extern int dmac_get_channel_ex(int channel, int (*handler) (void *), void *handler_args);
3707+extern int dmac_release_channel(int chan);
3708+
3709+extern int dmac_get_event (int chan, int ev);
3710+extern int dmac_release_event (int chan, int ev);
3711+
3712+extern uint32_t dmac_create_ctrlval (int src_inc, int s_bpb, int s_dt, int dst_inc, int d_bpb, int d_dt, int swap);
3713+/* enum - reg ? 0 => PL330_FTC, 1 => PL330_CS, 2 => PL330_CPC, 3 => PL330_SA,
3714+ * 4 => PL330_DA, 5=>PL330_CC, 6 => PL330_LC0, 7 => PL330_LC1
3715+ */
3716+typedef enum { PL330_FTC =0,
3717+ PL330_CS,
3718+ PL330_CPC,
3719+ PL330_SA,
3720+ PL330_DA,
3721+ PL330_CC,
3722+ PL330_LC0,
3723+ PL330_LC1
3724+} chregs_t;
3725+
3726+extern uint32_t DMAC_READ_CHREGS (int chan, chregs_t reg);
3727+
3728+/* Instruction Set */
3729+
3730+/******************************************************************************
3731+ *
3732+ * Instruction: DMAEND
3733+ * Description:
3734+ * | 7 6 5 4 | 3 2 1 0 |
3735+ * 0 0 0 0 0 0 0 0
3736+ * Example:
3737+ * DMAEND
3738+ * 00
3739+ ******************************************************************************/
3740+int DMAC_DMAEND(int ch_num);
3741+
3742+/******************************************************************************
3743+ *
3744+ * Instruction: DMAFLUSHP
3745+ * Description:
3746+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3747+ * <periph[4:0] > 0 0 0 0 0 1 1 0 1 0 1
3748+ * Example:
3749+ * DMAFLUSHP P0
3750+ * 35 00
3751+ ******************************************************************************/
3752+#define DMAFLUSHP_INSTR_SIZE 2
3753+int DMAC_DMAFLUSHP(int ch_num, int periph);
3754+
3755+/******************************************************************************
3756+ *
3757+ * Instruction: DMAGO
3758+ * Description:
3759+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3760+ * 0 0 0 0 0 <cn[2:0]> 1 0 1 0 0 0 ns 0
3761+ *
3762+ * | 47 16 |
3763+ * < imm[31:0] >
3764+ * Example:
3765+ * DMAGO C0, 0x40000000
3766+ * A0 00 00 00 00 40
3767+ ******************************************************************************/
3768+int DMAC_DMAGO(int ch_num);
3769+
3770+/******************************************************************************
3771+ *
3772+ * Instruction: DMALD
3773+ * Description:
3774+ * | 7 6 5 4 | 3 2 1 0 |
3775+ * 0 0 0 0 0 1 bs x
3776+ * Example:
3777+ * DMALD
3778+ * 04
3779+ ******************************************************************************/
3780+#define DMALD_INSTR_SIZE 1
3781+#define DMALDB_INSTR_SIZE 1
3782+#define DMALDS_INSTR_SIZE 1
3783+int DMAC_DMALD(int ch_num);
3784+
3785+int DMAC_DMALDB(int ch_num);
3786+
3787+int DMAC_DMALDS(int ch_num);
3788+
3789+/******************************************************************************
3790+ *
3791+ * Instruction: DMALP
3792+ * Description:
3793+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3794+ * < iter[7:0] > 0 0 1 0 0 0 lc 0
3795+ * Example:
3796+ * DMALP 8
3797+ * 20 07
3798+ ******************************************************************************/
3799+#define DMALP_INSTR_SIZE 2
3800+int DMAC_DMALP(int ch_num, int loop_reg_idx, int iter);
3801+
3802+/******************************************************************************
3803+ *
3804+ * Instruction: DMALPEND
3805+ * Description:
3806+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3807+ * < backwards_jump[7:0] > 0 0 1 nf 1 lc bs x
3808+ * Example:
3809+ * DMALPEND
3810+ * 38 04
3811+ ******************************************************************************/
3812+#define DMALPEND_INSTR_SIZE 2
3813+int DMAC_DMALPEND(int ch_num, int loop_reg_idx, int jump, int lpfe);
3814+
3815+/******************************************************************************
3816+ *
3817+ * Instruction: DMAMOV
3818+ * Description:
3819+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3820+ * 0 0 0 0 0 <rd[2:0]> 1 0 1 1 1 1 0 0
3821+ *
3822+ * | 47 16 |
3823+ * < imm[31:0] >
3824+ *
3825+ * # CCR Description
3826+ * # [30:28] Endian swap size
3827+ * # [27:25] AWCACHE[3,1:0] value
3828+ * # [24:22] AWPROT value
3829+ * # [21:18] AWLEN value
3830+ * # [17:15] AWSIZE value
3831+ * # [14] AWBURST[0] value
3832+ * 0 - FIXED / 1 - INCR
3833+ * # [13:11] ARCACHE[2:0] value
3834+ * # [10:8] ARPROT value
3835+ * # [7:4] ARLEN value
3836+ * # [3:1] ARSIZE value
3837+ * # [0] ARBURST[0] value
3838+ * 0 - FIXED / 1 - INCR
3839+ * Example:
3840+ * DMAMOV CCR, SB1 SS32 DB1 DS32
3841+ * BC 01 05 40 01 00
3842+ ******************************************************************************/
3843+
3844+#define DMAMOV_INSTR_SIZE 6
3845+/* ccr_sar_dar: 0 for SAR, 1, for CCR, 2 for DAR */
3846+typedef enum { SAR = 0, CCR = 1, DAR = 2 } dmamov_arg_t;
3847+int DMAC_DMAMOV(int ch_num, dmamov_arg_t ccr_sar_dar, uint32_t value);
3848+
3849+#define DMAWMB_INSTR_SIZE 1
3850+int DMAC_DMAWMB (int ch_num);
3851+
3852+#define DMANOP_INSTR_SIZE 1
3853+int DMAC_DMANOP (int ch_num);
3854+/******************************************************************************
3855+ *
3856+ * Instruction: DMAST
3857+ * Description:
3858+ * | 7 6 5 4 | 3 2 1 0 |
3859+ * 0 0 0 0 1 0 bs x
3860+ * Example:
3861+ * DMAST
3862+ * 08
3863+ ******************************************************************************/
3864+#define DMAST_INSTR_SIZE 1 /* 1 Byte */
3865+int DMAC_DMAST(int ch_num);
3866+
3867+#define DMASTB_INSTR_SIZE 1 /* 1 Byte */
3868+int DMAC_DMASTB(int ch_num);
3869+
3870+#define DMASTS_INSTR_SIZE 1 /* 1 Byte */
3871+int DMAC_DMASTS(int ch_num);
3872+
3873+/******************************************************************************
3874+ *
3875+ * Instruction: DMASTZ
3876+ * Description:
3877+ * | 7 6 5 4 | 3 2 1 0 |
3878+ * 0 0 0 0 1 1 0 0
3879+ * Example:
3880+ * DMASTZ
3881+ * 08
3882+ ******************************************************************************/
3883+/* Not done */
3884+
3885+/******************************************************************************
3886+ *
3887+ * Instruction: DMAWFE
3888+ * Description:
3889+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3890+ * <event_num[4:0]> 0 i 0 0 0 1 1 0 1 1 0
3891+ * Example:
3892+ * DMAWFE E0
3893+ * 36 00
3894+ ******************************************************************************/
3895+int DMAC_WFE(int ch_num, int event);
3896+#define DMAWFE_INSTR_SIZE 2
3897+
3898+/******************************************************************************
3899+ *
3900+ * Instruction: DMAWFP
3901+ * Description:
3902+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3903+ * < periph[4:0] > 0 0 0 0 0 1 1 0 0 bs p
3904+ * Example:
3905+ * DMAWFP P0, periph
3906+ * 31 00
3907+ ******************************************************************************/
3908+typedef enum { SINGLE = 0, BURST = 1, PERIPHERAL = 2} dmawfp_burst_type;
3909+int DMAC_DMAWFP(int ch_num, int periph_id,dmawfp_burst_type b);
3910+#define DMAWFP_INSTR_SIZE 2
3911+
3912+/******************************************************************************
3913+ *
3914+ * Instruction: DMAKILL
3915+ * Description:
3916+ * | 7 6 5 4 | 3 2 1 0 |
3917+ * 0 0 0 0 0 0 0 1
3918+ * Example:
3919+ * DMAKILL
3920+ * 01
3921+ ******************************************************************************/
3922+
3923+/******************************************************************************
3924+ *
3925+ * Instruction: DMASEV
3926+ * Description:
3927+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3928+ * <event_num[4:0]> 0 i 0 0 0 1 1 0 1 0 0
3929+ * Example:
3930+ * DMASEV E0
3931+ * 34 00
3932+ ******************************************************************************/
3933+int DMAC_DMASEV(int ch_num, int event_num);
3934+#define DMASEV_INSTR_SIZE 2
3935+
3936+/******************************************************************************
3937+ *
3938+ * Instruction: DMALDP<S|B>
3939+ * Description:
3940+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3941+ * < periph[4:0] > 0 0 0 0 0 1 0 0 1 bs 1
3942+ * Example:
3943+ * DMALDPS P0
3944+ * 25 00
3945+ ******************************************************************************/
3946+int DMAC_DMALDP(int ch_num, int periph_id, int burst);
3947+#define DMALDP_INSTR_SIZE 2
3948+
3949+/******************************************************************************
3950+ *
3951+ * Instruction: DMASTP<S|B>
3952+ * Description:
3953+ * | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
3954+ * < periph[4:0] > 0 0 0 0 0 1 0 1 0 bs 1
3955+ * Example:
3956+ * DMASTPS P0
3957+ * 29 00
3958+ ******************************************************************************/
3959+int DMAC_DMASTP(int ch_num, int periph_id, int burst);
3960+#define DMASTP_INSTR_SIZE 2
3961+
3962+#endif
3963--- /dev/null
3964+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
3965@@ -0,0 +1,105 @@
3966+/*
3967+ * arch/arm/mach-cns3xxx/include/mach/entry-macro.S
3968+ *
3969+ * Low-level IRQ helper macros for Cavium Networks platforms
3970+ *
3971+ * Copyright (c) 2008 Cavium Networks
3972+ *
3973+ * This file is free software; you can redistribute it and/or modify
3974+ * it under the terms of the GNU General Public License, Version 2, as
3975+ * published by the Free Software Foundation.
3976+ *
3977+ * This file is distributed in the hope that it will be useful,
3978+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
3979+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
3980+ * NONINFRINGEMENT. See the GNU General Public License for more details.
3981+ *
3982+ * You should have received a copy of the GNU General Public License
3983+ * along with this file; if not, write to the Free Software
3984+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
3985+ * visit http://www.gnu.org/licenses/.
3986+ *
3987+ * This file may also be available under a different license from Cavium.
3988+ * Contact Cavium Networks for more information
3989+ */
3990+#include <mach/hardware.h>
3991+#include <asm/hardware/gic.h>
3992+
3993+ .macro disable_fiq
3994+ .endm
3995+
3996+ .macro get_irqnr_preamble, base, tmp
3997+ ldr \base, =gic_cpu_base_addr
3998+ ldr \base, [\base]
3999+ .endm
4000+
4001+ .macro arch_ret_to_user, tmp1, tmp2
4002+ .endm
4003+
4004+ /*
4005+ * The interrupt numbering scheme is defined in the
4006+ * interrupt controller spec. To wit:
4007+ *
4008+ * Interrupts 0-15 are IPI
4009+ * 16-28 are reserved
4010+ * 29-31 are local. We allow 30 to be used for the watchdog.
4011+ * 32-1020 are global
4012+ * 1021-1022 are reserved
4013+ * 1023 is "spurious" (no interrupt)
4014+ *
4015+ * For now, we ignore all local interrupts so only return an interrupt if it's
4016+ * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
4017+ *
4018+ * A simple read from the controller will tell us the number of the highest
4019+ * priority enabled interrupt. We then just need to check whether it is in the
4020+ * valid range for an IRQ (30-1020 inclusive).
4021+ */
4022+
4023+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
4024+
4025+ ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
4026+
4027+ ldr \tmp, =1021
4028+
4029+ bic \irqnr, \irqstat, #0x1c00
4030+
4031+ cmp \irqnr, #29
4032+ cmpcc \irqnr, \irqnr
4033+ cmpne \irqnr, \tmp
4034+ cmpcs \irqnr, \irqnr
4035+
4036+ .endm
4037+
4038+ /* We assume that irqstat (the raw value of the IRQ acknowledge
4039+ * register) is preserved from the macro above.
4040+ * If there is an IPI, we immediately signal end of interrupt on the
4041+ * controller, since this requires the original irqstat value which
4042+ * we won't easily be able to recreate later.
4043+ */
4044+
4045+ .macro test_for_ipi, irqnr, irqstat, base, tmp
4046+ bic \irqnr, \irqstat, #0x1c00
4047+ cmp \irqnr, #16
4048+ strcc \irqstat, [\base, #GIC_CPU_EOI]
4049+ cmpcs \irqnr, \irqnr
4050+ .endm
4051+
4052+ /* As above, this assumes that irqstat and base are preserved.. */
4053+
4054+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
4055+ bic \irqnr, \irqstat, #0x1c00
4056+ mov \tmp, #0
4057+ cmp \irqnr, #29
4058+ moveq \tmp, #1
4059+ streq \irqstat, [\base, #GIC_CPU_EOI]
4060+ cmp \tmp, #0
4061+ .endm
4062+
4063+ .macro test_for_cache_ipi, irqnr, irqstat, base, tmp
4064+ bic \irqnr, \irqstat, #0x1c00
4065+ mov \tmp, #0
4066+ cmp \irqnr, #1
4067+ moveq \tmp, #1
4068+ streq \irqstat, [\base, #GIC_CPU_EOI]
4069+ cmp \tmp, #0
4070+ .endm
4071--- /dev/null
4072+++ b/arch/arm/mach-cns3xxx/include/mach/gpio.h
4073@@ -0,0 +1,94 @@
4074+/*
4075+ * arch/arm/mach-ixp4xx/include/mach/gpio.h
4076+ *
4077+ * IXP4XX GPIO wrappers for arch-neutral GPIO calls
4078+ *
4079+ * Written by Milan Svoboda <msvoboda@ra.rockwell.com>
4080+ * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
4081+ *
4082+ * This program is free software; you can redistribute it and/or modify
4083+ * it under the terms of the GNU General Public License as published by
4084+ * the Free Software Foundation; either version 2 of the License, or
4085+ * (at your option) any later version.
4086+ *
4087+ * This program is distributed in the hope that it will be useful,
4088+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4089+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4090+ * GNU General Public License for more details.
4091+ *
4092+ * You should have received a copy of the GNU General Public License
4093+ * along with this program; if not, write to the Free Software
4094+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4095+ *
4096+ */
4097+
4098+#ifndef __ASM_ARCH_IXP4XX_GPIO_H
4099+#define __ASM_ARCH_IXP4XX_GPIO_H
4100+
4101+#include <linux/kernel.h>
4102+#include <mach/hardware.h>
4103+#include <asm-generic/gpio.h> /* cansleep wrappers */
4104+
4105+#define NR_BUILTIN_GPIO 64
4106+
4107+#define CNS3XXX_GPIO_IN 0x0
4108+#define CNS3XXX_GPIO_OUT 0x1
4109+
4110+#define CNS3XXX_GPIO_LO 0
4111+#define CNS3XXX_GPIO_HI 1
4112+
4113+#define CNS3XXX_GPIO_OUTPUT 0x00
4114+#define CNS3XXX_GPIO_INPUT 0x04
4115+#define CNS3XXX_GPIO_DIR 0x08
4116+#define CNS3XXX_GPIO_SET 0x10
4117+#define CNS3XXX_GPIO_CLEAR 0x14
4118+
4119+static inline void gpio_line_get(u8 line, int *value)
4120+{
4121+ if (line < 32)
4122+ *value = ((__raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> line) & 0x1);
4123+ else
4124+ *value = ((__raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> (line - 32)) & 0x1);
4125+}
4126+
4127+static inline void gpio_line_set(u8 line, int value)
4128+{
4129+ if (line < 32) {
4130+ if (value)
4131+ __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_SET);
4132+ else
4133+ __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
4134+ } else {
4135+ if (value)
4136+ __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_SET);
4137+ else
4138+ __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
4139+ }
4140+}
4141+
4142+static inline int gpio_get_value(unsigned gpio)
4143+{
4144+ if (gpio < NR_BUILTIN_GPIO)
4145+ {
4146+ int value;
4147+ gpio_line_get(gpio, &value);
4148+ return value;
4149+ }
4150+ else
4151+ return __gpio_get_value(gpio);
4152+}
4153+
4154+static inline void gpio_set_value(unsigned gpio, int value)
4155+{
4156+ if (gpio < NR_BUILTIN_GPIO)
4157+ gpio_line_set(gpio, value);
4158+ else
4159+ __gpio_set_value(gpio, value);
4160+}
4161+
4162+#define gpio_cansleep __gpio_cansleep
4163+
4164+extern int gpio_to_irq(int gpio);
4165+extern int irq_to_gpio(int gpio);
4166+
4167+#endif
4168--- /dev/null
4169+++ b/arch/arm/mach-cns3xxx/include/mach/hardware.h
4170@@ -0,0 +1,40 @@
4171+/*
4172+ * arch/arm/mach-cns3xxx/include/mach/hardware.h
4173+ *
4174+ * This file contains the hardware definitions of the Cavium Networks boards.
4175+ *
4176+ * Copyright (c) 2008 Cavium Networks
4177+ * Copyright (C) 2003 ARM Limited.
4178+ *
4179+ * This file is free software; you can redistribute it and/or modify
4180+ * it under the terms of the GNU General Public License, Version 2, as
4181+ * published by the Free Software Foundation.
4182+ *
4183+ * This file is distributed in the hope that it will be useful,
4184+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
4185+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4186+ * NONINFRINGEMENT. See the GNU General Public License for more details.
4187+ *
4188+ * You should have received a copy of the GNU General Public License
4189+ * along with this file; if not, write to the Free Software
4190+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
4191+ * visit http://www.gnu.org/licenses/.
4192+ *
4193+ * This file may also be available under a different license from Cavium.
4194+ * Contact Cavium Networks for more information
4195+ */
4196+
4197+#ifndef __ASM_ARCH_HARDWARE_H
4198+#define __ASM_ARCH_HARDWARE_H
4199+
4200+/* macro to get at IO space when running virtually */
4201+#define PCIBIOS_MIN_IO 0x00000000
4202+#define PCIBIOS_MIN_MEM 0x00000000
4203+
4204+#define pcibios_assign_all_busses() 0
4205+
4206+#include "board.h"
4207+
4208+#include "platform.h"
4209+
4210+#endif
4211--- /dev/null
4212+++ b/arch/arm/mach-cns3xxx/include/mach/io.h
4213@@ -0,0 +1,41 @@
4214+/*
4215+ * arch/arm/mach-cns3xxx/include/mach/io.h
4216+ *
4217+ * Copyright (c) 2008 Cavium Networks
4218+ * Copyright (C) 2003 ARM Limited
4219+ *
4220+ * This file is free software; you can redistribute it and/or modify
4221+ * it under the terms of the GNU General Public License, Version 2, as
4222+ * published by the Free Software Foundation.
4223+ *
4224+ * This file is distributed in the hope that it will be useful,
4225+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
4226+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4227+ * NONINFRINGEMENT. See the GNU General Public License for more details.
4228+ *
4229+ * You should have received a copy of the GNU General Public License
4230+ * along with this file; if not, write to the Free Software
4231+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
4232+ * visit http://www.gnu.org/licenses/.
4233+ *
4234+ * This file may also be available under a different license from Cavium.
4235+ * Contact Cavium Networks for more information
4236+ */
4237+#ifndef __ASM_ARM_ARCH_IO_H
4238+#define __ASM_ARM_ARCH_IO_H
4239+
4240+#include "board.h"
4241+
4242+#define IO_SPACE_LIMIT 0xffffffff
4243+
4244+#if 1
4245+static inline void __iomem *__io(unsigned long addr)
4246+{
4247+ return (void __iomem *)((addr - CNS3XXX_PCIE0_IO_BASE)
4248+ + CNS3XXX_PCIE0_IO_BASE_VIRT);
4249+}
4250+#endif
4251+#define __io(a) __io(a)
4252+#define __mem_pci(a) (a)
4253+
4254+#endif
4255--- /dev/null
4256+++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
4257@@ -0,0 +1,45 @@
4258+/*
4259+ * arch/arm/mach-cns3xxx/include/mach/irqs.h
4260+ *
4261+ * Copyright (c) 2008 Cavium Networks
4262+ * Copyright (C) 2003 ARM Limited
4263+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
4264+ *
4265+ * This file is free software; you can redistribute it and/or modify
4266+ * it under the terms of the GNU General Public License, Version 2, as
4267+ * published by the Free Software Foundation.
4268+ *
4269+ * This file is distributed in the hope that it will be useful,
4270+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
4271+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4272+ * NONINFRINGEMENT. See the GNU General Public License for more details.
4273+ *
4274+ * You should have received a copy of the GNU General Public License
4275+ * along with this file; if not, write to the Free Software
4276+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
4277+ * visit http://www.gnu.org/licenses/.
4278+ *
4279+ * This file may also be available under a different license from Cavium.
4280+ * Contact Cavium Networks for more information
4281+ */
4282+
4283+#ifndef __ASM_ARCH_IRQS_H
4284+#define __ASM_ARCH_IRQS_H
4285+
4286+#include <mach/board.h>
4287+
4288+#define IRQ_LOCALTIMER 29
4289+#define IRQ_LOCALWDOG 30
4290+
4291+#define IRQ_GIC_START 32
4292+#define IRQ_CLCD 44
4293+
4294+#ifdef CONFIG_CNS_RAID
4295+#define IRQ_CNS_RAID (43)
4296+#endif /* CONFIG_CNS_RAID */
4297+
4298+#ifndef NR_IRQS
4299+#error "NR_IRQS not defined by the board-specific files"
4300+#endif
4301+
4302+#endif
4303--- /dev/null
4304+++ b/arch/arm/mach-cns3xxx/include/mach/lm.h
4305@@ -0,0 +1,32 @@
4306+#include <linux/version.h>
4307+
4308+struct lm_device {
4309+ struct device dev;
4310+ struct resource resource;
4311+ unsigned int irq;
4312+ unsigned int id;
4313+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
4314+ void *lm_drvdata;
4315+#endif
4316+};
4317+
4318+struct lm_driver {
4319+ struct device_driver drv;
4320+ int (*probe)(struct lm_device *);
4321+ void (*remove)(struct lm_device *);
4322+ int (*suspend)(struct lm_device *, pm_message_t);
4323+ int (*resume)(struct lm_device *);
4324+};
4325+
4326+int lm_driver_register(struct lm_driver *drv);
4327+void lm_driver_unregister(struct lm_driver *drv);
4328+
4329+int lm_device_register(struct lm_device *dev);
4330+
4331+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
4332+# define lm_get_drvdata(lm) ((lm)->lm_drvdata)
4333+# define lm_set_drvdata(lm,d) do { (lm)->lm_drvdata = (d); } while (0)
4334+#else
4335+# define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
4336+# define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
4337+#endif
4338--- /dev/null
4339+++ b/arch/arm/mach-cns3xxx/include/mach/memory.h
4340@@ -0,0 +1,43 @@
4341+/*
4342+ * arch/arm/mach-cns3xxx/include/mach/memory.h
4343+ *
4344+ * Copyright (c) 2008 Cavium Networks
4345+ * Copyright (C) 2003 ARM Limited
4346+ *
4347+ * This file is free software; you can redistribute it and/or modify
4348+ * it under the terms of the GNU General Public License, Version 2, as
4349+ * published by the Free Software Foundation.
4350+ *
4351+ * This file is distributed in the hope that it will be useful,
4352+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
4353+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4354+ * NONINFRINGEMENT. See the GNU General Public License for more details.
4355+ *
4356+ * You should have received a copy of the GNU General Public License
4357+ * along with this file; if not, write to the Free Software
4358+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
4359+ * visit http://www.gnu.org/licenses/.
4360+ *
4361+ * This file may also be available under a different license from Cavium.
4362+ * Contact Cavium Networks for more information
4363+ */
4364+
4365+#ifndef __ASM_ARCH_MEMORY_H
4366+#define __ASM_ARCH_MEMORY_H
4367+
4368+/*
4369+ * Physical DRAM offset.
4370+ */
4371+#define PHYS_OFFSET UL(0x00000000)
4372+
4373+/*
4374+ * Virtual view <-> DMA view memory address translations
4375+ * virt_to_bus: Used to translate the virtual address to an
4376+ * address suitable to be passed to set_dma_addr
4377+ * bus_to_virt: Used to convert an address for DMA operations
4378+ * to an address that the kernel can use.
4379+ */
4380+#define __virt_to_bus(x) ((x) - PAGE_OFFSET)
4381+#define __bus_to_virt(x) ((x) + PAGE_OFFSET)
4382+
4383+#endif
4384--- /dev/null
4385+++ b/arch/arm/mach-cns3xxx/include/mach/misc.h
4386@@ -0,0 +1,670 @@
4387+/******************************************************************************
4388+ * MODULE NAME: star_misc.h
4389+ * PROJECT CODE: Vega
4390+ * DESCRIPTION:
4391+ * MAINTAINER: Jacky Hou
4392+ * DATE: 9 February 2009
4393+ *
4394+ * SOURCE CONTROL:
4395+ *
4396+ * LICENSE:
4397+ * This source code is copyright (c) 2008-2009 Cavium Networks Inc.
4398+ * All rights reserved.
4399+ *
4400+ * REVISION HISTORY:
4401+ *
4402+ *
4403+ * SOURCE:
4404+ * ISSUES:
4405+ * NOTES TO USERS:
4406+ ******************************************************************************/
4407+
4408+#ifndef _CNS3XXX_MISC_H_
4409+#define _CNS3XXX_MISC_H_
4410+#include <mach/board.h>
4411+#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + offset)))
4412+
4413+
4414+/*
4415+ * define access macros
4416+ */
4417+#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
4418+#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
4419+#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
4420+#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
4421+#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10)
4422+#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14)
4423+#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18)
4424+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C)
4425+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20)
4426+#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24)
4427+#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28)
4428+#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C)
4429+#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30)
4430+#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34)
4431+#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40)
4432+#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44)
4433+#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48)
4434+#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C)
4435+#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50)
4436+#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54)
4437+
4438+
4439+
4440+// USB MISC
4441+#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800)
4442+#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804)
4443+#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808)
4444+#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c)
4445+#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810)
4446+#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814)
4447+
4448+#define MISC_PCIEPHY_CMCTL0_REG MISC_MEM_MAP_VALUE(0x900)
4449+#define MISC_PCIEPHY_CMCTL1_REG MISC_MEM_MAP_VALUE(0x904)
4450+
4451+#define MISC_PCIEPHY0_CTL_REG MISC_MEM_MAP_VALUE(0x940)
4452+#define MISC_PCIE0_AXIS_AWMISC_REG MISC_MEM_MAP_VALUE(0x944)
4453+#define MISC_PCIE0_AXIS_ARMISC_REG MISC_MEM_MAP_VALUE(0x948)
4454+#define MISC_PCIE0_AXIS_RMISC_REG MISC_MEM_MAP_VALUE(0x94C)
4455+#define MISC_PCIE0_AXIS_BMISC_REG MISC_MEM_MAP_VALUE(0x950)
4456+#define MISC_PCIE0_AXIM_RMISC_REG MISC_MEM_MAP_VALUE(0x954)
4457+#define MISC_PCIE0_AXIM_BMISC_REG MISC_MEM_MAP_VALUE(0x958)
4458+#define MISC_PCIE0_CTRL_REG MISC_MEM_MAP_VALUE(0x95C)
4459+#define MISC_PCIE0_PM_DEBUG_REG MISC_MEM_MAP_VALUE(0x960)
4460+#define MISC_PCIE0_RFC_DEBUG_REG MISC_MEM_MAP_VALUE(0x964)
4461+#define MISC_PCIE0_CXPL_DEBUGL_REG MISC_MEM_MAP_VALUE(0x968)
4462+#define MISC_PCIE0_CXPL_DEBUGH_REG MISC_MEM_MAP_VALUE(0x96C)
4463+#define MISC_PCIE0_DIAG_DEBUGH_REG MISC_MEM_MAP_VALUE(0x970)
4464+#define MISC_PCIE0_W1CLR_REG MISC_MEM_MAP_VALUE(0x974)
4465+#define MISC_PCIE0_INT_MASK_REG MISC_MEM_MAP_VALUE(0x978)
4466+#define MISC_PCIE0_INT_STATUS_REG MISC_MEM_MAP_VALUE(0x97C)
4467+
4468+#define MISC_PCIEPHY1_CTL_REG MISC_MEM_MAP_VALUE(0xa40)
4469+#define MISC_PCIE1_AXIS_AWMISC_REG MISC_MEM_MAP_VALUE(0xa44)
4470+#define MISC_PCIE1_AXIS_ARMISC_REG MISC_MEM_MAP_VALUE(0xa48)
4471+#define MISC_PCIE1_AXIS_RMISC_REG MISC_MEM_MAP_VALUE(0xa4C)
4472+#define MISC_PCIE1_AXIS_BMISC_REG MISC_MEM_MAP_VALUE(0xa50)
4473+#define MISC_PCIE1_AXIM_RMISC_REG MISC_MEM_MAP_VALUE(0xa54)
4474+#define MISC_PCIE1_AXIM_BMISC_REG MISC_MEM_MAP_VALUE(0xa58)
4475+#define MISC_PCIE1_CTRL_REG MISC_MEM_MAP_VALUE(0xa5C)
4476+#define MISC_PCIE1_PM_DEBUG_REG MISC_MEM_MAP_VALUE(0xa60)
4477+#define MISC_PCIE1_RFC_DEBUG_REG MISC_MEM_MAP_VALUE(0xa64)
4478+#define MISC_PCIE1_CXPL_DEBUGL_REG MISC_MEM_MAP_VALUE(0xa68)
4479+#define MISC_PCIE1_CXPL_DEBUGH_REG MISC_MEM_MAP_VALUE(0xa6C)
4480+#define MISC_PCIE1_DIAG_DEBUGH_REG MISC_MEM_MAP_VALUE(0xa70)
4481+#define MISC_PCIE1_W1CLR_REG MISC_MEM_MAP_VALUE(0xa74)
4482+#define MISC_PCIE1_INT_MASK_REG MISC_MEM_MAP_VALUE(0xa78)
4483+#define MISC_PCIE1_INT_STATUS_REG MISC_MEM_MAP_VALUE(0xa7C)
4484+
4485+
4486+
4487+
4488+
4489+
4490+/*
4491+ * define constants macros
4492+ */
4493+#define MISC_PARALLEL_FLASH_BOOT (0x0)
4494+#define MISC_SPI_SERIAL_FLASH_BOOT (0x1)
4495+#define MISC_NAND_FLASH_BOOT (0x2)
4496+
4497+#define MISC_ALIGN_LITTLE_ENDIAN (0x0)
4498+#define MISC_UNALIGN_LITTLE_ENDIAN (0x2)
4499+#define MISC_UNALIGN_BIG_ENDIAN (0x3)
4500+
4501+#define MISC_CPU_CLOCK_333_MHZ (0)
4502+#define MISC_CPU_CLOCK_366_MHZ (1)
4503+#define MISC_CPU_CLOCK_400_MHZ (2)
4504+#define MISC_CPU_CLOCK_433_MHZ (3)
4505+#define MISC_CPU_CLOCK_466_MHZ (4)
4506+#define MISC_CPU_CLOCK_500_MHZ (5)
4507+#define MISC_CPU_CLOCK_533_MHZ (6)
4508+#define MISC_CPU_CLOCK_566_MHZ (7)
4509+#define MISC_CPU_CLOCK_600_MHZ (8)
4510+#define MISC_CPU_CLOCK_633_MHZ (9)
4511+#define MISC_CPU_CLOCK_666_MHZ (10)
4512+#define MISC_CPU_CLOCK_700_MHZ (11)
4513+
4514+/*
4515+ * Macro-defines for shared pins with GPIO_A
4516+ */
4517+#if 0
4518+#define MISC_LCD_PWR_PIN ((0x1 << 0))
4519+#define MISC_CIM_OE_PIN ((0x1 << 1))
4520+
4521+#define MISC_SMC_PINS ((0x1 << 2) | (0x1 << 3) | (0x1 << 4) | (0x1 << 5)| (0x1 << 6))
4522+#define MISC_SMC_CS3_PIN ((0x1 << 2))
4523+#define MISC_SMC_CS2_PIN ((0x1 << 3))
4524+#define MISC_SMC_CLK_PIN ((0x1 << 4))
4525+#define MISC_SMC_ADV_PIN ((0x1 << 5))
4526+#define MISC_SMC_CRE_PIN ((0x1 << 6))
4527+
4528+
4529+#define MISC_NFI_PINS ((0x1 << 7) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10)| (0x1 << 11))
4530+#define MISC_NFI_BUSY_PIN ((0x1 << 7))
4531+#define MISC_NFI_CS3_PIN ((0x1 << 8))
4532+#define MISC_NFI_CS2_PIN ((0x1 << 9))
4533+#define MISC_NFI_CE1_PIN ((0x1 << 10))
4534+#define MISC_NFI_CE0_PIN ((0x1 << 11))
4535+
4536+#define MISC_EXT_INT2_PIN ((0x1 << 12))
4537+#define MISC_EXT_INT1_PIN ((0x1 << 13))
4538+#define MISC_EXT_INT0_PIN ((0x1 << 14))
4539+
4540+
4541+#define MISC_UART0_PINS ((0x1 << 15) | (0x1 << 16) | (0x1 << 17) | (0x1 << 18))
4542+#define MISC_UART0_RTS_PIN ((0x1 << 15))
4543+#define MISC_UART0_CTS_PIN ((0x1 << 16))
4544+#define MISC_UART0_TXD_PIN ((0x1 << 17))
4545+#define MISC_UART0_RXD_PIN ((0x1 << 18))
4546+
4547+#define MISC_UART1_PINS ((0x1 << 19) | (0x1 << 20) | (0x1 << 21) | (0x1 << 22))
4548+#define MISC_UART1_RTS_PIN ((0x1 << 19))
4549+#define MISC_UART1_CTS_PIN ((0x1 << 20))
4550+#define MISC_UART1_RXD_PIN ((0x1 << 21))
4551+#define MISC_UART1_TXD_PIN ((0x1 << 22))
4552+
4553+#define MISC_UART2_PINS ((0x1 << 23) | (0x1 << 24))
4554+#define MISC_UART2_RXD_PIN ((0x1 << 23))
4555+#define MISC_UART2_TXD_PIN ((0x1 << 24))
4556+
4557+#define MISC_PCM_PINS ((0x1 << 25) | (0x1 << 26) | (0x1 << 27) | (0x1 << 28))
4558+#define MISC_PCM_CLK_PIN ((0x1 << 25))
4559+#define MISC_PCM_FS_PIN ((0x1 << 26))
4560+#define MISC_PCM_DT_PIN ((0x1 << 27))
4561+#define MISC_PCM_DR_PIN ((0x1 << 28))
4562+
4563+#define MISC_SPI_CS1_PIN ((0x1 << 29))
4564+#define MISC_SPI_CS0_PIN ((0x1 << 30))
4565+#define MISC_SPI_CLK_PIN ((0x1 << 31))
4566+#else
4567+#define MISC_SD_PWR_ON_PIN ((0x1 << 2))
4568+#define MISC_OTG_DRVVBUS_PIN ((0x1 << 3))
4569+#define MISC_CIM_OE_PIN ((0x1 << 8))
4570+#define MISC_LCD_PWR_PIN ((0x1 << 9))
4571+#define MISC_SMC_CS3_PIN ((0x1 << 10))
4572+#define MISC_SMC_CS2_PIN ((0x1 << 11))
4573+#define MISC_SMC_CLK_PIN ((0x1 << 12))
4574+#define MISC_SMC_ADV_PIN ((0x1 << 13))
4575+#define MISC_SMC_CRE_PIN ((0x1 << 14))
4576+#define MISC_SMC_ADDR_26_PIN ((0x1 << 15))
4577+
4578+#define MISC_SD_nCD_PIN ((0x1 << 16))
4579+#define MISC_SD_nWP_PIN ((0x1 << 17))
4580+#define MISC_SD_CLK_PIN ((0x1 << 18))
4581+#define MISC_SD_CMD_PIN ((0x1 << 19))
4582+#define MISC_SD_DT7_PIN ((0x1 << 20))
4583+#define MISC_SD_DT6_PIN ((0x1 << 21))
4584+#define MISC_SD_DT5_PIN ((0x1 << 22))
4585+#define MISC_SD_DT4_PIN ((0x1 << 23))
4586+#define MISC_SD_DT3_PIN ((0x1 << 24))
4587+#define MISC_SD_DT2_PIN ((0x1 << 25))
4588+#define MISC_SD_DT1_PIN ((0x1 << 26))
4589+#define MISC_SD_DT0_PIN ((0x1 << 27))
4590+#define MISC_SD_LED_PIN ((0x1 << 28))
4591+
4592+#define MISC_UR_RXD1_PIN ((0x1 << 29))
4593+#define MISC_UR_TXD1_PIN ((0x1 << 30))
4594+#define MISC_UR_RTS2_PIN ((0x1 << 31))
4595+
4596+#endif
4597+
4598+
4599+/*
4600+ * Macro-defines for shared pins with GPIO_B
4601+ */
4602+#if 0
4603+#define MISC_SPI_DT_PIN ((0x1 << 0))
4604+#define MISC_SPI_DR_PIN ((0x1 << 1))
4605+
4606+#define MISC_SD_CD_PIN ((0x1 << 2))
4607+#define MISC_SD_WP_PIN ((0x1 << 3))
4608+#define MISC_SD_CLK_PIN ((0x1 << 4))
4609+#define MISC_SD_CMD_PIN ((0x1 << 5))
4610+#define MISC_SD_DT7_PIN ((0x1 << 6))
4611+#define MISC_SD_DT6_PIN ((0x1 << 7))
4612+#define MISC_SD_DT5_PIN ((0x1 << 8))
4613+#define MISC_SD_DT4_PIN ((0x1 << 9))
4614+#define MISC_SD_DT3_PIN ((0x1 << 10))
4615+#define MISC_SD_DT2_PIN ((0x1 << 11))
4616+#define MISC_SD_DT1_PIN ((0x1 << 12))
4617+#define MISC_SD_DT0_PIN ((0x1 << 13))
4618+#define MISC_SD_LED_PIN ((0x1 << 14))
4619+
4620+
4621+#define MISC_I2S_CLK_PIN ((0x1 << 15))
4622+#define MISC_I2S_FS_PIN ((0x1 << 16))
4623+#define MISC_I2S_DT_PIN ((0x1 << 17))
4624+#define MISC_I2S_DR_PIN ((0x1 << 18))
4625+
4626+//Tim.Liao modify
4627+#define MISC_I2C_SCL_PIN ((0x1 << 19))
4628+#define MISC_I2C_SDA_PIN ((0x1 << 20))
4629+
4630+#define MISC_GSW_P2_CRS_PIN ((0x1 << 21))
4631+#define MISC_GSW_P2_COL_PIN ((0x1 << 22))
4632+#define MISC_GSW_P1_CRS_PIN ((0x1 << 23))
4633+#define MISC_GSW_P1_COL_PIN ((0x1 << 24))
4634+#define MISC_GSW_P0_CRS_PIN ((0x1 << 25))
4635+#define MISC_GSW_P0_COL_PIN ((0x1 << 26))
4636+
4637+#define MISC_GSW_MDC_PIN ((0x1 << 27))
4638+#define MISC_GSW_MDIO_PIN ((0x1 << 28))
4639+
4640+#define MISC_CLOCK_OUTPUT_PIN ((0x1 << 29))
4641+
4642+#define MISC_SATA_LED1_PIN ((0x1 << 30))
4643+#define MISC_SATA_LED0_PIN ((0x1 << 31))
4644+#else
4645+#define MISC_UR_CTS2_PIN ((0x1 << 0))
4646+#define MISC_UR_RXD2_PIN ((0x1 << 1))
4647+#define MISC_UR_TXD2_PIN ((0x1 << 2))
4648+#define MISC_PCMCLK_PIN ((0x1 << 3))
4649+#define MISC_PCMFS_PIN ((0x1 << 4))
4650+#define MISC_PCMDT_PIN ((0x1 << 5))
4651+#define MISC_PCMDR_PIN ((0x1 << 6))
4652+#define MISC_PCM_PINS (MISC_PCMCLK_PIN|MISC_PCMFS_PIN|MISC_PCMDT_PIN|MISC_PCMDR_PIN)
4653+
4654+#define MISC_SPInCS1_PIN ((0x1 << 7))
4655+#define MISC_SPInCS0_PIN ((0x1 << 8))
4656+#define MISC_SPICLK_PIN ((0x1 << 9))
4657+#define MISC_SPIDT_PIN ((0x1 << 10))
4658+#define MISC_SPIDR_PIN ((0x1 << 11))
4659+
4660+#define MISC_I2C_SCL_PIN ((0x1 << 12))
4661+#define MISC_I2C_SDA_PIN ((0x1 << 13))
4662+
4663+#define MISC_GSW_P2_CRS_PIN ((0x1 << 14))
4664+#define MISC_GSW_P2_COL_PIN ((0x1 << 15))
4665+#define MISC_GSW_P1_CRS_PIN ((0x1 << 16))
4666+#define MISC_GSW_P1_COL_PIN ((0x1 << 17))
4667+#define MISC_GSW_P0_CRS_PIN ((0x1 << 18))
4668+#define MISC_GSW_P0_COL_PIN ((0x1 << 19))
4669+
4670+#define MISC_GSW_MDC_PIN ((0x1 << 20))
4671+#define MISC_GSW_MDIO_PIN ((0x1 << 21))
4672+
4673+#define MISC_I2S_CLK_PIN (0x1 << 22)
4674+#define MISC_I2S_FS_PIN (0x1 << 23)
4675+#define MISC_I2S_DT_PIN (0x1 << 24)
4676+#define MISC_I2S_DR_PIN (0x1 << 25)
4677+
4678+#define MISC_CLOCK_OUTPUT_PIN ((0x1 << 26))
4679+
4680+#define MISC_EXT_INT2_PIN ((0x1 << 27))
4681+#define MISC_EXT_INT1_PIN ((0x1 << 28))
4682+#define MISC_EXT_INT0_PIN ((0x1 << 29))
4683+
4684+#define MISC_SATA_LED1_PIN ((0x1 << 30))
4685+#define MISC_SATA_LED0_PIN ((0x1 << 31))
4686+
4687+#define MISC_CLOCK_OUTPUT_PIN ((0x1 << 26))
4688+
4689+#define MISC_EXT_INT2_PIN ((0x1 << 27))
4690+#define MISC_EXT_INT1_PIN ((0x1 << 28))
4691+#define MISC_EXT_INT0_PIN ((0x1 << 29))
4692+
4693+#define MISC_SATA_LED1_PIN ((0x1 << 30))
4694+#define MISC_SATA_LED0_PIN ((0x1 << 31))
4695+
4696+#define MISC_CLOCK_OUTPUT_PIN ((0x1 << 26))
4697+
4698+#define MISC_EXT_INT2_PIN ((0x1 << 27))
4699+#define MISC_EXT_INT1_PIN ((0x1 << 28))
4700+#define MISC_EXT_INT0_PIN ((0x1 << 29))
4701+
4702+#define MISC_SATA_LED1_PIN ((0x1 << 30))
4703+#define MISC_SATA_LED0_PIN ((0x1 << 31))
4704+
4705+#define MISC_CLOCK_OUTPUT_PIN ((0x1 << 26))
4706+
4707+#define MISC_EXT_INT2_PIN ((0x1 << 27))
4708+#define MISC_EXT_INT1_PIN ((0x1 << 28))
4709+#define MISC_EXT_INT0_PIN ((0x1 << 29))
4710+
4711+#define MISC_SATA_LED1_PIN ((0x1 << 30))
4712+#define MISC_SATA_LED0_PIN ((0x1 << 31))
4713+
4714+#define MISC_CLOCK_OUTPUT_PIN ((0x1 << 26))
4715+
4716+#define MISC_EXT_INT2_PIN ((0x1 << 27))
4717+#define MISC_EXT_INT1_PIN ((0x1 << 28))
4718+#define MISC_EXT_INT0_PIN ((0x1 << 29))
4719+
4720+#define MISC_SATA_LED1_PIN ((0x1 << 30))
4721+#define MISC_SATA_LED0_PIN ((0x1 << 31))
4722+
4723+#define MISC_CLOCK_OUTPUT_PIN ((0x1 << 26))
4724+
4725+#define MISC_EXT_INT2_PIN ((0x1 << 27))
4726+#define MISC_EXT_INT1_PIN ((0x1 << 28))
4727+#define MISC_EXT_INT0_PIN ((0x1 << 29))
4728+
4729+#define MISC_SATA_LED1_PIN ((0x1 << 30))
4730+#define MISC_SATA_LED0_PIN ((0x1 << 31))
4731+
4732+#define MISC_CLOCK_OUTPUT_PIN ((0x1 << 26))
4733+
4734+#define MISC_EXT_INT2_PIN ((0x1 << 27))
4735+#define MISC_EXT_INT1_PIN ((0x1 << 28))
4736+#define MISC_EXT_INT0_PIN ((0x1 << 29))
4737+
4738+#define MISC_SATA_LED1_PIN ((0x1 << 30))
4739+#define MISC_SATA_LED0_PIN ((0x1 << 31))
4740+
4741+#endif
4742+/*
4743+ * Other defines
4744+ */
4745+#define MISC_GPIOA_PIN_0 (0)
4746+#define MISC_GPIOA_PIN_1 (1)
4747+#define MISC_GPIOA_PIN_2 (2)
4748+#define MISC_GPIOA_PIN_3 (3)
4749+#define MISC_GPIOA_PIN_4 (4)
4750+#define MISC_GPIOA_PIN_5 (5)
4751+#define MISC_GPIOA_PIN_6 (6)
4752+#define MISC_GPIOA_PIN_7 (7)
4753+#define MISC_GPIOA_PIN_8 (8)
4754+#define MISC_GPIOA_PIN_9 (9)
4755+#define MISC_GPIOA_PIN_10 (10)
4756+#define MISC_GPIOA_PIN_11 (11)
4757+#define MISC_GPIOA_PIN_12 (12)
4758+#define MISC_GPIOA_PIN_13 (13)
4759+#define MISC_GPIOA_PIN_14 (14)
4760+#define MISC_GPIOA_PIN_15 (15)
4761+
4762+
4763+#define MISC_GPIOA_RESISTOR_PULL_DOWN (1)
4764+#define MISC_GPIOA_RESISTOR_PULL_UP (1)
4765+
4766+
4767+
4768+/*
4769+ * function declarations
4770+ */
4771+
4772+
4773+/*
4774+ * macro declarations
4775+ */
4776+#define HAL_MISC_GET_SYSTEM_ALIGN_ENDIAN_MODE(mode) \
4777+{ \
4778+ (mode) = (MISC_CHIP_CONFIG_REG) & 0x3; \
4779+}
4780+
4781+
4782+#define HAL_MISC_GET_SYSTEM_CPU_CLOCK(cpu_clock) \
4783+{ \
4784+ (cpu_clock) = (MISC_CHIP_CONFIG_REG >> 5) & 0xF; \
4785+}
4786+
4787+
4788+#define HAL_MISC_ENABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
4789+{ \
4790+ (MISC_CHIP_CONFIG_REG) |= (0x1 << 16); \
4791+}
4792+
4793+#define HAL_MISC_DISABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
4794+{ \
4795+ (MISC_CHIP_CONFIG_REG) &= ~(0x1 << 16); \
4796+}
4797+
4798+
4799+/*
4800+ * Macro defines for GPIOA and GPIOB Pin Enable Register
4801+ */
4802+#define HAL_MISC_ENABLE_EXT_INT0_PIN() \
4803+{ \
4804+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_EXT_INT0_PIN); \
4805+}
4806+
4807+#define HAL_MISC_DISABLE_EXT_INT1_PIN() \
4808+{ \
4809+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_EXT_INT1_PIN); \
4810+}
4811+
4812+#define HAL_MISC_ENABLE_EXT_INT2_PIN() \
4813+{ \
4814+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_EXT_INT2_PIN); \
4815+}
4816+
4817+#define HAL_MISC_DISABLE_EXT_INT2_PIN() \
4818+{ \
4819+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_EXT_INT2_PIN); \
4820+}
4821+
4822+#define HAL_MISC_ENABLE_EXT_INT1_PIN() \
4823+{ \
4824+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_EXT_INT1_PIN); \
4825+}
4826+
4827+#define HAL_MISC_DISABLE_EXT_INT0_PIN() \
4828+{ \
4829+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_EXT_INT0_PIN); \
4830+}
4831+
4832+
4833+#define HAL_MISC_ENABLE_PCM_PINS() \
4834+{ \
4835+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCM_PINS); \
4836+}
4837+
4838+#define HAL_MISC_DISABLE_PCM_PINS() \
4839+{ \
4840+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCM_PINS); \
4841+}
4842+
4843+
4844+#define HAL_MISC_ENABLE_CIM_OE_PIN() \
4845+{ \
4846+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_CIM_OE_PIN); \
4847+}
4848+
4849+#define HAL_MISC_DISABLE_CIM_OE_PIN() \
4850+{ \
4851+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_CIM_OE_PIN); \
4852+}
4853+
4854+
4855+#define HAL_MISC_ENABLE_LCD_PWR_PIN() \
4856+{ \
4857+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LCD_PWR_PIN); \
4858+}
4859+
4860+#define HAL_MISC_DISABLE_LCD_PWR_PIN() \
4861+{ \
4862+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LCD_PWR_PIN); \
4863+}
4864+
4865+
4866+#define HAL_MISC_ENABLE_NFI_PINS() \
4867+{ \
4868+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_NFI_PINS); \
4869+}
4870+
4871+#define HAL_MISC_DISABLE_NFI_PINS() \
4872+{ \
4873+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_NFI_PINS); \
4874+}
4875+
4876+
4877+
4878+#define HAL_MISC_ENABLE_SMC_PINS() \
4879+{ \
4880+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SMC_PINS); \
4881+}
4882+
4883+#define HAL_MISC_DISABLE_SMC_PINS() \
4884+{ \
4885+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SMC_PINS); \
4886+}
4887+
4888+#define HAL_MISC_ENABLE_UART0_PINS() \
4889+{ \
4890+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART0_PINS); \
4891+}
4892+
4893+#define HAL_MISC_DISABLE_UART0_PINS() \
4894+{ \
4895+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART0_PINS); \
4896+}
4897+
4898+#define HAL_MISC_ENABLE_UART1_PINS() \
4899+{ \
4900+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART1_PINS); \
4901+}
4902+
4903+#define HAL_MISC_DISABLE_UART1_PINS() \
4904+{ \
4905+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART1_PINS); \
4906+}
4907+
4908+#define HAL_MISC_ENABLE_UART2_PINS() \
4909+{ \
4910+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART2_PINS); \
4911+}
4912+
4913+#define HAL_MISC_DISABLE_UART2_PINS() \
4914+{ \
4915+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART2_PINS); \
4916+}
4917+
4918+
4919+
4920+
4921+
4922+/*
4923+ * Macro-defines for GPIO_B
4924+ */
4925+#define HAL_MISC_ENABLE_SPI_PINS() \
4926+{ \
4927+ (MISC_GPIOB_PIN_ENABLE_REG) |= \
4928+ (MISC_SPInCS1_PIN | MISC_SPInCS0_PIN | \
4929+ MISC_SPICLK_PIN | MISC_SPIDT_PIN | MISC_SPIDR_PIN); \
4930+}
4931+
4932+#define HAL_MISC_DISABLE_SPI_PINS() \
4933+{ \
4934+ (MISC_GPIOB_PIN_ENABLE_REG) &= \
4935+ ~(MISC_SPInCS1_PIN | MISC_SPInCS0_PIN | \
4936+ MISC_SPICLK_PIN | MISC_SPIDT_PIN | MISC_SPIDR_PIN); \
4937+}
4938+
4939+#define HAL_MISC_ENABLE_SD_PINS() \
4940+{ \
4941+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SD_CD_PIN | MISC_SD_WP_PIN | MISC_SD_CLK_PIN |MISC_SD_CMD_PIN |MISC_SD_DT7_PIN|MISC_SD_DT6_PIN | \
4942+ MISC_SD_DT5_PIN | MISC_SD_DT4_PIN |MISC_SD_DT3_PIN | MISC_SD_DT2_PIN| MISC_SD_DT1_PIN | MISC_SD_DT0_PIN | MISC_SD_LED_PIN); \
4943+}
4944+
4945+#define HAL_MISC_DISABLE_SD_PINS() \
4946+{ \
4947+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SD_CD_PIN | MISC_SD_WP_PIN | MISC_SD_CLK_PIN |MISC_SD_CMD_PIN |MISC_SD_DT7_PIN|MISC_SD_DT6_PIN |\
4948+ MISC_SD_DT5_PIN | MISC_SD_DT4_PIN |MISC_SD_DT3_PIN | MISC_SD_DT2_PIN| MISC_SD_DT1_PIN | MISC_SD_DT0_PIN | MISC_SD_LED_PIN); \
4949+}
4950+
4951+
4952+#define HAL_MISC_ENABLE_I2S_PINS() \
4953+{ \
4954+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_I2S_CLK_PIN | MISC_I2S_FS_PIN | MISC_I2S_DT_PIN |MISC_I2S_DR_PIN |MISC_I2S_DR_PIN); \
4955+}
4956+
4957+#define HAL_MISC_DISABLE_I2S_PINS() \
4958+{ \
4959+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_I2S_CLK_PIN | MISC_I2S_FS_PIN | MISC_I2S_DT_PIN |MISC_I2S_DR_PIN |MISC_I2S_DR_PIN); \
4960+}
4961+
4962+//Tim.Liao modify I2C pin
4963+#define HAL_MISC_ENABLE_I2C_PINS() \
4964+{ \
4965+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2C_SCL_PIN | MISC_I2C_SDA_PIN); \
4966+}
4967+
4968+#define HAL_MISC_DISABLE_I2C_PINS() \
4969+{ \
4970+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2C_SCL_PIN | MISC_I2C_SDA_PIN); \
4971+}
4972+
4973+#define HAL_MISC_ENABLE_GSW_P2_CRS_COL_PINS() \
4974+{ \
4975+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_GSW_P2_CRS_PIN | MISC_GSW_P2_COL_PIN); \
4976+}
4977+
4978+#define HAL_MISC_DISABLE_GSW_P2_CRS_COL_PINS() \
4979+{ \
4980+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_GSW_P2_CRS_PIN | MISC_GSW_P2_COL_PIN); \
4981+}
4982+
4983+
4984+#define HAL_MISC_ENABLE_GSW_P1_CRS_COL_PINS() \
4985+{ \
4986+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_GSW_P1_CRS_PIN | MISC_GSW_P1_COL_PIN); \
4987+}
4988+
4989+#define HAL_MISC_DISABLE_GSW_P1_CRS_COL_PINS() \
4990+{ \
4991+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_GSW_P1_CRS_PIN | MISC_GSW_P1_COL_PIN); \
4992+}
4993+
4994+
4995+
4996+#define HAL_MISC_ENABLE_GSW_P0_CRS_COL_PINS() \
4997+{ \
4998+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_GSW_P0_CRS_PIN | MISC_GSW_P0_COL_PIN); \
4999+}
5000+
5001+#define HAL_MISC_DISABLE_GSW_P0_CRS_COL_PINS() \
5002+{ \
5003+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_GSW_P0_CRS_PIN | MISC_GSW_P0_COL_PIN); \
5004+}
5005+
5006+
5007+#define HAL_MISC_ENABLE_MDC_MDIO_PINS() \
5008+{ \
5009+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_GSW_MDC_PIN | MISC_GSW_MDIO_PIN); \
5010+}
5011+
5012+#define HAL_MISC_DISABLE_MDC_MDIO_PINS() \
5013+{ \
5014+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_GSW_MDC_PIN | MISC_GSW_MDIO_PIN); \
5015+}
5016+
5017+
5018+
5019+#define HAL_MISC_ENABLE_SATA_LED_PINS() \
5020+{ \
5021+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SATA_LED1_PIN | MISC_SATA_LED0_PIN); \
5022+}
5023+
5024+#define HAL_MISC_DISABLE_SATA_LED_PINS() \
5025+{ \
5026+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SATA_LED1_PIN | MISC_SATA_LED0_PIN); \
5027+}
5028+
5029+
5030+
5031+#define HAL_MISC_ENABLE_CLOCK_OUTPUT_PIN() \
5032+{ \
5033+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_CLOCK_OUTPUT_PIN); \
5034+}
5035+
5036+#define HAL_MISC_DISABLE_CLOCK_OUTPUT_PIN() \
5037+{ \
5038+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_CLOCK_OUTPUT_PIN); \
5039+}
5040+
5041+
5042+#define HAL_MISC_ENABLE_ALL_SHARED_GPIO_PINS() \
5043+{ \
5044+ (MISC_GPIOA_PIN_ENABLE_REG) = (0x0); \
5045+ (MISC_GPIOB_PIN_ENABLE_REG) = (0x0); \
5046+}
5047+
5048+#define HAL_MISC_DISABLE_ALL_SHARED_GPIO_PINS() \
5049+{ \
5050+ (MISC_GPIOA_PIN_ENABLE_REG) = (0xFFFFFFFF); \
5051+ (MISC_GPIOB_PIN_ENABLE_REG) = (0xFFFFFFFF); \
5052+}
5053+
5054+
5055+
5056+#endif // end of #ifndef _STAR_MISC_H_
5057--- /dev/null
5058+++ b/arch/arm/mach-cns3xxx/include/mach/pcie.h
5059@@ -0,0 +1,149 @@
5060+/*******************************************************************************
5061+ *
5062+ * Copyright (c) 2008 Cavium Networks
5063+ *
5064+ * This file is free software; you can redistribute it and/or modify
5065+ * it under the terms of the GNU General Public License, Version 2, as
5066+ * published by the Free Software Foundation.
5067+ *
5068+ * This file is distributed in the hope that it will be useful,
5069+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
5070+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
5071+ * NONINFRINGEMENT. See the GNU General Public License for more details.
5072+ *
5073+ * You should have received a copy of the GNU General Public License
5074+ * along with this file; if not, write to the Free Software
5075+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
5076+ * visit http://www.gnu.org/licenses/.
5077+ *
5078+ * This file may also be available under a different license from Cavium.
5079+ * Contact Cavium Networks for more information
5080+ *
5081+ ******************************************************************************/
5082+
5083+#ifndef _CNS3XXX_PCIE_H_
5084+#define _CNS3XXX_PCIE_H_
5085+
5086+#include "mach/board.h"
5087+
5088+#define PCIE0_IO_SPACE_START (CNS3XXX_PCIE0_IO_BASE)
5089+#define PCIE0_IO_SPACE_SIZE 0x01000000 /* 16MB */
5090+#define PCIE0_IO_SPACE_END (CNS3XXX_PCIE0_IO_BASE + PCIE0_IO_SPACE_SIZE - 1)
5091+
5092+#define PCIE0_MEM_SPACE_START (CNS3XXX_PCIE0_MEM_BASE)
5093+#define PCIE0_MEM_SPACE_SIZE 0x01000000 /* 176MB */
5094+#define PCIE0_MEM_SPACE_END (CNS3XXX_PCIE0_MEM_BASE + PCIE0_MEM_SPACE_SIZE - 1)
5095+
5096+#define PCIE1_IO_SPACE_START (CNS3XXX_PCIE1_IO_BASE)
5097+#define PCIE1_IO_SPACE_SIZE 0x01000000 /* 16MB */
5098+#define PCIE1_IO_SPACE_END (CNS3XXX_PCIE1_IO_BASE + PCIE1_IO_SPACE_SIZE - 1)
5099+
5100+#define PCIE1_MEM_SPACE_START (CNS3XXX_PCIE1_MEM_BASE)
5101+#define PCIE1_MEM_SPACE_SIZE 0x01000000 /* 16MB */
5102+#define PCIE1_MEM_SPACE_END (CNS3XXX_PCIE1_MEM_BASE + PCIE1_MEM_SPACE_SIZE - 1)
5103+
5104+#define PCIB_MEM_MAP_VALUE(base, reg_offset) (*((u32 volatile *)(SYSVA_PCI_BRIDGE_##base##_ADDR + reg_offset)))
5105+
5106+/*
5107+ * define access macros
5108+ */
5109+#define PCI_BRIDGE_CONFIG_DATA PCIB_MEM_MAP_VALUE(CONFIG_DATA_BASE, 0x2C)
5110+#define PCI_BRIDGE_CONFIG_ADDR PCIB_MEM_MAP_VALUE(CONFIG_ADDR_BASE, 0x28)
5111+
5112+#define PCI_BRIDGE_CONFIG_DATA_REG_OFFSET 0x2C
5113+#define PCI_BRIDGE_CONFIG_ADDR_REG_OFFSET 0x28
5114+
5115+
5116+/* PCIe MISC 0 Register */
5117+#define CNS3XXX_PCIEPHY0_CMCTL0 (CNS3XXX_MISC_BASE_VIRT + 0x900)
5118+#define CNS3XXX_PCIEPHY0_CMCTL1 (CNS3XXX_MISC_BASE_VIRT + 0x904)
5119+#define CNS3XXX_PCIEPHY0_CTL1 (CNS3XXX_MISC_BASE_VIRT + 0x940)
5120+#define CNS3XXX_PCIE0_AXIS_AWMISC (CNS3XXX_MISC_BASE_VIRT + 0x944)
5121+#define CNS3XXX_PCIE0_AXIS_ARMISC (CNS3XXX_MISC_BASE_VIRT + 0x948)
5122+#define CNS3XXX_PCIE0_AXIS_RMISC (CNS3XXX_MISC_BASE_VIRT + 0x94C)
5123+#define CNS3XXX_PCIE0_AXIS_BMISC (CNS3XXX_MISC_BASE_VIRT + 0x950)
5124+#define CNS3XXX_PCIE0_AXIM_RMISC (CNS3XXX_MISC_BASE_VIRT + 0x954)
5125+#define CNS3XXX_PCIE0_AXIM_BMISC (CNS3XXX_MISC_BASE_VIRT + 0x958)
5126+#define CNS3XXX_PCIE0_CTRL (CNS3XXX_MISC_BASE_VIRT + 0x95C)
5127+#define CNS3XXX_PCIE0_PM_DEBUG (CNS3XXX_MISC_BASE_VIRT + 0x960)
5128+#define CNS3XXX_PCIE0_RFC_DEBUG (CNS3XXX_MISC_BASE_VIRT + 0x964)
5129+#define CNS3XXX_PCIE0_CXPL_DEBUGL (CNS3XXX_MISC_BASE_VIRT + 0x968)
5130+#define CNS3XXX_PCIE0_CXPL_DEBUGH (CNS3XXX_MISC_BASE_VIRT + 0x96C)
5131+#define CNS3XXX_PCIE0_DIAG (CNS3XXX_MISC_BASE_VIRT + 0x970)
5132+#define CNS3XXX_PCIE0_INT_STATUS (CNS3XXX_MISC_BASE_VIRT + 0x974)
5133+#define CNS3XXX_PCIE0_INT_MASK (CNS3XXX_MISC_BASE_VIRT + 0x978)
5134+
5135+
5136+/* PCIe MISC 1 Register */
5137+#define CNS3XXX_PCIEPHY1_CMCTL0 (CNS3XXX_MISC_BASE_VIRT + 0xA00)
5138+#define CNS3XXX_PCIEPHY1_CMCTL1 (CNS3XXX_MISC_BASE_VIRT + 0xA04)
5139+#define CNS3XXX_PCIEPHY1_CTL1 (CNS3XXX_MISC_BASE_VIRT + 0xA40)
5140+#define CNS3XXX_PCIE1_AXIS_AWMISC (CNS3XXX_MISC_BASE_VIRT + 0xA44)
5141+#define CNS3XXX_PCIE1_AXIS_ARMISC (CNS3XXX_MISC_BASE_VIRT + 0xA48)
5142+#define CNS3XXX_PCIE1_AXIS_RMISC (CNS3XXX_MISC_BASE_VIRT + 0xA4C)
5143+#define CNS3XXX_PCIE1_AXIS_BMISC (CNS3XXX_MISC_BASE_VIRT + 0xA50)
5144+#define CNS3XXX_PCIE1_AXIM_RMISC (CNS3XXX_MISC_BASE_VIRT + 0xA54)
5145+#define CNS3XXX_PCIE1_AXIM_BMISC (CNS3XXX_MISC_BASE_VIRT + 0x958)
5146+#define CNS3XXX_PCIE1_CTRL (CNS3XXX_MISC_BASE_VIRT + 0xA5C)
5147+#define CNS3XXX_PCIE1_PM_DEBUG (CNS3XXX_MISC_BASE_VIRT + 0xA60)
5148+#define CNS3XXX_PCIE1_RFC_DEBUG (CNS3XXX_MISC_BASE_VIRT + 0xA64)
5149+#define CNS3XXX_PCIE1_CXPL_DEBUGL (CNS3XXX_MISC_BASE_VIRT + 0xA68)
5150+#define CNS3XXX_PCIE1_CXPL_DEBUGH (CNS3XXX_MISC_BASE_VIRT + 0xA6C)
5151+#define CNS3XXX_PCIE1_DIAG (CNS3XXX_MISC_BASE_VIRT + 0xA70)
5152+#define CNS3XXX_PCIE1_INT_STATUS (CNS3XXX_MISC_BASE_VIRT + 0xA74)
5153+#define CNS3XXX_PCIE1_INT_MASK (CNS3XXX_MISC_BASE_VIRT + 0xA78)
5154+
5155+
5156+/*
5157+ * define constants macros
5158+ */
5159+
5160+#define PCIB_DEVICE_ID 0x3400
5161+#define PCIB_VENDOR_ID 0x177D
5162+#define PCIB_CLASS_CODE 0xFF0000
5163+#define PCIB_REVISION_ID 0x00
5164+#define PCIB_BAR0_MEMORY_SPACE_BASE 0x20000000
5165+#define PCIB_BAR1_IO_SPACE_BASE 0x20000000
5166+#define PCI_MEMORY_SPACE_BASE 0xB0000000
5167+#define PCI_IO_SPACE_BASE 0xA8000000
5168+#define PCI_MAX_BUS_NUM 0x01
5169+#define PCI_MAX_DEVICE_NUM 0x14
5170+#define PCI_MAX_FUNCTION_NUM 0x01
5171+#define PCI_MAX_REG_NUM 0x3C
5172+
5173+#define PCI_MAX_DEVICE_TYPE_NUM 0x13
5174+#define PCI_MAX_BAR_NUM 0x06
5175+
5176+#define PCI_CSH_VENDOR_ID_REG_ADDR 0x00
5177+#define PCI_CSH_DEVICE_ID_REG_ADDR 0x02
5178+#define PCI_CSH_COMMAND_REG_ADDR 0x04
5179+#define PCI_CSH_STATUS_REG_ADDR 0x06
5180+#define PCI_CSH_REVISION_CLASS_REG_ADDR 0x08
5181+#define PCI_CSH_CACHE_LINE_SIZE_REG_ADDR 0x0C
5182+#define PCI_CSH_LATENCY_TIMER_REG_ADDR 0x0D
5183+#define PCI_CSH_HEADER_TYPE_REG_ADDR 0x0E
5184+#define PCI_CSH_BIST_REG_ADDR 0x0F
5185+#define PCI_CSH_BAR_REG_ADDR 0x10
5186+
5187+
5188+#define PCI_IO_SPACE_SIZE_1M 0x00
5189+#define PCI_IO_SPACE_SIZE_2M 0x01
5190+#define PCI_IO_SPACE_SIZE_4M 0x02
5191+#define PCI_IO_SPACE_SIZE_8M 0x03
5192+#define PCI_IO_SPACE_SIZE_16M 0x04
5193+#define PCI_IO_SPACE_SIZE_32M 0x05
5194+#define PCI_IO_SPACE_SIZE_64M 0x06
5195+#define PCI_IO_SPACE_SIZE_128M 0x07
5196+#define PCI_IO_SPACE_SIZE_256M 0x08
5197+#define PCI_IO_SPACE_SIZE_512M 0x09
5198+#define PCI_IO_SPACE_SIZE_1G 0x0A
5199+#define PCI_IO_SPACE_SIZE_2G 0x0B
5200+
5201+
5202+struct pcie_dbgfs_reg{
5203+ char *name;
5204+ u32 *addr;
5205+};
5206+
5207+#endif /* end of #ifndef _STAR_PCIE_H_ */
5208+
5209--- /dev/null
5210+++ b/arch/arm/mach-cns3xxx/include/mach/pcm.h
5211@@ -0,0 +1,277 @@
5212+/******************************************************************************
5213+ *
5214+ * Copyright (c) 2008 Cavium Networks
5215+ *
5216+ * This file is free software; you can redistribute it and/or modify
5217+ * it under the terms of the GNU General Public License, Version 2, as
5218+ * published by the Free Software Foundation.
5219+ *
5220+ * This file is distributed in the hope that it will be useful,
5221+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
5222+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
5223+ * NONINFRINGEMENT. See the GNU General Public License for more details.
5224+ *
5225+ * You should have received a copy of the GNU General Public License
5226+ * along with this file; if not, write to the Free Software
5227+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
5228+ * visit http://www.gnu.org/licenses/.
5229+ *
5230+ * This file may also be available under a different license from Cavium.
5231+ * Contact Cavium Networks for more information
5232+ *
5233+ ******************************************************************************/
5234+
5235+#ifndef _STAR_PCM_H_
5236+#define _STAR_PCM_H_
5237+
5238+/******************************************************************************
5239+ * MODULE NAME: star_pcm.h
5240+ * PROJECT CODE: Orion
5241+ * DESCRIPTION:
5242+ * MAINTAINER: MJLIU
5243+ * DATE: 15 September 2005
5244+ *
5245+ * SOURCE CONTROL:
5246+ *
5247+ * LICENSE:
5248+ * This source code is copyright (c) 2005 Star Semi Inc.
5249+ * All rights reserved.
5250+ *
5251+ * REVISION HISTORY:
5252+ * 15 September 2005 - MJLIU - Initial Version v1.0
5253+ *
5254+ *
5255+ * SOURCE:
5256+ * ISSUES:
5257+ * NOTES TO USERS:
5258+ ******************************************************************************/
5259+
5260+//#include <asm/arch/star_sys_memory_map.h>
5261+
5262+#define PCM_BASE_ADDR (CNS3XXX_SSP_BASE_VIRT)
5263+#define PCM_MEM_MAP_ADDR(reg_offset) (PCM_BASE_ADDR + reg_offset)
5264+#define PCM_MEM_MAP_VALUE(reg_offset) (*((u32 volatile *)PCM_MEM_MAP_ADDR(reg_offset)))
5265+
5266+
5267+/*
5268+ * define access macros
5269+ */
5270+#define PCM_CONFIGURATION_0_REG PCM_MEM_MAP_VALUE(0x80)
5271+#define PCM_CONFIGURATION_1_REG PCM_MEM_MAP_VALUE(0x84)
5272+
5273+#define PCM_CHANNEL_0_CONFIG_REG PCM_MEM_MAP_VALUE(0x88)
5274+#define PCM_CHANNEL_1_CONFIG_REG PCM_MEM_MAP_VALUE(0x8C)
5275+#define PCM_CHANNEL_2_CONFIG_REG PCM_MEM_MAP_VALUE(0x90)
5276+#define PCM_CHANNEL_3_CONFIG_REG PCM_MEM_MAP_VALUE(0x94)
5277+
5278+#define PCM_TX_DATA_31_0_REG PCM_MEM_MAP_VALUE(0x98)
5279+#define PCM_TX_DATA_63_32_REG PCM_MEM_MAP_VALUE(0x9C)
5280+
5281+#define PCM_RX_DATA_31_0_REG PCM_MEM_MAP_VALUE(0xA0)
5282+#define PCM_RX_DATA_63_32_REG PCM_MEM_MAP_VALUE(0xA4)
5283+
5284+#define PCM_INTERRUPT_STATUS_REG PCM_MEM_MAP_VALUE(0xA8)
5285+#define PCM_INTERRUPT_ENABLE_REG PCM_MEM_MAP_VALUE(0xAC)
5286+
5287+
5288+
5289+/*
5290+ * define constants macros
5291+ */
5292+#define CH0_BIT_INDEX (0x1)
5293+#define CH1_BIT_INDEX (0x2)
5294+#define CH2_BIT_INDEX (0x4)
5295+#define CH3_BIT_INDEX (0x8)
5296+
5297+#define PCM_RXBUF_FULL_FG (0x1)
5298+#define PCM_TXBUF_EMPTY_FG (0x2)
5299+#define PCM_RXBUF_OVERRUN_FG (0x4)
5300+#define PCM_TXBUF_UNDERRUN_FG (0x8)
5301+
5302+#define PCM_ENABLE_FG (0x1 << 23)
5303+
5304+#define PCM_IDL_MODE (0)
5305+#define PCM_GCI_MODE (1)
5306+
5307+#define PCM_DATA_BIT_8 (0)
5308+#define PCM_DATA_BIT_16 (1)
5309+
5310+
5311+/*
5312+ * Set Commands Variables
5313+ */
5314+#define Software_Reset (0x02)
5315+#define Hardware_Reset (0x04)
5316+#define Write_Transmit_Time_Slot (0x40)
5317+#define Read_Transmit_Time_Slot (0x41)
5318+#define Write_Receive_Time_Slot (0x42)
5319+#define Read_Receive_Time_Slot (0x43)
5320+#define Write_Tx_Rx_CLK_Slot_Tx_CLK_Edge (0x44)
5321+#define Read_Tx_Rx_CLK_Slot_Tx_CLK_Edge (0x45)
5322+#define Write_Device_Configure_Reg (0x46)
5323+#define Read_Device_Configure_Reg (0x47)
5324+#define Write_Channel_Enable_Operating_Mode_Reg (0x4A)
5325+#define Read_Channel_Enable_Operating_Mode_Reg (0x4B)
5326+#define Read_Signal_Reg (0x4D)
5327+#define Input_Data_Reg (0x52)
5328+#define Output_Data_Reg (0x53)
5329+#define Input_Direction_Reg (0x54)
5330+#define Output_Direction_Reg (0x55)
5331+#define Write_System_State (0x56)
5332+#define Read_System_State (0x57)
5333+#define Write_Operating_Functon (0x60)
5334+#define Read_Operating_Functon (0x61)
5335+#define Write_System_State_Config (0x68)
5336+#define Read_System_State_Config (0x69)
5337+#define Write_Interrupt_Mask_Reg (0x6C)
5338+#define Read_Interrupt_Mask_Reg (0x6D)
5339+#define Write_Operating_Condition (0x70)
5340+#define Write_Loop_Supervision_Parameter (0xC2)
5341+#define Write_DC_Feed_Parameter (0xC6)
5342+#define Write_Signal_A_B_Parameter (0xD2)
5343+#define Write_Switching_Reg_Parameter (0xE4)
5344+#define Write_Switching_Reg_Control (0xE6)
5345+
5346+
5347+/*
5348+ * define data structure
5349+ */
5350+typedef struct _PCM_CHANNEL_OBJECT_ PCM_CHANNEL_OBJECT_T;
5351+
5352+struct _PCM_CHANNEL_OBJECT_
5353+{
5354+ u16 channel_0_tx_data;
5355+ u16 channel_0_rx_data;
5356+ u32 channel_0_data_width; /* 0 : 8-bit, 1 : 16-bit */
5357+
5358+ u16 channel_1_tx_data;
5359+ u16 channel_1_rx_data;
5360+ u32 channel_1_data_width;
5361+
5362+ u16 channel_2_tx_data;
5363+ u16 channel_2_rx_data;
5364+ u32 channel_2_data_width;
5365+
5366+ u16 channel_3_tx_data;
5367+ u16 channel_3_rx_data;
5368+ u32 channel_3_data_width;
5369+
5370+ u32 channel_enable_config; /* bit[0] = 0 : channel 0 disabled
5371+ [0] = 1 : channel 0 enabled
5372+ bit[1] = 0 : channel 1 disabled
5373+ [1] = 1 : channel 1 enabled
5374+ bit[2] = 0 : channel 2 disabled
5375+ [2] = 1 : channel 2 enabled
5376+ bit[3] = 0 : channel 3 disabled
5377+ [3] = 1 : channel 3 enabled */
5378+};
5379+
5380+
5381+typedef struct _PCM_OBJECT_ PCM_OBJECT_T;
5382+
5383+struct _PCM_OBJECT_
5384+{
5385+ u32 config_0;
5386+ u32 config_1;
5387+
5388+ u32 channel_0_config;
5389+ u32 channel_1_config;
5390+ u32 channel_2_config;
5391+ u32 channel_3_config;
5392+
5393+ u32 interrupt_config;
5394+
5395+ /*
5396+ * For interrupt setting
5397+ */
5398+// INTC_OBJECT_T intc_obj;
5399+};
5400+
5401+
5402+
5403+/*
5404+ * function declarations
5405+ */
5406+void Hal_Pcm_Initialize(PCM_OBJECT_T *);
5407+
5408+
5409+/*
5410+ * macro declarations
5411+ */
5412+#define HAL_PCM_ENABLE_PCM() \
5413+{ \
5414+ (PCM_CONFIGURATION_0_REG) |= ((u32)0x1 << 31); \
5415+}
5416+
5417+#define HAL_PCM_DISABLE_PCM() \
5418+{ \
5419+ (PCM_CONFIGURATION_0_REG) &= ~((u32)0x1 << 31); \
5420+}
5421+
5422+#define HAL_PCM_ENABLE_DATA_SWAP() \
5423+{ \
5424+ (PCM_CONFIGURATION_0_REG) |= (0x1 << 24); \
5425+}
5426+
5427+#define HAL_PCM_DISABLE_DATA_SWAP() \
5428+{ \
5429+ (PCM_CONFIGURATION_0_REG) &= ~(0x1 << 24); \
5430+}
5431+
5432+#define HAL_PCM_WRITE_TX_DATA_0(tx_data_0) \
5433+{ \
5434+ (PCM_TX_DATA_31_0_REG) = tx_data_0; \
5435+}
5436+
5437+#define HAL_PCM_WRITE_TX_DATA_1(tx_data_1) \
5438+{ \
5439+ (PCM_TX_DATA_63_32_REG) = tx_data_1; \
5440+}
5441+
5442+#define HAL_PCM_READ_RX_DATA_0(rx_data_0) \
5443+{ \
5444+ (rx_data_0) = PCM_RX_DATA_31_0_REG; \
5445+}
5446+
5447+#define HAL_PCM_READ_RX_DATA_1(rx_data_1) \
5448+{ \
5449+ (rx_data_1) = PCM_RX_DATA_63_32_REG; \
5450+}
5451+
5452+#define HAL_PCM_READ_INTERRUPT_STATUS(status) \
5453+{ \
5454+ (status) = PCM_INTERRUPT_STATUS_REG; \
5455+}
5456+
5457+#define HAL_PCM_CLEAR_INTERRUPT_STATUS(status) \
5458+{ \
5459+ (PCM_INTERRUPT_STATUS_REG) = (status & 0xC); \
5460+}
5461+
5462+#define HAL_PCM_DISABLE_RECEIVE_BUFFER_FULL_INTERRUPT() \
5463+{ \
5464+ (PCM_INTERRUPT_ENABLE_REG) &= ~(0x1 << 0); \
5465+}
5466+
5467+#define HAL_PCM_DISABLE_TRANSMIT_BUFFER_EMPTY_INTERRUPT() \
5468+{ \
5469+ (PCM_INTERRUPT_ENABLE_REG) &= ~(0x1 << 1); \
5470+}
5471+
5472+#define HAL_PCM_DISABLE_RECEIVE_BUFFER_OVERRUN_INTERRUPT() \
5473+{ \
5474+ (PCM_INTERRUPT_ENABLE_REG) &= ~(0x1 << 2); \
5475+}
5476+
5477+#define HAL_PCM_DISABLE_TRANSMIT_BUFFER_UNDERRUN_INTERRUPT() \
5478+{ \
5479+ (PCM_INTERRUPT_ENABLE_REG) &= ~(0x1 << 3); \
5480+}
5481+
5482+#define HAL_PCM_DISABLE_ALL_INTERRUPT_SOURCES() \
5483+{ \
5484+ (PCM_INTERRUPT_ENABLE_REG) = 0; \
5485+}
5486+
5487+#endif // end of #ifndef _STAR_PCM_H_
5488+
5489--- /dev/null
5490+++ b/arch/arm/mach-cns3xxx/include/mach/platform.h
5491@@ -0,0 +1,297 @@
5492+/*
5493+ * arch/arm/mach-cns3xxx/include/mach/platform.h
5494+ *
5495+ * Copyright (c) 2008 Cavium Networks
5496+ * Copyright (c) ARM Limited 2003. All rights reserved.
5497+ *
5498+ * This file is free software; you can redistribute it and/or modify
5499+ * it under the terms of the GNU General Public License, Version 2, as
5500+ * published by the Free Software Foundation.
5501+ *
5502+ * This file is distributed in the hope that it will be useful,
5503+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
5504+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
5505+ * NONINFRINGEMENT. See the GNU General Public License for more details.
5506+ *
5507+ * You should have received a copy of the GNU General Public License
5508+ * along with this file; if not, write to the Free Software
5509+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
5510+ * visit http://www.gnu.org/licenses/.
5511+ *
5512+ * This file may also be available under a different license from Cavium.
5513+ * Contact Cavium Networks for more information
5514+ */
5515+
5516+#ifndef __ASM_ARCH_PLATFORM_H
5517+#define __ASM_ARCH_PLATFORM_H
5518+
5519+#ifndef __ASSEMBLY__
5520+
5521+#include <linux/io.h>
5522+
5523+/*
5524+ * SDRAM
5525+ */
5526+#define CNS3XXX_SDRAM_BASE 0x00000000
5527+
5528+/* ------------------------------------------------------------------------
5529+ * Cavium Networks Registers
5530+ * ------------------------------------------------------------------------
5531+ *
5532+ */
5533+#define CNS3XXX_SYS_ID_OFFSET 0x00
5534+#define CNS3XXX_SYS_SW_OFFSET 0x04
5535+#define CNS3XXX_SYS_LED_OFFSET 0x08
5536+#define CNS3XXX_SYS_OSC0_OFFSET 0x0C
5537+
5538+#define CNS3XXX_SYS_OSC1_OFFSET 0x10
5539+#define CNS3XXX_SYS_OSC2_OFFSET 0x14
5540+#define CNS3XXX_SYS_OSC3_OFFSET 0x18
5541+#define CNS3XXX_SYS_OSC4_OFFSET 0x1C /* OSC1 for Cavium Networks/AB */
5542+
5543+#define CNS3XXX_SYS_LOCK_OFFSET 0x20
5544+#define CNS3XXX_SYS_100HZ_OFFSET 0x24
5545+#define CNS3XXX_SYS_CFGDATA1_OFFSET 0x28
5546+#define CNS3XXX_SYS_CFGDATA2_OFFSET 0x2C
5547+#define CNS3XXX_SYS_FLAGS_OFFSET 0x30
5548+#define CNS3XXX_SYS_FLAGSSET_OFFSET 0x30
5549+#define CNS3XXX_SYS_FLAGSCLR_OFFSET 0x34
5550+#define CNS3XXX_SYS_NVFLAGS_OFFSET 0x38
5551+#define CNS3XXX_SYS_NVFLAGSSET_OFFSET 0x38
5552+#define CNS3XXX_SYS_NVFLAGSCLR_OFFSET 0x3C
5553+#define CNS3XXX_SYS_RESETCTL_OFFSET 0x40
5554+#define CNS3XXX_SYS_PCICTL_OFFSET 0x44
5555+#define CNS3XXX_SYS_MCI_OFFSET 0x48
5556+#define CNS3XXX_SYS_FLASH_OFFSET 0x4C
5557+#define CNS3XXX_SYS_CLCD_OFFSET 0x50
5558+#define CNS3XXX_SYS_CLCDSER_OFFSET 0x54
5559+#define CNS3XXX_SYS_BOOTCS_OFFSET 0x58
5560+#define CNS3XXX_SYS_24MHz_OFFSET 0x5C
5561+#define CNS3XXX_SYS_MISC_OFFSET 0x60
5562+#define CNS3XXX_SYS_IOSEL_OFFSET 0x70
5563+#define CNS3XXX_SYS_PROCID_OFFSET 0x84
5564+#define CNS3XXX_SYS_TEST_OSC0_OFFSET 0xC0
5565+#define CNS3XXX_SYS_TEST_OSC1_OFFSET 0xC4
5566+#define CNS3XXX_SYS_TEST_OSC2_OFFSET 0xC8
5567+#define CNS3XXX_SYS_TEST_OSC3_OFFSET 0xCC
5568+#define CNS3XXX_SYS_TEST_OSC4_OFFSET 0xD0
5569+
5570+#define CNS3XXX_SYS_BASE 0x10000000
5571+#define CNS3XXX_SYS_ID (CNS3XXX_SYS_BASE + CNS3XXX_SYS_ID_OFFSET)
5572+#define CNS3XXX_SYS_SW (CNS3XXX_SYS_BASE + CNS3XXX_SYS_SW_OFFSET)
5573+#define CNS3XXX_SYS_LED (CNS3XXX_SYS_BASE + CNS3XXX_SYS_LED_OFFSET)
5574+#define CNS3XXX_SYS_OSC0 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_OSC0_OFFSET)
5575+#define CNS3XXX_SYS_OSC1 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_OSC1_OFFSET)
5576+
5577+#define CNS3XXX_SYS_LOCK (CNS3XXX_SYS_BASE + CNS3XXX_SYS_LOCK_OFFSET)
5578+#define CNS3XXX_SYS_100HZ (CNS3XXX_SYS_BASE + CNS3XXX_SYS_100HZ_OFFSET)
5579+#define CNS3XXX_SYS_CFGDATA1 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_CFGDATA1_OFFSET)
5580+#define CNS3XXX_SYS_CFGDATA2 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_CFGDATA2_OFFSET)
5581+#define CNS3XXX_SYS_FLAGS (CNS3XXX_SYS_BASE + CNS3XXX_SYS_FLAGS_OFFSET)
5582+#define CNS3XXX_SYS_FLAGSSET (CNS3XXX_SYS_BASE + CNS3XXX_SYS_FLAGSSET_OFFSET)
5583+#define CNS3XXX_SYS_FLAGSCLR (CNS3XXX_SYS_BASE + CNS3XXX_SYS_FLAGSCLR_OFFSET)
5584+#define CNS3XXX_SYS_NVFLAGS (CNS3XXX_SYS_BASE + CNS3XXX_SYS_NVFLAGS_OFFSET)
5585+#define CNS3XXX_SYS_NVFLAGSSET (CNS3XXX_SYS_BASE + CNS3XXX_SYS_NVFLAGSSET_OFFSET)
5586+#define CNS3XXX_SYS_NVFLAGSCLR (CNS3XXX_SYS_BASE + CNS3XXX_SYS_NVFLAGSCLR_OFFSET)
5587+#define CNS3XXX_SYS_RESETCTL (CNS3XXX_SYS_BASE + CNS3XXX_SYS_RESETCTL_OFFSET)
5588+#define CNS3XXX_SYS_PCICTL (CNS3XXX_SYS_BASE + CNS3XXX_SYS_PCICTL_OFFSET)
5589+#define CNS3XXX_SYS_MCI (CNS3XXX_SYS_BASE + CNS3XXX_SYS_MCI_OFFSET)
5590+#define CNS3XXX_SYS_FLASH (CNS3XXX_SYS_BASE + CNS3XXX_SYS_FLASH_OFFSET)
5591+#define CNS3XXX_SYS_CLCD (CNS3XXX_SYS_BASE + CNS3XXX_SYS_CLCD_OFFSET)
5592+#define CNS3XXX_SYS_CLCDSER (CNS3XXX_SYS_BASE + CNS3XXX_SYS_CLCDSER_OFFSET)
5593+#define CNS3XXX_SYS_BOOTCS (CNS3XXX_SYS_BASE + CNS3XXX_SYS_BOOTCS_OFFSET)
5594+#define CNS3XXX_SYS_24MHz (CNS3XXX_SYS_BASE + CNS3XXX_SYS_24MHz_OFFSET)
5595+#define CNS3XXX_SYS_MISC (CNS3XXX_SYS_BASE + CNS3XXX_SYS_MISC_OFFSET)
5596+#define CNS3XXX_SYS_IOSEL (CNS3XXX_SYS_BASE + CNS3XXX_SYS_IOSEL_OFFSET)
5597+#define CNS3XXX_SYS_PROCID (CNS3XXX_SYS_BASE + CNS3XXX_SYS_PROCID_OFFSET)
5598+#define CNS3XXX_SYS_TEST_OSC0 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_TEST_OSC0_OFFSET)
5599+#define CNS3XXX_SYS_TEST_OSC1 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_TEST_OSC1_OFFSET)
5600+#define CNS3XXX_SYS_TEST_OSC2 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_TEST_OSC2_OFFSET)
5601+#define CNS3XXX_SYS_TEST_OSC3 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_TEST_OSC3_OFFSET)
5602+#define CNS3XXX_SYS_TEST_OSC4 (CNS3XXX_SYS_BASE + CNS3XXX_SYS_TEST_OSC4_OFFSET)
5603+
5604+/*
5605+ * Values for CNS3XXX_SYS_RESET_CTRL
5606+ */
5607+#define CNS3XXX_SYS_CTRL_RESET_CONFIGCLR 0x01
5608+#define CNS3XXX_SYS_CTRL_RESET_CONFIGINIT 0x02
5609+#define CNS3XXX_SYS_CTRL_RESET_DLLRESET 0x03
5610+#define CNS3XXX_SYS_CTRL_RESET_PLLRESET 0x04
5611+#define CNS3XXX_SYS_CTRL_RESET_POR 0x05
5612+#define CNS3XXX_SYS_CTRL_RESET_DoC 0x06
5613+
5614+#define CNS3XXX_SYS_CTRL_LED (1 << 0)
5615+
5616+
5617+/* ------------------------------------------------------------------------
5618+ * Cavium Networks control registers
5619+ * ------------------------------------------------------------------------
5620+ */
5621+
5622+/*
5623+ * CNS3XXX_IDFIELD
5624+ *
5625+ * 31:24 = manufacturer (0x41 = ARM)
5626+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
5627+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
5628+ * 11:4 = build value
5629+ * 3:0 = revision number (0x1 = rev B (AHB))
5630+ */
5631+
5632+/*
5633+ * CNS3XXX_SYS_LOCK
5634+ * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
5635+ * SYS_CLD, SYS_BOOTCS
5636+ */
5637+#define CNS3XXX_SYS_LOCK_LOCKED (1 << 16)
5638+#define CNS3XXX_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
5639+
5640+/*
5641+ * CNS3XXX_SYS_FLASH
5642+ */
5643+#define CNS3XXX_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
5644+
5645+/*
5646+ * CNS3XXX_INTREG
5647+ * - used to acknowledge and control MMCI and UART interrupts
5648+ */
5649+#define CNS3XXX_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
5650+#define CNS3XXX_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
5651+#define CNS3XXX_INTREG_CARDIN 0x08 /* MMCI card in detect */
5652+ /* write 1 to acknowledge and clear */
5653+#define CNS3XXX_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
5654+#define CNS3XXX_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
5655+
5656+/*
5657+ * Cavium Networks common peripheral addresses
5658+ */
5659+#define CNS3XXX_SCTL_BASE 0x10001000 /* System controller */
5660+
5661+/* PCI space */
5662+#define CNS3XXX_PCI_BASE 0x41000000 /* PCI Interface */
5663+#define CNS3XXX_PCI_CFG_BASE 0x42000000
5664+#define CNS3XXX_PCI_MEM_BASE0 0x44000000
5665+#define CNS3XXX_PCI_MEM_BASE1 0x50000000
5666+#define CNS3XXX_PCI_MEM_BASE2 0x60000000
5667+/* Sizes of above maps */
5668+#define CNS3XXX_PCI_BASE_SIZE 0x01000000
5669+#define CNS3XXX_PCI_CFG_BASE_SIZE 0x02000000
5670+#define CNS3XXX_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
5671+#define CNS3XXX_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
5672+#define CNS3XXX_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
5673+
5674+#define CNS3XXX_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
5675+#define CNS3XXX_LT_BASE 0x80000000 /* Logic Tile expansion */
5676+
5677+/*
5678+ * LED settings, bits [7:0]
5679+ */
5680+#define CNS3XXX_SYS_LED0 (1 << 0)
5681+#define CNS3XXX_SYS_LED1 (1 << 1)
5682+#define CNS3XXX_SYS_LED2 (1 << 2)
5683+#define CNS3XXX_SYS_LED3 (1 << 3)
5684+#define CNS3XXX_SYS_LED4 (1 << 4)
5685+#define CNS3XXX_SYS_LED5 (1 << 5)
5686+#define CNS3XXX_SYS_LED6 (1 << 6)
5687+#define CNS3XXX_SYS_LED7 (1 << 7)
5688+
5689+#define ALL_LEDS 0xFF
5690+
5691+#define LED_BANK CNS3XXX_SYS_LED
5692+
5693+/*
5694+ * Control registers
5695+ */
5696+#define CNS3XXX_IDFIELD_OFFSET 0x0 /* Cavium Networks build information */
5697+#define CNS3XXX_FLASHPROG_OFFSET 0x4 /* Flash devices */
5698+#define CNS3XXX_INTREG_OFFSET 0x8 /* Interrupt control */
5699+#define CNS3XXX_DECODE_OFFSET 0xC /* Fitted logic modules */
5700+
5701+/*
5702+ * System controller bit assignment
5703+ */
5704+#define CNS3XXX_REFCLK 0
5705+#define CNS3XXX_TIMCLK 1
5706+
5707+#define CNS3XXX_TIMER1_EnSel 15
5708+#define CNS3XXX_TIMER2_EnSel 17
5709+#define CNS3XXX_TIMER3_EnSel 19
5710+#define CNS3XXX_TIMER4_EnSel 21
5711+
5712+
5713+#define MAX_TIMER 2
5714+#define MAX_PERIOD 699050
5715+#define TICKS_PER_uSEC 1
5716+
5717+/*
5718+ * These are useconds NOT ticks.
5719+ *
5720+ */
5721+#define mSEC_1 1000
5722+#define mSEC_5 (mSEC_1 * 5)
5723+#define mSEC_10 (mSEC_1 * 10)
5724+#define mSEC_25 (mSEC_1 * 25)
5725+#define SEC_1 (mSEC_1 * 1000)
5726+
5727+#define CNS3XXX_CSR_BASE 0x10000000
5728+#define CNS3XXX_CSR_SIZE 0x10000000
5729+
5730+/* Platform Level Setup Functions */
5731+
5732+extern void cns3xxx_sys_init(void);
5733+extern int cns3xxx_pcie_init(u8 ports);
5734+
5735+/* Information about built-in Ethernet MAC interfaces */
5736+struct eth_plat_info {
5737+ u8 ports; /* Bitmap of enabled Ports */
5738+ u8 eth0_hwaddr[6];
5739+ u8 eth1_hwaddr[6];
5740+ u8 eth2_hwaddr[6];
5741+ u8 cpu_hwaddr[6];
5742+};
5743+
5744+// Config 1 Bitmap
5745+#define ETH0_LOAD BIT(0)
5746+#define ETH1_LOAD BIT(1)
5747+#define ETH2_LOAD BIT(2)
5748+#define SATA0_LOAD BIT(3)
5749+#define SATA1_LOAD BIT(4)
5750+#define PCM_LOAD BIT(5)
5751+#define I2S_LOAD BIT(6)
5752+#define SPI0_LOAD BIT(7)
5753+#define SPI1_LOAD BIT(8)
5754+#define PCIe0_LOAD BIT(9)
5755+#define PCIe1_LOAD BIT(10)
5756+#define USB0_LOAD BIT(11)
5757+#define USB1_LOAD BIT(12)
5758+#define USB1_ROUTE BIT(13)
5759+#define SD_LOAD BIT(14)
5760+#define UART0_LOAD BIT(15)
5761+#define UART1_LOAD BIT(16)
5762+#define UART2_LOAD BIT(17)
5763+#define mPCI0_LOAD BIT(18)
5764+#define mPCI1_LOAD BIT(19)
5765+#define mPCI2_LOAD BIT(20)
5766+#define mPCI3_LOAD BIT(21)
5767+#define FP_BUT_LOAD BIT(22)
5768+#define FP_BUT_HEADER_LOAD BIT(23)
5769+#define FP_LED_LOAD BIT(24)
5770+#define FP_LED_HEADER_LOAD BIT(25)
5771+#define FP_TAMPER_LOAD BIT(26)
5772+#define HEADER_33v_LOAD BIT(27)
5773+#define SATA_POWER_LOAD BIT(28)
5774+#define FP_POWER_LOAD BIT(29)
5775+#define GPIO_HEADER_LOAD BIT(30)
5776+#define GSP_BAT_LOAD BIT(31)
5777+
5778+// Config 2 Bitmap
5779+#define FAN_LOAD BIT(0)
5780+#define SPI_FLASH_LOAD BIT(1)
5781+#define NOR_FLASH_LOAD BIT(2)
5782+#define GPS_LOAD BIT(3)
5783+#define SUPPLY_5v_LOAD BIT(6)
5784+#define SUPPLY_33v_LOAD BIT(7)
5785+
5786+
5787+#endif /* __ASM_ARCH_PLATFORM_H */
5788+#endif
5789--- /dev/null
5790+++ b/arch/arm/mach-cns3xxx/include/mach/pm.h
5791@@ -0,0 +1,333 @@
5792+/******************************************************************************
5793+ *
5794+ * Copyright (c) 2008 Cavium Networks
5795+ *
5796+ * This file is free software; you can redistribute it and/or modify
5797+ * it under the terms of the GNU General Public License, Version 2, as
5798+ * published by the Free Software Foundation.
5799+ *
5800+ * This file is distributed in the hope that it will be useful,
5801+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
5802+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
5803+ * NONINFRINGEMENT. See the GNU General Public License for more details.
5804+ *
5805+ * You should have received a copy of the GNU General Public License
5806+ * along with this file; if not, write to the Free Software
5807+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
5808+ * visit http://www.gnu.org/licenses/.
5809+ *
5810+ * This file may also be available under a different license from Cavium.
5811+ * Contact Cavium Networks for more information
5812+ *
5813+ ******************************************************************************/
5814+
5815+#ifndef _CNS3XXX_PM_H_
5816+#define _CNS3XXX_PM_H_
5817+#include <mach/board.h>
5818+#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT+offset)))
5819+
5820+#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000)
5821+#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004)
5822+#define PM_HS_CFG_REG PMU_REG_VALUE(0x008)
5823+#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C)
5824+#define PM_PWR_STA_REG PMU_REG_VALUE(0x010)
5825+#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014)
5826+#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018)
5827+#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C)
5828+#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020)
5829+#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024)
5830+#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028)
5831+#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C)
5832+#define PM_CSR_REG PMU_REG_VALUE(0x030)
5833+
5834+/* PM_CLK_GATE_REG */
5835+#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
5836+#define PM_CLK_GATE_REG_OFFSET_GPU (24)
5837+#define PM_CLK_GATE_REG_OFFSET_CIM (23)
5838+#define PM_CLK_GATE_REG_OFFSET_LCDC (22)
5839+#define PM_CLK_GATE_REG_OFFSET_I2S (21)
5840+#define PM_CLK_GATE_REG_OFFSET_RAID (20)
5841+#define PM_CLK_GATE_REG_OFFSET_SATA (19)
5842+#define PM_CLK_GATE_REG_OFFSET_PCIE0 (17)
5843+#define PM_CLK_GATE_REG_OFFSET_PCIE1 (18)
5844+#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
5845+#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
5846+#define PM_CLK_GATE_REG_OFFSET_TIMER (14)
5847+#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
5848+#define PM_CLK_GATE_REG_OFFSET_HCIE (12)
5849+#define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
5850+#define PM_CLK_GATE_REG_OFFSET_GPIO (10)
5851+#define PM_CLK_GATE_REG_OFFSET_UART3 (9)
5852+#define PM_CLK_GATE_REG_OFFSET_UART2 (8)
5853+#define PM_CLK_GATE_REG_OFFSET_UART1 (7)
5854+#define PM_CLK_GATE_REG_OFFSET_RTC (5)
5855+#define PM_CLK_GATE_REG_OFFSET_GDMA (4)
5856+#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)
5857+#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)
5858+#define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
5859+
5860+/* PM_SOFT_RST_REG */
5861+#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)
5862+#define PM_SOFT_RST_REG_OFFST_CPU1 (29)
5863+#define PM_SOFT_RST_REG_OFFST_CPU0 (28)
5864+#define PM_SOFT_RST_REG_OFFST_SDIO (25)
5865+#define PM_SOFT_RST_REG_OFFST_GPU (24)
5866+#define PM_SOFT_RST_REG_OFFST_CIM (23)
5867+#define PM_SOFT_RST_REG_OFFST_LCDC (22)
5868+#define PM_SOFT_RST_REG_OFFST_I2S (21)
5869+#define PM_SOFT_RST_REG_OFFST_RAID (20)
5870+#define PM_SOFT_RST_REG_OFFST_SATA (19)
5871+#define PM_SOFT_RST_REG_OFFST_PCIE1 (18)
5872+#define PM_SOFT_RST_REG_OFFST_PCIE0 (17)
5873+#define PM_SOFT_RST_REG_OFFST_USB_HOST (16)
5874+#define PM_SOFT_RST_REG_OFFST_USB_OTG (15)
5875+#define PM_SOFT_RST_REG_OFFST_TIMER (14)
5876+#define PM_SOFT_RST_REG_OFFST_CRYPTO (13)
5877+#define PM_SOFT_RST_REG_OFFST_HCIE (12)
5878+#define PM_SOFT_RST_REG_OFFST_SWITCH (11)
5879+#define PM_SOFT_RST_REG_OFFST_GPIO (10)
5880+#define PM_SOFT_RST_REG_OFFST_UART3 (9)
5881+#define PM_SOFT_RST_REG_OFFST_UART2 (8)
5882+#define PM_SOFT_RST_REG_OFFST_UART1 (7)
5883+#define PM_SOFT_RST_REG_OFFST_RTC (5)
5884+#define PM_SOFT_RST_REG_OFFST_GDMA (4)
5885+#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)
5886+#define PM_SOFT_RST_REG_OFFST_DMC (2)
5887+#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)
5888+#define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
5889+#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
5890+
5891+/* PMHS_CFG_REG */
5892+#define PM_HS_CFG_REG_OFFSET_SDIO (25)
5893+#define PM_HS_CFG_REG_OFFSET_GPU (24)
5894+#define PM_HS_CFG_REG_OFFSET_CIM (23)
5895+#define PM_HS_CFG_REG_OFFSET_LCDC (22)
5896+#define PM_HS_CFG_REG_OFFSET_I2S (21)
5897+#define PM_HS_CFG_REG_OFFSET_RAID (20)
5898+#define PM_HS_CFG_REG_OFFSET_SATA (19)
5899+#define PM_HS_CFG_REG_OFFSET_PCIE1 (18)
5900+#define PM_HS_CFG_REG_OFFSET_PCIE0 (17)
5901+#define PM_HS_CFG_REG_OFFSET_USB_HOST (16)
5902+#define PM_HS_CFG_REG_OFFSET_USB_OTG (15)
5903+#define PM_HS_CFG_REG_OFFSET_TIMER (14)
5904+#define PM_HS_CFG_REG_OFFSET_CRYPTO (13)
5905+#define PM_HS_CFG_REG_OFFSET_HCIE (12)
5906+#define PM_HS_CFG_REG_OFFSET_SWITCH (11)
5907+#define PM_HS_CFG_REG_OFFSET_GPIO (10)
5908+#define PM_HS_CFG_REG_OFFSET_UART3 (9)
5909+#define PM_HS_CFG_REG_OFFSET_UART2 (8)
5910+#define PM_HS_CFG_REG_OFFSET_UART1 (7)
5911+#define PM_HS_CFG_REG_OFFSET_RTC (5)
5912+#define PM_HS_CFG_REG_OFFSET_GDMA (4)
5913+#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)
5914+#define PM_HS_CFG_REG_OFFSET_DMC (2)
5915+#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)
5916+#define PM_HS_CFG_REG_MASK (0x03FFFFBE)
5917+#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
5918+
5919+/* PM_CACTIVE_STA_REG */
5920+#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)
5921+#define PM_CACTIVE_STA_REG_OFFSET_GPU (24)
5922+#define PM_CACTIVE_STA_REG_OFFSET_CIM (23)
5923+#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)
5924+#define PM_CACTIVE_STA_REG_OFFSET_I2S (21)
5925+#define PM_CACTIVE_STA_REG_OFFSET_RAID (20)
5926+#define PM_CACTIVE_STA_REG_OFFSET_SATA (19)
5927+#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)
5928+#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)
5929+#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)
5930+#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)
5931+#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)
5932+#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)
5933+#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)
5934+#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)
5935+#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)
5936+#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)
5937+#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)
5938+#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)
5939+#define PM_CACTIVE_STA_REG_OFFSET_RTC (5)
5940+#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)
5941+#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)
5942+#define PM_CACTIVE_STA_REG_OFFSET_DMC (2)
5943+#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)
5944+#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
5945+
5946+/* PM_PWR_STA_REG */
5947+#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)
5948+#define PM_PWR_STA_REG_REG_OFFSET_GPU (24)
5949+#define PM_PWR_STA_REG_REG_OFFSET_CIM (23)
5950+#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)
5951+#define PM_PWR_STA_REG_REG_OFFSET_I2S (21)
5952+#define PM_PWR_STA_REG_REG_OFFSET_RAID (20)
5953+#define PM_PWR_STA_REG_REG_OFFSET_SATA (19)
5954+#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)
5955+#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)
5956+#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)
5957+#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)
5958+#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)
5959+#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)
5960+#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)
5961+#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)
5962+#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)
5963+#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)
5964+#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)
5965+#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)
5966+#define PM_PWR_STA_REG_REG_OFFSET_RTC (5)
5967+#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)
5968+#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)
5969+#define PM_PWR_STA_REG_REG_OFFSET_DMC (2)
5970+#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)
5971+#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
5972+
5973+/* PM_CLK_CTRL_REG */
5974+#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)
5975+#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)
5976+#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)
5977+#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)
5978+#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)
5979+#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)
5980+#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)
5981+#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)
5982+#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)
5983+#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)
5984+#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)
5985+#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)
5986+#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)
5987+#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)
5988+#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)
5989+#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
5990+
5991+#define PM_CPU_CLK_DIV(DIV) { \
5992+ PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
5993+ PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
5994+}
5995+
5996+#define PM_PLL_CPU_SEL(CPU) { \
5997+ PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
5998+ PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
5999+}
6000+
6001+/* PM_PLL_LCD_I2S_CTRL_REG */
6002+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)
6003+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)
6004+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)
6005+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)
6006+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
6007+
6008+/* PM_PLL_HM_PD_CTRL_REG */
6009+/*
6010+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PCIE_PHY1 (13)
6011+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PCIE_PHY0 (12)
6012+*/
6013+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)
6014+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)
6015+/*
6016+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_USB_PHY1 (9)
6017+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_USB_PHY0 (8)
6018+*/
6019+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)
6020+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)
6021+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)
6022+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)
6023+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)
6024+#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
6025+
6026+/* PM_REGULAT_CTRL_REG */
6027+
6028+/* PM_WDT_CTRL_REG */
6029+#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
6030+
6031+/* PM_WU_CTRL0_REG */
6032+
6033+/* PM_WU_CTRL1_REG */
6034+
6035+/* PM_CSR_REG - Clock Scaling Register*/
6036+#define PM_CSR_REG_OFFSET_CSR_EN (30)
6037+#define PM_CSR_REG_OFFSET_CSR_NUM (0)
6038+
6039+
6040+#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
6041+
6042+/* Software reset*/
6043+#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
6044+
6045+
6046+
6047+/* CNS3XXX support several power saving mode as following,
6048+ * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate
6049+ */
6050+#define CNS3XXX_PWR_CPU_MODE_DFS (0)
6051+#define CNS3XXX_PWR_CPU_MODE_IDLE (1)
6052+#define CNS3XXX_PWR_CPU_MODE_HALT (2)
6053+#define CNS3XXX_PWR_CPU_MODE_DOZE (3)
6054+#define CNS3XXX_PWR_CPU_MODE_SLEEP (4)
6055+#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)
6056+
6057+
6058+/* Enable functional block */
6059+#if 0
6060+#define CNS3XXX_PWR_PLL_PCIE_PHY1 (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PCIE_PHY1)
6061+#define CNS3XXX_PWR_PLL_PCIE_PHY0 (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PCIE_PHY0)
6062+#define CNS3XXX_PWR_PLL_SATA_PHY1 (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1)
6063+#define CNS3XXX_PWR_PLL_SATA_PHY0 (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_USB_PHY0)
6064+#define CNS3XXX_PWR_PLL_USB_PHY1 (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_USB_PHY1)
6065+#define CNS3XXX_PWR_PLL_USB_PHY0 (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_USB_PHY0)
6066+#define CNS3XXX_PWR_PLL_I2SCD (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD)
6067+#define CNS3XXX_PWR_PLL_I2S (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S)
6068+#define CNS3XXX_PWR_PLL_LCD (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD)
6069+#define CNS3XXX_PWR_PLL_USB (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB)
6070+#define CNS3XXX_PWR_PLL_RGMII (0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII)
6071+#else
6072+#define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
6073+#endif
6074+#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK
6075+
6076+void cns3xxx_pwr_power_up(unsigned int dev_num);
6077+void cns3xxx_pwr_power_down(unsigned int dev_num);
6078+
6079+
6080+/* Change CPU frequency and divider */
6081+#define CNS3XXX_PWR_PLL_CPU_300MHZ (0)
6082+#define CNS3XXX_PWR_PLL_CPU_333MHZ (1)
6083+#define CNS3XXX_PWR_PLL_CPU_366MHZ (2)
6084+#define CNS3XXX_PWR_PLL_CPU_400MHZ (3)
6085+#define CNS3XXX_PWR_PLL_CPU_433MHZ (4)
6086+#define CNS3XXX_PWR_PLL_CPU_466MHZ (5)
6087+#define CNS3XXX_PWR_PLL_CPU_500MHZ (6)
6088+#define CNS3XXX_PWR_PLL_CPU_533MHZ (7)
6089+#define CNS3XXX_PWR_PLL_CPU_566MHZ (8)
6090+#define CNS3XXX_PWR_PLL_CPU_600MHZ (9)
6091+#define CNS3XXX_PWR_PLL_CPU_633MHZ (10)
6092+#define CNS3XXX_PWR_PLL_CPU_666MHZ (11)
6093+#define CNS3XXX_PWR_PLL_CPU_700MHZ (12)
6094+
6095+#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)
6096+#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)
6097+#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)
6098+
6099+
6100+void cns3xxx_pwr_change_pll_cpu(unsigned int cpu_sel);
6101+
6102+
6103+
6104+/* Change DDR2 frequency */
6105+#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)
6106+#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1)
6107+#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2)
6108+#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3)
6109+
6110+/* Clock enable*/
6111+void cns3xxx_pwr_clk_en(unsigned int block);
6112+/* Software reset*/
6113+void cns3xxx_pwr_soft_rst(unsigned int block);
6114+void cns3xxx_pwr_soft_rst_force(unsigned int block);
6115+/* PLL/Hard macro */
6116+void cns3xxx_pwr_power_up(unsigned int dev_num);
6117+void cns3xxx_pwr_power_down(unsigned int dev_num);
6118+/* Change CPU clock */
6119+void cns3xxx_pwr_change_cpu_clock(unsigned int cpu_sel, unsigned int div_sel);
6120+/* System enter into sleep mode */
6121+void cns3xxx_pwr_sleep(void);
6122+
6123+int cns3xxx_cpu_clock(void);
6124+#endif
6125--- /dev/null
6126+++ b/arch/arm/mach-cns3xxx/include/mach/scu.h
6127@@ -0,0 +1,34 @@
6128+/*
6129+ * Copyright (c) 2008 Cavium Networks
6130+ *
6131+ * This file is free software; you can redistribute it and/or modify
6132+ * it under the terms of the GNU General Public License, Version 2, as
6133+ * published by the Free Software Foundation.
6134+ *
6135+ * This file is distributed in the hope that it will be useful,
6136+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
6137+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6138+ * NONINFRINGEMENT. See the GNU General Public License for more details.
6139+ *
6140+ * You should have received a copy of the GNU General Public License
6141+ * along with this file; if not, write to the Free Software
6142+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
6143+ * visit http://www.gnu.org/licenses/.
6144+ *
6145+ * This file may also be available under a different license from Cavium.
6146+ * Contact Cavium Networks for more information
6147+ */
6148+
6149+#ifndef __ASMARM_ARCH_SCU_H
6150+#define __ASMARM_ARCH_SCU_H
6151+
6152+/*
6153+ * SCU registers
6154+ */
6155+#define SCU_CTRL 0x00
6156+#define SCU_CONFIG 0x04
6157+#define SCU_CPU_STATUS 0x08
6158+#define SCU_INVALIDATE 0x0c
6159+#define SCU_FPGA_REVISION 0x10
6160+
6161+#endif
6162--- /dev/null
6163+++ b/arch/arm/mach-cns3xxx/include/mach/sdhci.h
6164@@ -0,0 +1,42 @@
6165+/*******************************************************************************
6166+ *
6167+ * arch/arm/mach-cns3xxx/include/mach/sdhci.h
6168+ *
6169+ * Scott Shu
6170+ *
6171+ * Copyright (c) 2009 Cavium Networks
6172+ *
6173+ * SDHCI platform data definitions
6174+ *
6175+ * This file is free software; you can redistribute it and/or modify
6176+ * it under the terms of the GNU General Public License, Version 2, as
6177+ * published by the Free Software Foundation.
6178+ *
6179+ * This file is distributed in the hope that it will be useful,
6180+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
6181+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6182+ * NONINFRINGEMENT. See the GNU General Public License for more details.
6183+ *
6184+ * You should have received a copy of the GNU General Public License
6185+ * along with this file; if not, write to the Free Software
6186+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
6187+ * visit http://www.gnu.org/licenses/.
6188+ *
6189+ * This file may also be available under a different license from Cavium.
6190+ * Contact Cavium Networks for more information
6191+ *
6192+ ******************************************************************************/
6193+
6194+#ifndef _CNS3XXX_SDHCI_H_
6195+#define _CNS3XXX_SDHCI_H_
6196+
6197+struct platform_device;
6198+
6199+struct cns3xxx_sdhci_platdata {
6200+ unsigned int max_width;
6201+ unsigned int host_caps;
6202+ char **clocks;
6203+
6204+ struct sdhci_host * sdhci_host;
6205+};
6206+#endif
6207--- /dev/null
6208+++ b/arch/arm/mach-cns3xxx/include/mach/smp.h
6209@@ -0,0 +1,49 @@
6210+/*
6211+ * Copyright (c) 2008 Cavium Networks
6212+ *
6213+ * This file is free software; you can redistribute it and/or modify
6214+ * it under the terms of the GNU General Public License, Version 2, as
6215+ * published by the Free Software Foundation.
6216+ *
6217+ * This file is distributed in the hope that it will be useful,
6218+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
6219+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6220+ * NONINFRINGEMENT. See the GNU General Public License for more details.
6221+ *
6222+ * You should have received a copy of the GNU General Public License
6223+ * along with this file; if not, write to the Free Software
6224+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
6225+ * visit http://www.gnu.org/licenses/.
6226+ *
6227+ * This file may also be available under a different license from Cavium.
6228+ * Contact Cavium Networks for more information
6229+ */
6230+
6231+#ifndef ASMARM_ARCH_SMP_H
6232+#define ASMARM_ARCH_SMP_H
6233+
6234+
6235+#include <asm/hardware/gic.h>
6236+
6237+#define hard_smp_processor_id() \
6238+ ({ \
6239+ unsigned int cpunum; \
6240+ __asm__("mrc p15, 0, %0, c0, c0, 5" \
6241+ : "=r" (cpunum)); \
6242+ cpunum &= 0x0F; \
6243+ })
6244+
6245+/*
6246+ * We use IRQ1 as the IPI
6247+ */
6248+static inline void smp_cross_call(const struct cpumask *mask)
6249+{
6250+ gic_raise_softirq(mask, 2);
6251+}
6252+
6253+static inline void smp_cross_call_cache(const struct cpumask *mask)
6254+{
6255+ gic_raise_softirq(mask, 1);
6256+}
6257+
6258+#endif
6259--- /dev/null
6260+++ b/arch/arm/mach-cns3xxx/include/mach/system.h
6261@@ -0,0 +1,51 @@
6262+/*
6263+ * arch/arm/mach-cns3xxx/include/mach/system.h
6264+ *
6265+ * Copyright (c) 2008 Cavium Networks
6266+ * Copyright (C) 2003 ARM Limited
6267+ * Copyright (C) 2000 Deep Blue Solutions Ltd
6268+ *
6269+ * This file is free software; you can redistribute it and/or modify
6270+ * it under the terms of the GNU General Public License, Version 2, as
6271+ * published by the Free Software Foundation.
6272+ *
6273+ * This file is distributed in the hope that it will be useful,
6274+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
6275+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6276+ * NONINFRINGEMENT. See the GNU General Public License for more details.
6277+ *
6278+ * You should have received a copy of the GNU General Public License
6279+ * along with this file; if not, write to the Free Software
6280+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
6281+ * visit http://www.gnu.org/licenses/.
6282+ *
6283+ * This file may also be available under a different license from Cavium.
6284+ * Contact Cavium Networks for more information
6285+ */
6286+#ifndef __ASM_ARCH_SYSTEM_H
6287+#define __ASM_ARCH_SYSTEM_H
6288+
6289+#include <linux/io.h>
6290+#include <mach/hardware.h>
6291+#include <mach/platform.h>
6292+#include <mach/pm.h>
6293+
6294+static inline void arch_idle(void)
6295+{
6296+ /*
6297+ * This should do all the clock switching
6298+ * and wait for interrupt tricks
6299+ */
6300+ cpu_do_idle();
6301+}
6302+
6303+static inline void arch_reset(char mode, const char *cmd)
6304+{
6305+ /*
6306+ * To reset, we hit the on-board reset register
6307+ * in the system FPGA
6308+ */
6309+ cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
6310+}
6311+
6312+#endif
6313--- /dev/null
6314+++ b/arch/arm/mach-cns3xxx/include/mach/timex.h
6315@@ -0,0 +1,27 @@
6316+/*
6317+ * arch/arm/mach-cns3xxx/include/mach/timex.h
6318+ *
6319+ * Cavium Networks architecture timex specifications
6320+ *
6321+ * Copyright (c) 2008 Cavium Networks
6322+ * Copyright (C) 2003 ARM Limited
6323+ *
6324+ * This file is free software; you can redistribute it and/or modify
6325+ * it under the terms of the GNU General Public License, Version 2, as
6326+ * published by the Free Software Foundation.
6327+ *
6328+ * This file is distributed in the hope that it will be useful,
6329+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
6330+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6331+ * NONINFRINGEMENT. See the GNU General Public License for more details.
6332+ *
6333+ * You should have received a copy of the GNU General Public License
6334+ * along with this file; if not, write to the Free Software
6335+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
6336+ * visit http://www.gnu.org/licenses/.
6337+ *
6338+ * This file may also be available under a different license from Cavium.
6339+ * Contact Cavium Networks for more information
6340+ */
6341+
6342+#define CLOCK_TICK_RATE (50000000 / 16)
6343--- /dev/null
6344+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
6345@@ -0,0 +1,68 @@
6346+/*
6347+ * arch/arm/mach-cns3xxx/include/mach/uncompress.h
6348+ *
6349+ * Copyright (c) 2008 Cavium Networks
6350+ * Copyright (C) 2003 ARM Limited
6351+ *
6352+ * This file is free software; you can redistribute it and/or modify
6353+ * it under the terms of the GNU General Public License, Version 2, as
6354+ * published by the Free Software Foundation.
6355+ *
6356+ * This file is distributed in the hope that it will be useful,
6357+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
6358+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6359+ * NONINFRINGEMENT. See the GNU General Public License for more details.
6360+ *
6361+ * You should have received a copy of the GNU General Public License
6362+ * along with this file; if not, write to the Free Software
6363+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
6364+ * visit http://www.gnu.org/licenses/.
6365+ *
6366+ * This file may also be available under a different license from Cavium.
6367+ * Contact Cavium Networks for more information
6368+ */
6369+
6370+#include <mach/hardware.h>
6371+#include <asm/mach-types.h>
6372+
6373+#include <mach/board.h>
6374+
6375+#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
6376+#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
6377+#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
6378+#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
6379+
6380+/*
6381+ * Return the UART base address
6382+ */
6383+static inline unsigned long get_uart_base(void)
6384+{
6385+ return CNS3XXX_UART0_BASE;
6386+}
6387+
6388+/*
6389+ * This does not append a newline
6390+ */
6391+static inline void putc(int c)
6392+{
6393+ unsigned long base = get_uart_base();
6394+
6395+ while (AMBA_UART_FR(base) & (1 << 5))
6396+ barrier();
6397+
6398+ AMBA_UART_DR(base) = c;
6399+}
6400+
6401+static inline void flush(void)
6402+{
6403+ unsigned long base = get_uart_base();
6404+
6405+ while (AMBA_UART_FR(base) & (1 << 3))
6406+ barrier();
6407+}
6408+
6409+/*
6410+ * nothing to do
6411+ */
6412+#define arch_decomp_setup()
6413+#define arch_decomp_wdog()
6414--- /dev/null
6415+++ b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
6416@@ -0,0 +1,26 @@
6417+/*
6418+ * arch/arm/mach-cns3xxx/include/mach/vmalloc.h
6419+ *
6420+ * Copyright (c) 2008 Cavium Networks
6421+ * Copyright (C) 2003 ARM Limited
6422+ * Copyright (C) 2000 Russell King.
6423+ *
6424+ * This file is free software; you can redistribute it and/or modify
6425+ * it under the terms of the GNU General Public License, Version 2, as
6426+ * published by the Free Software Foundation.
6427+ *
6428+ * This file is distributed in the hope that it will be useful,
6429+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
6430+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6431+ * NONINFRINGEMENT. See the GNU General Public License for more details.
6432+ *
6433+ * You should have received a copy of the GNU General Public License
6434+ * along with this file; if not, write to the Free Software
6435+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
6436+ * visit http://www.gnu.org/licenses/.
6437+ *
6438+ * This file may also be available under a different license from Cavium.
6439+ * Contact Cavium Networks for more information
6440+ */
6441+
6442+#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
6443--- /dev/null
6444+++ b/arch/arm/mach-cns3xxx/Kconfig
6445@@ -0,0 +1,101 @@
6446+menu "CNS3XXX platform type"
6447+ depends on ARCH_CNS3XXX
6448+
6449+config MACH_GW2388
6450+ bool "Support Gateworks Laguna Platform"
6451+ select ARM_GIC
6452+ help
6453+ Include support for the Cavium Networks CNS3XXX MPCore Platform Baseboard.
6454+ This is a platform with an on-board ARM11 MPCore and has support for USB,
6455+ USB-OTG, MMC/SD/SDIO and PCI-E, etc.
6456+
6457+config CNS3XXX_PM_API
6458+ bool "Support for CNS3XXX Power Managemnet API"
6459+ depends on ARCH_CNS3XXX
6460+ default y
6461+ help
6462+ Enable support for the CNS3XXX Power Managemnet API.
6463+
6464+config CNS3XXX_RAID
6465+ bool "Support for CNS3XXX RAID"
6466+ depends on ARCH_CNS3XXX
6467+ help
6468+ Enable RAID 4/5/6 Hardware accelartion in CNS3XXX.
6469+ If unsure, say N.
6470+
6471+config CNS3XXX_DMAC
6472+ bool "Support for CNS3XXX DMAC"
6473+ depends on ARCH_CNS3XXX
6474+ help
6475+ Enable support for the CNS3XXX DMA controllers.
6476+
6477+choice
6478+ prompt "PROM VERSTION"
6479+ default SILICON
6480+ help
6481+ Select the PROM interrupt ID mapping.
6482+config SILICON
6483+ bool "CNS3XXX_SILICON"
6484+ help
6485+ Temporary option.
6486+ Interrupt
6487+ ID Source Function Trigger Type
6488+ --- ------------- ------------- ----------------
6489+ 32 clkscale_intr PMU rising edge
6490+ 33 sdio_intr SDIO high level
6491+ 34 l2cc_intr L2CC high level
6492+ 35 rtc_intr RTC high level
6493+ 36 i2s_intr I2S high level
6494+ 37 pcm_intr_n PCM high level
6495+ 38 spi_intr_n SPI high level
6496+ 39 i2c_intr_n I2C high level
6497+ 40 cim_intr CIM high level
6498+ 41 gpu_intr GPU high level
6499+ 42 lcd_intr LCD high level
6500+ 43 gpioa_intr GPIOA programmable
6501+ 44 gpiob_intr GPIOB programmable
6502+ 45 irda0_intr UART0 high level
6503+ 46 irda1_intr UART1 high level
6504+ 47 irda2_intr UART2 high level
6505+ 48 arm11_intr ARM11 high level
6506+ 49 swsta_intr PSE Status high level
6507+ 50 tstc_r0_intr PSE R0TxComplete rising edge
6508+ 51 fstc_r0_intr PSE R0RxComplete rising edge
6509+ 52 tsqe_r0_intr PSE R0QEmpty rising edge
6510+ 53 tsqe_r0_intr PSE R0QFull rising edge
6511+ 54 tstc_r1_intr PSE R1TxComplete rising edge
6512+ 55 fstc_r1_intr PSE R1RxComplete rising edge
6513+ 56 tsqe_r1_intr PSE R1QEmpty rising edge
6514+ 57 tsqe_r1_intr PSE R1QFull rising edge
6515+ 58 hnat_intr PPE high level
6516+ 59 crypto_intr CRYPTO high level
6517+ 60 hcie_intr HCIE rising edge
6518+ 61 pcie0_intr PCIE0 Device high level
6519+ 62 pcie1_intr PCIE1 Device high level
6520+ 63 usbotg_intr USB OTG high level
6521+ 64 ehci_intr USB EHCI high level
6522+ 65 sata_intr SATA high level
6523+ 66 raid_intr_n RAID high level
6524+ 67 smc_intr_n SMC high level
6525+ 68 dmac_abort_intr DMAC high level
6526+ 86:69 dmac_intr[17:0] DMAC high level
6527+ 87 pcie0_rc_intr PCIE0 RC high level
6528+ 88 pcie1_rc_intr PCIE1 RC high level
6529+ 89 timer1_intr TIMER 1 high level
6530+ 90 timer2_intr TIMER 2 high level
6531+ 91 ochi_intr_n USB OCHI high level
6532+ 92 timer3_intr TIMER 3 high level
6533+ 93 ext_intr0 Extrenal Pin programmable
6534+ 94 ext_intr1 Extrenal Pin programmable
6535+ 95 ext_intr2 Extrenal Pin programmable
6536+
6537+endchoice
6538+
6539+config CNS3XXX_GPU_ENVIRONMENT
6540+ bool "CNS3XXX GPU(GC300 2D Acceleration) Support"
6541+ default n
6542+ help
6543+ Say Y if you want to support 2D acceleration.
6544+
6545+endmenu
6546+
6547--- /dev/null
6548+++ b/arch/arm/mach-cns3xxx/laguna-setup.c
6549@@ -0,0 +1,593 @@
6550+/*
6551+ * linux/arch/arm/mach-cns3xxx/laguna.c
6552+ *
6553+ * Copyright (c) 2008 Cavium Networks
6554+ * Copyright (C) 2008 ARM Limited
6555+ * Copyright (C) 2000 Deep Blue Solutions Ltd
6556+ *
6557+ * This file is free software; you can redistribute it and/or modify
6558+ * it under the terms of the GNU General Public License, Version 2, as
6559+ * published by the Free Software Foundation.
6560+ *
6561+ * This file is distributed in the hope that it will be useful,
6562+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
6563+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6564+ * NONINFRINGEMENT. See the GNU General Public License for more details.
6565+ *
6566+ * You should have received a copy of the GNU General Public License
6567+ * along with this file; if not, write to the Free Software
6568+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
6569+ * visit http://www.gnu.org/licenses/.
6570+ *
6571+ * This file may also be available under a different license from Cavium.
6572+ * Contact Cavium Networks for more information
6573+ */
6574+
6575+#include <linux/init.h>
6576+#include <linux/kernel.h>
6577+#include <linux/device.h>
6578+#include <linux/if_ether.h>
6579+#include <linux/socket.h>
6580+#include <linux/netdevice.h>
6581+
6582+#include <linux/serial.h>
6583+#include <linux/tty.h>
6584+#include <linux/serial_8250.h>
6585+#include <linux/slab.h>
6586+#include <linux/spi/spi.h>
6587+#include <linux/spi/flash.h>
6588+#include <linux/i2c.h>
6589+#include <linux/i2c/at24.h>
6590+#include <linux/leds.h>
6591+#include <linux/i2c/pca953x.h>
6592+#include <linux/mtd/mtd.h>
6593+#include <linux/mtd/partitions.h>
6594+#include <linux/mtd/physmap.h>
6595+#include <linux/mmc/host.h>
6596+#include <mach/lm.h>
6597+#include <mach/sdhci.h>
6598+
6599+#include <asm/types.h>
6600+#include <asm/setup.h>
6601+#include <asm/memory.h>
6602+#include <mach/hardware.h>
6603+#include <asm/mach-types.h>
6604+#include <asm/irq.h>
6605+#include <asm/mach/arch.h>
6606+#include <linux/irq.h>
6607+
6608+#include "core.h"
6609+
6610+struct laguna_board_info {
6611+ char model[6];
6612+ u32 config_bitmap;
6613+ u32 config2_bitmap;
6614+ u8 nor_flash_size;
6615+ u8 spi_flash_size;
6616+};
6617+
6618+static struct laguna_board_info laguna_info __initdata;
6619+
6620+/*
6621+ * Cavium Networks ARM11 MPCore platform devices
6622+ */
6623+
6624+static struct mtd_partition laguna_norflash_partitions[] = {
6625+ /* Bootloader */
6626+ {
6627+ .name = "bootloader",
6628+ .offset = 0,
6629+ .size = SZ_256K,
6630+ .mask_flags = MTD_WRITEABLE, /* force read-only */
6631+ },
6632+ /* Bootloader params */
6633+ {
6634+ .name = "params",
6635+ .offset = SZ_256K,
6636+ .size = SZ_128K,
6637+ .mask_flags = 0,
6638+ },
6639+ /* linux */
6640+ {
6641+ .name = "linux",
6642+ .offset = SZ_256K + SZ_128K,
6643+ .size = SZ_2M,
6644+ .mask_flags = 0,
6645+ },
6646+ /* Root FS */
6647+ {
6648+ .name = "rootfs",
6649+ .offset = SZ_256K + SZ_128K + SZ_2M,
6650+ .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
6651+ .mask_flags = 0,
6652+ }
6653+};
6654+
6655+static struct physmap_flash_data laguna_norflash_data = {
6656+ .width = 2,
6657+ .parts = laguna_norflash_partitions,
6658+ .nr_parts = ARRAY_SIZE(laguna_norflash_partitions),
6659+};
6660+
6661+static struct resource laguna_norflash_resource = {
6662+ .start = CNS3XXX_FLASH0_BASE,
6663+ .end = CNS3XXX_FLASH0_BASE + SZ_16M - 1,
6664+ .flags = IORESOURCE_MEM,
6665+};
6666+
6667+static struct platform_device laguna_norflash_device = {
6668+ .name = "physmap-flash",
6669+ .id = 0,
6670+ .dev = {
6671+ .platform_data = &laguna_norflash_data,
6672+ },
6673+ .num_resources = 1,
6674+ .resource = &laguna_norflash_resource,
6675+};
6676+
6677+/* UART0 */
6678+static struct resource laguna_uart_resources[] = {
6679+ {
6680+ .start = CNS3XXX_UART0_BASE,
6681+ .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
6682+ .flags = IORESOURCE_MEM
6683+ },{
6684+ .start = CNS3XXX_UART1_BASE,
6685+ .end = CNS3XXX_UART1_BASE + SZ_4K - 1,
6686+ .flags = IORESOURCE_MEM
6687+ },{
6688+ .start = CNS3XXX_UART2_BASE,
6689+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
6690+ .flags = IORESOURCE_MEM
6691+ },
6692+};
6693+
6694+static struct plat_serial8250_port laguna_uart_data[] = {
6695+ {
6696+ .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
6697+ .mapbase = (CNS3XXX_UART0_BASE),
6698+ .irq = IRQ_CNS3XXX_UART0,
6699+ .iotype = UPIO_MEM,
6700+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
6701+ .regshift = 2,
6702+ .uartclk = 24000000,
6703+ .type = PORT_16550A,
6704+ },{
6705+ .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
6706+ .mapbase = (CNS3XXX_UART1_BASE),
6707+ .irq = IRQ_CNS3XXX_UART1,
6708+ .iotype = UPIO_MEM,
6709+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
6710+ .regshift = 2,
6711+ .uartclk = 24000000,
6712+ .type = PORT_16550A,
6713+ },{
6714+ .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
6715+ .mapbase = (CNS3XXX_UART2_BASE),
6716+ .irq = IRQ_CNS3XXX_UART2,
6717+ .iotype = UPIO_MEM,
6718+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
6719+ .regshift = 2,
6720+ .uartclk = 24000000,
6721+ .type = PORT_16550A,
6722+ },
6723+ { },
6724+};
6725+
6726+static struct platform_device laguna_uart = {
6727+ .name = "serial8250",
6728+ .id = PLAT8250_DEV_PLATFORM,
6729+ .dev.platform_data = laguna_uart_data,
6730+ .num_resources = 3,
6731+ .resource = laguna_uart_resources
6732+};
6733+
6734+/* SDIO, MMC/SD */
6735+static struct resource laguna_sdio_resource[] = {
6736+ {
6737+ .start = CNS3XXX_SDIO_BASE,
6738+ .end = CNS3XXX_SDIO_BASE + SZ_4K - 1,
6739+ .flags = IORESOURCE_MEM,
6740+ },{
6741+ .start = IRQ_CNS3XXX_SDIO,
6742+ .end = IRQ_CNS3XXX_SDIO,
6743+ .flags = IORESOURCE_IRQ,
6744+ },
6745+};
6746+
6747+struct cns3xxx_sdhci_platdata laguna_sdio_platform_data = {
6748+ .max_width = 4,
6749+ .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
6750+};
6751+
6752+static u64 laguna_device_sdhci_dmamask = 0xffffffffUL;
6753+
6754+static struct platform_device laguna_sdio_device = {
6755+ .name = "cns3xxx-sdhci",
6756+ .id = 0,
6757+ .num_resources = ARRAY_SIZE(laguna_sdio_resource),
6758+ .resource = laguna_sdio_resource,
6759+ .dev = {
6760+ .dma_mask = &laguna_device_sdhci_dmamask,
6761+ .coherent_dma_mask = 0xffffffffUL,
6762+ .platform_data = &laguna_sdio_platform_data,
6763+ }
6764+};
6765+
6766+static struct pca953x_platform_data laguna_pca_data = {
6767+ .gpio_base = 100,
6768+};
6769+
6770+static struct resource laguna_i2c_resource[] = {
6771+ {
6772+ .start = CNS3XXX_SSP_BASE + 0x20,
6773+ .end = 0x7100003f,
6774+ .flags = IORESOURCE_MEM,
6775+ },{
6776+ .start = IRQ_CNS3XXX_I2C,
6777+ .flags = IORESOURCE_IRQ,
6778+ },
6779+};
6780+
6781+static struct platform_device laguna_i2c_controller_device = {
6782+ .name = "cns3xxx-i2c",
6783+ .num_resources = 2,
6784+ .resource = laguna_i2c_resource,
6785+};
6786+
6787+static struct resource laguna_usb_ehci_resource[] = {
6788+ {
6789+ .start = CNS3XXX_USB_BASE,
6790+ .end = CNS3XXX_USB_BASE + SZ_16M - 1,
6791+ .flags = IORESOURCE_MEM,
6792+ },{
6793+ .start = IRQ_CNS3XXX_USB_EHCI,
6794+ .flags = IORESOURCE_IRQ,
6795+ },
6796+};
6797+
6798+static u64 laguna_usb_dma_mask = 0xffffffffULL;
6799+
6800+static struct platform_device laguna_usb_ehci_device = {
6801+ .name = "cns3xxx-ehci",
6802+ .num_resources = ARRAY_SIZE(laguna_usb_ehci_resource),
6803+ .resource = laguna_usb_ehci_resource,
6804+ .dev = {
6805+ .dma_mask = &laguna_usb_dma_mask,
6806+ .coherent_dma_mask = 0xffffffffULL,
6807+ },
6808+};
6809+
6810+static struct resource laguna_usb_ohci_resource[] = {
6811+ {
6812+ .start = CNS3XXX_USB_OHCI_BASE,
6813+ .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
6814+ .flags = IORESOURCE_MEM,
6815+ },{
6816+ .start = IRQ_CNS3XXX_USB_OHCI,
6817+ .flags = IORESOURCE_IRQ,
6818+ },
6819+};
6820+
6821+static u64 laguna_usb_ohci_dma_mask = 0xffffffffULL;
6822+static struct platform_device laguna_usb_ohci_device = {
6823+ .name = "cns3xxx-ohci",
6824+ .dev = {
6825+ .dma_mask = &laguna_usb_ohci_dma_mask,
6826+ .coherent_dma_mask = 0xffffffffULL,
6827+ },
6828+ .num_resources = 2,
6829+ .resource = laguna_usb_ohci_resource,
6830+};
6831+
6832+static u64 laguna_usbotg_dma_mask = 0xffffffffULL;
6833+static struct lm_device laguna_usb_otg_device = {
6834+ .dev = {
6835+ .dma_mask = &laguna_usbotg_dma_mask,
6836+ .coherent_dma_mask = 0xffffffffULL,
6837+ },
6838+ .resource = {
6839+ .start = CNS3XXX_USBOTG_BASE,
6840+ .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
6841+ .flags = IORESOURCE_MEM,
6842+ },
6843+ .irq = IRQ_CNS3XXX_USB_OTG,
6844+};
6845+
6846+static struct resource laguna_ahci_resource[] = {
6847+ {
6848+ .start = CNS3XXX_SATA2_BASE,
6849+ .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
6850+ .flags = IORESOURCE_MEM,
6851+ },
6852+ {
6853+ .start = IRQ_CNS3XXX_SATA,
6854+ .end = IRQ_CNS3XXX_SATA,
6855+ .flags = IORESOURCE_IRQ,
6856+ },
6857+};
6858+
6859+static u64 laguna_device_ahci_dmamask = 0xffffffffUL;
6860+
6861+static struct platform_device laguna_ahci = {
6862+ .name = "cns3xxx_ahci",
6863+ .id = -1,
6864+ .dev = {
6865+ .dma_mask = &laguna_device_ahci_dmamask,
6866+ .coherent_dma_mask = 0xffffffffUL,
6867+ },
6868+ .resource = laguna_ahci_resource,
6869+ .num_resources = ARRAY_SIZE(laguna_ahci_resource),
6870+};
6871+
6872+/* SPI Flash */
6873+static struct mtd_partition laguna_spiflash_partitions[] = {
6874+ /* Bootloader */
6875+ {
6876+ .name = "bootloader",
6877+ .offset = 0,
6878+ .size = SZ_128K,
6879+ },
6880+ /* Bootloader params */
6881+ {
6882+ .name = "params",
6883+ .offset = SZ_128K,
6884+ .size = SZ_128K,
6885+ },
6886+ /* linux */
6887+ {
6888+ .name = "linux",
6889+ .offset = SZ_256K,
6890+ .size = 0x180000,
6891+ .mask_flags = 0,
6892+ },
6893+ /* FileSystem */
6894+ {
6895+ .name = "rootfs",
6896+ .offset = SZ_256K + 0x180000,
6897+ .size = SZ_4M - SZ_256K - 0x180000,
6898+ }
6899+};
6900+
6901+static struct flash_platform_data laguna_spiflash_data = {
6902+ .parts = laguna_spiflash_partitions,
6903+ .nr_parts = ARRAY_SIZE(laguna_spiflash_partitions),
6904+};
6905+
6906+static struct spi_board_info __initdata laguna_spi_devices[] = {
6907+ {
6908+ .modalias = "m25p80",
6909+ .platform_data = &laguna_spiflash_data,
6910+ .max_speed_hz = 50000000,
6911+ .bus_num = 1,
6912+ .chip_select = 0,
6913+ },
6914+};
6915+
6916+static struct platform_device laguna_spi_controller_device = {
6917+ .name = "cns3xxx_spi",
6918+};
6919+
6920+static struct gpio_led laguna_gpio_leds[] = {
6921+ {
6922+ .name = "user1", /* Green Led */
6923+ .gpio = 115,
6924+ .active_low = 1,
6925+ },
6926+ {
6927+ .name = "user2", /* Red Led */
6928+ .gpio = 114,
6929+ .active_low = 1,
6930+ },
6931+};
6932+
6933+static struct gpio_led_platform_data laguna_gpio_leds_data = {
6934+ .num_leds = 2,
6935+ .leds = laguna_gpio_leds,
6936+};
6937+
6938+static struct platform_device laguna_gpio_leds_device = {
6939+ .name = "leds-gpio",
6940+ .id = -1,
6941+ .dev.platform_data = &laguna_gpio_leds_data,
6942+};
6943+
6944+static struct eth_plat_info laguna_net_data = {
6945+ .ports = 3, // Bring Up both Eth port by Default
6946+};
6947+
6948+static struct platform_device laguna_net_device = {
6949+ .name = "cns3xxx-net",
6950+ .id = -1,
6951+ .dev.platform_data = &laguna_net_data,
6952+};
6953+
6954+static struct memory_accessor *at24_mem_acc;
6955+
6956+static void at24_setup(struct memory_accessor *mem_acc, void *context)
6957+{
6958+ char buf[8];
6959+
6960+ at24_mem_acc = mem_acc;
6961+
6962+ /* Read MAC addresses */
6963+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
6964+ memcpy(&laguna_net_data.eth0_hwaddr, buf, ETH_ALEN);
6965+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
6966+ memcpy(&laguna_net_data.eth1_hwaddr, buf, ETH_ALEN);
6967+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
6968+ memcpy(&laguna_net_data.eth2_hwaddr, buf, ETH_ALEN);
6969+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
6970+ memcpy(&laguna_net_data.cpu_hwaddr, buf, ETH_ALEN);
6971+
6972+ /* Read out Model Information */
6973+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
6974+ memcpy(&laguna_info.model, buf, 16);
6975+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
6976+ memcpy(&laguna_info.nor_flash_size, buf, 1);
6977+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
6978+ memcpy(&laguna_info.spi_flash_size, buf, 1);
6979+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
6980+ memcpy(&laguna_info.config_bitmap, buf, 8);
6981+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
6982+ memcpy(&laguna_info.config2_bitmap, buf, 8);
6983+};
6984+
6985+static struct at24_platform_data laguna_eeprom_info = {
6986+ .byte_len = 1024,
6987+ .page_size = 16,
6988+ .flags = AT24_FLAG_READONLY,
6989+ .setup = at24_setup,
6990+};
6991+
6992+static struct i2c_board_info __initdata laguna_i2c_devices[] = {
6993+ {
6994+ I2C_BOARD_INFO("pca9555", 0x23),
6995+ .platform_data = &laguna_pca_data,
6996+ },
6997+ {
6998+ I2C_BOARD_INFO("gsp", 0x29),
6999+ },
7000+ {
7001+ I2C_BOARD_INFO ("24c08",0x50),
7002+ .platform_data = &laguna_eeprom_info,
7003+ },
7004+ {
7005+ I2C_BOARD_INFO("ds1672", 0x68),
7006+ },
7007+};
7008+
7009+static void __init laguna_init(void)
7010+{
7011+ cns3xxx_sys_init();
7012+
7013+ platform_device_register(&laguna_i2c_controller_device);
7014+
7015+ i2c_register_board_info(0, laguna_i2c_devices, ARRAY_SIZE(laguna_i2c_devices));
7016+
7017+ pm_power_off = cns3xxx_power_off;
7018+}
7019+
7020+static int __init laguna_model_setup(void)
7021+{
7022+ if (!machine_is_gw2388())
7023+ return 0;
7024+
7025+ printk("Running on Gateworks Laguna %s\n", laguna_info.model);
7026+
7027+ if (strncmp(laguna_info.model, "GW", 2) == 0) {
7028+ if (laguna_info.config_bitmap & ETH0_LOAD)
7029+ laguna_net_data.ports |= BIT(0);
7030+ if (laguna_info.config_bitmap & ETH1_LOAD)
7031+ laguna_net_data.ports |= BIT(1);
7032+ if (laguna_info.config_bitmap & ETH2_LOAD)
7033+ laguna_net_data.ports |= BIT(2);
7034+ if (laguna_net_data.ports)
7035+ platform_device_register(&laguna_net_device);
7036+
7037+ if (laguna_info.config_bitmap & (SATA0_LOAD | SATA1_LOAD))
7038+ platform_device_register(&laguna_ahci);
7039+
7040+ if (laguna_info.config_bitmap & (PCIe0_LOAD))
7041+ cns3xxx_pcie_init(1);
7042+
7043+ if (laguna_info.config_bitmap & (PCIe1_LOAD))
7044+ cns3xxx_pcie_init(2);
7045+
7046+ if (laguna_info.config_bitmap & (USB0_LOAD))
7047+ lm_device_register(&laguna_usb_otg_device);
7048+
7049+ if (laguna_info.config_bitmap & (USB1_LOAD)) {
7050+ platform_device_register(&laguna_usb_ehci_device);
7051+ platform_device_register(&laguna_usb_ohci_device);
7052+ }
7053+
7054+ if (laguna_info.config_bitmap & (SD_LOAD))
7055+ platform_device_register(&laguna_sdio_device);
7056+
7057+ if (laguna_info.config_bitmap & (UART0_LOAD))
7058+ laguna_uart.num_resources = 1;
7059+ if (laguna_info.config_bitmap & (UART1_LOAD))
7060+ laguna_uart.num_resources = 2;
7061+ if (laguna_info.config_bitmap & (UART2_LOAD))
7062+ laguna_uart.num_resources = 3;
7063+ platform_device_register(&laguna_uart);
7064+
7065+ if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
7066+ switch (laguna_info.nor_flash_size) {
7067+ case 1:
7068+ laguna_norflash_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
7069+ laguna_norflash_resource.end = CNS3XXX_FLASH0_BASE + SZ_8M - 1;
7070+ break;
7071+ case 2:
7072+ laguna_norflash_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
7073+ laguna_norflash_resource.end = CNS3XXX_FLASH0_BASE + SZ_16M - 1;
7074+ break;
7075+ case 3:
7076+ laguna_norflash_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
7077+ laguna_norflash_resource.end = CNS3XXX_FLASH0_BASE + SZ_32M - 1;
7078+ break;
7079+ case 4:
7080+ laguna_norflash_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
7081+ laguna_norflash_resource.end = CNS3XXX_FLASH0_BASE + SZ_64M - 1;
7082+ break;
7083+ case 5:
7084+ laguna_norflash_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
7085+ laguna_norflash_resource.end = CNS3XXX_FLASH0_BASE + SZ_128M - 1;
7086+ break;
7087+ }
7088+ platform_device_register(&laguna_norflash_device);
7089+ }
7090+
7091+ if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
7092+ switch (laguna_info.spi_flash_size) {
7093+ case 1:
7094+ laguna_spiflash_partitions[3].size = SZ_4M - SZ_256K - 0x180000;
7095+ break;
7096+ case 2:
7097+ laguna_spiflash_partitions[3].size = SZ_8M - SZ_256K - 0x180000;
7098+ break;
7099+ case 3:
7100+ laguna_spiflash_partitions[3].size = SZ_16M - SZ_256K - 0x180000;
7101+ break;
7102+ case 4:
7103+ laguna_spiflash_partitions[3].size = SZ_32M - SZ_256K - 0x180000;
7104+ break;
7105+ case 5:
7106+ laguna_spiflash_partitions[3].size = SZ_64M - SZ_256K - 0x180000;
7107+ break;
7108+ }
7109+ spi_register_board_info(laguna_spi_devices, ARRAY_SIZE(laguna_spi_devices));
7110+ }
7111+
7112+ if (laguna_info.config_bitmap & (SPI0_LOAD | SPI1_LOAD))
7113+ {
7114+ platform_device_register(&laguna_spi_controller_device);
7115+ }
7116+
7117+ /*
7118+ * Do any model specific setup not known by the bitmap by matching
7119+ * the first 6 characters of the model name
7120+ */
7121+
7122+ if (strncmp(laguna_info.model, "GW2388", 6) == 0)
7123+ {
7124+ platform_device_register(&laguna_gpio_leds_device);
7125+ }
7126+ } else {
7127+ // Do some defaults here, not sure what yet
7128+ }
7129+
7130+ return 0;
7131+}
7132+late_initcall(laguna_model_setup);
7133+
7134+MACHINE_START(GW2388, "Gateworks Laguna Platform")
7135+ .phys_io = CNS3XXX_UART0_BASE,
7136+ .io_pg_offst = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc,
7137+ .boot_params = 0x00000100,
7138+ .map_io = cns3xxx_map_io,
7139+ .init_irq = cns3xxx_init_irq,
7140+ .timer = &cns3xxx_timer,
7141+ .init_machine = laguna_init,
7142+MACHINE_END
7143--- /dev/null
7144+++ b/arch/arm/mach-cns3xxx/lm.c
7145@@ -0,0 +1,98 @@
7146+/*
7147+ * linux/arch/arm/mach-integrator/lm.c
7148+ *
7149+ * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
7150+ *
7151+ * This program is free software; you can redistribute it and/or modify
7152+ * it under the terms of the GNU General Public License version 2 as
7153+ * published by the Free Software Foundation.
7154+ */
7155+#include <linux/module.h>
7156+#include <linux/init.h>
7157+#include <linux/device.h>
7158+#include <linux/version.h>
7159+#include <linux/slab.h>
7160+
7161+#include <mach/lm.h>
7162+
7163+#define to_lm_device(d) container_of(d, struct lm_device, dev)
7164+#define to_lm_driver(d) container_of(d, struct lm_driver, drv)
7165+
7166+static int lm_match(struct device *dev, struct device_driver *drv)
7167+{
7168+ return 1;
7169+}
7170+
7171+static int lm_bus_probe(struct device *dev)
7172+{
7173+ struct lm_device *lmdev = to_lm_device(dev);
7174+ struct lm_driver *lmdrv = to_lm_driver(dev->driver);
7175+
7176+ return lmdrv->probe(lmdev);
7177+}
7178+
7179+static int lm_bus_remove(struct device *dev)
7180+{
7181+ struct lm_device *lmdev = to_lm_device(dev);
7182+ struct lm_driver *lmdrv = to_lm_driver(dev->driver);
7183+
7184+ if (lmdrv->remove)
7185+ lmdrv->remove(lmdev);
7186+ return 0;
7187+}
7188+
7189+static struct bus_type lm_bustype = {
7190+ .name = "logicmodule",
7191+ .match = lm_match,
7192+ .probe = lm_bus_probe,
7193+ .remove = lm_bus_remove,
7194+};
7195+
7196+static int __init lm_init(void)
7197+{
7198+ return bus_register(&lm_bustype);
7199+}
7200+
7201+postcore_initcall(lm_init);
7202+
7203+int lm_driver_register(struct lm_driver *drv)
7204+{
7205+ drv->drv.bus = &lm_bustype;
7206+ return driver_register(&drv->drv);
7207+}
7208+
7209+void lm_driver_unregister(struct lm_driver *drv)
7210+{
7211+ driver_unregister(&drv->drv);
7212+}
7213+
7214+static void lm_device_release(struct device *dev)
7215+{
7216+ struct lm_device *d = to_lm_device(dev);
7217+
7218+ kfree(d);
7219+}
7220+
7221+int lm_device_register(struct lm_device *dev)
7222+{
7223+ int ret;
7224+
7225+ dev->dev.release = lm_device_release;
7226+ dev->dev.bus = &lm_bustype;
7227+
7228+ ret = dev_set_name(&dev->dev, "lm%d", dev->id);
7229+ if (ret)
7230+ return ret;
7231+ dev->resource.name = dev_name(&dev->dev);
7232+
7233+ ret = request_resource(&iomem_resource, &dev->resource);
7234+ if (ret == 0) {
7235+ ret = device_register(&dev->dev);
7236+ if (ret)
7237+ release_resource(&dev->resource);
7238+ }
7239+ return ret;
7240+}
7241+
7242+EXPORT_SYMBOL(lm_driver_register);
7243+EXPORT_SYMBOL(lm_driver_unregister);
7244--- /dev/null
7245+++ b/arch/arm/mach-cns3xxx/localtimer.c
7246@@ -0,0 +1,26 @@
7247+/*
7248+ * linux/arch/arm/mach-cns3xxx/localtimer.c
7249+ *
7250+ * Copyright (C) 2002 ARM Ltd.
7251+ * All Rights Reserved
7252+ *
7253+ * This program is free software; you can redistribute it and/or modify
7254+ * it under the terms of the GNU General Public License version 2 as
7255+ * published by the Free Software Foundation.
7256+ */
7257+#include <linux/init.h>
7258+#include <linux/smp.h>
7259+#include <linux/clockchips.h>
7260+
7261+#include <asm/irq.h>
7262+#include <asm/smp_twd.h>
7263+#include <asm/localtimer.h>
7264+
7265+/*
7266+ * Setup the local clock events for a CPU.
7267+ */
7268+void __cpuinit local_timer_setup(struct clock_event_device *evt)
7269+{
7270+ evt->irq = IRQ_LOCALTIMER;
7271+ twd_timer_setup(evt);
7272+}
7273--- /dev/null
7274+++ b/arch/arm/mach-cns3xxx/Makefile
7275@@ -0,0 +1,14 @@
7276+#
7277+# Makefile for the linux kernel.
7278+#
7279+
7280+obj-y := core.o lm.o
7281+obj-$(CONFIG_MACH_GW2388) += laguna-setup.o
7282+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
7283+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
7284+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
7285+obj-$(CONFIG_PCIEPORTBUS) += pcie.o
7286+obj-$(CONFIG_CNS3XXX_RAID) += rdma.o
7287+obj-$(CONFIG_CNS3XXX_DMAC) += dmac.o
7288+obj-$(CONFIG_CNS3XXX_PM_API) += pm.o
7289+
7290--- /dev/null
7291+++ b/arch/arm/mach-cns3xxx/Makefile.boot
7292@@ -0,0 +1,4 @@
7293+ zreladdr-y := 0x00008000
7294+params_phys-y := 0x00000100
7295+initrd_phys-y := 0x00C00000
7296+kernel_phys-y := 0x00600000
7297--- /dev/null
7298+++ b/arch/arm/mach-cns3xxx/platsmp.c
7299@@ -0,0 +1,220 @@
7300+/*
7301+ * linux/arch/arm/mach-cns3xxx/platsmp.c
7302+ *
7303+ * Copyright (c) 2008 Cavium Networks
7304+ * Copyright (C) 2002 ARM Ltd.
7305+ * All Rights Reserved
7306+ *
7307+ * This file is free software; you can redistribute it and/or modify
7308+ * it under the terms of the GNU General Public License, Version 2, as
7309+ * published by the Free Software Foundation.
7310+ *
7311+ * This file is distributed in the hope that it will be useful,
7312+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
7313+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
7314+ * NONINFRINGEMENT. See the GNU General Public License for more details.
7315+ *
7316+ * You should have received a copy of the GNU General Public License
7317+ * along with this file; if not, write to the Free Software
7318+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
7319+ * visit http://www.gnu.org/licenses/.
7320+ *
7321+ * This file may also be available under a different license from Cavium.
7322+ * Contact Cavium Networks for more information
7323+ */
7324+
7325+#include <linux/init.h>
7326+#include <linux/errno.h>
7327+#include <linux/delay.h>
7328+#include <linux/device.h>
7329+#include <linux/jiffies.h>
7330+#include <linux/smp.h>
7331+#include <linux/io.h>
7332+
7333+#include <asm/cacheflush.h>
7334+#include <mach/hardware.h>
7335+#include <asm/mach-types.h>
7336+#include <asm/localtimer.h>
7337+
7338+#include <asm/smp_scu.h>
7339+
7340+#include "core.h"
7341+
7342+extern void cns3xxx_secondary_startup(void);
7343+
7344+/*
7345+ * control for which core is the next to come out of the secondary
7346+ * boot "holding pen"
7347+ */
7348+volatile int __cpuinitdata pen_release = -1;
7349+
7350+static void __iomem *scu_base_addr(void)
7351+{
7352+ return (void __iomem *)(CNS3XXX_TC11MP_SCU_BASE_VIRT);
7353+}
7354+
7355+static inline unsigned int get_core_count(void)
7356+{
7357+ void __iomem *scu_base = scu_base_addr();
7358+ if (scu_base)
7359+ return scu_get_core_count(scu_base);
7360+ return 1;
7361+}
7362+
7363+static DEFINE_SPINLOCK(boot_lock);
7364+
7365+void __cpuinit platform_secondary_init(unsigned int cpu)
7366+{
7367+ trace_hardirqs_off();
7368+
7369+ /*
7370+ * if any interrupts are already enabled for the primary
7371+ * core (e.g. timer irq), then they will not have been enabled
7372+ * for us: do so
7373+ */
7374+ gic_cpu_init(0, (void __iomem *)(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
7375+ set_interrupt_pri(1, 0); // set cache broadcast ipi to highest priority
7376+
7377+ /*
7378+ * let the primary processor know we're out of the
7379+ * pen, then head off into the C entry point
7380+ */
7381+ pen_release = -1;
7382+ smp_wmb();
7383+
7384+ /*
7385+ * Synchronise with the boot thread.
7386+ */
7387+ spin_lock(&boot_lock);
7388+ spin_unlock(&boot_lock);
7389+}
7390+
7391+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
7392+{
7393+ unsigned long timeout;
7394+
7395+ /*
7396+ * set synchronisation state between this boot processor
7397+ * and the secondary one
7398+ */
7399+ spin_lock(&boot_lock);
7400+
7401+ /*
7402+ * The secondary processor is waiting to be released from
7403+ * the holding pen - release it, then wait for it to flag
7404+ * that it has been released by resetting pen_release.
7405+ *
7406+ * Note that "pen_release" is the hardware CPU ID, whereas
7407+ * "cpu" is Linux's internal ID.
7408+ */
7409+ pen_release = cpu;
7410+ flush_cache_all();
7411+
7412+ /*
7413+ * XXX
7414+ *
7415+ * This is a later addition to the booting protocol: the
7416+ * bootMonitor now puts secondary cores into WFI, so
7417+ * poke_milo() no longer gets the cores moving; we need
7418+ * to send a soft interrupt to wake the secondary core.
7419+ * Use smp_cross_call() for this, since there's little
7420+ * point duplicating the code here
7421+ */
7422+ smp_cross_call(cpumask_of(cpu));
7423+
7424+ timeout = jiffies + (1 * HZ);
7425+ while (time_before(jiffies, timeout)) {
7426+ smp_rmb();
7427+ if (pen_release == -1)
7428+ break;
7429+
7430+ udelay(10);
7431+ }
7432+
7433+ /*
7434+ * now the secondary core is starting up let it run its
7435+ * calibrations, then wait for it to finish
7436+ */
7437+ spin_unlock(&boot_lock);
7438+
7439+ return pen_release != -1 ? -ENOSYS : 0;
7440+}
7441+
7442+static void __init poke_milo(void)
7443+{
7444+ /* nobody is to be released from the pen yet */
7445+ pen_release = -1;
7446+
7447+ /* write the address of secondary startup into the general purpose register */
7448+ __raw_writel(virt_to_phys(cns3xxx_secondary_startup), (void __iomem *)(0xFFF07000 + 0x0600));
7449+
7450+ mb();
7451+}
7452+
7453+/*
7454+ * Initialise the CPU possible map early - this describes the CPUs
7455+ * which may be present or become present in the system.
7456+ */
7457+void __init smp_init_cpus(void)
7458+{
7459+ unsigned int i, ncores = get_core_count();
7460+
7461+ for (i = 0; i < ncores; i++)
7462+ set_cpu_possible(i, true);
7463+}
7464+
7465+void __init smp_prepare_cpus(unsigned int max_cpus)
7466+{
7467+ unsigned int ncores = get_core_count();
7468+ unsigned int cpu = smp_processor_id();
7469+ int i;
7470+
7471+ /* sanity check */
7472+ if (ncores == 0) {
7473+ printk(KERN_ERR
7474+ "CNS3XXX: strange CM count of 0? Default to 1\n");
7475+
7476+ ncores = 1;
7477+ }
7478+
7479+ if (ncores > NR_CPUS) {
7480+ printk(KERN_WARNING
7481+ "CNS3XXX: no. of cores (%d) greater than configured "
7482+ "maximum of %d - clipping\n",
7483+ ncores, NR_CPUS);
7484+ ncores = NR_CPUS;
7485+ }
7486+
7487+ smp_store_cpu_info(cpu);
7488+
7489+ /*
7490+ * are we trying to boot more cores than exist?
7491+ */
7492+ if (max_cpus > ncores)
7493+ max_cpus = ncores;
7494+
7495+ /*
7496+ * Initialise the present map, which describes the set of CPUs
7497+ * actually populated at the present time.
7498+ */
7499+ for (i = 0; i < max_cpus; i++)
7500+ set_cpu_present(i, true);
7501+
7502+ /*
7503+ * Initialise the SCU if there are more than one CPU and let
7504+ * them know where to start. Note that, on modern versions of
7505+ * MILO, the "poke" doesn't actually do anything until each
7506+ * individual core is sent a soft interrupt to get it out of
7507+ * WFI
7508+ */
7509+ if (max_cpus > 1) {
7510+ /*
7511+ * Enable the local timer or broadcast device for the
7512+ * boot CPU, but only if we have more than one CPU.
7513+ */
7514+ percpu_timer_setup();
7515+
7516+ scu_enable(scu_base_addr());
7517+ poke_milo();
7518+ }
7519+}
7520--- /dev/null
7521+++ b/arch/arm/mach-cns3xxx/pm.c
7522@@ -0,0 +1,476 @@
7523+/******************************************************************************
7524+ *
7525+ * Copyright (c) 2008 Cavium Networks
7526+ *
7527+ * This file is free software; you can redistribute it and/or modify
7528+ * it under the terms of the GNU General Public License, Version 2, as
7529+ * published by the Free Software Foundation.
7530+ *
7531+ * This file is distributed in the hope that it will be useful,
7532+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
7533+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
7534+ * NONINFRINGEMENT. See the GNU General Public License for more details.
7535+ *
7536+ * You should have received a copy of the GNU General Public License
7537+ * along with this file; if not, write to the Free Software
7538+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
7539+ * visit http://www.gnu.org/licenses/.
7540+ *
7541+ * This file may also be available under a different license from Cavium.
7542+ * Contact Cavium Networks for more information
7543+ *
7544+ ******************************************************************************/
7545+#include <linux/pm.h>
7546+#include <linux/interrupt.h>
7547+#include <mach/pm.h>
7548+#include <linux/init.h>
7549+#include <linux/module.h>
7550+#include <linux/proc_fs.h>
7551+#include <linux/delay.h>
7552+#include <mach/misc.h>
7553+
7554+/*
7555+ * cns3xxx_pwr_clk_en - clock enable
7556+ * @block: bitmap for peripheral
7557+ */
7558+void cns3xxx_pwr_clk_en(unsigned int block)
7559+{
7560+ PM_CLK_GATE_REG |= (block&PM_CLK_GATE_REG_MASK);
7561+}
7562+
7563+/*
7564+ * cns3xxx_pwr_soft_rst - software reset
7565+ * @block: bitmap for peripheral
7566+ */
7567+void cns3xxx_pwr_soft_rst_force(unsigned int block)
7568+{
7569+ /* bit 0, 28, 29 => program low to reset,
7570+ * the other else program low and then high
7571+ */
7572+ if (block & 0x30000001) {
7573+ PM_SOFT_RST_REG &= ~(block&PM_SOFT_RST_REG_MASK);
7574+ } else {
7575+ PM_SOFT_RST_REG &= ~(block&PM_SOFT_RST_REG_MASK);
7576+ PM_SOFT_RST_REG |= (block&PM_SOFT_RST_REG_MASK);
7577+ }
7578+}
7579+
7580+void cns3xxx_pwr_soft_rst(unsigned int block)
7581+{
7582+ static unsigned int soft_reset = 0;
7583+
7584+ if(soft_reset & block) {
7585+ //Because SPI/I2C/GPIO use the same block, just only reset once...
7586+ return;
7587+ }
7588+ else {
7589+ soft_reset |= block;
7590+ }
7591+ cns3xxx_pwr_soft_rst_force(block);
7592+}
7593+
7594+/*
7595+ * void cns3xxx_pwr_lp_hs - lower power handshake
7596+ * @dev: bitmap for device
7597+ *
7598+ */
7599+void cns3xxx_lp_hs(unsigned int dev)
7600+{
7601+
7602+ if (PM_HS_CFG_REG_MASK_SUPPORT & dev) {
7603+ PM_HS_CFG_REG |= dev;
7604+
7605+ /* TODO: disable clock */
7606+ }
7607+}
7608+
7609+/*
7610+ * cns3xxx_pwr_mode - change CPU power mode
7611+ * @pwr_mode: CPU power mode
7612+ * CNS3XXX_PWR_CPU_MODE_DFS, CNS3XXX_PWR_CPU_MODE_IDLE
7613+ * CNS3XXX_PWR_CPU_MODE_HALT, CNS3XXX_PWR_CPU_MODE_DOZE
7614+ * CNS3XXX_PWR_CPU_MODE_SLEEP, CNS3XXX_PWR_CPU_MODE_HIBERNATE
7615+ */
7616+static void cns3xxx_pwr_mode(unsigned int pwr_mode)
7617+{
7618+ if (CNS3XXX_PWR_CPU_MODE_HIBERNATE < pwr_mode) {
7619+ return;
7620+ }
7621+
7622+ PM_CLK_CTRL_REG &=
7623+ ~(0x7<<PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE);
7624+ PM_CLK_CTRL_REG |=
7625+ ((pwr_mode&0x7)<<PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE);
7626+};
7627+
7628+/* cns3xxx_pwr_power_up -
7629+ * cns3xxx_pwr_power_down -
7630+ * @dev_num: bitmap for functional block
7631+ * CNS3XXX_PWR_PLL_PCIE_PHY1, CNS3XXX_PWR_PLL_PCIE_PHY0
7632+ * CNS3XXX_PWR_PLL_SATA_PHY1, CNS3XXX_PWR_PLL_SATA_PHY0
7633+ * CNS3XXX_PWR_PLL_USB_PHY1, CNS3XXX_PWR_PLL_USB_PHY0
7634+ * CNS3XXX_PWR_PLL_I2SCD, CNS3XXX_PWR_PLL_I2S
7635+ * CNS3XXX_PWR_PLL_LCD, CNS3XXX_PWR_PLL_USB
7636+ * CNS3XXX_PWR_PLL_RGMII, CNS3XXX_PWR_PLL_ALL
7637+ */
7638+void cns3xxx_pwr_power_up(unsigned int dev_num)
7639+{
7640+ PM_PLL_HM_PD_CTRL_REG &= ~(dev_num & CNS3XXX_PWR_PLL_ALL);
7641+
7642+ /* TODO: wait for 300us for the PLL output clock locked */
7643+};
7644+
7645+void cns3xxx_pwr_power_down(unsigned int dev_num)
7646+{
7647+ /* write '1' to power down */
7648+ PM_PLL_HM_PD_CTRL_REG |= (dev_num & CNS3XXX_PWR_PLL_ALL);
7649+};
7650+
7651+#if 0
7652+/* cns3xxx_pwr_change_pll_ddr - change DDR2 frequency
7653+ * @ddr_sel: DDR2 clock select
7654+ * CNS3XXX_PWR_PLL_DDR2_200MHZ
7655+ * CNS3XXX_PWR_PLL_DDR2_266MHZ
7656+ * CNS3XXX_PWR_PLL_DDR2_333MHZ
7657+ * CNS3XXX_PWR_PLL_DDR2_400MHZ
7658+ */
7659+void cns3xxx_pwr_change_pll_ddr(unsigned int ddr_sel)
7660+{
7661+ if (CNS3XXX_PWR_PLL_DDR2_400MHZ < ddr_sel) {
7662+ return;
7663+ }
7664+
7665+ PM_CLK_CTRL_REG &= ~(0x3 << PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL);
7666+ PM_CLK_CTRL_REG |= (ddr_sel << PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL);
7667+}
7668+#endif
7669+
7670+#define GIC_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT+offset)))
7671+
7672+
7673+/* Change CPU frequency and divider */
7674+/*
7675+ * cns3xxx_pwr_change_pll_cpu - change PLL CPU frequency
7676+ * @cpu_sel: PLL CPU frequency
7677+ * @div_sel: divider
7678+ *
7679+ * This feature requires that 2nd core is in WFI mode and L2 cache is disabled
7680+ * Before calling this function, please make sure that L2 cache is not in use
7681+ *
7682+ */
7683+void cns3xxx_pwr_change_cpu_clock(unsigned int cpu_sel, unsigned int div_sel)
7684+{
7685+ /* 1. Set PLL_CPU_SEL
7686+ * 2. Set in DFS mode
7687+ * 3. disable all interrupt except interrupt ID-32 (clkscale_intr)
7688+ * 4. Let CPU enter into WFI state
7689+ * 5. Wait PMU to change PLL_CPU and divider and wake up CPU
7690+ */
7691+ int old_cpu, old_div;
7692+
7693+
7694+ /* sanity check */
7695+ if ((CNS3XXX_PWR_PLL_CPU_700MHZ < cpu_sel)
7696+ || (CNS3XXX_PWR_CPU_CLK_DIV_BY4 < div_sel)) {
7697+ return;
7698+ }
7699+
7700+ old_cpu = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) &0xf;
7701+ old_div = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
7702+
7703+ if ((cpu_sel == old_cpu)
7704+ && (div_sel == old_div)) {
7705+ return;
7706+ }
7707+
7708+ /* 1. Set PLL_CPU_SEL */
7709+ PM_PLL_CPU_SEL(cpu_sel);
7710+ PM_CPU_CLK_DIV(div_sel);
7711+
7712+ /* 2. Set in DFS mode */
7713+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DFS);
7714+
7715+ /* 3. disable all interrupt except interrupt ID-32 (clkscale_intr) */
7716+ /* disable all interrupt */
7717+ GIC_REG_VALUE(0x184) = 0xffffffff;
7718+ GIC_REG_VALUE(0x188) = 0xffffffff;
7719+ /* enable interrupt id 32*/
7720+ GIC_REG_VALUE(0x104) = 0x00000001;
7721+ GIC_REG_VALUE(0x108) = 0x80000000;
7722+
7723+ /* 4. Let CPU enter into WFI state */
7724+ asm volatile(
7725+ "mov r0, #0\n"
7726+ "mcr p15, 0, r0, c7, c0, 4\n"
7727+ );
7728+
7729+
7730+#if 0
7731+ {
7732+ int i;
7733+ for (i=IRQ_CNS3XXX_PMU+1; i<IRQ_CNS3XXX_EXTERNAL_PIN0; i++) {
7734+ enable_irq(i);
7735+ }
7736+ }
7737+#else
7738+ GIC_REG_VALUE(0x104) = 0xffffffff;
7739+ GIC_REG_VALUE(0x108) = 0xffffffff;
7740+#endif
7741+
7742+ {
7743+ /* for timer, because CPU clock is changed */
7744+ int pclk = (cns3xxx_cpu_clock() >> 3);
7745+ *(volatile unsigned int *) (CNS3XXX_TIMER1_2_3_BASE_VIRT + TIMER1_AUTO_RELOAD_OFFSET)
7746+ = pclk/15*0x25000;
7747+ }
7748+
7749+}
7750+
7751+
7752+/*
7753+ * clock_out_sel - select clock source to ClkOut pin
7754+ * This function just select pll_cpu to ClkOut pin,
7755+ * we can measure the ClkOut frequency to make sure whether pll_cpu is change
7756+ *
7757+ */
7758+void clock_out_sel(void)
7759+{
7760+
7761+ int temp = PM_CLK_CTRL_REG;
7762+ //MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 26); /* Set GPIOB26 to ClkOut*/
7763+ /* debug purpose, use ext intr 1 and 2 to generate interrupt */
7764+ //MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 27); /* Set GPIOB27 to external interrupt 2*/
7765+ //MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 28); /* Set GPIOB28 to external interrupt 1*/
7766+ /* select ClkOut source as pll_cpu_clk and ClkOut divider is by 16 */
7767+ temp &=~(0x3 << 20);
7768+ temp &=~(0xf << 16);
7769+ temp |= (0x3 << 20);
7770+ temp |= (0x1 << 16);
7771+ PM_CLK_CTRL_REG = temp;
7772+}
7773+
7774+void cns3xxx_wfi(void)
7775+{
7776+ mb();
7777+ asm volatile(
7778+ "mov r0, #0\n"
7779+ "mcr p15, 0, r0, c7, c10, 4\n"
7780+ "mcr p15, 0, r0, c7, c0, 4\n"
7781+ );
7782+}
7783+
7784+/*
7785+ * cns3xxx_pwr_sleep -
7786+ */
7787+void cns3xxx_pwr_sleep(void)
7788+{
7789+ /* 1. Set in sleep mode
7790+ * 2. disable all functional block
7791+ * 3. make sure that all function block are in power off state
7792+ * 4. power down all PLL
7793+ * 5. Let CPU enter into WFI state
7794+ * 6. Wait PMU to change PLL_CPU and divider and wake up CPU
7795+ */
7796+ int i, j, count = 0;
7797+ /* 1. Set in SLEEP mode */
7798+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_SLEEP);
7799+
7800+ /* 2. disable all functional block */
7801+ i = PM_CLK_GATE_REG;
7802+ PM_CLK_GATE_REG = 0x0;
7803+
7804+ /* 3. make sure that all function block are in power off state */
7805+ while (0x4 != PM_PWR_STA_REG) {
7806+ count++;
7807+ if (1000 == count) {
7808+ count = PM_PWR_STA_REG;
7809+ break;
7810+ }
7811+ };
7812+
7813+ /* 4. power down all PLL */
7814+ j = PM_PLL_HM_PD_CTRL_REG;
7815+ PM_PLL_HM_PD_CTRL_REG = 0x00003FFC;
7816+
7817+#if 0
7818+ /* set DMC to low power hand shake */
7819+ PM_HS_CFG_REG |= (0x1 << 2);
7820+ /* disable DMC */
7821+ PM_CLK_GATE_REG &= ~(0x1<<2);
7822+#endif
7823+
7824+ /* set wake up interrupt source, use ext_intr1 to wake up*/
7825+ PM_WU_CTRL0_REG = 0x0; PM_WU_CTRL1_REG = 0x40000000;
7826+ //MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 27);
7827+
7828+ /* 5. Let CPU enter into WFI state */
7829+ GIC_REG_VALUE(0x104) = 0x1; /* enable clock scaling interrupt */
7830+ printk("<0>enter WFI\n");
7831+ cns3xxx_wfi();
7832+ PM_CLK_GATE_REG = i;
7833+ PM_PLL_HM_PD_CTRL_REG = j;
7834+ printk("<0>leave WFI\n");
7835+ GIC_REG_VALUE(0x104) = 0xffffffff;
7836+ GIC_REG_VALUE(0x108) = 0xffffffff;
7837+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DFS);
7838+}
7839+
7840+/*
7841+ * cns3xxx_pwr_sleep_test - enter into sleep and won't be wake up
7842+ */
7843+void cns3xxx_pwr_sleep_test(void)
7844+{
7845+ int i, j, count = 0;
7846+ /* 1. Set in SLEEP mode */
7847+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_SLEEP);
7848+
7849+ /* 2. disable all functional block */
7850+ i = PM_CLK_GATE_REG;
7851+ PM_CLK_GATE_REG = 0x0;
7852+
7853+ /* 3. make sure that all function block are in power off state */
7854+ while (0x4 != PM_PWR_STA_REG) {
7855+ count++;
7856+ if (1000 == count) {
7857+ count = PM_PWR_STA_REG;
7858+ break;
7859+ }
7860+ };
7861+ /* 4. power down all PLL */
7862+ j = PM_PLL_HM_PD_CTRL_REG;
7863+ PM_PLL_HM_PD_CTRL_REG = 0x00003FFC;
7864+
7865+ /* set wake up interrupt source, do nothing */
7866+ PM_WU_CTRL0_REG = 0x0; PM_WU_CTRL1_REG = 0x00000000;
7867+
7868+ /* 5. Let CPU enter into WFI state */
7869+ GIC_REG_VALUE(0x104) = 0x1; /* enable clock scaling interrupt */
7870+ printk("<0>enter WFI\n");
7871+ cns3xxx_wfi();
7872+ PM_CLK_GATE_REG = i;
7873+ PM_PLL_HM_PD_CTRL_REG = j;
7874+ printk("<0>leave WFI, count 0x%.8x\n", count);
7875+ GIC_REG_VALUE(0x104) = 0xffffffff;
7876+ GIC_REG_VALUE(0x108) = 0xffffffff;
7877+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DFS);
7878+}
7879+
7880+/*
7881+ * cns3xxx_pwr_doze -
7882+ */
7883+void cns3xxx_pwr_doze(void)
7884+{
7885+ /* 1. Set in doze mode */
7886+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DOZE);
7887+
7888+
7889+ /* set wake up interrupt source*/
7890+ PM_WU_CTRL0_REG = 0x0; PM_WU_CTRL1_REG = 0x40000000;
7891+ //MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 27);
7892+
7893+ /* 5. Let CPU enter into WFI state */
7894+ GIC_REG_VALUE(0x104) = 0x1; /* enable clock scaling interrupt */
7895+ printk("<0>enter WFI\n");
7896+ cns3xxx_wfi();
7897+ printk("<0>leave WFI\n");
7898+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DFS);
7899+}
7900+
7901+/*
7902+ * cns3xxx_pwr_idle -
7903+ * IDLE mode just turn off CPU clock.
7904+ * L2 cache, peripheral, PLL, external DRAM and chip power are still on
7905+ */
7906+void cns3xxx_pwr_idle(void)
7907+{
7908+ /* 1. Set in IDLE mode */
7909+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_IDLE);
7910+
7911+#if 1
7912+ /* disable all interrupt except interrupt ID-32 (clkscale_intr)
7913+ *
7914+ * CPU can be wake up by any interrupt here,
7915+ * we disable all interrupt is just for testing
7916+ */
7917+
7918+ /* disable all interrupt */
7919+ GIC_REG_VALUE(0x184) = 0xffffffff; GIC_REG_VALUE(0x188) = 0xffffffff;
7920+ /* enable interrupt id 32*/
7921+ GIC_REG_VALUE(0x104) = 0x00000001; GIC_REG_VALUE(0x108) = 0x00000000;
7922+#endif
7923+
7924+ /* set wake up interrupt source*/
7925+ PM_WU_CTRL0_REG = 0x0; PM_WU_CTRL1_REG = 0x40000000;
7926+ //MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 27);
7927+
7928+ /* 5. Let CPU enter into WFI state */
7929+ printk("<0>enter WFI\n");
7930+ cns3xxx_wfi();
7931+ printk("<0>leave WFI\n");
7932+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DFS);
7933+ GIC_REG_VALUE(0x104) = 0xffffffff;
7934+ GIC_REG_VALUE(0x108) = 0xffffffff;
7935+}
7936+
7937+/*
7938+ * cns3xxx_pwr_halt -
7939+ * HALT mode just turn off CPU and L2 cache clock.
7940+ * peripheral, PLL, external DRAM and chip power are still on
7941+ */
7942+
7943+void cns3xxx_pwr_halt(void)
7944+{
7945+ /* 1. Set in HALT mode */
7946+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_HALT);
7947+
7948+ /*
7949+ * CPU can be wake up by any interrupt here,
7950+ * for test, we disable all interrupt except ID-32
7951+ */
7952+ /* disable all interrupt */
7953+ GIC_REG_VALUE(0x184) = 0xffffffff; GIC_REG_VALUE(0x188) = 0xffffffff;
7954+ /* enable interrupt id 32*/
7955+ GIC_REG_VALUE(0x104) = 0x00000001; GIC_REG_VALUE(0x108) = 0x00000000;
7956+
7957+ /* set wake up interrupt source to trigger clock scaling interrupt */
7958+ PM_WU_CTRL0_REG = 0x0; PM_WU_CTRL1_REG = 0x40000000;
7959+ //MISC_GPIOB_PIN_ENABLE_REG |= (0x1 << 27);
7960+
7961+ /* 5. Let CPU enter into WFI state */
7962+ cns3xxx_wfi();
7963+ cns3xxx_pwr_mode(CNS3XXX_PWR_CPU_MODE_DFS);
7964+ GIC_REG_VALUE(0x104) = 0xffffffff;
7965+ GIC_REG_VALUE(0x108) = 0xffffffff;
7966+}
7967+
7968+/*
7969+ * cns3xxx_cpu_clock - return CPU/L2 clock
7970+ * aclk: cpu clock/2
7971+ * hclk: cpu clock/4
7972+ * pclk: cpu clock/8
7973+ */
7974+int cns3xxx_cpu_clock(void)
7975+{
7976+#define CPU_BASE 300
7977+ int cpu, cpu_sel, div_sel;
7978+
7979+ cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
7980+ div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
7981+
7982+ cpu = (CPU_BASE + ((cpu_sel/3) * 100) + ((cpu_sel %3) *33)) >> div_sel;
7983+ return cpu;
7984+}
7985+
7986+static int __init cns3xxx_pmu_init(void)
7987+{
7988+ return 0;
7989+}
7990+
7991+
7992+EXPORT_SYMBOL(cns3xxx_pwr_power_up);
7993+EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
7994+EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
7995+EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
7996+EXPORT_SYMBOL(cns3xxx_cpu_clock);
7997+
7998+module_init(cns3xxx_pmu_init);
7999--- /dev/null
8000+++ b/arch/arm/mach-cns3xxx/rdma.c
8001@@ -0,0 +1,901 @@
8002+/*
8003+ * rdma.c - CNS3XXX RAID-DMA h/w acceleration
8004+ *
8005+ * Revision History: arch/arm/mach-cns3xxx/ChangeLog.cns_raid.txt
8006+ */
8007+#include <linux/kernel.h>
8008+#include <linux/types.h>
8009+#include <linux/init.h>
8010+#include <linux/sched.h>
8011+#include <linux/spinlock.h>
8012+#include <linux/slab.h>
8013+#include <linux/errno.h>
8014+#include <linux/interrupt.h>
8015+#include <linux/sched.h>
8016+#include <linux/wait.h>
8017+#include <linux/list.h>
8018+#include <linux/mm.h>
8019+#include <linux/pagemap.h>
8020+#include <linux/module.h>
8021+#include <linux/delay.h>
8022+#include <asm/io.h>
8023+#include <mach/irqs.h>
8024+#include <linux/mempool.h>
8025+#include <linux/dma-mapping.h>
8026+
8027+#include "rdma.h"
8028+#include <mach/pm.h>
8029+
8030+int rdma_verbose;
8031+u8 rdma_test_ptn[32] = {0};
8032+unsigned int dma_timeout_jiffies;
8033+mempool_t *rdma_sg_pool = NULL; /* pool */
8034+rdma_chan_t *dma = NULL; /* dma channel */
8035+
8036+static DEFINE_SPINLOCK(process_lock);
8037+
8038+/* Debug Printk */
8039+#define dprintk(x...) ((void)(rdma_verbose && printk(KERN_WARNING x)))
8040+#define dump_regs(x) \
8041+do { \
8042+ dprintk("pa:%08x sg:%08x bp:%08x fp:%08x st:%08x qp:%08x sz:%08x\n", \
8043+ *((x)->cregs->para), \
8044+ *((x)->cregs->sgad), \
8045+ *((x)->cregs->back), \
8046+ *((x)->cregs->frnt), \
8047+ *((x)->cregs->stat), \
8048+ *((x)->cregs->qpar), \
8049+ *((x)->cregs->blsz)); \
8050+} while (0)
8051+
8052+
8053+#define rdma_dmac_flush_range(start, bytes) \
8054+ do { \
8055+ dma_cache_maint(start, bytes, DMA_BIDIRECTIONAL); \
8056+ } while (0);
8057+
8058+#define rdma_dmac_inv_range(start, bytes) \
8059+ do { \
8060+ dma_cache_maint(start, bytes, DMA_FROM_DEVICE); \
8061+ } while (0);
8062+
8063+#define rdma_dmac_clean_range(start, bytes) \
8064+ do { \
8065+ dma_cache_maint(start, bytes, DMA_TO_DEVICE); \
8066+ } while (0);
8067+
8068+
8069+
8070+extern void *acs_mempool_alloc(mempool_t *pool);
8071+
8072+/**
8073+ * rdma_timeout_handle
8074+ */
8075+static void rdma_timeout_handle(rdma_chan_t *rdma)
8076+{
8077+ printk("%s: timeout handling\n", __FUNCTION__);
8078+ spin_lock_irq(&process_lock);
8079+
8080+ if (!list_empty(&rdma->process_q)) {
8081+ sg_t *sg_fin = list_entry(rdma->process_q.next, sg_t, lru);
8082+ list_del_init(&sg_fin->lru);
8083+ sg_fin->status = SG_STATUS_DONE;
8084+ }
8085+
8086+ *(dma->cregs->para) = 0;
8087+ *(dma->cregs->back) = rdma->q_first_phys;
8088+ *(dma->cregs->frnt) = rdma->q_first_phys;
8089+ flush_cache_all();
8090+ spin_unlock_irq(&process_lock);
8091+}
8092+
8093+/**
8094+ * rdma_mempool_alloc - return a sg from pool
8095+ * @gfp_mask: gfp flag
8096+ *
8097+ * Return:
8098+ * sg table
8099+ */
8100+static void *rdma_sg_mempool_alloc(unsigned int gfp_mask)
8101+{
8102+ void *element;
8103+ int exception_timeout = 30;
8104+
8105+repeat:
8106+ element = acs_mempool_alloc(rdma_sg_pool);
8107+ if (likely(element))
8108+ return element;
8109+
8110+ if (!(gfp_mask & __GFP_WAIT)) {
8111+ return NULL;
8112+ } else {
8113+ msleep(1000);
8114+ exception_timeout--;
8115+ WARN_ON(exception_timeout < 0); /* Thresh check, we should check or increase if any warning */
8116+ goto repeat;
8117+ }
8118+}
8119+
8120+#define rdma_mempool_create(pool, name, size, min_nr, alloc_fn, free_fn, privp) \
8121+do { \
8122+ printk("%s: pre-allocating %s: %d*%d=%d\n", \
8123+ __FUNCTION__, (name), (min_nr), (size), (min_nr) * (size)); \
8124+ pool = mempool_create((min_nr), (mempool_alloc_t *)(alloc_fn), free_fn, (privp)); \
8125+ if (!pool) \
8126+ goto abort; \
8127+} while(0);
8128+
8129+#define rdma_mempool_destroy(pool) \
8130+do { \
8131+ if (pool) \
8132+ mempool_destroy(pool); \
8133+} while(0);
8134+
8135+#define rdma_kfree_obj(obj) \
8136+do { \
8137+ if (obj) \
8138+ kfree(obj); \
8139+} while(0);
8140+
8141+/**
8142+ * rdma_sg_prealloc_fn - sg mempool pre-allocation callback
8143+ * @gfp_flags: GFP_ flags
8144+ * @data: private data, reserved
8145+ *
8146+ * Return:
8147+ * pre-alloc sg table
8148+ */
8149+static void *rdma_sg_prealloc_fn(int gfp_flags, void *data)
8150+{
8151+ sg_t *sg = NULL;
8152+ sg = kzalloc(sizeof(sg_t), gfp_flags);
8153+ INIT_LIST_HEAD(&sg->lru);
8154+ init_waitqueue_head(&sg->wait);
8155+ sg->status = SG_STATUS_FREE;
8156+
8157+ /* Remove Debug Message */
8158+#if 0
8159+ printk("%s: pre-allocating sg=0x%p, phy=0x%p\n",
8160+ __FUNCTION__, (void *)sg, (void *)virt_to_phys(sg));
8161+#endif
8162+
8163+ WARN_ON(!sg);
8164+ return (void *)sg;
8165+}
8166+
8167+/**
8168+ * rdma_sg_deconstruct_fn - sg mempool de-allocation callback
8169+ * @sg: sg elements
8170+ * @data: private data, reserved
8171+ */
8172+static void rdma_sg_deconstruct_fn(void *sg, void *data)
8173+{
8174+ if (sg) {
8175+ printk("%s: de-allocating sg=0x%p, phy=0x%p\n",
8176+ __FUNCTION__, (void *)sg, (void *)virt_to_phys(sg));
8177+ kfree(sg);
8178+ }
8179+ return;
8180+}
8181+
8182+
8183+
8184+/*-------------------------------------------------------- */
8185+/**
8186+ * rdma_get_sg - alloc an SG
8187+ * @dma: dma chan
8188+ */
8189+static sg_t *rdma_get_sg(rdma_chan_t *dma)
8190+{
8191+ sg_t *sg = (sg_t *)rdma_sg_mempool_alloc(GFP_KERNEL);
8192+
8193+ /*
8194+ * No need to zero rest of un-used SG entries;
8195+ * we detect the src+dst by parameter + sg, not by zero-valued sg.
8196+ */
8197+ // memzero(&(sg->entry[0]), SG_ENTRY_BYTES);
8198+
8199+ sg->status = SG_STATUS_ACQUIRED;
8200+
8201+ return sg;
8202+}
8203+
8204+
8205+/**
8206+ * rdma_queue_sg - queue an SG, wait done and put it.
8207+ * @dma: dma chan
8208+ * @sg: sg
8209+ * @q_para: parameter
8210+ * @q_blsz: block size
8211+ * @q_sgad: SG Addr
8212+ * @sg_cnt: count of (src_cnt + dst_cnt)
8213+ */
8214+#define QUEUE_MODE
8215+static void rdma_queue_sg(rdma_chan_t *rdma, sg_t *sg, u32 q_para, u32 q_blsz, u32 q_sgad, int sg_cnt)
8216+{
8217+ cmdq_t *this_virt = NULL;
8218+
8219+ spin_lock_irq(&process_lock);
8220+
8221+ sg->status = SG_STATUS_SCHEDULED;
8222+ list_add_tail(&sg->lru, &rdma->process_q);
8223+
8224+ dump_regs(rdma);
8225+
8226+#ifdef QUEUE_MODE
8227+ /* Setup BP */
8228+ this_virt = (cmdq_t *)(phys_to_virt(*(rdma->cregs->back)));
8229+ this_virt->parameter = q_para;
8230+ this_virt->block_size = q_blsz;
8231+ this_virt->sg_addr = q_sgad;
8232+ this_virt->reserved = 0;
8233+ dump_regs(rdma);
8234+
8235+ /* FP++ */
8236+ *(rdma->cregs->frnt) = *(rdma->cregs->frnt) + 16;
8237+ dump_regs(rdma);
8238+
8239+ /* FIXME */
8240+ {
8241+ void *sgp = (void *)sg;
8242+ void *cqp = (void *)this_virt;
8243+
8244+ rdma_dmac_flush_range(sgp, (sg_cnt * sizeof(u64)));
8245+ rdma_dmac_flush_range(cqp, sizeof(cmdq_t));
8246+ }
8247+
8248+ /* Queue Enable */
8249+ *(rdma->cregs->stat) = REG_STAT_CMD_QUEUE_ENABLE;
8250+ dump_regs(rdma);
8251+
8252+#else
8253+ *(dma->cregs->blsz) = q_blsz;
8254+ *(rdma->cregs->sgad) = q_sgad;
8255+ *(rdma->cregs->para) = q_para;
8256+ dump_regs(rdma);
8257+#endif /* QUEUE_MODE */
8258+
8259+ spin_unlock_irq(&process_lock);
8260+ dump_regs(rdma);
8261+
8262+ wait_event_timeout(sg->wait,
8263+ sg->status & (SG_STATUS_DONE | SG_STATUS_ERROR),
8264+ dma_timeout_jiffies);
8265+ dump_regs(rdma);
8266+
8267+ /* timed out */
8268+ if (unlikely(sg->status & SG_STATUS_SCHEDULED)) {
8269+ printk("%s: operation timeout\n", __FUNCTION__);
8270+ rdma_timeout_handle(rdma);
8271+ }
8272+
8273+ sg->status = SG_STATUS_FREE;
8274+ mempool_free(sg, rdma_sg_pool);
8275+ return;
8276+}
8277+
8278+
8279+#define R6_RECOV_PD 1
8280+#define R6_RECOV_DD 2
8281+#define R6_RECOV_DQ 3
8282+/**
8283+ * @src_no: source count
8284+ * @bytes: len in bytes
8285+ * @bh_ptr: srcs PA
8286+ * @w1_dst: pd: P, dd: DD1, qd: DD
8287+ * @w2_dst: pd: DD, dd: DD2, qd: Q
8288+ * @pd_dd_qd: failed layout to recover
8289+ * @w1_idx: idx of w1_dst
8290+ * @w2_idx: idx of w2_dst
8291+ * @src_idx: source index; utilize data index only.
8292+ *
8293+ * Desc:
8294+ * Recover P+DD / DD1+DD2 / DD+Q from bh_ptr
8295+ */
8296+void do_cns_rdma_gfgen_pd_dd_dq(unsigned int src_no, unsigned int bytes,
8297+ void **bh_ptr, void *w1_dst, void *w2_dst,
8298+ int pd_dd_qd, unsigned int w1_idx, unsigned int w2_idx,
8299+ unsigned int *src_idx)
8300+{
8301+ int i;
8302+ sg_t *sg = NULL;
8303+ u32 q_sgad, q_blsz, q_para;
8304+
8305+ /* clean src/dst */
8306+ for (i=0; i<src_no; i++)
8307+ {
8308+ if (likely(bh_ptr[i])) {
8309+ rdma_dmac_clean_range(bh_ptr[i], bytes);
8310+ }
8311+ else
8312+ goto abort;
8313+ }
8314+ rdma_dmac_clean_range(w1_dst, bytes);
8315+ rdma_dmac_clean_range(w2_dst, bytes);
8316+
8317+ sg = rdma_get_sg(dma);
8318+
8319+ /* Setup SG */
8320+ switch(pd_dd_qd)
8321+ {
8322+
8323+ case R6_RECOV_PD:
8324+ /* dd...dQ -> PD */
8325+ for (i=0; i<(src_no - 1); i++) {
8326+ sg->entry[i] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i])))
8327+ | (SG_READ_IDX_MASK & ((u64)src_idx[i]) << SG_IDX_SHIFT)
8328+ | (RWI_RD_D);
8329+ }
8330+ sg->entry[src_no-1] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i])))
8331+ | (RWI_RD_Q);
8332+
8333+ /* pd */
8334+ sg->entry[src_no] = (SG_ADDR_MASK & ((u64)virt_to_phys(w1_dst))) | (RWI_W_P1);
8335+ sg->entry[src_no+1] = (SG_ADDR_MASK & ((u64)virt_to_phys(w2_dst))) | (RWI_W_D2);
8336+
8337+ q_para = REG_PARA_ENABLE
8338+ | REG_PARA_XFER_END
8339+ | REG_PARA_CALC_P
8340+ | (REG_PARA_FAULTY_DISKS_CNT * 2)
8341+ | w2_idx * REG_PARA_FDISK_2_Q_IDX;
8342+ break;
8343+
8344+ case R6_RECOV_DD:
8345+ /* dd...PQ -> DD */
8346+ for (i=0; i<(src_no - 2); i++) {
8347+ sg->entry[i] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i])))
8348+ | (SG_READ_IDX_MASK & ((u64)src_idx[i]) << SG_IDX_SHIFT)
8349+ | (RWI_RD_D);
8350+ }
8351+
8352+ sg->entry[src_no-2] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i])))
8353+ | (RWI_RD_P);
8354+ sg->entry[src_no-1] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i+1])))
8355+ | (RWI_RD_Q);
8356+
8357+ /* dd */
8358+ sg->entry[src_no] = (SG_ADDR_MASK & ((u64)virt_to_phys(w1_dst))) | (RWI_W_D1);
8359+ sg->entry[src_no+1] = (SG_ADDR_MASK & ((u64)virt_to_phys(w2_dst))) | (RWI_W_D2);
8360+
8361+ q_para = REG_PARA_ENABLE
8362+ | REG_PARA_XFER_END
8363+ | REG_PARA_CALC_DATA
8364+ | (REG_PARA_FAULTY_DISKS_CNT * 2)
8365+ | w1_idx * REG_PARA_FDISK_1_P_IDX
8366+ | w2_idx * REG_PARA_FDISK_2_Q_IDX;
8367+
8368+ break;
8369+
8370+ case R6_RECOV_DQ:
8371+ /* dd...dP -> DQ */
8372+ for (i=0; i<(src_no - 1); i++) {
8373+ sg->entry[i] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i])))
8374+ | (SG_READ_IDX_MASK & ((u64)src_idx[i]) << SG_IDX_SHIFT)
8375+ | (RWI_RD_D);
8376+ }
8377+ sg->entry[src_no-1] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i])))
8378+ | (RWI_RD_P);
8379+
8380+ /* qd */
8381+ sg->entry[src_no] = (SG_ADDR_MASK & ((u64)virt_to_phys(w1_dst))) | (RWI_W_D1);
8382+ sg->entry[src_no+1] = (SG_ADDR_MASK & ((u64)virt_to_phys(w2_dst))) | (RWI_W_Q2);
8383+
8384+ q_para = REG_PARA_ENABLE
8385+ | REG_PARA_XFER_END
8386+ | REG_PARA_CALC_Q
8387+ | (REG_PARA_FAULTY_DISKS_CNT * 2)
8388+ | w1_idx * REG_PARA_FDISK_1_P_IDX;
8389+ break;
8390+
8391+ default:
8392+ BUG();
8393+ break;
8394+
8395+ }
8396+
8397+ q_sgad = virt_to_phys(&(sg->entry[0]));
8398+ q_blsz = bytes & REG_BLSZ_MASK;
8399+
8400+ if (unlikely(rdma_verbose)) {
8401+ for (i=0; i<src_no; i++)
8402+ printk("set-SG::SRC[%d] = 0x%016llx\n", i, sg->entry[i]);
8403+ printk("set-SG::DST1ptr= 0x%016llx\n", sg->entry[src_no]);
8404+ printk("set-SG::DST2ptr= 0x%016llx\n", sg->entry[src_no+1]);
8405+ }
8406+
8407+ /* Queue SG */
8408+ rdma_queue_sg(dma, sg, q_para, q_blsz, q_sgad, (src_no + 2));
8409+
8410+ /* Invalidate dst */
8411+ rdma_dmac_inv_range(w1_dst, bytes);
8412+ rdma_dmac_inv_range(w2_dst, bytes);
8413+
8414+abort:
8415+ return;
8416+}
8417+
8418+/**
8419+ * @src_no: source count
8420+ * @bytes: len in bytes
8421+ * @bh_ptr: srcs PA
8422+ * @p_dst: P dest PA
8423+ * @q_dst: Q dest PA
8424+ *
8425+ * Desc:
8426+ * p/q_dst = XOR/GFMUL(bh_ptr[0 ... src_no-1]), in Page Addr
8427+ */
8428+void do_cns_rdma_gfgen(unsigned int src_no, unsigned int bytes, void **bh_ptr,
8429+ void *p_dst, void *q_dst) // u8 *gfmr
8430+{
8431+ int i;
8432+ sg_t *sg = NULL;
8433+ u32 q_sgad, q_blsz, q_para;
8434+
8435+ /* clean src/dst */
8436+ for (i=0; i<src_no; i++)
8437+ {
8438+ if (likely(bh_ptr[i])) {
8439+ rdma_dmac_clean_range(bh_ptr[i], bytes);
8440+ }
8441+ else
8442+ goto abort;
8443+ }
8444+ rdma_dmac_clean_range(p_dst, bytes);
8445+ rdma_dmac_clean_range(q_dst, bytes);
8446+
8447+ sg = rdma_get_sg(dma);
8448+
8449+ /* Setup SG::Read::SRC */
8450+ for (i=0; i<src_no; i++) {
8451+ /* Set addr, idx#, rw */
8452+ sg->entry[i] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i])))
8453+ | (SG_READ_IDX_MASK & ((u64)i + 1) << SG_IDX_SHIFT)
8454+ | (RWI_RD_D);
8455+ }
8456+
8457+ /* Setup SG::Write::P1 + Q2 */
8458+ sg->entry[src_no] = (SG_ADDR_MASK & ((u64)virt_to_phys(p_dst))) | (RWI_W_P1);
8459+ sg->entry[src_no+1] = (SG_ADDR_MASK & ((u64)virt_to_phys(q_dst))) | (RWI_W_Q2);
8460+
8461+ /* Setup SGAD, BLSZ, PARAMETER */
8462+ q_sgad = virt_to_phys(&(sg->entry[0]));
8463+ q_blsz = bytes & REG_BLSZ_MASK;
8464+ q_para = REG_PARA_ENABLE
8465+ | REG_PARA_XFER_END
8466+ | REG_PARA_CALC_PQ
8467+ | (REG_PARA_FAULTY_DISKS_CNT * 2);
8468+
8469+ if (unlikely(rdma_verbose)) {
8470+ for (i=0; i<src_no; i++)
8471+ printk("set-SG::SRC[%d] = 0x%016llx\n", i, sg->entry[i]);
8472+ printk("set-SG::DST1ptr= 0x%016llx\n", sg->entry[src_no]);
8473+ printk("set-SG::DST2ptr= 0x%016llx\n", sg->entry[src_no+1]);
8474+ }
8475+
8476+ /* Queue SG */
8477+ rdma_queue_sg(dma, sg, q_para, q_blsz, q_sgad, (src_no + 2));
8478+
8479+ /* Invalidate dst */
8480+ rdma_dmac_inv_range(p_dst, bytes);
8481+ rdma_dmac_inv_range(q_dst, bytes);
8482+
8483+abort:
8484+ return;
8485+}
8486+
8487+/**
8488+ * @src_no: source count
8489+ * @bytes: len in bytes
8490+ * @bh_ptr: srcs PA
8491+ * @dst_ptr: dest PA
8492+ *
8493+ * Desc:
8494+ * dst_ptr = XOR(bh_ptr[0 ... src_no-1]), in Page Addr
8495+ */
8496+void do_cns_rdma_xorgen(unsigned int src_no, unsigned int bytes, void **bh_ptr, void *dst_ptr)
8497+{
8498+ int i;
8499+ sg_t *sg = NULL;
8500+ u32 q_sgad, q_blsz, q_para;
8501+
8502+ /* clean src/dst */
8503+ for (i=0; i<src_no; i++)
8504+ {
8505+ if (likely(bh_ptr[i])) {
8506+ rdma_dmac_clean_range(bh_ptr[i], bytes);
8507+ }
8508+ else
8509+ goto abort;
8510+ }
8511+ rdma_dmac_clean_range(dst_ptr, bytes);
8512+
8513+ sg = rdma_get_sg(dma);
8514+
8515+ /* Setup SG::Read::SRC */
8516+ for (i=0; i<src_no; i++) {
8517+ sg->entry[i] = (SG_ADDR_MASK & ((u64)virt_to_phys(bh_ptr[i])))
8518+ | (SG_READ_IDX_MASK & ((u64)i + 1) << SG_IDX_SHIFT)
8519+ | (RWI_RD_D);
8520+ }
8521+
8522+ /* Setup SG::Write::P1 */
8523+ sg->entry[src_no] = (SG_ADDR_MASK & ((u64)virt_to_phys(dst_ptr)))
8524+ | (RWI_W_P1);
8525+
8526+ /* Setup SGAD, BLSZ, PARAMETER */
8527+ q_sgad = virt_to_phys(&(sg->entry[0]));
8528+ q_blsz = bytes & REG_BLSZ_MASK;
8529+ q_para = REG_PARA_ENABLE
8530+ | REG_PARA_XFER_END
8531+ | REG_PARA_CALC_P
8532+ | (REG_PARA_FAULTY_DISKS_CNT * 1);
8533+
8534+ if (unlikely(rdma_verbose)) {
8535+ for (i=0; i<src_no; i++)
8536+ printk("set-SG::SRC[%d] = 0x%016llx\n", i, sg->entry[i]);
8537+ printk("set-SG::DST1ptr= 0x%016llx\n", sg->entry[src_no]);
8538+ }
8539+
8540+ /* Queue SG */
8541+ rdma_queue_sg(dma, sg, q_para, q_blsz, q_sgad, (src_no + 1));
8542+
8543+ /* Invalidate dst */
8544+ rdma_dmac_inv_range(dst_ptr, bytes);
8545+
8546+abort:
8547+ return;
8548+}
8549+
8550+
8551+/**
8552+ * rdma_isr - rdma isr
8553+ * @irq: irq#
8554+ * @dev_id: private data
8555+ */
8556+static irqreturn_t rdma_isr(int irq, void *dev_id)
8557+{
8558+ unsigned long flags;
8559+ rdma_chan_t *this_dma = (rdma_chan_t *)dev_id;
8560+
8561+ /* Make sure the INT is for us */
8562+ if (unlikely(dma != this_dma))
8563+ {
8564+ printk(KERN_ERR "Unexpected Interrupt, irq=%d, dma=%p, dev_id=%p\n", irq, dma, dev_id);
8565+ return IRQ_NONE;
8566+ }
8567+
8568+ dprintk("%s: pstat=0x%08x\n", __FUNCTION__, *(this_dma->cregs->stat));
8569+
8570+ spin_lock_irqsave(&process_lock, flags);
8571+
8572+ /* clear */
8573+ *(this_dma->cregs->stat) = REG_STAT_XFER_COMPLETE | REG_STAT_INTERRUPT_FLAG;
8574+
8575+ if (!list_empty(&this_dma->process_q)) {
8576+ sg_t *sg_fin = list_entry(this_dma->process_q.next, sg_t, lru);
8577+
8578+ BUG_ON(!(sg_fin->status & SG_STATUS_SCHEDULED));
8579+
8580+ list_del_init(&sg_fin->lru);
8581+ sg_fin->status = SG_STATUS_DONE; // TODO: slave/decoder error handling
8582+
8583+ /* FP rewind */
8584+ if (*(dma->cregs->frnt) == this_dma->q_last_phys) {
8585+ *(dma->cregs->back) = this_dma->q_first_phys;
8586+ *(dma->cregs->frnt) = this_dma->q_first_phys;
8587+ }
8588+
8589+ wake_up(&sg_fin->wait);
8590+ }
8591+ spin_unlock_irqrestore(&process_lock, flags);
8592+
8593+ return IRQ_HANDLED;
8594+}
8595+
8596+/**
8597+ * test_show - show unit test result
8598+ */
8599+static void test_show(void **src, unsigned int bytes, void *p, void *q, unsigned int src_cnt, int stage)
8600+{
8601+ int i;
8602+ char *buf;
8603+
8604+ for (i=0; i<src_cnt; i++) {
8605+ buf = (char *)src[i];
8606+ printk("SRC[%d]-stage=%d: %02x %02x %02x %02x %02x %02x %02x %02x %02x, phys=%lx\n",
8607+ i, stage,
8608+ buf[0], buf[1], buf[16], buf[64],
8609+ buf[bytes/16], buf[bytes/8], buf[bytes/4], buf[bytes/2], buf[bytes-1],
8610+ virt_to_phys(src[i]));
8611+ }
8612+
8613+ buf = (char *)p;
8614+ printk("P-stage=%d: %02x %02x %02x %02x %02x %02x %02x %02x %02x, phys=%lx\n", stage,
8615+ buf[0], buf[1], buf[16], buf[64],
8616+ buf[bytes/16], buf[bytes/8], buf[bytes/4], buf[bytes/2], buf[bytes-1],
8617+ virt_to_phys(p));
8618+
8619+ buf = (char *)q;
8620+ printk("Q-stage=%d: %02x %02x %02x %02x %02x %02x %02x %02x %02x, phys=%lx\n", stage,
8621+ buf[0], buf[1], buf[16], buf[64],
8622+ buf[bytes/16], buf[bytes/8], buf[bytes/4], buf[bytes/2], buf[bytes-1],
8623+ virt_to_phys(q));
8624+}
8625+
8626+/**
8627+ * rdma_unit_test - unit tset invoked by sysfs
8628+ * @action: test item
8629+ * @src_cnt: how many srcs
8630+ * @bytes: length
8631+ *
8632+ * Desc:
8633+ * Unit Test
8634+ */
8635+void rdma_unit_test(int action, unsigned int src_cnt, unsigned int bytes)
8636+{
8637+ int i, cnt;
8638+ void *src_ptrs[MAX_ENTRIES_PER_SG];
8639+ void *p_dst, *q_dst;
8640+ unsigned int w1_idx, w2_idx;
8641+ unsigned int read_idx[32] = {0};
8642+
8643+ /*
8644+ * The lx330 demo board has only 256MB installed,
8645+ * we'd be careful.
8646+ */
8647+ if (src_cnt >= (MAX_ENTRIES_PER_SG - 2))
8648+ src_cnt = MAX_ENTRIES_PER_SG - 2;
8649+
8650+ if (src_cnt < 2)
8651+ src_cnt = 2;
8652+
8653+ if (bytes > 65536)
8654+ bytes = 65536;
8655+
8656+ if (bytes < 4096)
8657+ bytes = 4096;
8658+
8659+ for (i = 0; i < MAX_ENTRIES_PER_SG; i++) {
8660+ if (i < src_cnt) {
8661+ src_ptrs[i] = kmalloc(bytes, GFP_KERNEL);
8662+ } else {
8663+ src_ptrs[i] = NULL;
8664+ }
8665+ }
8666+ p_dst = kmalloc(bytes, GFP_KERNEL);
8667+ q_dst = kmalloc(bytes, GFP_KERNEL);
8668+
8669+ printk("%s: ACTION=%d, src_cnt=%u, bytes=%u p/w1=0x%p, q/w2=0x%p\n",
8670+ __FUNCTION__, action, src_cnt, bytes, p_dst, q_dst);
8671+
8672+ /* Shuffle the src and dst */
8673+ for (i = 0; i < src_cnt; i++) {
8674+ if (rdma_test_ptn[0] == 0) {
8675+ memset(src_ptrs[i], (jiffies % 240)+1, bytes);
8676+ msleep(10 + 10 * i);
8677+ } else {
8678+ memset(src_ptrs[i], rdma_test_ptn[i], bytes);
8679+ }
8680+ }
8681+ memset(p_dst, 0xff, bytes);
8682+ memset(q_dst, 0xff, bytes);
8683+
8684+ // flush_cache_all();
8685+ test_show(src_ptrs, bytes, p_dst, q_dst, src_cnt, 1);
8686+
8687+ switch (action)
8688+ {
8689+ /* P */
8690+ case 1:
8691+ printk("\n%s: XORgen\n\n", __FUNCTION__);
8692+ do_cns_rdma_xorgen(src_cnt, bytes, src_ptrs, p_dst);
8693+ break;
8694+
8695+ /* PQ */
8696+ case 2:
8697+ printk("\n%s: PQgen\n\n", __FUNCTION__);
8698+ do_cns_rdma_gfgen(src_cnt, bytes, src_ptrs, p_dst, q_dst);
8699+ break;
8700+
8701+ /* PD */
8702+ case 3:
8703+ w1_idx = src_cnt + 1;
8704+ w2_idx = 1;
8705+ cnt = 0;
8706+
8707+ printk("read_idx: ");
8708+ for (i=1; i<=(src_cnt+2); i++)
8709+ if (i != w1_idx && i != w2_idx) {
8710+ read_idx[cnt] = i;
8711+ printk("%d ", i);
8712+ cnt++;
8713+ }
8714+ printk("\n%s: PDgen w1/w2_idx=%u/%u\n\n", __FUNCTION__, w1_idx, w2_idx);
8715+ do_cns_rdma_gfgen_pd_dd_dq(src_cnt, bytes, src_ptrs, p_dst, q_dst,
8716+ R6_RECOV_PD, w1_idx, w2_idx, read_idx);
8717+ break;
8718+
8719+ /* DD */
8720+ case 4:
8721+ w1_idx = 1;
8722+ w2_idx = 2;
8723+ cnt = 0;
8724+
8725+ printk("read_idx: ");
8726+ for (i=1; i<=(src_cnt+2); i++)
8727+ if (i != w1_idx && i != w2_idx) {
8728+ read_idx[cnt] = i;
8729+ printk("%d ", i);
8730+ cnt++;
8731+ }
8732+ printk("\n%s: DDgen w1/w2_idx=%u/%u\n\n", __FUNCTION__, w1_idx, w2_idx);
8733+ do_cns_rdma_gfgen_pd_dd_dq(src_cnt, bytes, src_ptrs, p_dst, q_dst,
8734+ R6_RECOV_DD, w1_idx, w2_idx, read_idx);
8735+ break;
8736+
8737+ /* DQ */
8738+ case 5:
8739+ w1_idx = 1;
8740+ w2_idx = src_cnt + 2;
8741+ cnt = 0;
8742+
8743+ printk("read_idx: ");
8744+ for (i=1; i<=(src_cnt+2); i++)
8745+ if (i != w1_idx && i != w2_idx) {
8746+ read_idx[cnt] = i;
8747+ printk("%d ", i);
8748+ cnt++;
8749+ }
8750+ printk("\n%s: DQgen w1/w2_idx=%u/%u\n\n", __FUNCTION__, w1_idx, w2_idx);
8751+ do_cns_rdma_gfgen_pd_dd_dq(src_cnt, bytes, src_ptrs, p_dst, q_dst,
8752+ R6_RECOV_DQ, w1_idx, w2_idx, read_idx);
8753+ break;
8754+
8755+ /* Verbose */
8756+ case 9999:
8757+ rdma_verbose = (rdma_verbose == 1 ? 0 : 1);
8758+ printk("\n%s: Setup verbose mode => %d\n\n", __FUNCTION__, rdma_verbose);
8759+ break;
8760+
8761+ /*
8762+ * SRC Pattern Assign
8763+ * e.g. 0x00000000 <-- do not assign
8764+ * e.g. 0xbbccddee <-- 4 src: bb cc dd ee
8765+ */
8766+ default:
8767+ rdma_test_ptn[0] = (u8)(action >> 24 & 0x000000FF);
8768+ rdma_test_ptn[1] = (u8)(action >> 16 & 0x000000FF);
8769+ rdma_test_ptn[2] = (u8)(action >> 8 & 0x000000FF);
8770+ rdma_test_ptn[3] = (u8)(action & 0x000000FF);
8771+
8772+ printk("\n%s: Setup src test pattern => 0x%02x %02x %02x %02x\n\n", __FUNCTION__,
8773+ rdma_test_ptn[0],
8774+ rdma_test_ptn[1],
8775+ rdma_test_ptn[2],
8776+ rdma_test_ptn[3]);
8777+ break;
8778+ }
8779+
8780+ // flush_cache_all();
8781+ test_show(src_ptrs, bytes, p_dst, q_dst, src_cnt, 2);
8782+
8783+ for (i = 0; i < MAX_ENTRIES_PER_SG; i++) {
8784+ rdma_kfree_obj(src_ptrs[i]);
8785+ }
8786+ rdma_kfree_obj(p_dst);
8787+ rdma_kfree_obj(q_dst);
8788+
8789+}
8790+
8791+void cns_rdma_hw_init(void){
8792+
8793+ cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_RAID);
8794+ cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_RAID);
8795+}
8796+
8797+/**
8798+ * cns_rdma_init - module init
8799+ */
8800+int __init cns_rdma_init(void)
8801+{
8802+ int err = 0;
8803+
8804+ printk("%s: start\n", __FUNCTION__);
8805+
8806+ cns_rdma_hw_init();
8807+
8808+ rdma_test_ptn[0] = 0;
8809+ rdma_verbose = 0;
8810+ dma_timeout_jiffies = HZ;
8811+
8812+ /* DMA chan */
8813+ dma = (rdma_chan_t *) kzalloc(sizeof(rdma_chan_t), GFP_KERNEL);
8814+ if (dma == NULL)
8815+ goto abort;
8816+
8817+ INIT_LIST_HEAD(&(dma->process_q));
8818+
8819+ //static DEFINE_SPINLOCK(dma->process_lock);
8820+ dma->irq = IRQ_CNS3XXX_RAID;
8821+ dma->irq_str = "CNS3XXX RAID acceleration";
8822+ dma->cregs = NULL;
8823+ dma->q_virt = NULL;
8824+
8825+ /* control register */
8826+ dma->cregs = (struct ctrl_regs *) kzalloc(sizeof(struct ctrl_regs) + GENERIC_ALIGN, GFP_KERNEL);
8827+ dma->cregs = (struct ctrl_regs *) (((u32) dma->cregs & GENERIC_ALIGN_MASK) + GENERIC_ALIGN);
8828+
8829+ if (dma->cregs == NULL)
8830+ goto abort;
8831+
8832+ printk("%s: reg1: virt=0x%p\n",
8833+ __FUNCTION__, (void *)dma->cregs);
8834+
8835+ dma->cregs->para = RDMA_REGS_VIRT(REG_PARA_OFFSET);
8836+ dma->cregs->blsz = RDMA_REGS_VIRT(REG_BLSZ_OFFSET);
8837+ dma->cregs->sgad = RDMA_REGS_VIRT(REG_SGAD_OFFSET);
8838+ dma->cregs->stat = RDMA_REGS_VIRT(REG_STAT_OFFSET);
8839+ dma->cregs->frnt = RDMA_REGS_VIRT(REG_FRNT_OFFSET);
8840+ dma->cregs->back = RDMA_REGS_VIRT(REG_BACK_OFFSET);
8841+ dma->cregs->qpar = RDMA_REGS_VIRT(REG_QPAR_OFFSET);
8842+
8843+ /* Pre-allocate S/G table */
8844+ rdma_mempool_create(rdma_sg_pool, "rdma_sg", sizeof(sg_t),
8845+ MAX_SG, rdma_sg_prealloc_fn, rdma_sg_deconstruct_fn, NULL);
8846+
8847+ /* Pre-allocate Queue Cmds */
8848+ dma->q_virt = (cmdq_t *) kzalloc(sizeof(cmdq_t) * CURR_Q_DEPTH + CURR_Q_DEPTH_ALIGN, GFP_KERNEL);
8849+ dma->q_virt = (cmdq_t *) (((u32) dma->q_virt & CURR_Q_DEPTH_ALIGN_MASK) + CURR_Q_DEPTH_ALIGN);
8850+
8851+ if (dma->q_virt == NULL)
8852+ goto abort;
8853+
8854+ dma->q_first_phys = virt_to_phys((void *)dma->q_virt);
8855+ dma->q_last_phys = dma->q_first_phys + sizeof(cmdq_t) * (CURR_Q_DEPTH - 1);
8856+
8857+ printk("%s: q1: virt=0x%p, phy=0x%x -> 0x%x\n",
8858+ __FUNCTION__, (void *)dma->q_virt, dma->q_first_phys, dma->q_last_phys);
8859+
8860+ *(dma->cregs->qpar) = REG_QPAR_DEPTH_32;
8861+ *(dma->cregs->back) = dma->q_first_phys;
8862+ *(dma->cregs->frnt) = dma->q_first_phys;
8863+
8864+ /* Register IRQ */
8865+ err = request_irq(dma->irq, rdma_isr, 0, dma->irq_str, dma);
8866+ if (err) {
8867+ printk("%s: request irq failed\n", __FUNCTION__);
8868+ goto abort;
8869+ }
8870+
8871+ /* Clear 31 & 0 */
8872+ *(dma->cregs->stat) = REG_STAT_INTERRUPT_FLAG;
8873+
8874+ err = 0;
8875+ goto done;
8876+
8877+abort:
8878+ rdma_mempool_destroy(rdma_sg_pool);
8879+ rdma_kfree_obj(dma->cregs);
8880+ rdma_kfree_obj(dma);
8881+
8882+
8883+done:
8884+ printk("%s: done, err=%d\n", __FUNCTION__, err);
8885+ return err;
8886+}
8887+
8888+/**
8889+ * cns_rdma_exit - module exit
8890+ */
8891+void cns_rdma_exit(void)
8892+{
8893+ printk("%s: start\n", __FUNCTION__);
8894+
8895+ rdma_mempool_destroy(rdma_sg_pool);
8896+ rdma_kfree_obj(dma->cregs);
8897+ rdma_kfree_obj(dma);
8898+ printk("%s: done\n", __FUNCTION__);
8899+}
8900+
8901+//module_init(cns_rdma_init);
8902+//module_exit(cns_rdma_exit);
8903--- /dev/null
8904+++ b/arch/arm/mach-cns3xxx/rdma.h
8905@@ -0,0 +1,178 @@
8906+/*
8907+ * rdma.h - CNS3xxx hardware RAID acceleration
8908+ */
8909+#ifndef _CNS3XXX_RDMA_H_
8910+#define _CNS3XXX_RDMA_H_
8911+
8912+#include <mach/hardware.h>
8913+
8914+#define RDMA_REGS_PHYS(x) ((u32)(CNS3XXX_RAID_BASE + (x)))
8915+#define RDMA_REGS_VIRT(x) ((u32 volatile *)(CNS3XXX_RAID_BASE_VIRT + (x)))
8916+#define RDMA_REGS_VALUE(x) (*((u32 volatile *)(CNS3XXX_RAID_BASE_VIRT + (x))))
8917+
8918+
8919+#define GENERIC_ALIGN 0x8 /* 64-bits */
8920+#define GENERIC_ALIGN_MASK 0xFFFFFFF8UL
8921+#define QUEUE_DEPTH_ALIGN_MUL 0x10 /* 16 bytes; ALIGNMENT == QDEPTH * 16 bytes */
8922+
8923+
8924+/* Register Offset */
8925+#define REG_PARA_OFFSET 0x00UL /* Parameter */
8926+#define REG_BLSZ_OFFSET 0x04UL /* Block Size */
8927+#define REG_SGAD_OFFSET 0x08UL /* SG Address */
8928+#define REG_STAT_OFFSET 0x0CUL /* Status */
8929+#define REG_FRNT_OFFSET 0x10UL /* FP */
8930+#define REG_BACK_OFFSET 0x14UL /* BP */
8931+#define REG_QPAR_OFFSET 0x18UL /* Queue Parameter */
8932+
8933+
8934+/* 0x00: PARA */
8935+#define REG_PARA_ENABLE 0x80000000UL /* 31 */
8936+#define REG_PARA_XFER_END 0x40000000UL /* 30 */
8937+#define REG_PARA_MEMORY_WR_DISABLE 0x20000000UL /* 29 */
8938+#define REG_PARA_FAULTY_DISKS_CNT 0x08000000UL /* 28:27 */
8939+
8940+#define REG_PARA_CALC 0x01000000UL /* 26:24 */
8941+ #define REG_PARA_CALC_DATA 0x00000000UL
8942+ #define REG_PARA_CALC_P 0x01000000UL
8943+ #define REG_PARA_CALC_Q 0x02000000UL
8944+ #define REG_PARA_CALC_R 0x04000000UL
8945+ #define REG_PARA_CALC_PQ 0x03000000UL
8946+ #define REG_PARA_CALC_PR 0x05000000UL
8947+ #define REG_PARA_CALC_QR 0x06000000UL
8948+ #define REG_PARA_CALC_PQR 0x07000000UL
8949+
8950+#define REG_PARA_FDISK_3_R_IDX 0x00010000UL /* 23:16 */
8951+#define REG_PARA_FDISK_2_Q_IDX 0x00000100UL /* 15:8 */
8952+#define REG_PARA_FDISK_1_P_IDX 0x00000001UL /* 7:0 */
8953+
8954+/* 0x04: BLSZ */
8955+#define REG_BLSZ_SHIFT 3 /* 19:3 */
8956+#define REG_BLSZ_MASK 0x000FFFF8UL /* N * 8bytes */
8957+
8958+/* 0x08: SGAD */
8959+#define REG_SGAD_SHIFT 0
8960+
8961+/* 0x0C: STAT */
8962+#define REG_STAT_XFER_COMPLETE 0x80000000UL /* 31 */
8963+#define REG_STAT_SLAVE_ERROR 0x40000000UL /* 30 */
8964+#define REG_STAT_DECODER_ERROR 0x20000000UL /* 29 */
8965+#define REG_STAT_R_FLAG 0x00080000UL /* 19 */
8966+#define REG_STAT_Q_FLAG 0x00040000UL /* 18 */
8967+#define REG_STAT_P_FLAG 0x00020000UL /* 17 */
8968+#define REG_STAT_CMD_QUEUE_ENABLE 0x00000002UL /* 1 */
8969+#define REG_STAT_INTERRUPT_FLAG 0x00000001UL /* 0 */
8970+
8971+/* 0x10/14: FRNT/BACK */
8972+#define REG_FRNT_SHIFT 0
8973+#define REG_BACK_SHIFT 0
8974+
8975+/* 0x18: QPAR */
8976+#define MAX_Q_DEPTH 256
8977+#define REG_QPAR_DEPTH_256 0xFF
8978+#define REG_QPAR_DEPTH_128 0x7F
8979+#define REG_QPAR_DEPTH_64 0x3F
8980+#define REG_QPAR_DEPTH_32 0x1F
8981+#define REG_QPAR_DEPTH_16 0xF
8982+#define REG_QPAR_DEPTH_8 0x7
8983+#define REG_QPAR_DEPTH_4 0x3
8984+#define REG_QPAR_DEPTH_2 0x1
8985+
8986+/* len = 32 */
8987+#define CURR_Q_DEPTH (REG_QPAR_DEPTH_32 + 1)
8988+#define CURR_Q_DEPTH_ALIGN ((CURR_Q_DEPTH) * (QUEUE_DEPTH_ALIGN_MUL)) /* 0x200 */
8989+#define CURR_Q_DEPTH_ALIGN_MASK 0xFFFFFE00UL
8990+
8991+
8992+#define MAX_SG 32 // cf. CURR_Q_DEPTH or MAX_Q_DEPTH
8993+#define MAX_ENTRIES_PER_SG 32
8994+
8995+/* SG Table */
8996+#define SG_ADDR_MASK 0x00000000FFFFFFFFULL
8997+
8998+#define SG_READ_IDX_MASK 0x000000FF00000000ULL
8999+#define SG_IDX_SHIFT 32
9000+
9001+// ---------------------- 7654321076543210
9002+#define SG_RW_MASK 0x00000F0000000000ULL
9003+#define RWI_RD_D 0x0000000000000000ULL
9004+#define RWI_RD_P 0x0000010000000000ULL
9005+#define RWI_RD_Q 0x0000020000000000ULL
9006+#define RWI_RD_R 0x0000030000000000ULL
9007+#define RWI_W_D1 0x0000040000000000ULL
9008+#define RWI_W_P1 0x0000050000000000ULL
9009+#define RWI_W_Q1 0x0000060000000000ULL
9010+#define RWI_W_R1 0x0000070000000000ULL
9011+#define RWI_W_D2 0x0000080000000000ULL
9012+#define RWI_W_P2 0x0000090000000000ULL
9013+#define RWI_W_Q2 0x00000A0000000000ULL
9014+#define RWI_W_R2 0x00000B0000000000ULL
9015+#define RWI_W_D3 0x00000C0000000000ULL
9016+#define RWI_W_P3 0x00000D0000000000ULL
9017+#define RWI_W_Q3 0x00000E0000000000ULL
9018+#define RWI_W_R3 0x00000F0000000000ULL
9019+
9020+
9021+#define SG_STATUS_FREE 0x00000001UL
9022+#define SG_STATUS_ACQUIRED 0x00000002UL
9023+#define SG_STATUS_SCHEDULED 0x00000004UL
9024+#define SG_STATUS_DONE 0x00000008UL
9025+#define SG_STATUS_ERROR 0x00000010UL
9026+
9027+#define SG_ENTRY_BYTES (8 * MAX_ENTRIES_PER_SG)
9028+
9029+typedef struct rdma_sgtable sg_t;
9030+struct rdma_sgtable {
9031+ u64 entry[MAX_ENTRIES_PER_SG];
9032+
9033+ struct list_head lru; /* list_add_tail/list_del to/from process_q when schedule or isr */
9034+ wait_queue_head_t wait;
9035+
9036+ u32 status;
9037+};
9038+
9039+/* Command Queue: cmdq_t */
9040+typedef struct rdma_cmdq cmdq_t;
9041+struct rdma_cmdq {
9042+ volatile u32 parameter;
9043+ volatile u32 block_size;
9044+ volatile u32 sg_addr;
9045+ volatile u32 reserved;
9046+};
9047+
9048+struct ctrl_regs {
9049+ volatile u32 *para;
9050+ volatile u32 *blsz;
9051+ volatile u32 *sgad;
9052+ volatile u32 *stat;
9053+ volatile u32 *frnt;
9054+ volatile u32 *back;
9055+ volatile u32 *qpar;
9056+};
9057+
9058+/* channel */
9059+#define RDMA_CHANNEL_COUNT 1
9060+typedef struct rdma_channel rdma_chan_t;
9061+struct rdma_channel
9062+{
9063+ struct list_head process_q;
9064+ spinlock_t process_lock; /* process queue lock */
9065+
9066+ int irq;
9067+ const char *irq_str;
9068+
9069+ /* cmd queue start address */
9070+ volatile cmdq_t *q_virt;
9071+ volatile u32 q_first_phys;
9072+ volatile u32 q_last_phys;
9073+
9074+ /* control regs */
9075+ struct ctrl_regs *cregs;
9076+
9077+ // wait_queue_head_t wait;
9078+};
9079+
9080+int __init cns_rdma_init(void);
9081+
9082+#endif
9083+
9084--- a/arch/arm/Makefile
9085+++ b/arch/arm/Makefile
9086@@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_ORION5X) := orion
9087 machine-$(CONFIG_ARCH_PNX4008) := pnx4008
9088 machine-$(CONFIG_ARCH_PXA) := pxa
9089 machine-$(CONFIG_ARCH_REALVIEW) := realview
9090+machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
9091 machine-$(CONFIG_ARCH_RPC) := rpc
9092 machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
9093 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
9094--- /dev/null
9095+++ b/arch/arm/mm/cache-l2cc.c
9096@@ -0,0 +1,218 @@
9097+/*******************************************************************************
9098+ *
9099+ * arch/arm/mm/cache-l2cc.c - L2 cache controller support
9100+ *
9101+ * Copyright (c) 2008 Cavium Networks
9102+ *
9103+ * This file is free software; you can redistribute it and/or modify
9104+ * it under the terms of the GNU General Public License, Version 2, as
9105+ * published by the Free Software Foundation.
9106+ *
9107+ * This file is distributed in the hope that it will be useful,
9108+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
9109+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
9110+ * NONINFRINGEMENT. See the GNU General Public License for more details.
9111+ *
9112+ * You should have received a copy of the GNU General Public License
9113+ * along with this file; if not, write to the Free Software
9114+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
9115+ * visit http://www.gnu.org/licenses/.
9116+ *
9117+ * This file may also be available under a different license from Cavium.
9118+ * Contact Cavium Networks for more information
9119+ *
9120+ ******************************************************************************/
9121+
9122+#include <linux/init.h>
9123+#include <linux/spinlock.h>
9124+
9125+#include <asm/cacheflush.h>
9126+#include <asm/io.h>
9127+#include <asm/hardware/cache-l2cc.h>
9128+
9129+#define CACHE_LINE_SIZE 32
9130+
9131+static void __iomem *cns3xxx_l2_base;
9132+static DEFINE_SPINLOCK(cns3xxx_l2_lock);
9133+
9134+static inline void cache_wait(void __iomem *reg, unsigned long mask)
9135+{
9136+#ifndef CONFIG_L2CC_NO_WAIT
9137+ /* wait for the operation to complete */
9138+ while (readl(reg) & mask);
9139+#endif
9140+}
9141+
9142+static inline void sync_writel(unsigned long val, unsigned long reg,
9143+ unsigned long complete_mask)
9144+{
9145+ unsigned long flags;
9146+
9147+ spin_lock_irqsave(&cns3xxx_l2_lock, flags);
9148+ writel(val, cns3xxx_l2_base + reg);
9149+ /* wait for the operation to complete */
9150+ while (readl(cns3xxx_l2_base + reg) & complete_mask)
9151+ ;
9152+ spin_unlock_irqrestore(&cns3xxx_l2_lock, flags);
9153+}
9154+
9155+static inline void cache_sync(void)
9156+{
9157+ sync_writel(0, L2CC_CACHE_SYNC, 1);
9158+}
9159+
9160+static inline void cns3xxx_l2_inv_all(void)
9161+{
9162+ /* invalidate all ways */
9163+ sync_writel(0xffff, L2CC_INV_WAY, 0xffff);
9164+ cache_sync();
9165+}
9166+
9167+static void cns3xxx_l2_inv_range(unsigned long start, unsigned long end)
9168+{
9169+ unsigned long addr;
9170+
9171+ if (start & (CACHE_LINE_SIZE - 1)) {
9172+ start &= ~(CACHE_LINE_SIZE - 1);
9173+ writel(start, cns3xxx_l2_base + L2CC_CLEAN_INV_LINE_PA);
9174+ start += CACHE_LINE_SIZE;
9175+ }
9176+
9177+ if (end & (CACHE_LINE_SIZE - 1)) {
9178+ end &= ~(CACHE_LINE_SIZE - 1);
9179+ writel(end, cns3xxx_l2_base + L2CC_CLEAN_INV_LINE_PA);
9180+ }
9181+
9182+ for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
9183+ writel(addr, cns3xxx_l2_base + L2CC_INV_LINE_PA);
9184+
9185+ cache_sync();
9186+}
9187+
9188+static void cns3xxx_l2_clean_range(unsigned long start, unsigned long end)
9189+{
9190+ unsigned long addr;
9191+
9192+ start &= ~(CACHE_LINE_SIZE - 1);
9193+ for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
9194+ writel(addr, cns3xxx_l2_base + L2CC_CLEAN_LINE_PA);
9195+
9196+ cache_wait(cns3xxx_l2_base + L2CC_CLEAN_LINE_PA, 1);
9197+ cache_sync();
9198+}
9199+
9200+static void cns3xxx_l2_flush_range(unsigned long start, unsigned long end)
9201+{
9202+ unsigned long addr;
9203+
9204+ start &= ~(CACHE_LINE_SIZE - 1);
9205+ for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
9206+ writel(addr, cns3xxx_l2_base + L2CC_CLEAN_INV_LINE_PA);
9207+
9208+ cache_wait(cns3xxx_l2_base + L2CC_CLEAN_INV_LINE_PA, 1);
9209+ cache_sync();
9210+}
9211+
9212+void __init l2cc_init(void __iomem *base)
9213+{
9214+ __u32 aux, prefetch, tag, data;
9215+
9216+ printk(KERN_INFO "Initializing CNS3XXX L2 cache controller... ");
9217+
9218+ cns3xxx_l2_base = base;
9219+
9220+ /* disable L2CC */
9221+ writel(0, cns3xxx_l2_base + L2CC_CTRL);
9222+
9223+ /*
9224+ * Auxiliary control register
9225+ *
9226+ * bit[22] - shared attribute internally ignored
9227+ * bit[21] - parity enabled
9228+ * bit[20] -
9229+ * bit[19:17] - 32kB way size
9230+ * bit[16] - way associative
9231+ * bit[12] - exclusive cache disabled
9232+ *
9233+ */
9234+ aux = readl(cns3xxx_l2_base + L2CC_AUX_CTRL);
9235+ aux &= 0xfe000fff;
9236+#ifdef CONFIG_CACHE_L2_I_PREFETCH
9237+ aux |= 0x20000000; /* bit[29]: Instruction prefetching enable, bit[29]: Data prefetching enable */
9238+#endif
9239+#ifdef CONFIG_CACHE_L2_D_PREFETCH
9240+ aux |= 0x10000000; /* bit[28]: Instruction prefetching enable, bit[28]: Data prefetching enable */
9241+#endif
9242+ aux |= 0x00540000; /* ...010..., 32KB, 8-way, Parity Disable*/
9243+ writel(aux, cns3xxx_l2_base + L2CC_AUX_CTRL);
9244+
9245+ prefetch = readl(cns3xxx_l2_base + 0xF60);
9246+ prefetch |= 0x00000008; /* prefetch offset, bit[4..0] */
9247+#ifdef CONFIG_CACHE_L2_I_PREFETCH
9248+ prefetch |= 0x20000000;
9249+#endif
9250+#ifdef CONFIG_CACHE_L2_D_PREFETCH
9251+ prefetch |= 0x10000000;
9252+#endif
9253+ writel(prefetch, cns3xxx_l2_base + 0xF60);
9254+
9255+ /* Tag RAM Control register
9256+ *
9257+ * bit[10:8] - 1 cycle of write accesses latency
9258+ * bit[6:4] - 1 cycle of read accesses latency
9259+ * bit[3:0] - 1 cycle of setup latency
9260+ *
9261+ * 1 cycle of latency for setup, read and write accesses
9262+ */
9263+ tag = readl(cns3xxx_l2_base + L2CC_TAG_RAM_LATENCY_CTRL);
9264+ tag &= 0xfffff888;
9265+ tag |= 0x00000000;
9266+ writel(tag, cns3xxx_l2_base + L2CC_TAG_RAM_LATENCY_CTRL);
9267+
9268+ /* Data RAM Control register
9269+ *
9270+ * bit[10:8] - 1 cycles of write accesses latency
9271+ * bit[6:4] - 1 cycles of read accesses latency
9272+ * bit[3:0] - 1 cycle of setup latency
9273+ *
9274+ * 1 cycle of setup latency, 2 cycles of read and write accesses latency
9275+ */
9276+ data = readl(cns3xxx_l2_base + L2CC_DATA_RAM_LATENCY_CTRL);
9277+ data &= 0xfffff888;
9278+ data |= 0x00000000;
9279+ writel(data, cns3xxx_l2_base + L2CC_DATA_RAM_LATENCY_CTRL);
9280+
9281+ cns3xxx_l2_inv_all();
9282+
9283+ /* lockdown required ways for different effective size of the L2 cache */
9284+#ifdef CONFIG_CACHE_L2CC_32KB
9285+ /* 32KB, lock way7..1 */
9286+ writel(0xfe, cns3xxx_l2_base + L2CC_LOCKDOWN_0_WAY_D);
9287+ writel(0xfe, cns3xxx_l2_base + L2CC_LOCKDOWN_0_WAY_I);
9288+ printk(KERN_INFO "CNS3XXX L2 cache lock down : way7..1\n");
9289+#elif defined(CONFIG_CACHE_L2CC_64KB)
9290+ /* 64KB, lock way7..2 */
9291+ writel(0xfc, cns3xxx_l2_base + L2CC_LOCKDOWN_0_WAY_D);
9292+ writel(0xfc, cns3xxx_l2_base + L2CC_LOCKDOWN_0_WAY_I);
9293+ printk(KERN_INFO "CNS3XXX L2 cache lock down : way7..2\n");
9294+#elif defined(CONFIG_CACHE_L2CC_96KB)
9295+ /* 96KB, lock way7..3 */
9296+ writel(0xf8, cns3xxx_l2_base + L2CC_LOCKDOWN_0_WAY_D);
9297+ writel(0xf8, cns3xxx_l2_base + L2CC_LOCKDOWN_0_WAY_I);
9298+ printk(KERN_INFO "CNS3XXX L2 cache lock down : way7..3\n");
9299+#elif defined(CONFIG_CACHE_L2CC_128KB)
9300+ /* 128KB, lock way7..4 */
9301+ writel(0xf0, cns3xxx_l2_base + L2CC_LOCKDOWN_0_WAY_D);
9302+ writel(0xf0, cns3xxx_l2_base + L2CC_LOCKDOWN_0_WAY_I);
9303+ printk(KERN_INFO "CNS3XXX L2 cache lock down : way7..4\n");
9304+#endif
9305+
9306+ /* enable L2CC */
9307+ writel(1, cns3xxx_l2_base + L2CC_CTRL);
9308+
9309+ outer_cache.inv_range = cns3xxx_l2_inv_range;
9310+ outer_cache.clean_range = cns3xxx_l2_clean_range;
9311+ outer_cache.flush_range = cns3xxx_l2_flush_range;
9312+
9313+ printk("done.\n");
9314+}
9315--- a/arch/arm/mm/cache-l2x0.c
9316+++ b/arch/arm/mm/cache-l2x0.c
9317@@ -109,6 +109,25 @@ void __init l2x0_init(void __iomem *base
9318 
9319     l2x0_inv_all();
9320 
9321+ /* lockdown required ways for different effective size of the L2 cache */
9322+#ifdef CONFIG_CACHE_L2X0_128KB
9323+ /* 128KB, lock way7..1 */
9324+ writel(0xfe, l2x0_base + L2X0_LOCKDOWN_WAY_D);
9325+ writel(0xfe, l2x0_base + L2X0_LOCKDOWN_WAY_I);
9326+#elif defined(CONFIG_CACHE_L2X0_256KB)
9327+ /* 256KB, lock way7..2 */
9328+ writel(0xfc, l2x0_base + L2X0_LOCKDOWN_WAY_D);
9329+ writel(0xfc, l2x0_base + L2X0_LOCKDOWN_WAY_I);
9330+#elif defined(CONFIG_CACHE_L2X0_512KB)
9331+ /* 512KB, lock way7..3 */
9332+ writel(0xf8, l2x0_base + L2X0_LOCKDOWN_WAY_D);
9333+ writel(0xf8, l2x0_base + L2X0_LOCKDOWN_WAY_I);
9334+#elif defined(CONFIG_CACHE_L2X0_1MB)
9335+ /* 1MB, lock way7..4 */
9336+ writel(0xf0, l2x0_base + L2X0_LOCKDOWN_WAY_D);
9337+ writel(0xf0, l2x0_base + L2X0_LOCKDOWN_WAY_I);
9338+#endif
9339+
9340     /* enable L2X0 */
9341     writel(1, l2x0_base + L2X0_CTRL);
9342 
9343--- a/arch/arm/mm/dma-mapping.c
9344+++ b/arch/arm/mm/dma-mapping.c
9345@@ -29,7 +29,8 @@
9346 #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
9347 #endif
9348 
9349-#define CONSISTENT_END (0xffe00000)
9350+//#define CONSISTENT_END (0xffe00000)
9351+#define CONSISTENT_END (0xf2000000)
9352 #define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE)
9353 
9354 #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
9355@@ -208,7 +209,7 @@ __dma_alloc(struct device *dev, size_t s
9356     {
9357         void *ptr = page_address(page);
9358         memset(ptr, 0, size);
9359- dmac_flush_range(ptr, ptr + size);
9360+ smp_dma_flush_range(ptr, ptr + size);
9361         outer_flush_range(__pa(ptr), __pa(ptr) + size);
9362     }
9363 
9364@@ -498,15 +499,15 @@ void dma_cache_maint(const void *start,
9365 
9366     switch (direction) {
9367     case DMA_FROM_DEVICE: /* invalidate only */
9368- inner_op = dmac_inv_range;
9369+ inner_op = smp_dma_inv_range;
9370         outer_op = outer_inv_range;
9371         break;
9372     case DMA_TO_DEVICE: /* writeback only */
9373- inner_op = dmac_clean_range;
9374+ inner_op = smp_dma_clean_range;
9375         outer_op = outer_clean_range;
9376         break;
9377     case DMA_BIDIRECTIONAL: /* writeback and invalidate */
9378- inner_op = dmac_flush_range;
9379+ inner_op = smp_dma_flush_range;
9380         outer_op = outer_flush_range;
9381         break;
9382     default:
9383@@ -528,15 +529,15 @@ static void dma_cache_maint_contiguous(s
9384 
9385     switch (direction) {
9386     case DMA_FROM_DEVICE: /* invalidate only */
9387- inner_op = dmac_inv_range;
9388+ inner_op = smp_dma_inv_range;
9389         outer_op = outer_inv_range;
9390         break;
9391     case DMA_TO_DEVICE: /* writeback only */
9392- inner_op = dmac_clean_range;
9393+ inner_op = smp_dma_clean_range;
9394         outer_op = outer_clean_range;
9395         break;
9396     case DMA_BIDIRECTIONAL: /* writeback and invalidate */
9397- inner_op = dmac_flush_range;
9398+ inner_op = smp_dma_flush_range;
9399         outer_op = outer_flush_range;
9400         break;
9401     default:
9402--- a/arch/arm/mm/Kconfig
9403+++ b/arch/arm/mm/Kconfig
9404@@ -391,7 +391,7 @@ config CPU_FEROCEON_OLD_ID
9405 
9406 # ARMv6
9407 config CPU_V6
9408- bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
9409+ bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_CNS3XXX || MACH_REALVIEW_PBX
9410     select CPU_32v6
9411     select CPU_ABRT_EV6
9412     select CPU_PABRT_NOIFAR
9413@@ -516,6 +516,16 @@ config CPU_CACHE_VIPT
9414 config CPU_CACHE_FA
9415     bool
9416 
9417+config CPU_NO_CACHE_BCAST
9418+ bool
9419+ depends on SMP
9420+ default y if CPU_V6
9421+
9422+config CPU_NO_CACHE_BCAST_DEBUG
9423+ bool
9424+ depends on SMP
9425+ default y if CPU_V6
9426+
9427 if MMU
9428 # The copy-page model
9429 config CPU_COPY_V3
9430@@ -759,11 +769,84 @@ config CACHE_L2X0
9431     bool "Enable the L2x0 outer cache controller"
9432     depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
9433            REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX
9434- default y
9435+ default n
9436     select OUTER_CACHE
9437     help
9438       This option enables the L2x0 PrimeCell.
9439 
9440+choice
9441+ prompt "L2 Cache Size"
9442+ depends on CACHE_L2X0
9443+ default CACHE_L2X0_1MB
9444+
9445+config CACHE_L2X0_128KB
9446+ bool "128KB"
9447+ help
9448+ 16KB/way, 8-way, evmon/parity/share enabled
9449+
9450+config CACHE_L2X0_256KB
9451+ bool "256KB"
9452+ help
9453+ 32KB/way, 8-way, evmon/parity/share enabled
9454+
9455+config CACHE_L2X0_512KB
9456+ bool "512KB"
9457+ help
9458+ 64KB/way, 8-way, evmon/parity/share enabled
9459+
9460+config CACHE_L2X0_1MB
9461+ bool "1MB"
9462+ help
9463+ 128KB/way, 8-way, evmon/parity/share enabled
9464+endchoice
9465+
9466+config CACHE_L2CC
9467+ bool "Enable the L2 outer cache controller"
9468+ depends on ARCH_CNS3XXX
9469+ default n
9470+ select OUTER_CACHE
9471+ help
9472+ This option enables the L2 cache controller.
9473+
9474+choice
9475+ prompt "L2 Cache Size"
9476+ depends on CACHE_L2CC
9477+ default CACHE_L2CC_256KB
9478+
9479+config CACHE_L2CC_32KB
9480+ bool "32KB"
9481+ help
9482+ 4KB/way, 8-way, evmon/share enabled
9483+
9484+config CACHE_L2CC_64KB
9485+ bool "64KB"
9486+ help
9487+ 8KB/way, 8-way, evmon/share enabled
9488+
9489+config CACHE_L2CC_96KB
9490+ bool "96KB"
9491+ help
9492+ 12KB/way, 8-way, evmon/share enabled
9493+
9494+config CACHE_L2CC_128KB
9495+ bool "128KB"
9496+ help
9497+ 16KB/way, 8-way, evmon/share enabled
9498+
9499+config CACHE_L2CC_256KB
9500+ bool "256KB"
9501+ help
9502+ 32KB/way, 8-way, evmon/share enabled
9503+
9504+endchoice
9505+
9506+config CACHE_L2_I_PREFETCH
9507+ bool "Enable the L2 instruction prefetching"
9508+ depends on CACHE_L2CC
9509+ default y
9510+ help
9511+ This option enables instruction prefetching.
9512+
9513 config CACHE_XSC3L2
9514     bool "Enable the L2 cache on XScale3"
9515     depends on CPU_XSC3
9516--- a/arch/arm/mm/Makefile
9517+++ b/arch/arm/mm/Makefile
9518@@ -82,5 +82,6 @@ obj-$(CONFIG_CPU_V7) += proc-v7.o
9519 
9520 obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
9521 obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
9522+obj-$(CONFIG_CACHE_L2CC) += cache-l2cc.o
9523 obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
9524 
9525--- a/arch/arm/mm/mmu.c
9526+++ b/arch/arm/mm/mmu.c
9527@@ -687,7 +687,7 @@ __early_param("vmalloc=", early_vmalloc)
9528 
9529 static void __init sanity_check_meminfo(void)
9530 {
9531- int i, j, highmem = 0;
9532+ int i, j;
9533 
9534     for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
9535         struct membank *bank = &meminfo.bank[j];
9536--- a/include/linux/pci_ids.h
9537+++ b/include/linux/pci_ids.h
9538@@ -2668,3 +2668,5 @@
9539 #define PCI_DEVICE_ID_RME_DIGI32 0x9896
9540 #define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897
9541 #define PCI_DEVICE_ID_RME_DIGI32_8 0x9898
9542+
9543+#define PCI_VENDOR_ID_CAVIUM 0x177d
9544--- a/arch/arm/tools/mach-types
9545+++ b/arch/arm/tools/mach-types
9546@@ -12,7 +12,7 @@
9547 #
9548 # http://www.arm.linux.org.uk/developer/machines/?action=new
9549 #
9550-# Last update: Sat Jun 20 22:28:39 2009
9551+# Last update: Wed Jun 9 02:11:30 2010
9552 #
9553 # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
9554 #
9555@@ -928,7 +928,7 @@ palmt5 MACH_PALMT5 PALMT5 917
9556 palmtc MACH_PALMTC PALMTC 918
9557 omap_apollon MACH_OMAP_APOLLON OMAP_APOLLON 919
9558 mxc30030evb MACH_MXC30030EVB MXC30030EVB 920
9559-rea_2d MACH_REA_2D REA_2D 921
9560+rea_cpu2 MACH_REA_2D REA_2D 921
9561 eti3e524 MACH_TI3E524 TI3E524 922
9562 ateb9200 MACH_ATEB9200 ATEB9200 923
9563 auckland MACH_AUCKLAND AUCKLAND 924
9564@@ -1319,7 +1319,7 @@ mistral MACH_MISTRAL MISTRAL 1315
9565 msm MACH_MSM MSM 1316
9566 ct5910 MACH_CT5910 CT5910 1317
9567 ct5912 MACH_CT5912 CT5912 1318
9568-hynet_ine MACH_HYNET_INE HYNET_INE 1319
9569+argonst_foundation MACH_HYNET_INE HYNET_INE 1319
9570 hynet_app MACH_HYNET_APP HYNET_APP 1320
9571 msm7200 MACH_MSM7200 MSM7200 1321
9572 msm7600 MACH_MSM7600 MSM7600 1322
9573@@ -1638,7 +1638,7 @@ mx35evb MACH_MX35EVB MX35EVB 1643
9574 aml_m8050 MACH_AML_M8050 AML_M8050 1644
9575 mx35_3ds MACH_MX35_3DS MX35_3DS 1645
9576 mars MACH_MARS MARS 1646
9577-ntosd_644xa MACH_NTOSD_644XA NTOSD_644XA 1647
9578+neuros_osd2 MACH_NEUROS_OSD2 NEUROS_OSD2 1647
9579 badger MACH_BADGER BADGER 1648
9580 trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649
9581 trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650
9582@@ -1654,7 +1654,7 @@ vf10xx MACH_VF10XX VF10XX 1659
9583 zoran43xx MACH_ZORAN43XX ZORAN43XX 1660
9584 sonix926 MACH_SONIX926 SONIX926 1661
9585 celestialsemi MACH_CELESTIALSEMI CELESTIALSEMI 1662
9586-cc9m2443 MACH_CC9M2443 CC9M2443 1663
9587+cc9m2443js MACH_CC9M2443JS CC9M2443JS 1663
9588 tw5334 MACH_TW5334 TW5334 1664
9589 omap_htcartemis MACH_HTCARTEMIS HTCARTEMIS 1665
9590 nal_hlite MACH_NAL_HLITE NAL_HLITE 1666
9591@@ -1769,14 +1769,15 @@ mx31cicada MACH_MX31CICADA MX31CICADA
9592 mi424wr MACH_MI424WR MI424WR 1778
9593 axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779
9594 at572d940deb MACH_AT572D940DEB AT572D940DEB 1780
9595-davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781
9596+davinci_da830_evm MACH_DAVINCI_DA830_EVM DAVINCI_DA830_EVM 1781
9597 ep9302 MACH_EP9302 EP9302 1782
9598 at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783
9599 cybook3 MACH_CYBOOK3 CYBOOK3 1784
9600 wdg002 MACH_WDG002 WDG002 1785
9601 sg560adsl MACH_SG560ADSL SG560ADSL 1786
9602 nextio_n2800_ica MACH_NEXTIO_N2800_ICA NEXTIO_N2800_ICA 1787
9603-marvell_newdb MACH_MARVELL_NEWDB MARVELL_NEWDB 1789
9604+dove_db MACH_DOVE_DB DOVE_DB 1788
9605+dove_avng MACH_MARVELL_NEWDB MARVELL_NEWDB 1789
9606 vandihud MACH_VANDIHUD VANDIHUD 1790
9607 magx_e8 MACH_MAGX_E8 MAGX_E8 1791
9608 magx_z6 MACH_MAGX_Z6 MAGX_Z6 1792
9609@@ -1802,7 +1803,7 @@ ccw9p9215js MACH_CCW9P9215JS CCW9P9215J
9610 rd88f5181l_ge MACH_RD88F5181L_GE RD88F5181L_GE 1812
9611 sifmain MACH_SIFMAIN SIFMAIN 1813
9612 sam9_l9261 MACH_SAM9_L9261 SAM9_L9261 1814
9613-cc9m2443js MACH_CC9M2443JS CC9M2443JS 1815
9614+cc9m2443 MACH_CC9M2443 CC9M2443 1815
9615 xaria300 MACH_XARIA300 XARIA300 1816
9616 it9200 MACH_IT9200 IT9200 1817
9617 rd88f5181l_fxo MACH_RD88F5181L_FXO RD88F5181L_FXO 1818
9618@@ -1962,7 +1963,7 @@ ethernut5 MACH_ETHERNUT5 ETHERNUT5 19
9619 arm11 MACH_ARM11 ARM11 1972
9620 cpuat9260 MACH_CPUAT9260 CPUAT9260 1973
9621 cpupxa255 MACH_CPUPXA255 CPUPXA255 1974
9622-cpuimx27 MACH_CPUIMX27 CPUIMX27 1975
9623+eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975
9624 cheflux MACH_CHEFLUX CHEFLUX 1976
9625 eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977
9626 opcotec MACH_OPCOTEC OPCOTEC 1978
9627@@ -2249,14 +2250,14 @@ omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_
9628 darwin MACH_DARWIN DARWIN 2262
9629 oratiscomu MACH_ORATISCOMU ORATISCOMU 2263
9630 rtsbc20 MACH_RTSBC20 RTSBC20 2264
9631-i780 MACH_I780 I780 2265
9632+sgh_i780 MACH_I780 I780 2265
9633 gemini324 MACH_GEMINI324 GEMINI324 2266
9634 oratislan MACH_ORATISLAN ORATISLAN 2267
9635 oratisalog MACH_ORATISALOG ORATISALOG 2268
9636 oratismadi MACH_ORATISMADI ORATISMADI 2269
9637 oratisot16 MACH_ORATISOT16 ORATISOT16 2270
9638 oratisdesk MACH_ORATISDESK ORATISDESK 2271
9639-v2p_ca9 MACH_V2P_CA9 V2P_CA9 2272
9640+vexpress MACH_VEXPRESS VEXPRESS 2272
9641 sintexo MACH_SINTEXO SINTEXO 2273
9642 cm3389 MACH_CM3389 CM3389 2274
9643 omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275
9644@@ -2280,3 +2281,615 @@ htcrhodium MACH_HTCRHODIUM HTCRHODIUM
9645 htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293
9646 matrix504 MACH_MATRIX504 MATRIX504 2294
9647 mrfsa MACH_MRFSA MRFSA 2295
9648+sc_p270 MACH_SC_P270 SC_P270 2296
9649+atlas5_evb MACH_ATLAS5_EVB ATLAS5_EVB 2297
9650+pelco_lobox MACH_PELCO_LOBOX PELCO_LOBOX 2298
9651+dilax_pcu200 MACH_DILAX_PCU200 DILAX_PCU200 2299
9652+leonardo MACH_LEONARDO LEONARDO 2300
9653+zoran_approach7 MACH_ZORAN_APPROACH7 ZORAN_APPROACH7 2301
9654+dp6xx MACH_DP6XX DP6XX 2302
9655+bcm2153_vesper MACH_BCM2153_VESPER BCM2153_VESPER 2303
9656+mahimahi MACH_MAHIMAHI MAHIMAHI 2304
9657+clickc MACH_CLICKC CLICKC 2305
9658+zb_gateway MACH_ZB_GATEWAY ZB_GATEWAY 2306
9659+tazcard MACH_TAZCARD TAZCARD 2307
9660+tazdev MACH_TAZDEV TAZDEV 2308
9661+annax_cb_arm MACH_ANNAX_CB_ARM ANNAX_CB_ARM 2309
9662+annax_dm3 MACH_ANNAX_DM3 ANNAX_DM3 2310
9663+cerebric MACH_CEREBRIC CEREBRIC 2311
9664+orca MACH_ORCA ORCA 2312
9665+pc9260 MACH_PC9260 PC9260 2313
9666+ems285a MACH_EMS285A EMS285A 2314
9667+gec2410 MACH_GEC2410 GEC2410 2315
9668+gec2440 MACH_GEC2440 GEC2440 2316
9669+mw903 MACH_ARCH_MW903 ARCH_MW903 2317
9670+mw2440 MACH_MW2440 MW2440 2318
9671+ecac2378 MACH_ECAC2378 ECAC2378 2319
9672+tazkiosk MACH_TAZKIOSK TAZKIOSK 2320
9673+whiterabbit_mch MACH_WHITERABBIT_MCH WHITERABBIT_MCH 2321
9674+sbox9263 MACH_SBOX9263 SBOX9263 2322
9675+oreo_camera MACH_OREO OREO 2323
9676+smdk6442 MACH_SMDK6442 SMDK6442 2324
9677+openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325
9678+incredible MACH_INCREDIBLE INCREDIBLE 2326
9679+incrediblec MACH_INCREDIBLEC INCREDIBLEC 2327
9680+heroct MACH_HEROCT HEROCT 2328
9681+mmnet1000 MACH_MMNET1000 MMNET1000 2329
9682+devkit8000 MACH_DEVKIT8000 DEVKIT8000 2330
9683+devkit9000 MACH_DEVKIT9000 DEVKIT9000 2331
9684+mx31txtr MACH_MX31TXTR MX31TXTR 2332
9685+u380 MACH_U380 U380 2333
9686+oamp3_hualu MACH_HUALU_BOARD HUALU_BOARD 2334
9687+npcmx50 MACH_NPCMX50 NPCMX50 2335
9688+mx51_lange51 MACH_MX51_LANGE51 MX51_LANGE51 2336
9689+mx51_lange52 MACH_MX51_LANGE52 MX51_LANGE52 2337
9690+riom MACH_RIOM RIOM 2338
9691+comcas MACH_COMCAS COMCAS 2339
9692+wsi_mx27 MACH_WSI_MX27 WSI_MX27 2340
9693+cm_t35 MACH_CM_T35 CM_T35 2341
9694+net2big MACH_NET2BIG NET2BIG 2342
9695+motorola_a1600 MACH_MOTOROLA_A1600 MOTOROLA_A1600 2343
9696+igep0020 MACH_IGEP0020 IGEP0020 2344
9697+igep0010 MACH_IGEP0010 IGEP0010 2345
9698+mv6281gtwge2 MACH_MV6281GTWGE2 MV6281GTWGE2 2346
9699+scat100 MACH_SCAT100 SCAT100 2347
9700+sanmina MACH_SANMINA SANMINA 2348
9701+momento MACH_MOMENTO MOMENTO 2349
9702+nuc9xx MACH_NUC9XX NUC9XX 2350
9703+nuc910evb MACH_NUC910EVB NUC910EVB 2351
9704+nuc920evb MACH_NUC920EVB NUC920EVB 2352
9705+nuc950evb MACH_NUC950EVB NUC950EVB 2353
9706+nuc945evb MACH_NUC945EVB NUC945EVB 2354
9707+nuc960evb MACH_NUC960EVB NUC960EVB 2355
9708+nuc932evb MACH_NUC932EVB NUC932EVB 2356
9709+nuc900 MACH_NUC900 NUC900 2357
9710+sd1soc MACH_SD1SOC SD1SOC 2358
9711+ln2440bc MACH_LN2440BC LN2440BC 2359
9712+rsbc MACH_RSBC RSBC 2360
9713+openrd_client MACH_OPENRD_CLIENT OPENRD_CLIENT 2361
9714+hpipaq11x MACH_HPIPAQ11X HPIPAQ11X 2362
9715+wayland MACH_WAYLAND WAYLAND 2363
9716+acnbsx102 MACH_ACNBSX102 ACNBSX102 2364
9717+hwat91 MACH_HWAT91 HWAT91 2365
9718+at91sam9263cs MACH_AT91SAM9263CS AT91SAM9263CS 2366
9719+csb732 MACH_CSB732 CSB732 2367
9720+u8500 MACH_U8500 U8500 2368
9721+huqiu MACH_HUQIU HUQIU 2369
9722+mx51_kunlun MACH_MX51_KUNLUN MX51_KUNLUN 2370
9723+pmt1g MACH_PMT1G PMT1G 2371
9724+htcelf MACH_HTCELF HTCELF 2372
9725+armadillo420 MACH_ARMADILLO420 ARMADILLO420 2373
9726+armadillo440 MACH_ARMADILLO440 ARMADILLO440 2374
9727+u_chip_dual_arm MACH_U_CHIP_DUAL_ARM U_CHIP_DUAL_ARM 2375
9728+csr_bdb3 MACH_CSR_BDB3 CSR_BDB3 2376
9729+dolby_cat1018 MACH_DOLBY_CAT1018 DOLBY_CAT1018 2377
9730+hy9307 MACH_HY9307 HY9307 2378
9731+aspire_easystore MACH_A_ES A_ES 2379
9732+davinci_irif MACH_DAVINCI_IRIF DAVINCI_IRIF 2380
9733+agama9263 MACH_AGAMA9263 AGAMA9263 2381
9734+marvell_jasper MACH_MARVELL_JASPER MARVELL_JASPER 2382
9735+flint MACH_FLINT FLINT 2383
9736+tavorevb3 MACH_TAVOREVB3 TAVOREVB3 2384
9737+sch_m490 MACH_SCH_M490 SCH_M490 2386
9738+rbl01 MACH_RBL01 RBL01 2387
9739+omnifi MACH_OMNIFI OMNIFI 2388
9740+otavalo MACH_OTAVALO OTAVALO 2389
9741+siena MACH_SIENNA SIENNA 2390
9742+htc_excalibur_s620 MACH_HTC_EXCALIBUR_S620 HTC_EXCALIBUR_S620 2391
9743+htc_opal MACH_HTC_OPAL HTC_OPAL 2392
9744+touchbook MACH_TOUCHBOOK TOUCHBOOK 2393
9745+latte MACH_LATTE LATTE 2394
9746+xa200 MACH_XA200 XA200 2395
9747+nimrod MACH_NIMROD NIMROD 2396
9748+cc9p9215_3g MACH_CC9P9215_3G CC9P9215_3G 2397
9749+cc9p9215_3gjs MACH_CC9P9215_3GJS CC9P9215_3GJS 2398
9750+tk71 MACH_TK71 TK71 2399
9751+comham3525 MACH_COMHAM3525 COMHAM3525 2400
9752+mx31erebus MACH_MX31EREBUS MX31EREBUS 2401
9753+mcardmx27 MACH_MCARDMX27 MCARDMX27 2402
9754+paradise MACH_PARADISE PARADISE 2403
9755+tide MACH_TIDE TIDE 2404
9756+wzl2440 MACH_WZL2440 WZL2440 2405
9757+sdrdemo MACH_SDRDEMO SDRDEMO 2406
9758+ethercan2 MACH_ETHERCAN2 ETHERCAN2 2407
9759+ecmimg20 MACH_ECMIMG20 ECMIMG20 2408
9760+omap_dragon MACH_OMAP_DRAGON OMAP_DRAGON 2409
9761+halo MACH_HALO HALO 2410
9762+huangshan MACH_HUANGSHAN HUANGSHAN 2411
9763+vl_ma2sc MACH_VL_MA2SC VL_MA2SC 2412
9764+raumfeld_rc MACH_RAUMFELD_RC RAUMFELD_RC 2413
9765+raumfeld_connector MACH_RAUMFELD_CONNECTOR RAUMFELD_CONNECTOR 2414
9766+raumfeld_speaker MACH_RAUMFELD_SPEAKER RAUMFELD_SPEAKER 2415
9767+multibus_master MACH_MULTIBUS_MASTER MULTIBUS_MASTER 2416
9768+multibus_pbk MACH_MULTIBUS_PBK MULTIBUS_PBK 2417
9769+tnetv107x MACH_TNETV107X TNETV107X 2418
9770+snake MACH_SNAKE SNAKE 2419
9771+cwmx27 MACH_CWMX27 CWMX27 2420
9772+sch_m480 MACH_SCH_M480 SCH_M480 2421
9773+platypus MACH_PLATYPUS PLATYPUS 2422
9774+pss2 MACH_PSS2 PSS2 2423
9775+davinci_apm150 MACH_DAVINCI_APM150 DAVINCI_APM150 2424
9776+str9100 MACH_STR9100 STR9100 2425
9777+net5big MACH_NET5BIG NET5BIG 2426
9778+seabed9263 MACH_SEABED9263 SEABED9263 2427
9779+mx51_m2id MACH_MX51_M2ID MX51_M2ID 2428
9780+octvocplus_eb MACH_OCTVOCPLUS_EB OCTVOCPLUS_EB 2429
9781+klk_firefox MACH_KLK_FIREFOX KLK_FIREFOX 2430
9782+klk_wirma_module MACH_KLK_WIRMA_MODULE KLK_WIRMA_MODULE 2431
9783+klk_wirma_mmi MACH_KLK_WIRMA_MMI KLK_WIRMA_MMI 2432
9784+supersonic MACH_SUPERSONIC SUPERSONIC 2433
9785+liberty MACH_LIBERTY LIBERTY 2434
9786+mh355 MACH_MH355 MH355 2435
9787+pc7802 MACH_PC7802 PC7802 2436
9788+gnet_sgc MACH_GNET_SGC GNET_SGC 2437
9789+einstein15 MACH_EINSTEIN15 EINSTEIN15 2438
9790+cmpd MACH_CMPD CMPD 2439
9791+davinci_hase1 MACH_DAVINCI_HASE1 DAVINCI_HASE1 2440
9792+lgeincitephone MACH_LGEINCITEPHONE LGEINCITEPHONE 2441
9793+ea313x MACH_EA313X EA313X 2442
9794+fwbd_39064 MACH_FWBD_39064 FWBD_39064 2443
9795+fwbd_390128 MACH_FWBD_390128 FWBD_390128 2444
9796+pelco_moe MACH_PELCO_MOE PELCO_MOE 2445
9797+minimix27 MACH_MINIMIX27 MINIMIX27 2446
9798+omap3_thunder MACH_OMAP3_THUNDER OMAP3_THUNDER 2447
9799+passionc MACH_PASSIONC PASSIONC 2448
9800+mx27amata MACH_MX27AMATA MX27AMATA 2449
9801+bgat1 MACH_BGAT1 BGAT1 2450
9802+buzz MACH_BUZZ BUZZ 2451
9803+mb9g20 MACH_MB9G20 MB9G20 2452
9804+yushan MACH_YUSHAN YUSHAN 2453
9805+lizard MACH_LIZARD LIZARD 2454
9806+omap3polycom MACH_OMAP3POLYCOM OMAP3POLYCOM 2455
9807+smdkv210 MACH_SMDKV210 SMDKV210 2456
9808+bravo MACH_BRAVO BRAVO 2457
9809+siogentoo1 MACH_SIOGENTOO1 SIOGENTOO1 2458
9810+siogentoo2 MACH_SIOGENTOO2 SIOGENTOO2 2459
9811+sm3k MACH_SM3K SM3K 2460
9812+acer_tempo_f900 MACH_ACER_TEMPO_F900 ACER_TEMPO_F900 2461
9813+sst61vc010_dev MACH_SST61VC010_DEV SST61VC010_DEV 2462
9814+glittertind MACH_GLITTERTIND GLITTERTIND 2463
9815+omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464
9816+omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465
9817+cybook2440 MACH_CYBOOK2440 CYBOOK2440 2466
9818+torino_s MACH_TORINO_S TORINO_S 2467
9819+havana MACH_HAVANA HAVANA 2468
9820+beaumont_11 MACH_BEAUMONT_11 BEAUMONT_11 2469
9821+vanguard MACH_VANGUARD VANGUARD 2470
9822+s5pc110_draco MACH_S5PC110_DRACO S5PC110_DRACO 2471
9823+cartesio_two MACH_CARTESIO_TWO CARTESIO_TWO 2472
9824+aster MACH_ASTER ASTER 2473
9825+voguesv210 MACH_VOGUESV210 VOGUESV210 2474
9826+acm500x MACH_ACM500X ACM500X 2475
9827+km9260 MACH_KM9260 KM9260 2476
9828+nideflexg1 MACH_NIDEFLEXG1 NIDEFLEXG1 2477
9829+ctera_plug_io MACH_CTERA_PLUG_IO CTERA_PLUG_IO 2478
9830+smartq7 MACH_SMARTQ7 SMARTQ7 2479
9831+at91sam9g10ek2 MACH_AT91SAM9G10EK2 AT91SAM9G10EK2 2480
9832+asusp527 MACH_ASUSP527 ASUSP527 2481
9833+at91sam9g20mpm2 MACH_AT91SAM9G20MPM2 AT91SAM9G20MPM2 2482
9834+topasa900 MACH_TOPASA900 TOPASA900 2483
9835+electrum_100 MACH_ELECTRUM_100 ELECTRUM_100 2484
9836+mx51grb MACH_MX51GRB MX51GRB 2485
9837+xea300 MACH_XEA300 XEA300 2486
9838+htcstartrek MACH_HTCSTARTREK HTCSTARTREK 2487
9839+lima MACH_LIMA LIMA 2488
9840+csb740 MACH_CSB740 CSB740 2489
9841+usb_s8815 MACH_USB_S8815 USB_S8815 2490
9842+watson_efm_plugin MACH_WATSON_EFM_PLUGIN WATSON_EFM_PLUGIN 2491
9843+milkyway MACH_MILKYWAY MILKYWAY 2492
9844+g4evm MACH_G4EVM G4EVM 2493
9845+picomod6 MACH_PICOMOD6 PICOMOD6 2494
9846+omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495
9847+ip6000 MACH_IP6000 IP6000 2496
9848+ip6010 MACH_IP6010 IP6010 2497
9849+utm400 MACH_UTM400 UTM400 2498
9850+omap3_zybex MACH_OMAP3_ZYBEX OMAP3_ZYBEX 2499
9851+wireless_space MACH_WIRELESS_SPACE WIRELESS_SPACE 2500
9852+sx560 MACH_SX560 SX560 2501
9853+ts41x MACH_TS41X TS41X 2502
9854+elphel10373 MACH_ELPHEL10373 ELPHEL10373 2503
9855+rhobot MACH_RHOBOT RHOBOT 2504
9856+mx51_refresh MACH_MX51_REFRESH MX51_REFRESH 2505
9857+ls9260 MACH_LS9260 LS9260 2506
9858+shank MACH_SHANK SHANK 2507
9859+qsd8x50_st1 MACH_QSD8X50_ST1 QSD8X50_ST1 2508
9860+at91sam9m10ekes MACH_AT91SAM9M10EKES AT91SAM9M10EKES 2509
9861+hiram MACH_HIRAM HIRAM 2510
9862+phy3250 MACH_PHY3250 PHY3250 2511
9863+ea3250 MACH_EA3250 EA3250 2512
9864+fdi3250 MACH_FDI3250 FDI3250 2513
9865+htcwhitestone MACH_WHITESTONE WHITESTONE 2514
9866+at91sam9263nit MACH_AT91SAM9263NIT AT91SAM9263NIT 2515
9867+ccmx51 MACH_CCMX51 CCMX51 2516
9868+ccmx51js MACH_CCMX51JS CCMX51JS 2517
9869+ccwmx51 MACH_CCWMX51 CCWMX51 2518
9870+ccwmx51js MACH_CCWMX51JS CCWMX51JS 2519
9871+mini6410 MACH_MINI6410 MINI6410 2520
9872+tiny6410 MACH_TINY6410 TINY6410 2521
9873+nano6410 MACH_NANO6410 NANO6410 2522
9874+at572d940hfnldb MACH_AT572D940HFNLDB AT572D940HFNLDB 2523
9875+htcleo MACH_HTCLEO HTCLEO 2524
9876+avp13 MACH_AVP13 AVP13 2525
9877+xxsvideod MACH_XXSVIDEOD XXSVIDEOD 2526
9878+vpnext MACH_VPNEXT VPNEXT 2527
9879+swarco_itc3 MACH_SWARCO_ITC3 SWARCO_ITC3 2528
9880+tx51 MACH_TX51 TX51 2529
9881+dolby_cat1021 MACH_DOLBY_CAT1021 DOLBY_CAT1021 2530
9882+mx28evk MACH_MX28EVK MX28EVK 2531
9883+phoenix260 MACH_PHOENIX260 PHOENIX260 2532
9884+uvaca_stork MACH_UVACA_STORK UVACA_STORK 2533
9885+smartq5 MACH_SMARTQ5 SMARTQ5 2534
9886+all3078 MACH_ALL3078 ALL3078 2535
9887+ctera_2bay_ds MACH_CTERA_2BAY_DS CTERA_2BAY_DS 2536
9888+siogentoo3 MACH_SIOGENTOO3 SIOGENTOO3 2537
9889+epb5000 MACH_EPB5000 EPB5000 2538
9890+hy9263 MACH_HY9263 HY9263 2539
9891+acer_tempo_m900 MACH_ACER_TEMPO_M900 ACER_TEMPO_M900 2540
9892+acer_tempo_dx650 MACH_ACER_TEMPO_DX900 ACER_TEMPO_DX900 2541
9893+acer_tempo_x960 MACH_ACER_TEMPO_X960 ACER_TEMPO_X960 2542
9894+acer_eten_v900 MACH_ACER_ETEN_V900 ACER_ETEN_V900 2543
9895+acer_eten_x900 MACH_ACER_ETEN_X900 ACER_ETEN_X900 2544
9896+bonnell MACH_BONNELL BONNELL 2545
9897+oht_mx27 MACH_OHT_MX27 OHT_MX27 2546
9898+htcquartz MACH_HTCQUARTZ HTCQUARTZ 2547
9899+davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548
9900+c3ax03 MACH_C3AX03 C3AX03 2549
9901+mxt_td60 MACH_MXT_TD60 MXT_TD60 2550
9902+esyx MACH_ESYX ESYX 2551
9903+dove_db2 MACH_DOVE_DB2 DOVE_DB2 2552
9904+bulldog MACH_BULLDOG BULLDOG 2553
9905+derell_me2000 MACH_DERELL_ME2000 DERELL_ME2000 2554
9906+bcmring_base MACH_BCMRING_BASE BCMRING_BASE 2555
9907+bcmring_evm MACH_BCMRING_EVM BCMRING_EVM 2556
9908+bcmring_evm_jazz MACH_BCMRING_EVM_JAZZ BCMRING_EVM_JAZZ 2557
9909+bcmring_sp MACH_BCMRING_SP BCMRING_SP 2558
9910+bcmring_sv MACH_BCMRING_SV BCMRING_SV 2559
9911+bcmring_sv_jazz MACH_BCMRING_SV_JAZZ BCMRING_SV_JAZZ 2560
9912+bcmring_tablet MACH_BCMRING_TABLET BCMRING_TABLET 2561
9913+bcmring_vp MACH_BCMRING_VP BCMRING_VP 2562
9914+bcmring_evm_seikor MACH_BCMRING_EVM_SEIKOR BCMRING_EVM_SEIKOR 2563
9915+bcmring_sp_wqvga MACH_BCMRING_SP_WQVGA BCMRING_SP_WQVGA 2564
9916+bcmring_custom MACH_BCMRING_CUSTOM BCMRING_CUSTOM 2565
9917+acer_s200 MACH_ACER_S200 ACER_S200 2566
9918+bt270 MACH_BT270 BT270 2567
9919+iseo MACH_ISEO ISEO 2568
9920+cezanne MACH_CEZANNE CEZANNE 2569
9921+lucca MACH_LUCCA LUCCA 2570
9922+supersmart MACH_SUPERSMART SUPERSMART 2571
9923+arm11_board MACH_CS_MISANO CS_MISANO 2572
9924+magnolia2 MACH_MAGNOLIA2 MAGNOLIA2 2573
9925+emxx MACH_EMXX EMXX 2574
9926+outlaw MACH_OUTLAW OUTLAW 2575
9927+riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576
9928+riot_vox MACH_RIOT_VOX RIOT_VOX 2577
9929+riot_x37 MACH_RIOT_X37 RIOT_X37 2578
9930+mega25mx MACH_MEGA25MX MEGA25MX 2579
9931+benzina2 MACH_BENZINA2 BENZINA2 2580
9932+ignite MACH_IGNITE IGNITE 2581
9933+foggia MACH_FOGGIA FOGGIA 2582
9934+arezzo MACH_AREZZO AREZZO 2583
9935+leica_skywalker MACH_LEICA_SKYWALKER LEICA_SKYWALKER 2584
9936+jacinto2_jamr MACH_JACINTO2_JAMR JACINTO2_JAMR 2585
9937+gts_nova MACH_GTS_NOVA GTS_NOVA 2586
9938+p3600 MACH_P3600 P3600 2587
9939+dlt2 MACH_DLT2 DLT2 2588
9940+df3120 MACH_DF3120 DF3120 2589
9941+ecucore_9g20 MACH_ECUCORE_9G20 ECUCORE_9G20 2590
9942+nautel_lpc3240 MACH_NAUTEL_LPC3240 NAUTEL_LPC3240 2591
9943+glacier MACH_GLACIER GLACIER 2592
9944+phrazer_bulldog MACH_PHRAZER_BULLDOG PHRAZER_BULLDOG 2593
9945+omap3_bulldog MACH_OMAP3_BULLDOG OMAP3_BULLDOG 2594
9946+pca101 MACH_PCA101 PCA101 2595
9947+buzzc MACH_BUZZC BUZZC 2596
9948+sasie2 MACH_SASIE2 SASIE2 2597
9949+davinci_dm6467_cio MACH_DAVINCI_CIO DAVINCI_CIO 2598
9950+smartmeter_dl MACH_SMARTMETER_DL SMARTMETER_DL 2599
9951+wzl6410 MACH_WZL6410 WZL6410 2600
9952+wzl6410m MACH_WZL6410M WZL6410M 2601
9953+wzl6410f MACH_WZL6410F WZL6410F 2602
9954+wzl6410i MACH_WZL6410I WZL6410I 2603
9955+spacecom1 MACH_SPACECOM1 SPACECOM1 2604
9956+pingu920 MACH_PINGU920 PINGU920 2605
9957+bravoc MACH_BRAVOC BRAVOC 2606
9958+cybo2440 MACH_CYBO2440 CYBO2440 2607
9959+vdssw MACH_VDSSW VDSSW 2608
9960+romulus MACH_ROMULUS ROMULUS 2609
9961+omap_magic MACH_OMAP_MAGIC OMAP_MAGIC 2610
9962+eltd100 MACH_ELTD100 ELTD100 2611
9963+capc7117 MACH_CAPC7117 CAPC7117 2612
9964+swan MACH_SWAN SWAN 2613
9965+veu MACH_VEU VEU 2614
9966+rm2 MACH_RM2 RM2 2615
9967+tt2100 MACH_TT2100 TT2100 2616
9968+venice MACH_VENICE VENICE 2617
9969+pc7323 MACH_PC7323 PC7323 2618
9970+masp MACH_MASP MASP 2619
9971+fujitsu_tvstbsoc0 MACH_FUJITSU_TVSTBSOC FUJITSU_TVSTBSOC 2620
9972+fujitsu_tvstbsoc1 MACH_FUJITSU_TVSTBSOC1 FUJITSU_TVSTBSOC1 2621
9973+lexikon MACH_LEXIKON LEXIKON 2622
9974+mini2440v2 MACH_MINI2440V2 MINI2440V2 2623
9975+icontrol MACH_ICONTROL ICONTROL 2624
9976+sheevad MACH_SHEEVAD SHEEVAD 2625
9977+qsd8x50a_st1_1 MACH_QSD8X50A_ST1_1 QSD8X50A_ST1_1 2626
9978+qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627
9979+bee MACH_BEE BEE 2628
9980+mx23evk MACH_MX23EVK MX23EVK 2629
9981+ap4evb MACH_AP4EVB AP4EVB 2630
9982+stockholm MACH_STOCKHOLM STOCKHOLM 2631
9983+lpc_h3131 MACH_LPC_H3131 LPC_H3131 2632
9984+stingray MACH_STINGRAY STINGRAY 2633
9985+kraken MACH_KRAKEN KRAKEN 2634
9986+gw2388 MACH_GW2388 GW2388 2635
9987+jadecpu MACH_JADECPU JADECPU 2636
9988+carlisle MACH_CARLISLE CARLISLE 2637
9989+lux_sf9 MACH_LUX_SFT9 LUX_SFT9 2638
9990+nemid_tb MACH_NEMID_TB NEMID_TB 2639
9991+terrier MACH_TERRIER TERRIER 2640
9992+turbot MACH_TURBOT TURBOT 2641
9993+sanddab MACH_SANDDAB SANDDAB 2642
9994+mx35_cicada MACH_MX35_CICADA MX35_CICADA 2643
9995+ghi2703d MACH_GHI2703D GHI2703D 2644
9996+lux_sfx9 MACH_LUX_SFX9 LUX_SFX9 2645
9997+lux_sf9g MACH_LUX_SF9G LUX_SF9G 2646
9998+lux_edk9 MACH_LUX_EDK9 LUX_EDK9 2647
9999+hw90240 MACH_HW90240 HW90240 2648
10000+dm365_leopard MACH_DM365_LEOPARD DM365_LEOPARD 2649
10001+mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650
10002+scat110 MACH_SCAT110 SCAT110 2651
10003+acer_a1 MACH_ACER_A1 ACER_A1 2652
10004+cmcontrol MACH_CMCONTROL CMCONTROL 2653
10005+pelco_lamar MACH_PELCO_LAMAR PELCO_LAMAR 2654
10006+rfp43 MACH_RFP43 RFP43 2655
10007+sk86r0301 MACH_SK86R0301 SK86R0301 2656
10008+ctpxa MACH_CTPXA CTPXA 2657
10009+epb_arm9_a MACH_EPB_ARM9_A EPB_ARM9_A 2658
10010+guruplug MACH_GURUPLUG GURUPLUG 2659
10011+spear310 MACH_SPEAR310 SPEAR310 2660
10012+spear320 MACH_SPEAR320 SPEAR320 2661
10013+robotx MACH_ROBOTX ROBOTX 2662
10014+lsxhl MACH_LSXHL LSXHL 2663
10015+smartlite MACH_SMARTLITE SMARTLITE 2664
10016+cws2 MACH_CWS2 CWS2 2665
10017+m619 MACH_M619 M619 2666
10018+smartview MACH_SMARTVIEW SMARTVIEW 2667
10019+lsa_salsa MACH_LSA_SALSA LSA_SALSA 2668
10020+kizbox MACH_KIZBOX KIZBOX 2669
10021+htccharmer MACH_HTCCHARMER HTCCHARMER 2670
10022+guf_neso_lt MACH_GUF_NESO_LT GUF_NESO_LT 2671
10023+pm9g45 MACH_PM9G45 PM9G45 2672
10024+htcpanther MACH_HTCPANTHER HTCPANTHER 2673
10025+htcpanther_cdma MACH_HTCPANTHER_CDMA HTCPANTHER_CDMA 2674
10026+reb01 MACH_REB01 REB01 2675
10027+aquila MACH_AQUILA AQUILA 2676
10028+spark_sls_hw2 MACH_SPARK_SLS_HW2 SPARK_SLS_HW2 2677
10029+sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678
10030+msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679
10031+micro2440 MACH_MICRO2440 MICRO2440 2680
10032+am2440 MACH_AM2440 AM2440 2681
10033+tq2440 MACH_TQ2440 TQ2440 2682
10034+lpc2478oem MACH_LPC2478OEM LPC2478OEM 2683
10035+ak880x MACH_AK880X AK880X 2684
10036+cobra3530 MACH_COBRA3530 COBRA3530 2685
10037+pmppb MACH_PMPPB PMPPB 2686
10038+u6715 MACH_U6715 U6715 2687
10039+axar1500_sender MACH_AXAR1500_SENDER AXAR1500_SENDER 2688
10040+g30_dvb MACH_G30_DVB G30_DVB 2689
10041+vc088x MACH_VC088X VC088X 2690
10042+mioa702 MACH_MIOA702 MIOA702 2691
10043+hpmin MACH_HPMIN HPMIN 2692
10044+ak880xak MACH_AK880XAK AK880XAK 2693
10045+arm926tomap850 MACH_ARM926TOMAP850 ARM926TOMAP850 2694
10046+lkevm MACH_LKEVM LKEVM 2695
10047+mw6410 MACH_MW6410 MW6410 2696
10048+terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697
10049+cpu8000e MACH_CPU8000E CPU8000E 2698
10050+catania MACH_CATANIA CATANIA 2699
10051+tokyo MACH_TOKYO TOKYO 2700
10052+msm7201a_surf MACH_MSM7201A_SURF MSM7201A_SURF 2701
10053+msm7201a_ffa MACH_MSM7201A_FFA MSM7201A_FFA 2702
10054+msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703
10055+msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704
10056+msm7x27_surf MACH_MSM7X27_SURF MSM7X27_SURF 2705
10057+msm7x27_ffa MACH_MSM7X27_FFA MSM7X27_FFA 2706
10058+msm7x30_ffa MACH_MSM7X30_FFA MSM7X30_FFA 2707
10059+qsd8x50_surf MACH_QSD8X50_SURF QSD8X50_SURF 2708
10060+qsd8x50_comet MACH_QSD8X50_COMET QSD8X50_COMET 2709
10061+qsd8x50_ffa MACH_QSD8X50_FFA QSD8X50_FFA 2710
10062+qsd8x50a_surf MACH_QSD8X50A_SURF QSD8X50A_SURF 2711
10063+qsd8x50a_ffa MACH_QSD8X50A_FFA QSD8X50A_FFA 2712
10064+adx_xgcp10 MACH_ADX_XGCP10 ADX_XGCP10 2713
10065+mcgwumts2a MACH_MCGWUMTS2A MCGWUMTS2A 2714
10066+mobikt MACH_MOBIKT MOBIKT 2715
10067+mx53_evk MACH_MX53_EVK MX53_EVK 2716
10068+igep0030 MACH_IGEP0030 IGEP0030 2717
10069+axell_h40_h50_ctrl MACH_AXELL_H40_H50_CTRL AXELL_H40_H50_CTRL 2718
10070+dtcommod MACH_DTCOMMOD DTCOMMOD 2719
10071+gould MACH_GOULD GOULD 2720
10072+siberia MACH_SIBERIA SIBERIA 2721
10073+sbc3530 MACH_SBC3530 SBC3530 2722
10074+qarm MACH_QARM QARM 2723
10075+mips MACH_MIPS MIPS 2724
10076+mx27grb MACH_MX27GRB MX27GRB 2725
10077+sbc8100 MACH_SBC8100 SBC8100 2726
10078+saarb MACH_SAARB SAARB 2727
10079+omap3mini MACH_OMAP3MINI OMAP3MINI 2728
10080+cnmbook7se MACH_CNMBOOK7SE CNMBOOK7SE 2729
10081+catan MACH_CATAN CATAN 2730
10082+harmony MACH_HARMONY HARMONY 2731
10083+tonga MACH_TONGA TONGA 2732
10084+cybook_orizon MACH_CYBOOK_ORIZON CYBOOK_ORIZON 2733
10085+htcrhodiumcdma MACH_HTCRHODIUMCDMA HTCRHODIUMCDMA 2734
10086+epc_g45 MACH_EPC_G45 EPC_G45 2735
10087+epc_lpc3250 MACH_EPC_LPC3250 EPC_LPC3250 2736
10088+mxc91341evb MACH_MXC91341EVB MXC91341EVB 2737
10089+rtw1000 MACH_RTW1000 RTW1000 2738
10090+bobcat MACH_BOBCAT BOBCAT 2739
10091+trizeps6 MACH_TRIZEPS6 TRIZEPS6 2740
10092+msm7x30_fluid MACH_MSM7X30_FLUID MSM7X30_FLUID 2741
10093+nedap9263 MACH_NEDAP9263 NEDAP9263 2742
10094+netgear_ms2110 MACH_NETGEAR_MS2110 NETGEAR_MS2110 2743
10095+bmx MACH_BMX BMX 2744
10096+netstream MACH_NETSTREAM NETSTREAM 2745
10097+vpnext_rcu MACH_VPNEXT_RCU VPNEXT_RCU 2746
10098+vpnext_mpu MACH_VPNEXT_MPU VPNEXT_MPU 2747
10099+bcmring_tablet_v1 MACH_BCMRING_TABLET_V1 BCMRING_TABLET_V1 2748
10100+sgarm10 MACH_SGARM10 SGARM10 2749
10101+cm_t3517 MACH_CM_T3517 CM_T3517 2750
10102+omap3_cps MACH_OMAP3_CPS OMAP3_CPS 2751
10103+axar1500_receiver MACH_AXAR1500_RECEIVER AXAR1500_RECEIVER 2752
10104+wbd222 MACH_WBD222 WBD222 2753
10105+mt65xx MACH_MT65XX MT65XX 2754
10106+msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755
10107+msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756
10108+vmc300 MACH_VMC300 VMC300 2757
10109+tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758
10110+nanos MACH_NANOS NANOS 2759
10111+stamp9g10 MACH_STAMP9G10 STAMP9G10 2760
10112+stamp9g45 MACH_STAMP9G45 STAMP9G45 2761
10113+h6053 MACH_H6053 H6053 2762
10114+smint01 MACH_SMINT01 SMINT01 2763
10115+prtlvt2 MACH_PRTLVT2 PRTLVT2 2764
10116+ap420 MACH_AP420 AP420 2765
10117+htcclio MACH_HTCSHIFT HTCSHIFT 2766
10118+davinci_dm365_fc MACH_DAVINCI_DM365_FC DAVINCI_DM365_FC 2767
10119+msm8x55_surf MACH_MSM8X55_SURF MSM8X55_SURF 2768
10120+msm8x55_ffa MACH_MSM8X55_FFA MSM8X55_FFA 2769
10121+esl_vamana MACH_ESL_VAMANA ESL_VAMANA 2770
10122+sbc35 MACH_SBC35 SBC35 2771
10123+mpx6446 MACH_MPX6446 MPX6446 2772
10124+oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773
10125+kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774
10126+ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775
10127+cns3420vb MACH_CNS3420VB CNS3420VB 2776
10128+lpc_evo MACH_LPC2 LPC2 2777
10129+olympus MACH_OLYMPUS OLYMPUS 2778
10130+vortex MACH_VORTEX VORTEX 2779
10131+s5pc200 MACH_S5PC200 S5PC200 2780
10132+ecucore_9263 MACH_ECUCORE_9263 ECUCORE_9263 2781
10133+smdkc200 MACH_SMDKC200 SMDKC200 2782
10134+emsiso_sx27 MACH_EMSISO_SX27 EMSISO_SX27 2783
10135+apx_som9g45_ek MACH_APX_SOM9G45_EK APX_SOM9G45_EK 2784
10136+songshan MACH_SONGSHAN SONGSHAN 2785
10137+tianshan MACH_TIANSHAN TIANSHAN 2786
10138+vpx500 MACH_VPX500 VPX500 2787
10139+am3517sam MACH_AM3517SAM AM3517SAM 2788
10140+skat91_sim508 MACH_SKAT91_SIM508 SKAT91_SIM508 2789
10141+skat91_s3e MACH_SKAT91_S3E SKAT91_S3E 2790
10142+omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
10143+df7220 MACH_DF7220 DF7220 2792
10144+nemini MACH_NEMINI NEMINI 2793
10145+t8200 MACH_T8200 T8200 2794
10146+apf51 MACH_APF51 APF51 2795
10147+dr_rc_unit MACH_DR_RC_UNIT DR_RC_UNIT 2796
10148+bordeaux MACH_BORDEAUX BORDEAUX 2797
10149+catania_b MACH_CATANIA_B CATANIA_B 2798
10150+mx51_ocean MACH_MX51_OCEAN MX51_OCEAN 2799
10151+ti8168evm MACH_TI8168EVM TI8168EVM 2800
10152+neocoreomap MACH_NEOCOREOMAP NEOCOREOMAP 2801
10153+withings_wbp MACH_WITHINGS_WBP WITHINGS_WBP 2802
10154+dbps MACH_DBPS DBPS 2803
10155+at91sam9261 MACH_SBC9261 SBC9261 2804
10156+pcbfp0001 MACH_PCBFP0001 PCBFP0001 2805
10157+speedy MACH_SPEEDY SPEEDY 2806
10158+chrysaor MACH_CHRYSAOR CHRYSAOR 2807
10159+tango MACH_TANGO TANGO 2808
10160+synology_dsx11 MACH_SYNOLOGY_DSX11 SYNOLOGY_DSX11 2809
10161+hanlin_v3ext MACH_HANLIN_V3EXT HANLIN_V3EXT 2810
10162+hanlin_v5 MACH_HANLIN_V5 HANLIN_V5 2811
10163+hanlin_v3plus MACH_HANLIN_V3PLUS HANLIN_V3PLUS 2812
10164+iriver_story MACH_IRIVER_STORY IRIVER_STORY 2813
10165+irex_iliad MACH_IREX_ILIAD IREX_ILIAD 2814
10166+irex_dr1000 MACH_IREX_DR1000 IREX_DR1000 2815
10167+teton_bga MACH_TETON_BGA TETON_BGA 2816
10168+snapper9g45 MACH_SNAPPER9G45 SNAPPER9G45 2817
10169+tam3517 MACH_TAM3517 TAM3517 2818
10170+pdc100 MACH_PDC100 PDC100 2819
10171+eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820
10172+eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821
10173+eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822
10174+eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823
10175+p565 MACH_P565 P565 2824
10176+acer_a4 MACH_ACER_A4 ACER_A4 2825
10177+davinci_dm368_bip MACH_DAVINCI_DM368_BIP DAVINCI_DM368_BIP 2826
10178+eshare MACH_ESHARE ESHARE 2827
10179+hw_omapl138_europa MACH_HW_OMAPL138_EUROPA HW_OMAPL138_EUROPA 2828
10180+wlbargn MACH_WLBARGN WLBARGN 2829
10181+bm170 MACH_BM170 BM170 2830
10182+netspace_mini_v2 MACH_NETSPACE_MINI_V2 NETSPACE_MINI_V2 2831
10183+netspace_plug_v2 MACH_NETSPACE_PLUG_V2 NETSPACE_PLUG_V2 2832
10184+siemens_l1 MACH_SIEMENS_L1 SIEMENS_L1 2833
10185+elv_lcu1 MACH_ELV_LCU1 ELV_LCU1 2834
10186+mcu1 MACH_MCU1 MCU1 2835
10187+omap3_tao3530 MACH_OMAP3_TAO3530 OMAP3_TAO3530 2836
10188+omap3_pcutouch MACH_OMAP3_PCUTOUCH OMAP3_PCUTOUCH 2837
10189+smdkc210 MACH_SMDKC210 SMDKC210 2838
10190+omap3_braillo MACH_OMAP3_BRAILLO OMAP3_BRAILLO 2839
10191+spyplug MACH_SPYPLUG SPYPLUG 2840
10192+ginger MACH_GINGER GINGER 2841
10193+tny_t3530 MACH_TNY_T3530 TNY_T3530 2842
10194+pca102 MACH_PCA102 PCA102 2843
10195+spade MACH_SPADE SPADE 2844
10196+mxc25_topaz MACH_MXC25_TOPAZ MXC25_TOPAZ 2845
10197+t5325 MACH_T5325 T5325 2846
10198+gw2361 MACH_GW2361 GW2361 2847
10199+elog MACH_ELOG ELOG 2848
10200+income MACH_INCOME INCOME 2849
10201+bcm589x MACH_BCM589X BCM589X 2850
10202+etna MACH_ETNA ETNA 2851
10203+hawks MACH_HAWKS HAWKS 2852
10204+meson MACH_MESON MESON 2853
10205+xsbase255 MACH_XSBASE255 XSBASE255 2854
10206+pvm2030 MACH_PVM2030 PVM2030 2855
10207+mioa502 MACH_MIOA502 MIOA502 2856
10208+vvbox_sdorig2 MACH_VVBOX_SDORIG2 VVBOX_SDORIG2 2857
10209+vvbox_sdlite2 MACH_VVBOX_SDLITE2 VVBOX_SDLITE2 2858
10210+vvbox_sdpro4 MACH_VVBOX_SDPRO4 VVBOX_SDPRO4 2859
10211+htc_spv_m700 MACH_HTC_SPV_M700 HTC_SPV_M700 2860
10212+mx257sx MACH_MX257SX MX257SX 2861
10213+goni MACH_GONI GONI 2862
10214+msm8x55_svlte_ffa MACH_MSM8X55_SVLTE_FFA MSM8X55_SVLTE_FFA 2863
10215+msm8x55_svlte_surf MACH_MSM8X55_SVLTE_SURF MSM8X55_SVLTE_SURF 2864
10216+quickstep MACH_QUICKSTEP QUICKSTEP 2865
10217+dmw96 MACH_DMW96 DMW96 2866
10218+hammerhead MACH_HAMMERHEAD HAMMERHEAD 2867
10219+trident MACH_TRIDENT TRIDENT 2868
10220+lightning MACH_LIGHTNING LIGHTNING 2869
10221+iconnect MACH_ICONNECT ICONNECT 2870
10222+autobot MACH_AUTOBOT AUTOBOT 2871
10223+coconut MACH_COCONUT COCONUT 2872
10224+durian MACH_DURIAN DURIAN 2873
10225+cayenne MACH_CAYENNE CAYENNE 2874
10226+fuji MACH_FUJI FUJI 2875
10227+synology_6282 MACH_SYNOLOGY_6282 SYNOLOGY_6282 2876
10228+em1sy MACH_EM1SY EM1SY 2877
10229+m502 MACH_M502 M502 2878
10230+matrix518 MACH_MATRIX518 MATRIX518 2879
10231+tiny_gurnard MACH_TINY_GURNARD TINY_GURNARD 2880
10232+spear1310 MACH_SPEAR1310 SPEAR1310 2881
10233+bv07 MACH_BV07 BV07 2882
10234+mxt_td61 MACH_MXT_TD61 MXT_TD61 2883
10235+openrd_ultimate MACH_OPENRD_ULTIMATE OPENRD_ULTIMATE 2884
10236+devixp MACH_DEVIXP DEVIXP 2885
10237+miccpt MACH_MICCPT MICCPT 2886
10238+mic256 MACH_MIC256 MIC256 2887
10239+as1167 MACH_AS1167 AS1167 2888
10240+omap3_ibiza MACH_OMAP3_IBIZA OMAP3_IBIZA 2889
10241+u5500 MACH_U5500 U5500 2890
10242+davinci_picto MACH_DAVINCI_PICTO DAVINCI_PICTO 2891
10243+mecha MACH_MECHA MECHA 2892
10244+bubba3 MACH_BUBBA3 BUBBA3 2893
10245+pupitre MACH_PUPITRE PUPITRE 2894
10246+tegra_harmony MACH_TEGRA_HARMONY TEGRA_HARMONY 2895
10247+tegra_vogue MACH_TEGRA_VOGUE TEGRA_VOGUE 2896
10248+tegra_e1165 MACH_TEGRA_E1165 TEGRA_E1165 2897
10249+simplenet MACH_SIMPLENET SIMPLENET 2898
10250+ec4350tbm MACH_EC4350TBM EC4350TBM 2899
10251+pec_tc MACH_PEC_TC PEC_TC 2900
10252+pec_hc2 MACH_PEC_HC2 PEC_HC2 2901
10253+esl_mobilis_a MACH_ESL_MOBILIS_A ESL_MOBILIS_A 2902
10254+esl_mobilis_b MACH_ESL_MOBILIS_B ESL_MOBILIS_B 2903
10255+esl_wave_a MACH_ESL_WAVE_A ESL_WAVE_A 2904
10256+esl_wave_b MACH_ESL_WAVE_B ESL_WAVE_B 2905
10257+unisense_mmm MACH_UNISENSE_MMM UNISENSE_MMM 2906
10258+blueshark MACH_BLUESHARK BLUESHARK 2907
10259+e10 MACH_E10 E10 2908
10260--- a/arch/arm/include/asm/thread_info.h
10261+++ b/arch/arm/include/asm/thread_info.h
10262@@ -115,7 +115,8 @@ extern void iwmmxt_task_restore(struct t
10263 extern void iwmmxt_task_release(struct thread_info *);
10264 extern void iwmmxt_task_switch(struct thread_info *);
10265 
10266-extern void vfp_sync_state(struct thread_info *thread);
10267+extern void vfp_sync_hwstate(struct thread_info *);
10268+extern void vfp_flush_hwstate(struct thread_info *);
10269 
10270 #endif
10271 
10272--- a/arch/arm/kernel/ptrace.c
10273+++ b/arch/arm/kernel/ptrace.c
10274@@ -663,7 +663,7 @@ static int ptrace_getvfpregs(struct task
10275     union vfp_state *vfp = &thread->vfpstate;
10276     struct user_vfp __user *ufp = data;
10277 
10278- vfp_sync_state(thread);
10279+ vfp_sync_hwstate(thread);
10280 
10281     /* copy the floating point registers */
10282     if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
10283@@ -686,7 +686,7 @@ static int ptrace_setvfpregs(struct task
10284     union vfp_state *vfp = &thread->vfpstate;
10285     struct user_vfp __user *ufp = data;
10286 
10287- vfp_sync_state(thread);
10288+ vfp_sync_hwstate(thread);
10289 
10290     /* copy the floating point registers */
10291     if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
10292@@ -697,6 +697,8 @@ static int ptrace_setvfpregs(struct task
10293     if (get_user(vfp->hard.fpscr, &ufp->fpscr))
10294         return -EFAULT;
10295 
10296+ vfp_flush_hwstate(thread);
10297+
10298     return 0;
10299 }
10300 #endif
10301--- a/arch/arm/vfp/entry.S
10302+++ b/arch/arm/vfp/entry.S
10303@@ -42,6 +42,7 @@ ENTRY(vfp_null_entry)
10304     mov pc, lr
10305 ENDPROC(vfp_null_entry)
10306 
10307+ .align 2
10308 .LCvfp:
10309     .word vfp_vector
10310 
10311@@ -61,6 +62,7 @@ ENTRY(vfp_testing_entry)
10312     mov pc, r9 @ we have handled the fault
10313 ENDPROC(vfp_testing_entry)
10314 
10315+ .align 2
10316 VFP_arch_address:
10317     .word VFP_arch
10318 
10319--- a/arch/arm/vfp/vfphw.S
10320+++ b/arch/arm/vfp/vfphw.S
10321@@ -209,40 +209,55 @@ ENDPROC(vfp_save_state)
10322 last_VFP_context_address:
10323     .word last_VFP_context
10324 
10325-ENTRY(vfp_get_float)
10326- add pc, pc, r0, lsl #3
10327+ .macro tbl_branch, base, tmp, shift
10328+#ifdef CONFIG_THUMB2_KERNEL
10329+ adr \tmp, 1f
10330+ add \tmp, \tmp, \base, lsl \shift
10331+ mov pc, \tmp
10332+#else
10333+ add pc, pc, \base, lsl \shift
10334     mov r0, r0
10335+#endif
10336+1:
10337+ .endm
10338+
10339+ENTRY(vfp_get_float)
10340+ tbl_branch r0, r3, #3
10341     .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
10342- mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
10343+1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
10344     mov pc, lr
10345- mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
10346+ .org 1b + 8
10347+1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
10348     mov pc, lr
10349+ .org 1b + 8
10350     .endr
10351 ENDPROC(vfp_get_float)
10352 
10353 ENTRY(vfp_put_float)
10354- add pc, pc, r1, lsl #3
10355- mov r0, r0
10356+ tbl_branch r1, r3, #3
10357     .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
10358- mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
10359+1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
10360     mov pc, lr
10361- mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
10362+ .org 1b + 8
10363+1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
10364     mov pc, lr
10365+ .org 1b + 8
10366     .endr
10367 ENDPROC(vfp_put_float)
10368 
10369 ENTRY(vfp_get_double)
10370- add pc, pc, r0, lsl #3
10371- mov r0, r0
10372+ tbl_branch r0, r3, #3
10373     .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
10374- fmrrd r0, r1, d\dr
10375+1: fmrrd r0, r1, d\dr
10376     mov pc, lr
10377+ .org 1b + 8
10378     .endr
10379 #ifdef CONFIG_VFPv3
10380     @ d16 - d31 registers
10381     .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
10382- mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
10383+1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
10384     mov pc, lr
10385+ .org 1b + 8
10386     .endr
10387 #endif
10388 
10389@@ -253,17 +268,18 @@ ENTRY(vfp_get_double)
10390 ENDPROC(vfp_get_double)
10391 
10392 ENTRY(vfp_put_double)
10393- add pc, pc, r2, lsl #3
10394- mov r0, r0
10395+ tbl_branch r2, r3, #3
10396     .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
10397- fmdrr d\dr, r0, r1
10398+1: fmdrr d\dr, r0, r1
10399     mov pc, lr
10400+ .org 1b + 8
10401     .endr
10402 #ifdef CONFIG_VFPv3
10403     @ d16 - d31 registers
10404     .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
10405- mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr
10406+1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
10407     mov pc, lr
10408+ .org 1b + 8
10409     .endr
10410 #endif
10411 ENDPROC(vfp_put_double)
10412--- a/arch/arm/vfp/vfpmodule.c
10413+++ b/arch/arm/vfp/vfpmodule.c
10414@@ -38,16 +38,75 @@ union vfp_state *last_VFP_context[NR_CPU
10415  */
10416 unsigned int VFP_arch;
10417 
10418+/*
10419+ * Per-thread VFP initialization.
10420+ */
10421+static void vfp_thread_flush(struct thread_info *thread)
10422+{
10423+ union vfp_state *vfp = &thread->vfpstate;
10424+ unsigned int cpu;
10425+
10426+ memset(vfp, 0, sizeof(union vfp_state));
10427+
10428+ vfp->hard.fpexc = FPEXC_EN;
10429+ vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
10430+
10431+ /*
10432+ * Disable VFP to ensure we initialize it first. We must ensure
10433+ * that the modification of last_VFP_context[] and hardware disable
10434+ * are done for the same CPU and without preemption.
10435+ */
10436+ cpu = get_cpu();
10437+ if (last_VFP_context[cpu] == vfp)
10438+ last_VFP_context[cpu] = NULL;
10439+ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
10440+ put_cpu();
10441+}
10442+
10443+static void vfp_thread_exit(struct thread_info *thread)
10444+{
10445+ /* release case: Per-thread VFP cleanup. */
10446+ union vfp_state *vfp = &thread->vfpstate;
10447+ unsigned int cpu = get_cpu();
10448+
10449+ if (last_VFP_context[cpu] == vfp)
10450+ last_VFP_context[cpu] = NULL;
10451+ put_cpu();
10452+}
10453+
10454+/*
10455+ * When this function is called with the following 'cmd's, the following
10456+ * is true while this function is being run:
10457+ * THREAD_NOFTIFY_SWTICH:
10458+ * - the previously running thread will not be scheduled onto another CPU.
10459+ * - the next thread to be run (v) will not be running on another CPU.
10460+ * - thread->cpu is the local CPU number
10461+ * - not preemptible as we're called in the middle of a thread switch
10462+ * THREAD_NOTIFY_FLUSH:
10463+ * - the thread (v) will be running on the local CPU, so
10464+ * v === current_thread_info()
10465+ * - thread->cpu is the local CPU number at the time it is accessed,
10466+ * but may change at any time.
10467+ * - we could be preempted if tree preempt rcu is enabled, so
10468+ * it is unsafe to use thread->cpu.
10469+ * THREAD_NOTIFY_EXIT
10470+ * - the thread (v) will be running on the local CPU, so
10471+ * v === current_thread_info()
10472+ * - thread->cpu is the local CPU number at the time it is accessed,
10473+ * but may change at any time.
10474+ * - we could be preempted if tree preempt rcu is enabled, so
10475+ * it is unsafe to use thread->cpu.
10476+ */
10477 static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
10478 {
10479     struct thread_info *thread = v;
10480- union vfp_state *vfp;
10481- __u32 cpu = thread->cpu;
10482 
10483     if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
10484         u32 fpexc = fmrx(FPEXC);
10485 
10486 #ifdef CONFIG_SMP
10487+ unsigned int cpu = thread->cpu;
10488+
10489         /*
10490          * On SMP, if VFP is enabled, save the old state in
10491          * case the thread migrates to a different CPU. The
10492@@ -74,25 +133,10 @@ static int vfp_notifier(struct notifier_
10493         return NOTIFY_DONE;
10494     }
10495 
10496- vfp = &thread->vfpstate;
10497- if (cmd == THREAD_NOTIFY_FLUSH) {
10498- /*
10499- * Per-thread VFP initialisation.
10500- */
10501- memset(vfp, 0, sizeof(union vfp_state));
10502-
10503- vfp->hard.fpexc = FPEXC_EN;
10504- vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
10505-
10506- /*
10507- * Disable VFP to ensure we initialise it first.
10508- */
10509- fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
10510- }
10511-
10512- /* flush and release case: Per-thread VFP cleanup. */
10513- if (last_VFP_context[cpu] == vfp)
10514- last_VFP_context[cpu] = NULL;
10515+ if (cmd == THREAD_NOTIFY_FLUSH)
10516+ vfp_thread_flush(thread);
10517+ else
10518+ vfp_thread_exit(thread);
10519 
10520     return NOTIFY_DONE;
10521 }
10522@@ -153,10 +197,13 @@ static void vfp_raise_exceptions(u32 exc
10523     }
10524 
10525     /*
10526- * Update the FPSCR with the additional exception flags.
10527+ * If any of the status flags are set, update the FPSCR.
10528      * Comparison instructions always return at least one of
10529      * these flags set.
10530      */
10531+ if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
10532+ fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
10533+
10534     fpscr |= exceptions;
10535 
10536     fmxr(FPSCR, fpscr);
10537@@ -381,54 +428,60 @@ static void vfp_pm_init(void)
10538 static inline void vfp_pm_init(void) { }
10539 #endif /* CONFIG_PM */
10540 
10541-/*
10542- * Synchronise the hardware VFP state of a thread other than current with the
10543- * saved one. This function is used by the ptrace mechanism.
10544- */
10545-#ifdef CONFIG_SMP
10546-void vfp_sync_state(struct thread_info *thread)
10547+void vfp_sync_hwstate(struct thread_info *thread)
10548 {
10549+ unsigned int cpu = get_cpu();
10550+
10551     /*
10552- * On SMP systems, the VFP state is automatically saved at every
10553- * context switch. We mark the thread VFP state as belonging to a
10554- * non-existent CPU so that the saved one will be reloaded when
10555- * needed.
10556+ * If the thread we're interested in is the current owner of the
10557+ * hardware VFP state, then we need to save its state.
10558      */
10559- thread->vfpstate.hard.cpu = NR_CPUS;
10560+ if (last_VFP_context[cpu] == &thread->vfpstate) {
10561+ u32 fpexc = fmrx(FPEXC);
10562+
10563+ /*
10564+ * Save the last VFP state on this CPU.
10565+ */
10566+ fmxr(FPEXC, fpexc | FPEXC_EN);
10567+ vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN);
10568+ fmxr(FPEXC, fpexc);
10569+ }
10570+
10571+ put_cpu();
10572 }
10573-#else
10574-void vfp_sync_state(struct thread_info *thread)
10575+
10576+void vfp_flush_hwstate(struct thread_info *thread)
10577 {
10578     unsigned int cpu = get_cpu();
10579- u32 fpexc = fmrx(FPEXC);
10580 
10581     /*
10582- * If VFP is enabled, the previous state was already saved and
10583- * last_VFP_context updated.
10584+ * If the thread we're interested in is the current owner of the
10585+ * hardware VFP state, then we need to save its state.
10586      */
10587- if (fpexc & FPEXC_EN)
10588- goto out;
10589+ if (last_VFP_context[cpu] == &thread->vfpstate) {
10590+ u32 fpexc = fmrx(FPEXC);
10591 
10592- if (!last_VFP_context[cpu])
10593- goto out;
10594+ fmxr(FPEXC, fpexc & ~FPEXC_EN);
10595 
10596- /*
10597- * Save the last VFP state on this CPU.
10598- */
10599- fmxr(FPEXC, fpexc | FPEXC_EN);
10600- vfp_save_state(last_VFP_context[cpu], fpexc);
10601- fmxr(FPEXC, fpexc);
10602+ /*
10603+ * Set the context to NULL to force a reload the next time
10604+ * the thread uses the VFP.
10605+ */
10606+ last_VFP_context[cpu] = NULL;
10607+ }
10608 
10609+#ifdef CONFIG_SMP
10610     /*
10611- * Set the context to NULL to force a reload the next time the thread
10612- * uses the VFP.
10613+ * For SMP we still have to take care of the case where the thread
10614+ * migrates to another CPU and then back to the original CPU on which
10615+ * the last VFP user is still the same thread. Mark the thread VFP
10616+ * state as belonging to a non-existent CPU so that the saved one will
10617+ * be reloaded in the above case.
10618      */
10619- last_VFP_context[cpu] = NULL;
10620-
10621-out:
10622+ thread->vfpstate.hard.cpu = NR_CPUS;
10623+#endif
10624     put_cpu();
10625 }
10626-#endif
10627 
10628 #include <linux/smp.h>
10629 
10630@@ -481,7 +534,7 @@ static int __init vfp_init(void)
10631          */
10632         elf_hwcap |= HWCAP_VFP;
10633 #ifdef CONFIG_VFPv3
10634- if (VFP_arch >= 3) {
10635+ if (VFP_arch >= 2) {
10636             elf_hwcap |= HWCAP_VFPv3;
10637 
10638             /*
10639--- /dev/null
10640+++ b/arch/arm/mach-cns3xxx/pcie.c
10641@@ -0,0 +1,360 @@
10642+/*******************************************************************************
10643+ *
10644+ * Copyright (c) 2008 Cavium Networks
10645+ *
10646+ * This file is free software; you can redistribute it and/or modify
10647+ * it under the terms of the GNU General Public License, Version 2, as
10648+ * published by the Free Software Foundation.
10649+ *
10650+ * This file is distributed in the hope that it will be useful,
10651+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
10652+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
10653+ * NONINFRINGEMENT. See the GNU General Public License for more details.
10654+ *
10655+ * You should have received a copy of the GNU General Public License
10656+ * along with this file; if not, write to the Free Software
10657+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
10658+ * visit http://www.gnu.org/licenses/.
10659+ *
10660+ * This file may also be available under a different license from Cavium.
10661+ * Contact Cavium Networks for more information
10662+ *
10663+ ******************************************************************************/
10664+
10665+#include <linux/kernel.h>
10666+#include <linux/pci.h>
10667+#include <linux/ptrace.h>
10668+#include <linux/slab.h>
10669+#include <linux/ioport.h>
10670+#include <linux/interrupt.h>
10671+#include <linux/spinlock.h>
10672+#include <linux/init.h>
10673+
10674+#include <mach/hardware.h>
10675+#include <asm/io.h>
10676+#include <asm/irq.h>
10677+#include <asm/system.h>
10678+#include <asm/mach/pci.h>
10679+#include <mach/pcie.h>
10680+#include <linux/proc_fs.h>
10681+#include <linux/delay.h>
10682+#include <asm/uaccess.h>
10683+#include <mach/pm.h>
10684+
10685+DEFINE_SPINLOCK(pci_config_lock);
10686+
10687+static int pcie_linked[2] = {0, 0}; // if 1, mean link ok.
10688+
10689+u32 cns3xxx_pcie0_irqs[2] = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, };
10690+u32 cns3xxx_pcie1_irqs[2] = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, };
10691+
10692+static u32 access_base[2][3] = {
10693+ { CNS3XXX_PCIE0_HOST_BASE_VIRT, CNS3XXX_PCIE0_CFG0_BASE_VIRT, CNS3XXX_PCIE0_CFG1_BASE_VIRT},
10694+ { CNS3XXX_PCIE1_HOST_BASE_VIRT, CNS3XXX_PCIE1_CFG0_BASE_VIRT, CNS3XXX_PCIE1_CFG1_BASE_VIRT},
10695+};
10696+
10697+static int cns3xxx_pci_cfg_base(struct pci_bus *bus,
10698+ unsigned int devfn, int where)
10699+{
10700+ int domain = pci_domain_nr(bus);
10701+ int slot = PCI_SLOT(devfn);
10702+ u32 base;
10703+
10704+ if ((!pcie_linked[domain]) && (bus->number || slot))
10705+ return 0;
10706+
10707+ if (!(bus->number)) {
10708+ if (slot > 1)
10709+ return 0;
10710+ // CFG0 Type
10711+ base = access_base[domain][slot];
10712+ } else {
10713+ // CFG1 Type
10714+ base = access_base[domain][2];
10715+ }
10716+ base += (((bus->number & 0xf) << 20)| (devfn << 12) | (where & 0xfc));
10717+ return base;
10718+}
10719+
10720+static int cns3xxx_pci_read_config(struct pci_bus *bus,
10721+ unsigned int devfn, int where, int size,
10722+ u32 * val)
10723+{
10724+ u32 v = 0xffffffff;
10725+ u32 base;
10726+ u32 mask = (0x1ull << (size * 8)) - 1;
10727+ int shift = (where % 4) * 8;
10728+
10729+ base = cns3xxx_pci_cfg_base(bus, devfn, where);
10730+ if (!base) {
10731+ *val = 0xFFFFFFFF;
10732+ return PCIBIOS_SUCCESSFUL;
10733+ }
10734+
10735+ v = __raw_readl(base);
10736+ if (bus->number == 0 && devfn == 0 &&
10737+ (where & 0xffc) == PCI_CLASS_REVISION) {
10738+ /* RC's class is 0xb, but Linux PCI driver needs 0x604 for a PCIe bridge. */
10739+ /* So we must dedicate the class code to 0x604 here */
10740+ v &= 0xff;
10741+ v |= (0x604 << 16);
10742+ }
10743+
10744+ *val = (v >> shift) & mask;
10745+ return PCIBIOS_SUCCESSFUL;
10746+}
10747+
10748+static int cns3xxx_pci_write_config(struct pci_bus *bus,
10749+ unsigned int devfn, int where, int size,
10750+ u32 val)
10751+{
10752+ u32 v;
10753+ u32 base;
10754+ u32 mask = (0x1ull << (size * 8)) - 1;
10755+ int shift = (where % 4) * 8;
10756+
10757+ base = cns3xxx_pci_cfg_base(bus, devfn, where);
10758+ if (!base)
10759+ return PCIBIOS_SUCCESSFUL;
10760+
10761+ v = __raw_readl(base);
10762+ v &= ~(mask << shift);
10763+ v |= (val & mask) << shift;
10764+ __raw_writel(v, base);
10765+
10766+ return PCIBIOS_SUCCESSFUL;
10767+}
10768+
10769+static struct pci_ops cns3xxx_pcie_ops = {
10770+ .read = cns3xxx_pci_read_config,
10771+ .write = cns3xxx_pci_write_config,
10772+};
10773+
10774+static struct resource cns3xxx_pcie0_io = {
10775+ .name = "PCIe0 I/O space",
10776+ .start = PCIE0_IO_SPACE_START,
10777+ .end = PCIE0_IO_SPACE_END,
10778+ .flags = IORESOURCE_IO,
10779+};
10780+
10781+static struct resource cns3xxx_pcie1_io = {
10782+ .name = "PCIe1 I/O space",
10783+ .start = PCIE1_IO_SPACE_START,
10784+ .end = PCIE1_IO_SPACE_END,
10785+ .flags = IORESOURCE_IO,
10786+};
10787+
10788+static struct resource cns3xxx_pcie0_mem = {
10789+ .name = "PCIe0 non-prefetchable",
10790+ .start = PCIE0_MEM_SPACE_START,
10791+ .end = PCIE0_MEM_SPACE_END,
10792+ .flags = IORESOURCE_MEM,
10793+};
10794+
10795+static struct resource cns3xxx_pcie1_mem = {
10796+ .name = "PCIe1 non-prefetchable",
10797+ .start = PCIE1_MEM_SPACE_START,
10798+ .end = PCIE1_MEM_SPACE_END,
10799+ .flags = IORESOURCE_MEM,
10800+};
10801+
10802+static int __init cns3xxx_pci_setup_resources(int nr, struct resource **resource)
10803+{
10804+ if(nr==0){
10805+ BUG_ON(request_resource(&iomem_resource, &cns3xxx_pcie0_io) ||
10806+ request_resource(&iomem_resource, &cns3xxx_pcie0_mem));
10807+ resource[0] = &cns3xxx_pcie0_io;
10808+ resource[1] = &cns3xxx_pcie0_mem;
10809+ }else{
10810+ BUG_ON(request_resource(&iomem_resource, &cns3xxx_pcie1_io) ||
10811+ request_resource(&iomem_resource, &cns3xxx_pcie1_mem));
10812+ resource[0] = &cns3xxx_pcie1_io;
10813+ resource[1] = &cns3xxx_pcie1_mem;
10814+ }
10815+ return 0;
10816+}
10817+
10818+int __init cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
10819+{
10820+ BUG_ON(cns3xxx_pci_setup_resources(sys->domain,sys->resource));
10821+ return 1;
10822+}
10823+
10824+struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
10825+{
10826+ struct pci_bus *ret;
10827+ ret = pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
10828+ pci_assign_unassigned_resources();
10829+ return ret;
10830+}
10831+
10832+/*
10833+ * CNS3XXX PCIe device don't support hotplugin, and we will check the link at start up.
10834+ *
10835+ */
10836+static void cns3xxx_pcie_check_link(int port)
10837+{
10838+
10839+ u32 reg;
10840+ u32 time;
10841+
10842+ time = jiffies; /* set the start time for the receive */
10843+ while (1) {
10844+ reg = __raw_readl( port == 0 ? CNS3XXX_PCIE0_PM_DEBUG : CNS3XXX_PCIE1_PM_DEBUG); /* check link up */
10845+ reg = __raw_readl( port == 0 ? CNS3XXX_PCIE0_PM_DEBUG : CNS3XXX_PCIE1_PM_DEBUG);
10846+ if (reg & 0x1) {
10847+ pcie_linked[port]++;
10848+ break;
10849+ } else if (time_after(jiffies, (unsigned long)(time + 50))) {
10850+ break;
10851+ }
10852+ }
10853+
10854+}
10855+
10856+static void cns3xxx_pcie_hw_init(int port){
10857+ struct pci_bus bus;
10858+ struct pci_sys_data sd;
10859+ u32 devfn = 0;
10860+ u8 pri_bus, sec_bus, sub_bus;
10861+ u8 cp, u8tmp;
10862+ u16 u16tmp,pos,dc;
10863+ u32 mem_base, host_base, io_base, cfg0_base;
10864+
10865+ bus.number = 0;
10866+ bus.ops = &cns3xxx_pcie_ops;
10867+ sd.domain = port;
10868+ bus.sysdata = &sd;
10869+
10870+ mem_base = ( port == 0 ? CNS3XXX_PCIE0_MEM_BASE : CNS3XXX_PCIE1_MEM_BASE );
10871+ mem_base = mem_base >> 16;
10872+
10873+ io_base = ( port == 0 ? CNS3XXX_PCIE0_IO_BASE : CNS3XXX_PCIE1_IO_BASE );
10874+ io_base = io_base >> 16;
10875+
10876+ host_base = ( port == 0 ? CNS3XXX_PCIE0_HOST_BASE_VIRT : CNS3XXX_PCIE1_HOST_BASE_VIRT );
10877+ host_base = ( host_base -1 ) >> 16;
10878+
10879+ cfg0_base = ( port == 0 ? CNS3XXX_PCIE0_CFG0_BASE_VIRT : CNS3XXX_PCIE1_CFG0_BASE_VIRT );
10880+ cfg0_base = ( cfg0_base -1 ) >> 16;
10881+
10882+ pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
10883+ pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
10884+ pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
10885+
10886+ pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &pri_bus);
10887+ pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &sec_bus);
10888+ pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &sub_bus);
10889+
10890+ pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
10891+ pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
10892+ pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
10893+ pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
10894+
10895+ pci_bus_read_config_byte(&bus, devfn, PCI_CAPABILITY_LIST, &cp);
10896+ while (cp != 0) {
10897+ pci_bus_read_config_byte(&bus, devfn, cp, &u8tmp);
10898+ // Read Next ID
10899+ pci_bus_read_config_word(&bus, devfn, cp, &u16tmp);
10900+ cp = (u16tmp & 0xFF00) >> 8;
10901+ }
10902+
10903+ /* Modify device's Max_Read_Request size */
10904+ devfn = PCI_DEVFN(1,0);
10905+ if (!pcie_linked[port])
10906+ return;
10907+
10908+ pci_bus_read_config_byte(&bus, devfn, PCI_CAPABILITY_LIST, &cp);
10909+ while (cp != 0) {
10910+ pci_bus_read_config_byte(&bus, devfn, cp, &u8tmp);
10911+ // Read Next ID
10912+ pci_bus_read_config_word(&bus, devfn, cp, &u16tmp);
10913+ cp = (u16tmp & 0xFF00) >> 8;
10914+ }
10915+
10916+ /* Set Device Max_Read_Request_Size to 128 byte */
10917+ pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
10918+ pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
10919+ dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
10920+ pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
10921+ pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
10922+
10923+ if (!port) {
10924+ /* Disable PCIe0 Interrupt Mask INTA to INTD */
10925+ __raw_writel(~0x3FFF, CNS3XXX_MISC_BASE_VIRT + 0x978);
10926+ } else {
10927+ /* Disable PCIe1 Interrupt Mask INTA to INTD */
10928+ __raw_writel(~0x3FFF, CNS3XXX_MISC_BASE_VIRT + 0xA78);
10929+ }
10930+}
10931+
10932+
10933+void __init cns3xxx_pcie0_preinit(void)
10934+{
10935+ cns3xxx_pcie_check_link(0);
10936+ cns3xxx_pcie_hw_init(0);
10937+}
10938+
10939+void __init cns3xxx_pcie1_preinit(void)
10940+{
10941+ cns3xxx_pcie_check_link(1);
10942+ cns3xxx_pcie_hw_init(1);
10943+}
10944+
10945+/*
10946+ * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
10947+ */
10948+
10949+static int __init cns3xxx_pcie0_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
10950+{
10951+ return cns3xxx_pcie0_irqs[slot];
10952+}
10953+
10954+static int __init cns3xxx_pcie1_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
10955+{
10956+ return cns3xxx_pcie1_irqs[slot];
10957+}
10958+
10959+static struct hw_pci cns3xxx_pcie[2] __initdata = {
10960+ {
10961+ .swizzle = pci_std_swizzle,
10962+ .map_irq = cns3xxx_pcie0_map_irq,
10963+ .nr_controllers = 1,
10964+ .nr_domains = 0,
10965+ .setup = cns3xxx_pci_setup,
10966+ .scan = cns3xxx_pci_scan_bus,
10967+ .preinit = cns3xxx_pcie0_preinit,
10968+ },
10969+ {
10970+ .swizzle = pci_std_swizzle,
10971+ .map_irq = cns3xxx_pcie1_map_irq,
10972+ .nr_controllers = 1,
10973+ .nr_domains = 1,
10974+ .setup = cns3xxx_pci_setup,
10975+ .scan = cns3xxx_pci_scan_bus,
10976+ .preinit = cns3xxx_pcie1_preinit,
10977+ }
10978+};
10979+
10980+static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
10981+ struct pt_regs *regs)
10982+{
10983+ if (fsr & (1 << 10))
10984+ regs->ARM_pc += 4;
10985+ return 0;
10986+}
10987+
10988+//extern void pci_common_init(struct hw_pci *);
10989+int cns3xxx_pcie_init(u8 ports)
10990+{
10991+ hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, "imprecise external abort");
10992+
10993+ if (ports & 0x1)
10994+ pci_common_init(&cns3xxx_pcie[0]);
10995+ if (ports & 0x2)
10996+ pci_common_init(&cns3xxx_pcie[1]);
10997+
10998+ return 0;
10999+}
11000+
11001+//device_initcall(cns3xxx_pcie_init);
11002

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive