| 1 | /*- |
| 2 | * The linux port of this code done by David McCullough |
| 3 | * Copyright (C) 2004-2010 David McCullough <david_mccullough@mcafee.com> |
| 4 | * The license and original author are listed below. |
| 5 | * |
| 6 | * Copyright (c) 2003 Sam Leffler, Errno Consulting |
| 7 | * Copyright (c) 2003 Global Technology Associates, Inc. |
| 8 | * All rights reserved. |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer in the |
| 17 | * documentation and/or other materials provided with the distribution. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 29 | * SUCH DAMAGE. |
| 30 | * |
| 31 | * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ |
| 32 | */ |
| 33 | #ifndef _SAFE_SAFEVAR_H_ |
| 34 | #define _SAFE_SAFEVAR_H_ |
| 35 | |
| 36 | /* Maximum queue length */ |
| 37 | #ifndef SAFE_MAX_NQUEUE |
| 38 | #define SAFE_MAX_NQUEUE 60 |
| 39 | #endif |
| 40 | |
| 41 | #define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ |
| 42 | #define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ |
| 43 | #define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ |
| 44 | #define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ |
| 45 | #define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ |
| 46 | /* total src+dst particle descriptors */ |
| 47 | #define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) |
| 48 | #define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) |
| 49 | |
| 50 | #define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ |
| 51 | |
| 52 | #define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) |
| 53 | #define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) |
| 54 | #define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) |
| 55 | |
| 56 | #define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ |
| 57 | #define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ |
| 58 | #define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ |
| 59 | |
| 60 | #ifdef __KERNEL__ |
| 61 | /* |
| 62 | * State associated with the allocation of each chunk |
| 63 | * of memory setup for DMA. |
| 64 | */ |
| 65 | struct safe_dma_alloc { |
| 66 | dma_addr_t dma_paddr; |
| 67 | void *dma_vaddr; |
| 68 | }; |
| 69 | |
| 70 | /* |
| 71 | * Cryptographic operand state. One of these exists for each |
| 72 | * source and destination operand passed in from the crypto |
| 73 | * subsystem. When possible source and destination operands |
| 74 | * refer to the same memory. More often they are distinct. |
| 75 | * We track the virtual address of each operand as well as |
| 76 | * where each is mapped for DMA. |
| 77 | */ |
| 78 | struct safe_operand { |
| 79 | union { |
| 80 | struct sk_buff *skb; |
| 81 | struct uio *io; |
| 82 | } u; |
| 83 | void *map; |
| 84 | int mapsize; /* total number of bytes in segs */ |
| 85 | struct { |
| 86 | dma_addr_t ds_addr; |
| 87 | int ds_len; |
| 88 | int ds_tlen; |
| 89 | } segs[SAFE_MAX_PART]; |
| 90 | int nsegs; |
| 91 | }; |
| 92 | |
| 93 | /* |
| 94 | * Packet engine ring entry and cryptographic operation state. |
| 95 | * The packet engine requires a ring of descriptors that contain |
| 96 | * pointers to various cryptographic state. However the ring |
| 97 | * configuration register allows you to specify an arbitrary size |
| 98 | * for ring entries. We use this feature to collect most of the |
| 99 | * state for each cryptographic request into one spot. Other than |
| 100 | * ring entries only the ``particle descriptors'' (scatter/gather |
| 101 | * lists) and the actual operand data are kept separate. The |
| 102 | * particle descriptors must also be organized in rings. The |
| 103 | * operand data can be located aribtrarily (modulo alignment constraints). |
| 104 | * |
| 105 | * Note that the descriptor ring is mapped onto the PCI bus so |
| 106 | * the hardware can DMA data. This means the entire ring must be |
| 107 | * contiguous. |
| 108 | */ |
| 109 | struct safe_ringentry { |
| 110 | struct safe_desc re_desc; /* command descriptor */ |
| 111 | struct safe_sarec re_sa; /* SA record */ |
| 112 | struct safe_sastate re_sastate; /* SA state record */ |
| 113 | |
| 114 | struct cryptop *re_crp; /* crypto operation */ |
| 115 | |
| 116 | struct safe_operand re_src; /* source operand */ |
| 117 | struct safe_operand re_dst; /* destination operand */ |
| 118 | |
| 119 | int re_sesn; /* crypto session ID */ |
| 120 | int re_flags; |
| 121 | #define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ |
| 122 | #define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ |
| 123 | }; |
| 124 | |
| 125 | #define re_src_skb re_src.u.skb |
| 126 | #define re_src_io re_src.u.io |
| 127 | #define re_src_map re_src.map |
| 128 | #define re_src_nsegs re_src.nsegs |
| 129 | #define re_src_segs re_src.segs |
| 130 | #define re_src_mapsize re_src.mapsize |
| 131 | |
| 132 | #define re_dst_skb re_dst.u.skb |
| 133 | #define re_dst_io re_dst.u.io |
| 134 | #define re_dst_map re_dst.map |
| 135 | #define re_dst_nsegs re_dst.nsegs |
| 136 | #define re_dst_segs re_dst.segs |
| 137 | #define re_dst_mapsize re_dst.mapsize |
| 138 | |
| 139 | struct rndstate_test; |
| 140 | |
| 141 | struct safe_session { |
| 142 | u_int32_t ses_used; |
| 143 | u_int32_t ses_klen; /* key length in bits */ |
| 144 | u_int32_t ses_key[8]; /* DES/3DES/AES key */ |
| 145 | u_int32_t ses_mlen; /* hmac length in bytes */ |
| 146 | u_int32_t ses_hminner[5]; /* hmac inner state */ |
| 147 | u_int32_t ses_hmouter[5]; /* hmac outer state */ |
| 148 | u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ |
| 149 | }; |
| 150 | |
| 151 | struct safe_pkq { |
| 152 | struct list_head pkq_list; |
| 153 | struct cryptkop *pkq_krp; |
| 154 | }; |
| 155 | |
| 156 | struct safe_softc { |
| 157 | softc_device_decl sc_dev; |
| 158 | u32 sc_irq; |
| 159 | |
| 160 | struct pci_dev *sc_pcidev; |
| 161 | ocf_iomem_t sc_base_addr; |
| 162 | |
| 163 | u_int sc_chiprev; /* major/minor chip revision */ |
| 164 | int sc_flags; /* device specific flags */ |
| 165 | #define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ |
| 166 | #define SAFE_FLAGS_RNG 0x02 /* hardware rng */ |
| 167 | int sc_suspended; |
| 168 | int sc_needwakeup; /* notify crypto layer */ |
| 169 | int32_t sc_cid; /* crypto tag */ |
| 170 | |
| 171 | struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ |
| 172 | struct safe_ringentry *sc_ring; /* PE ring */ |
| 173 | struct safe_ringentry *sc_ringtop; /* PE ring top */ |
| 174 | struct safe_ringentry *sc_front; /* next free entry */ |
| 175 | struct safe_ringentry *sc_back; /* next pending entry */ |
| 176 | int sc_nqchip; /* # passed to chip */ |
| 177 | spinlock_t sc_ringmtx; /* PE ring lock */ |
| 178 | struct safe_pdesc *sc_spring; /* src particle ring */ |
| 179 | struct safe_pdesc *sc_springtop; /* src particle ring top */ |
| 180 | struct safe_pdesc *sc_spfree; /* next free src particle */ |
| 181 | struct safe_dma_alloc sc_spalloc; /* src particle ring state */ |
| 182 | struct safe_pdesc *sc_dpring; /* dest particle ring */ |
| 183 | struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ |
| 184 | struct safe_pdesc *sc_dpfree; /* next free dest particle */ |
| 185 | struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ |
| 186 | int sc_nsessions; /* # of sessions */ |
| 187 | struct safe_session *sc_sessions; /* sessions */ |
| 188 | |
| 189 | struct timer_list sc_pkto; /* PK polling */ |
| 190 | spinlock_t sc_pkmtx; /* PK lock */ |
| 191 | struct list_head sc_pkq; /* queue of PK requests */ |
| 192 | struct safe_pkq *sc_pkq_cur; /* current processing request */ |
| 193 | u_int32_t sc_pk_reslen, sc_pk_resoff; |
| 194 | |
| 195 | int sc_max_dsize; /* maximum safe DMA size */ |
| 196 | }; |
| 197 | #endif /* __KERNEL__ */ |
| 198 | |
| 199 | struct safe_stats { |
| 200 | u_int64_t st_ibytes; |
| 201 | u_int64_t st_obytes; |
| 202 | u_int32_t st_ipackets; |
| 203 | u_int32_t st_opackets; |
| 204 | u_int32_t st_invalid; /* invalid argument */ |
| 205 | u_int32_t st_badsession; /* invalid session id */ |
| 206 | u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ |
| 207 | u_int32_t st_nodesc; /* op submitted w/o descriptors */ |
| 208 | u_int32_t st_badalg; /* unsupported algorithm */ |
| 209 | u_int32_t st_ringfull; /* PE descriptor ring full */ |
| 210 | u_int32_t st_peoperr; /* PE marked error */ |
| 211 | u_int32_t st_dmaerr; /* PE DMA error */ |
| 212 | u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ |
| 213 | u_int32_t st_skipmismatch; /* enc part begins before auth part */ |
| 214 | u_int32_t st_lenmismatch; /* enc length different auth length */ |
| 215 | u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ |
| 216 | u_int32_t st_cofftoobig; /* crypto offset > 255 words */ |
| 217 | u_int32_t st_iovmisaligned; /* iov op not aligned */ |
| 218 | u_int32_t st_iovnotuniform; /* iov op not suitable */ |
| 219 | u_int32_t st_unaligned; /* unaligned src caused copy */ |
| 220 | u_int32_t st_notuniform; /* non-uniform src caused copy */ |
| 221 | u_int32_t st_nomap; /* bus_dmamap_create failed */ |
| 222 | u_int32_t st_noload; /* bus_dmamap_load_* failed */ |
| 223 | u_int32_t st_nombuf; /* MGET* failed */ |
| 224 | u_int32_t st_nomcl; /* MCLGET* failed */ |
| 225 | u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ |
| 226 | u_int32_t st_rng; /* RNG requests */ |
| 227 | u_int32_t st_rngalarm; /* RNG alarm requests */ |
| 228 | u_int32_t st_noicvcopy; /* ICV data copies suppressed */ |
| 229 | }; |
| 230 | #endif /* _SAFE_SAFEVAR_H_ */ |
| 231 | |
