| 1 | --- a/drivers/ssb/driver_pcicore.c |
| 2 | +++ b/drivers/ssb/driver_pcicore.c |
| 3 | @@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s |
| 4 | pcicore_write32(pc, mdio_control, 0); |
| 5 | } |
| 6 | |
| 7 | -static void ssb_broadcast_value(struct ssb_device *dev, |
| 8 | - u32 address, u32 data) |
| 9 | -{ |
| 10 | - /* This is used for both, PCI and ChipCommon core, so be careful. */ |
| 11 | - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); |
| 12 | - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); |
| 13 | - |
| 14 | - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); |
| 15 | - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ |
| 16 | - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); |
| 17 | - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ |
| 18 | -} |
| 19 | - |
| 20 | -static void ssb_commit_settings(struct ssb_bus *bus) |
| 21 | -{ |
| 22 | - struct ssb_device *dev; |
| 23 | - |
| 24 | - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; |
| 25 | - if (WARN_ON(!dev)) |
| 26 | - return; |
| 27 | - /* This forces an update of the cached registers. */ |
| 28 | - ssb_broadcast_value(dev, 0xFD8, 0); |
| 29 | -} |
| 30 | - |
| 31 | int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, |
| 32 | struct ssb_device *dev) |
| 33 | { |
| 34 | --- a/drivers/ssb/main.c |
| 35 | +++ b/drivers/ssb/main.c |
| 36 | @@ -1406,6 +1406,31 @@ error: |
| 37 | } |
| 38 | EXPORT_SYMBOL(ssb_bus_powerup); |
| 39 | |
| 40 | +static void ssb_broadcast_value(struct ssb_device *dev, |
| 41 | + u32 address, u32 data) |
| 42 | +{ |
| 43 | + /* This is used for both, PCI and ChipCommon core, so be careful. */ |
| 44 | + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); |
| 45 | + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); |
| 46 | + |
| 47 | + ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); |
| 48 | + ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ |
| 49 | + ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); |
| 50 | + ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ |
| 51 | +} |
| 52 | + |
| 53 | +void ssb_commit_settings(struct ssb_bus *bus) |
| 54 | +{ |
| 55 | + struct ssb_device *dev; |
| 56 | + |
| 57 | + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; |
| 58 | + if (WARN_ON(!dev)) |
| 59 | + return; |
| 60 | + /* This forces an update of the cached registers. */ |
| 61 | + ssb_broadcast_value(dev, 0xFD8, 0); |
| 62 | +} |
| 63 | +EXPORT_SYMBOL(ssb_commit_settings); |
| 64 | + |
| 65 | u32 ssb_admatch_base(u32 adm) |
| 66 | { |
| 67 | u32 base = 0; |
| 68 | --- a/include/linux/ssb/ssb.h |
| 69 | +++ b/include/linux/ssb/ssb.h |
| 70 | @@ -675,6 +675,7 @@ extern int ssb_bus_may_powerdown(struct |
| 71 | * Otherwise static always-on powercontrol will be used. */ |
| 72 | extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl); |
| 73 | |
| 74 | +extern void ssb_commit_settings(struct ssb_bus *bus); |
| 75 | |
| 76 | /* Various helper functions */ |
| 77 | extern u32 ssb_admatch_base(u32 adm); |
| 78 | |
