| 1 | From 3924996bab2845bdf9a9d16ff7c20445de1ab55d Mon Sep 17 00:00:00 2001 |
| 2 | From: Nicolas Pitre <nico@fluxnic.net> |
| 3 | Date: Thu, 21 Oct 2010 15:48:33 -0400 |
| 4 | Subject: [PATCH] [ARM] Kirkwood: restrict the scope of the PCIe reset workaround |
| 5 | |
| 6 | Commit 21f0ba90a447 "orion/kirkwood: reset PCIe unit on boot" made the |
| 7 | reset of the PCIe unit unconditional. While this may fix problems on some |
| 8 | targets, this also causes problems on other targets. |
| 9 | |
| 10 | Saeed Bishara <saeed@marvell.com> said about the original problem: "We |
| 11 | couln't pinpoint the root cause of this issue, actually we failed to |
| 12 | reproduce that issue." |
| 13 | |
| 14 | So let's restrict the reset of the PCIe unit only to the target where |
| 15 | the original problem was observed. |
| 16 | |
| 17 | Signed-off-by: Nicolas Pitre <nico@fluxnic.net> |
| 18 | --- |
| 19 | arch/arm/mach-kirkwood/ts41x-setup.c | 14 +++++++++++++- |
| 20 | arch/arm/plat-orion/include/plat/pcie.h | 3 +++ |
| 21 | arch/arm/plat-orion/pcie.c | 5 ----- |
| 22 | 3 files changed, 16 insertions(+), 6 deletions(-) |
| 23 | |
| 24 | --- a/arch/arm/mach-kirkwood/ts41x-setup.c |
| 25 | +++ b/arch/arm/mach-kirkwood/ts41x-setup.c |
| 26 | @@ -27,6 +27,10 @@ |
| 27 | #include "mpp.h" |
| 28 | #include "tsx1x-common.h" |
| 29 | |
| 30 | +/* for the PCIe reset workaround */ |
| 31 | +#include <plat/pcie.h> |
| 32 | + |
| 33 | + |
| 34 | #define QNAP_TS41X_JUMPER_JP1 45 |
| 35 | |
| 36 | static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { |
| 37 | @@ -140,8 +144,16 @@ static void __init qnap_ts41x_init(void) |
| 38 | |
| 39 | static int __init ts41x_pci_init(void) |
| 40 | { |
| 41 | - if (machine_is_ts41x()) |
| 42 | + if (machine_is_ts41x()) { |
| 43 | + /* |
| 44 | + * Without this explicit reset, the PCIe SATA controller |
| 45 | + * (Marvell 88sx7042/sata_mv) is known to stop working |
| 46 | + * after a few minutes. |
| 47 | + */ |
| 48 | + orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE); |
| 49 | + |
| 50 | kirkwood_pcie_init(KW_PCIE0); |
| 51 | + } |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | --- a/arch/arm/plat-orion/include/plat/pcie.h |
| 56 | +++ b/arch/arm/plat-orion/include/plat/pcie.h |
| 57 | @@ -11,12 +11,15 @@ |
| 58 | #ifndef __PLAT_PCIE_H |
| 59 | #define __PLAT_PCIE_H |
| 60 | |
| 61 | +struct pci_bus; |
| 62 | + |
| 63 | u32 orion_pcie_dev_id(void __iomem *base); |
| 64 | u32 orion_pcie_rev(void __iomem *base); |
| 65 | int orion_pcie_link_up(void __iomem *base); |
| 66 | int orion_pcie_x4_mode(void __iomem *base); |
| 67 | int orion_pcie_get_local_bus_nr(void __iomem *base); |
| 68 | void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); |
| 69 | +void orion_pcie_reset(void __iomem *base); |
| 70 | void orion_pcie_setup(void __iomem *base, |
| 71 | struct mbus_dram_target_info *dram); |
| 72 | int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, |
| 73 | --- a/arch/arm/plat-orion/pcie.c |
| 74 | +++ b/arch/arm/plat-orion/pcie.c |
| 75 | @@ -182,11 +182,6 @@ void __init orion_pcie_setup(void __iome |
| 76 | u32 mask; |
| 77 | |
| 78 | /* |
| 79 | - * soft reset PCIe unit |
| 80 | - */ |
| 81 | - orion_pcie_reset(base); |
| 82 | - |
| 83 | - /* |
| 84 | * Point PCIe unit MBUS decode windows to DRAM space. |
| 85 | */ |
| 86 | orion_pcie_setup_wins(base, dram); |
| 87 | |
