| 1 | --- a/drivers/ssb/main.c |
| 2 | +++ b/drivers/ssb/main.c |
| 3 | @@ -383,6 +383,35 @@ static int ssb_device_uevent(struct devi |
| 4 | ssb_dev->id.revision); |
| 5 | } |
| 6 | |
| 7 | +#define ssb_config_attr(attrib, field, format_string) \ |
| 8 | +static ssize_t \ |
| 9 | +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ |
| 10 | +{ \ |
| 11 | + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ |
| 12 | +} |
| 13 | + |
| 14 | +ssb_config_attr(core_num, core_index, "%u\n") |
| 15 | +ssb_config_attr(coreid, id.coreid, "0x%04x\n") |
| 16 | +ssb_config_attr(vendor, id.vendor, "0x%04x\n") |
| 17 | +ssb_config_attr(revision, id.revision, "%u\n") |
| 18 | +ssb_config_attr(irq, irq, "%u\n") |
| 19 | +static ssize_t |
| 20 | +name_show(struct device *dev, struct device_attribute *attr, char *buf) |
| 21 | +{ |
| 22 | + return sprintf(buf, "%s\n", |
| 23 | + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); |
| 24 | +} |
| 25 | + |
| 26 | +static struct device_attribute ssb_device_attrs[] = { |
| 27 | + __ATTR_RO(name), |
| 28 | + __ATTR_RO(core_num), |
| 29 | + __ATTR_RO(coreid), |
| 30 | + __ATTR_RO(vendor), |
| 31 | + __ATTR_RO(revision), |
| 32 | + __ATTR_RO(irq), |
| 33 | + __ATTR_NULL, |
| 34 | +}; |
| 35 | + |
| 36 | static struct bus_type ssb_bustype = { |
| 37 | .name = "ssb", |
| 38 | .match = ssb_bus_match, |
| 39 | @@ -392,6 +421,7 @@ static struct bus_type ssb_bustype = { |
| 40 | .suspend = ssb_device_suspend, |
| 41 | .resume = ssb_device_resume, |
| 42 | .uevent = ssb_device_uevent, |
| 43 | + .dev_attrs = ssb_device_attrs, |
| 44 | }; |
| 45 | |
| 46 | static void ssb_buses_lock(void) |
| 47 | @@ -1162,10 +1192,10 @@ void ssb_device_enable(struct ssb_device |
| 48 | } |
| 49 | EXPORT_SYMBOL(ssb_device_enable); |
| 50 | |
| 51 | -/* Wait for a bit in a register to get set or unset. |
| 52 | +/* Wait for bitmask in a register to get set or cleared. |
| 53 | * timeout is in units of ten-microseconds */ |
| 54 | -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask, |
| 55 | - int timeout, int set) |
| 56 | +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, |
| 57 | + int timeout, int set) |
| 58 | { |
| 59 | int i; |
| 60 | u32 val; |
| 61 | @@ -1173,7 +1203,7 @@ static int ssb_wait_bit(struct ssb_devic |
| 62 | for (i = 0; i < timeout; i++) { |
| 63 | val = ssb_read32(dev, reg); |
| 64 | if (set) { |
| 65 | - if (val & bitmask) |
| 66 | + if ((val & bitmask) == bitmask) |
| 67 | return 0; |
| 68 | } else { |
| 69 | if (!(val & bitmask)) |
| 70 | @@ -1190,20 +1220,38 @@ static int ssb_wait_bit(struct ssb_devic |
| 71 | |
| 72 | void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) |
| 73 | { |
| 74 | - u32 reject; |
| 75 | + u32 reject, val; |
| 76 | |
| 77 | if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) |
| 78 | return; |
| 79 | |
| 80 | reject = ssb_tmslow_reject_bitmask(dev); |
| 81 | - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); |
| 82 | - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1); |
| 83 | - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); |
| 84 | - ssb_write32(dev, SSB_TMSLOW, |
| 85 | - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | |
| 86 | - reject | SSB_TMSLOW_RESET | |
| 87 | - core_specific_flags); |
| 88 | - ssb_flush_tmslow(dev); |
| 89 | + |
| 90 | + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { |
| 91 | + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); |
| 92 | + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); |
| 93 | + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); |
| 94 | + |
| 95 | + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { |
| 96 | + val = ssb_read32(dev, SSB_IMSTATE); |
| 97 | + val |= SSB_IMSTATE_REJECT; |
| 98 | + ssb_write32(dev, SSB_IMSTATE, val); |
| 99 | + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, |
| 100 | + 0); |
| 101 | + } |
| 102 | + |
| 103 | + ssb_write32(dev, SSB_TMSLOW, |
| 104 | + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | |
| 105 | + reject | SSB_TMSLOW_RESET | |
| 106 | + core_specific_flags); |
| 107 | + ssb_flush_tmslow(dev); |
| 108 | + |
| 109 | + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { |
| 110 | + val = ssb_read32(dev, SSB_IMSTATE); |
| 111 | + val &= ~SSB_IMSTATE_REJECT; |
| 112 | + ssb_write32(dev, SSB_IMSTATE, val); |
| 113 | + } |
| 114 | + } |
| 115 | |
| 116 | ssb_write32(dev, SSB_TMSLOW, |
| 117 | reject | SSB_TMSLOW_RESET | |
| 118 | --- a/drivers/ssb/pci.c |
| 119 | +++ b/drivers/ssb/pci.c |
| 120 | @@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss |
| 121 | out->antenna_gain.ghz5.a3 = gain; |
| 122 | } |
| 123 | |
| 124 | +/* Revs 4 5 and 8 have partially shared layout */ |
| 125 | +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in) |
| 126 | +{ |
| 127 | + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, |
| 128 | + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT); |
| 129 | + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, |
| 130 | + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT); |
| 131 | + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, |
| 132 | + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT); |
| 133 | + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, |
| 134 | + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT); |
| 135 | + |
| 136 | + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, |
| 137 | + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT); |
| 138 | + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, |
| 139 | + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT); |
| 140 | + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, |
| 141 | + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT); |
| 142 | + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, |
| 143 | + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT); |
| 144 | + |
| 145 | + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, |
| 146 | + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT); |
| 147 | + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, |
| 148 | + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT); |
| 149 | + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, |
| 150 | + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT); |
| 151 | + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, |
| 152 | + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT); |
| 153 | + |
| 154 | + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, |
| 155 | + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT); |
| 156 | + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, |
| 157 | + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT); |
| 158 | + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, |
| 159 | + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT); |
| 160 | + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, |
| 161 | + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT); |
| 162 | +} |
| 163 | + |
| 164 | static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) |
| 165 | { |
| 166 | int i; |
| 167 | @@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb |
| 168 | SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0); |
| 169 | SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0); |
| 170 | SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0); |
| 171 | + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0); |
| 172 | + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0); |
| 173 | } else { |
| 174 | SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0); |
| 175 | SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0); |
| 176 | SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0); |
| 177 | + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0); |
| 178 | + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0); |
| 179 | } |
| 180 | SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A, |
| 181 | SSB_SPROM4_ANTAVAIL_A_SHIFT); |
| 182 | @@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb |
| 183 | memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, |
| 184 | sizeof(out->antenna_gain.ghz5)); |
| 185 | |
| 186 | + sprom_extract_r458(out, in); |
| 187 | + |
| 188 | /* TODO - get remaining rev 4 stuff needed */ |
| 189 | } |
| 190 | |
| 191 | @@ -561,6 +607,8 @@ static void sprom_extract_r8(struct ssb_ |
| 192 | memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, |
| 193 | sizeof(out->antenna_gain.ghz5)); |
| 194 | |
| 195 | + sprom_extract_r458(out, in); |
| 196 | + |
| 197 | /* TODO - get remaining rev 8 stuff needed */ |
| 198 | } |
| 199 | |
| 200 | @@ -573,37 +621,34 @@ static int sprom_extract(struct ssb_bus |
| 201 | ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); |
| 202 | memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ |
| 203 | memset(out->et1mac, 0xFF, 6); |
| 204 | + |
| 205 | if ((bus->chip_id & 0xFF00) == 0x4400) { |
| 206 | /* Workaround: The BCM44XX chip has a stupid revision |
| 207 | * number stored in the SPROM. |
| 208 | * Always extract r1. */ |
| 209 | out->revision = 1; |
| 210 | + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision); |
| 211 | + } |
| 212 | + |
| 213 | + switch (out->revision) { |
| 214 | + case 1: |
| 215 | + case 2: |
| 216 | + case 3: |
| 217 | sprom_extract_r123(out, in); |
| 218 | - } else if (bus->chip_id == 0x4321) { |
| 219 | - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */ |
| 220 | - out->revision = 4; |
| 221 | + break; |
| 222 | + case 4: |
| 223 | + case 5: |
| 224 | sprom_extract_r45(out, in); |
| 225 | - } else { |
| 226 | - switch (out->revision) { |
| 227 | - case 1: |
| 228 | - case 2: |
| 229 | - case 3: |
| 230 | - sprom_extract_r123(out, in); |
| 231 | - break; |
| 232 | - case 4: |
| 233 | - case 5: |
| 234 | - sprom_extract_r45(out, in); |
| 235 | - break; |
| 236 | - case 8: |
| 237 | - sprom_extract_r8(out, in); |
| 238 | - break; |
| 239 | - default: |
| 240 | - ssb_printk(KERN_WARNING PFX "Unsupported SPROM" |
| 241 | - " revision %d detected. Will extract" |
| 242 | - " v1\n", out->revision); |
| 243 | - out->revision = 1; |
| 244 | - sprom_extract_r123(out, in); |
| 245 | - } |
| 246 | + break; |
| 247 | + case 8: |
| 248 | + sprom_extract_r8(out, in); |
| 249 | + break; |
| 250 | + default: |
| 251 | + ssb_printk(KERN_WARNING PFX "Unsupported SPROM" |
| 252 | + " revision %d detected. Will extract" |
| 253 | + " v1\n", out->revision); |
| 254 | + out->revision = 1; |
| 255 | + sprom_extract_r123(out, in); |
| 256 | } |
| 257 | |
| 258 | if (out->boardflags_lo == 0xFFFF) |
| 259 | @@ -618,7 +663,7 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 260 | struct ssb_sprom *sprom) |
| 261 | { |
| 262 | const struct ssb_sprom *fallback; |
| 263 | - int err = -ENOMEM; |
| 264 | + int err; |
| 265 | u16 *buf; |
| 266 | |
| 267 | if (!ssb_is_sprom_available(bus)) { |
| 268 | @@ -645,7 +690,7 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 269 | |
| 270 | buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); |
| 271 | if (!buf) |
| 272 | - goto out; |
| 273 | + return -ENOMEM; |
| 274 | bus->sprom_size = SSB_SPROMSIZE_WORDS_R123; |
| 275 | sprom_do_read(bus, buf); |
| 276 | err = sprom_check_crc(buf, bus->sprom_size); |
| 277 | @@ -655,7 +700,7 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 278 | buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), |
| 279 | GFP_KERNEL); |
| 280 | if (!buf) |
| 281 | - goto out; |
| 282 | + return -ENOMEM; |
| 283 | bus->sprom_size = SSB_SPROMSIZE_WORDS_R4; |
| 284 | sprom_do_read(bus, buf); |
| 285 | err = sprom_check_crc(buf, bus->sprom_size); |
| 286 | @@ -677,7 +722,6 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 287 | |
| 288 | out_free: |
| 289 | kfree(buf); |
| 290 | -out: |
| 291 | return err; |
| 292 | } |
| 293 | |
| 294 | --- a/drivers/ssb/pcihost_wrapper.c |
| 295 | +++ b/drivers/ssb/pcihost_wrapper.c |
| 296 | @@ -59,6 +59,7 @@ static int ssb_pcihost_probe(struct pci_ |
| 297 | struct ssb_bus *ssb; |
| 298 | int err = -ENOMEM; |
| 299 | const char *name; |
| 300 | + u32 val; |
| 301 | |
| 302 | ssb = kzalloc(sizeof(*ssb), GFP_KERNEL); |
| 303 | if (!ssb) |
| 304 | @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_ |
| 305 | goto err_pci_disable; |
| 306 | pci_set_master(dev); |
| 307 | |
| 308 | + /* Disable the RETRY_TIMEOUT register (0x41) to keep |
| 309 | + * PCI Tx retries from interfering with C3 CPU state */ |
| 310 | + pci_read_config_dword(dev, 0x40, &val); |
| 311 | + if ((val & 0x0000ff00) != 0) |
| 312 | + pci_write_config_dword(dev, 0x40, val & 0xffff00ff); |
| 313 | + |
| 314 | err = ssb_bus_pcibus_register(ssb, dev); |
| 315 | if (err) |
| 316 | goto err_pci_release_regions; |
| 317 | --- a/drivers/ssb/scan.c |
| 318 | +++ b/drivers/ssb/scan.c |
| 319 | @@ -405,10 +405,10 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 320 | /* Ignore PCI cores on PCI-E cards. |
| 321 | * Ignore PCI-E cores on PCI cards. */ |
| 322 | if (dev->id.coreid == SSB_DEV_PCI) { |
| 323 | - if (bus->host_pci->is_pcie) |
| 324 | + if (pci_is_pcie(bus->host_pci)) |
| 325 | continue; |
| 326 | } else { |
| 327 | - if (!bus->host_pci->is_pcie) |
| 328 | + if (!pci_is_pcie(bus->host_pci)) |
| 329 | continue; |
| 330 | } |
| 331 | } |
| 332 | @@ -420,6 +420,16 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 333 | bus->pcicore.dev = dev; |
| 334 | #endif /* CONFIG_SSB_DRIVER_PCICORE */ |
| 335 | break; |
| 336 | + case SSB_DEV_ETHERNET: |
| 337 | + if (bus->bustype == SSB_BUSTYPE_PCI) { |
| 338 | + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && |
| 339 | + (bus->host_pci->device & 0xFF00) == 0x4300) { |
| 340 | + /* This is a dangling ethernet core on a |
| 341 | + * wireless device. Ignore it. */ |
| 342 | + continue; |
| 343 | + } |
| 344 | + } |
| 345 | + break; |
| 346 | default: |
| 347 | break; |
| 348 | } |
| 349 | --- a/include/linux/ssb/ssb.h |
| 350 | +++ b/include/linux/ssb/ssb.h |
| 351 | @@ -55,6 +55,10 @@ struct ssb_sprom { |
| 352 | u8 tri5gl; /* 5.2GHz TX isolation */ |
| 353 | u8 tri5g; /* 5.3GHz TX isolation */ |
| 354 | u8 tri5gh; /* 5.8GHz TX isolation */ |
| 355 | + u8 txpid2g[4]; /* 2GHz TX power index */ |
| 356 | + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ |
| 357 | + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ |
| 358 | + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ |
| 359 | u8 rxpo2g; /* 2GHz RX power offset */ |
| 360 | u8 rxpo5g; /* 5GHz RX power offset */ |
| 361 | u8 rssisav2g; /* 2GHz RSSI params */ |
| 362 | --- a/include/linux/ssb/ssb_regs.h |
| 363 | +++ b/include/linux/ssb/ssb_regs.h |
| 364 | @@ -85,6 +85,8 @@ |
| 365 | #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */ |
| 366 | #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */ |
| 367 | #define SSB_IMSTATE_TO 0x00040000 /* Timeout */ |
| 368 | +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */ |
| 369 | +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */ |
| 370 | #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */ |
| 371 | #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ |
| 372 | #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ |
| 373 | @@ -97,7 +99,6 @@ |
| 374 | #define SSB_TMSLOW_RESET 0x00000001 /* Reset */ |
| 375 | #define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */ |
| 376 | #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */ |
| 377 | -#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */ |
| 378 | #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */ |
| 379 | #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ |
| 380 | #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */ |
| 381 | @@ -268,6 +269,8 @@ |
| 382 | /* SPROM Revision 4 */ |
| 383 | #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ |
| 384 | #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ |
| 385 | +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */ |
| 386 | +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */ |
| 387 | #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */ |
| 388 | #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */ |
| 389 | #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */ |
| 390 | @@ -299,6 +302,46 @@ |
| 391 | #define SSB_SPROM4_AGAIN2_SHIFT 0 |
| 392 | #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ |
| 393 | #define SSB_SPROM4_AGAIN3_SHIFT 8 |
| 394 | +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */ |
| 395 | +#define SSB_SPROM4_TXPID2G0 0x00FF |
| 396 | +#define SSB_SPROM4_TXPID2G0_SHIFT 0 |
| 397 | +#define SSB_SPROM4_TXPID2G1 0xFF00 |
| 398 | +#define SSB_SPROM4_TXPID2G1_SHIFT 8 |
| 399 | +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */ |
| 400 | +#define SSB_SPROM4_TXPID2G2 0x00FF |
| 401 | +#define SSB_SPROM4_TXPID2G2_SHIFT 0 |
| 402 | +#define SSB_SPROM4_TXPID2G3 0xFF00 |
| 403 | +#define SSB_SPROM4_TXPID2G3_SHIFT 8 |
| 404 | +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */ |
| 405 | +#define SSB_SPROM4_TXPID5G0 0x00FF |
| 406 | +#define SSB_SPROM4_TXPID5G0_SHIFT 0 |
| 407 | +#define SSB_SPROM4_TXPID5G1 0xFF00 |
| 408 | +#define SSB_SPROM4_TXPID5G1_SHIFT 8 |
| 409 | +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */ |
| 410 | +#define SSB_SPROM4_TXPID5G2 0x00FF |
| 411 | +#define SSB_SPROM4_TXPID5G2_SHIFT 0 |
| 412 | +#define SSB_SPROM4_TXPID5G3 0xFF00 |
| 413 | +#define SSB_SPROM4_TXPID5G3_SHIFT 8 |
| 414 | +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */ |
| 415 | +#define SSB_SPROM4_TXPID5GL0 0x00FF |
| 416 | +#define SSB_SPROM4_TXPID5GL0_SHIFT 0 |
| 417 | +#define SSB_SPROM4_TXPID5GL1 0xFF00 |
| 418 | +#define SSB_SPROM4_TXPID5GL1_SHIFT 8 |
| 419 | +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */ |
| 420 | +#define SSB_SPROM4_TXPID5GL2 0x00FF |
| 421 | +#define SSB_SPROM4_TXPID5GL2_SHIFT 0 |
| 422 | +#define SSB_SPROM4_TXPID5GL3 0xFF00 |
| 423 | +#define SSB_SPROM4_TXPID5GL3_SHIFT 8 |
| 424 | +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */ |
| 425 | +#define SSB_SPROM4_TXPID5GH0 0x00FF |
| 426 | +#define SSB_SPROM4_TXPID5GH0_SHIFT 0 |
| 427 | +#define SSB_SPROM4_TXPID5GH1 0xFF00 |
| 428 | +#define SSB_SPROM4_TXPID5GH1_SHIFT 8 |
| 429 | +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */ |
| 430 | +#define SSB_SPROM4_TXPID5GH2 0x00FF |
| 431 | +#define SSB_SPROM4_TXPID5GH2_SHIFT 0 |
| 432 | +#define SSB_SPROM4_TXPID5GH3 0xFF00 |
| 433 | +#define SSB_SPROM4_TXPID5GH3_SHIFT 8 |
| 434 | #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ |
| 435 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ |
| 436 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 437 | @@ -318,6 +361,8 @@ |
| 438 | #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */ |
| 439 | #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */ |
| 440 | #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */ |
| 441 | +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */ |
| 442 | +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */ |
| 443 | #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */ |
| 444 | #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */ |
| 445 | #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ |
| 446 | |
