Root/target/linux/lantiq/patches-2.6.32/550-dwc_otg.patch

1--- a/drivers/usb/Kconfig
2+++ b/drivers/usb/Kconfig
3@@ -107,6 +107,8 @@
4 
5 source "drivers/usb/host/Kconfig"
6 
7+source "drivers/usb/dwc_otg/Kconfig"
8+
9 source "drivers/usb/musb/Kconfig"
10 
11 source "drivers/usb/class/Kconfig"
12--- a/drivers/usb/Makefile
13+++ b/drivers/usb/Makefile
14@@ -26,6 +26,8 @@
15 
16 obj-$(CONFIG_USB_WUSB) += wusbcore/
17 
18+obj-$(CONFIG_DWC_OTG) += dwc_otg/
19+
20 obj-$(CONFIG_USB_ACM) += class/
21 obj-$(CONFIG_USB_PRINTER) += class/
22 obj-$(CONFIG_USB_WDM) += class/
23--- /dev/null
24+++ b/drivers/usb/dwc_otg/Kconfig
25@@ -0,0 +1,37 @@
26+config DWC_OTG
27+ tristate "Synopsis DWC_OTG support"
28+ depends on USB
29+ help
30+ This driver supports Synopsis DWC_OTG IP core
31+ embebbed on many SOCs (ralink, infineon, etc)
32+
33+choice
34+ prompt "USB Operation Mode"
35+ depends on DWC_OTG
36+ default DWC_OTG_HOST_ONLY
37+
38+config DWC_OTG_HOST_ONLY
39+ bool "HOST ONLY MODE"
40+ depends on DWC_OTG
41+
42+#config DWC_OTG_DEVICE_ONLY
43+# bool "DEVICE ONLY MODE"
44+# depends on DWC_OTG
45+endchoice
46+
47+choice
48+ prompt "Platform"
49+ depends on DWC_OTG
50+ default DWC_OTG_LANTIQ
51+
52+config DWC_OTG_LANTIQ
53+ bool "Lantiq"
54+ depends on LANTIQ
55+ help
56+ Danube USB Host Controller
57+ platform support
58+endchoice
59+
60+config DWC_OTG_DEBUG
61+ bool "Enable debug mode"
62+ depends on DWC_OTG
63--- /dev/null
64+++ b/drivers/usb/dwc_otg/Makefile
65@@ -0,0 +1,39 @@
66+#
67+# Makefile for DWC_otg Highspeed USB controller driver
68+#
69+
70+ifeq ($(CONFIG_DWC_OTG_DEBUG),y)
71+EXTRA_CFLAGS += -DDEBUG
72+endif
73+
74+# Use one of the following flags to compile the software in host-only or
75+# device-only mode based on the configuration selected by the user
76+ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y)
77+ EXTRA_CFLAGS += -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY
78+ EXTRA_CFLAGS += -DDWC_OTG_EN_ISOC -DDWC_EN_ISOC
79+else ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y)
80+ EXTRA_CFLAGS += -DDWC_OTG_DEVICE_ONLY
81+else
82+ EXTRA_CFLAGS += -DDWC_OTG_MODE
83+endif
84+
85+# EXTRA_CFLAGS += -DDWC_HS_ELECT_TST
86+# EXTRA_CFLAGS += -DDWC_OTG_EXT_CHG_PUMP
87+
88+ifeq ($(CONFIG_DWC_OTG_LANTIQ),y)
89+ EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -D__KERNEL__
90+endif
91+ifeq ($(CONFIG_DWC_OTG_LANTIQ),m)
92+ EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_HOST_ONLY -DMODULE -D__KERNEL__ -DDEBUG
93+endif
94+
95+obj-$(CONFIG_DWC_OTG) := dwc_otg.o
96+dwc_otg-objs := dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o
97+#dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
98+dwc_otg-objs += dwc_otg_attr.o
99+dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
100+dwc_otg-objs += dwc_otg_ifx.o
101+dwc_otg-objs += dwc_otg_driver.o
102+
103+#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o
104+#dwc_otg_ifx-objs := dwc_otg_ifx.o
105--- /dev/null
106+++ b/drivers/usb/dwc_otg/dwc_otg_attr.c
107@@ -0,0 +1,802 @@
108+/* ==========================================================================
109+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.c $
110+ * $Revision: 1.1.1.1 $
111+ * $Date: 2009-04-17 06:15:34 $
112+ * $Change: 537387 $
113+ *
114+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
115+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
116+ * otherwise expressly agreed to in writing between Synopsys and you.
117+ *
118+ * The Software IS NOT an item of Licensed Software or Licensed Product under
119+ * any End User Software License Agreement or Agreement for Licensed Product
120+ * with Synopsys or any supplement thereto. You are permitted to use and
121+ * redistribute this Software in source and binary forms, with or without
122+ * modification, provided that redistributions of source code must retain this
123+ * notice. You may not view, use, disclose, copy or distribute this file or
124+ * any information contained herein except pursuant to this license grant from
125+ * Synopsys. If you do not agree with this notice, including the disclaimer
126+ * below, then you are not authorized to use the Software.
127+ *
128+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
129+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
130+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
131+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
132+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
133+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
134+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
135+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
136+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
137+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
138+ * DAMAGE.
139+ * ========================================================================== */
140+
141+/** @file
142+ *
143+ * The diagnostic interface will provide access to the controller for
144+ * bringing up the hardware and testing. The Linux driver attributes
145+ * feature will be used to provide the Linux Diagnostic
146+ * Interface. These attributes are accessed through sysfs.
147+ */
148+
149+/** @page "Linux Module Attributes"
150+ *
151+ * The Linux module attributes feature is used to provide the Linux
152+ * Diagnostic Interface. These attributes are accessed through sysfs.
153+ * The diagnostic interface will provide access to the controller for
154+ * bringing up the hardware and testing.
155+
156+
157+ The following table shows the attributes.
158+ <table>
159+ <tr>
160+ <td><b> Name</b></td>
161+ <td><b> Description</b></td>
162+ <td><b> Access</b></td>
163+ </tr>
164+
165+ <tr>
166+ <td> mode </td>
167+ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
168+ <td> Read</td>
169+ </tr>
170+
171+ <tr>
172+ <td> hnpcapable </td>
173+ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
174+ Read returns the current value.</td>
175+ <td> Read/Write</td>
176+ </tr>
177+
178+ <tr>
179+ <td> srpcapable </td>
180+ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
181+ Read returns the current value.</td>
182+ <td> Read/Write</td>
183+ </tr>
184+
185+ <tr>
186+ <td> hnp </td>
187+ <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
188+ <td> Read/Write</td>
189+ </tr>
190+
191+ <tr>
192+ <td> srp </td>
193+ <td> Initiates the Session Request Protocol. Read returns the status.</td>
194+ <td> Read/Write</td>
195+ </tr>
196+
197+ <tr>
198+ <td> buspower </td>
199+ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
200+ <td> Read/Write</td>
201+ </tr>
202+
203+ <tr>
204+ <td> bussuspend </td>
205+ <td> Suspends the USB bus.</td>
206+ <td> Read/Write</td>
207+ </tr>
208+
209+ <tr>
210+ <td> busconnected </td>
211+ <td> Gets the connection status of the bus</td>
212+ <td> Read</td>
213+ </tr>
214+
215+ <tr>
216+ <td> gotgctl </td>
217+ <td> Gets or sets the Core Control Status Register.</td>
218+ <td> Read/Write</td>
219+ </tr>
220+
221+ <tr>
222+ <td> gusbcfg </td>
223+ <td> Gets or sets the Core USB Configuration Register</td>
224+ <td> Read/Write</td>
225+ </tr>
226+
227+ <tr>
228+ <td> grxfsiz </td>
229+ <td> Gets or sets the Receive FIFO Size Register</td>
230+ <td> Read/Write</td>
231+ </tr>
232+
233+ <tr>
234+ <td> gnptxfsiz </td>
235+ <td> Gets or sets the non-periodic Transmit Size Register</td>
236+ <td> Read/Write</td>
237+ </tr>
238+
239+ <tr>
240+ <td> gpvndctl </td>
241+ <td> Gets or sets the PHY Vendor Control Register</td>
242+ <td> Read/Write</td>
243+ </tr>
244+
245+ <tr>
246+ <td> ggpio </td>
247+ <td> Gets the value in the lower 16-bits of the General Purpose IO Register
248+ or sets the upper 16 bits.</td>
249+ <td> Read/Write</td>
250+ </tr>
251+
252+ <tr>
253+ <td> guid </td>
254+ <td> Gets or sets the value of the User ID Register</td>
255+ <td> Read/Write</td>
256+ </tr>
257+
258+ <tr>
259+ <td> gsnpsid </td>
260+ <td> Gets the value of the Synopsys ID Regester</td>
261+ <td> Read</td>
262+ </tr>
263+
264+ <tr>
265+ <td> devspeed </td>
266+ <td> Gets or sets the device speed setting in the DCFG register</td>
267+ <td> Read/Write</td>
268+ </tr>
269+
270+ <tr>
271+ <td> enumspeed </td>
272+ <td> Gets the device enumeration Speed.</td>
273+ <td> Read</td>
274+ </tr>
275+
276+ <tr>
277+ <td> hptxfsiz </td>
278+ <td> Gets the value of the Host Periodic Transmit FIFO</td>
279+ <td> Read</td>
280+ </tr>
281+
282+ <tr>
283+ <td> hprt0 </td>
284+ <td> Gets or sets the value in the Host Port Control and Status Register</td>
285+ <td> Read/Write</td>
286+ </tr>
287+
288+ <tr>
289+ <td> regoffset </td>
290+ <td> Sets the register offset for the next Register Access</td>
291+ <td> Read/Write</td>
292+ </tr>
293+
294+ <tr>
295+ <td> regvalue </td>
296+ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
297+ <td> Read/Write</td>
298+ </tr>
299+
300+ <tr>
301+ <td> remote_wakeup </td>
302+ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
303+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
304+ Wakeup signalling bit in the Device Control Register is set for 1
305+ milli-second.</td>
306+ <td> Read/Write</td>
307+ </tr>
308+
309+ <tr>
310+ <td> regdump </td>
311+ <td> Dumps the contents of core registers.</td>
312+ <td> Read</td>
313+ </tr>
314+
315+ <tr>
316+ <td> hcddump </td>
317+ <td> Dumps the current HCD state.</td>
318+ <td> Read</td>
319+ </tr>
320+
321+ <tr>
322+ <td> hcd_frrem </td>
323+ <td> Shows the average value of the Frame Remaining
324+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt
325+ occurs. This can be used to determine the average interrupt latency. Also
326+ shows the average Frame Remaining value for start_transfer and the "a" and
327+ "b" sample points. The "a" and "b" sample points may be used during debugging
328+ bto determine how long it takes to execute a section of the HCD code.</td>
329+ <td> Read</td>
330+ </tr>
331+
332+ <tr>
333+ <td> rd_reg_test </td>
334+ <td> Displays the time required to read the GNPTXFSIZ register many times
335+ (the output shows the number of times the register is read).
336+ <td> Read</td>
337+ </tr>
338+
339+ <tr>
340+ <td> wr_reg_test </td>
341+ <td> Displays the time required to write the GNPTXFSIZ register many times
342+ (the output shows the number of times the register is written).
343+ <td> Read</td>
344+ </tr>
345+
346+ </table>
347+
348+ Example usage:
349+ To get the current mode:
350+ cat /sys/devices/lm0/mode
351+
352+ To power down the USB:
353+ echo 0 > /sys/devices/lm0/buspower
354+ */
355+#include <linux/kernel.h>
356+#include <linux/module.h>
357+#include <linux/moduleparam.h>
358+#include <linux/init.h>
359+#include <linux/device.h>
360+#include <linux/errno.h>
361+#include <linux/types.h>
362+#include <linux/stat.h> /* permission constants */
363+
364+#include <asm/io.h>
365+
366+#include "dwc_otg_plat.h"
367+#include "dwc_otg_attr.h"
368+#include "dwc_otg_driver.h"
369+// #include "dwc_otg_pcd.h"
370+#include "dwc_otg_hcd.h"
371+
372+// 20070316, winder added.
373+#ifndef SZ_256K
374+#define SZ_256K 0x00040000
375+#endif
376+
377+/*
378+ * MACROs for defining sysfs attribute
379+ */
380+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
381+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
382+{ \
383+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
384+ uint32_t val; \
385+ val = dwc_read_reg32 (_addr_); \
386+ val = (val & (_mask_)) >> _shift_; \
387+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \
388+}
389+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
390+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
391+{ \
392+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
393+ uint32_t set = simple_strtoul(buf, NULL, 16); \
394+ uint32_t clear = set; \
395+ clear = ((~clear) << _shift_) & _mask_; \
396+ set = (set << _shift_) & _mask_; \
397+ dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \
398+ dwc_modify_reg32(_addr_, clear, set); \
399+ return count; \
400+}
401+
402+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
403+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
404+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
405+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
406+
407+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
408+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \
409+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
410+
411+/*
412+ * MACROs for defining sysfs attribute for 32-bit registers
413+ */
414+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
415+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
416+{ \
417+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
418+ uint32_t val; \
419+ val = dwc_read_reg32 (_addr_); \
420+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
421+}
422+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
423+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \
424+{ \
425+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\
426+ uint32_t val = simple_strtoul(buf, NULL, 16); \
427+ dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \
428+ dwc_write_reg32(_addr_, val); \
429+ return count; \
430+}
431+
432+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
433+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
434+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \
435+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
436+
437+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
438+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \
439+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
440+
441+
442+/** @name Functions for Show/Store of Attributes */
443+/**@{*/
444+
445+/**
446+ * Show the register offset of the Register Access.
447+ */
448+static ssize_t regoffset_show( struct device *_dev, struct device_attribute *attr, char *buf)
449+{
450+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
451+ return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset);
452+}
453+
454+/**
455+ * Set the register offset for the next Register Access Read/Write
456+ */
457+static ssize_t regoffset_store( struct device *_dev, struct device_attribute *attr, const char *buf,
458+ size_t count )
459+{
460+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
461+ uint32_t offset = simple_strtoul(buf, NULL, 16);
462+ //dev_dbg(_dev, "Offset=0x%08x\n", offset);
463+ if (offset < SZ_256K ) {
464+ otg_dev->reg_offset = offset;
465+ }
466+ else {
467+ dev_err( _dev, "invalid offset\n" );
468+ }
469+
470+ return count;
471+}
472+DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, regoffset_show, regoffset_store);
473+
474+/**
475+ * Show the value of the register at the offset in the reg_offset
476+ * attribute.
477+ */
478+static ssize_t regvalue_show( struct device *_dev, struct device_attribute *attr, char *buf)
479+{
480+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
481+ uint32_t val;
482+ volatile uint32_t *addr;
483+
484+ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
485+ /* Calculate the address */
486+ addr = (uint32_t*)(otg_dev->reg_offset +
487+ (uint8_t*)otg_dev->base);
488+ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
489+ val = dwc_read_reg32( addr );
490+ return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1,
491+ "Reg@0x%06x = 0x%08x\n",
492+ otg_dev->reg_offset, val);
493+ }
494+ else {
495+ dev_err(_dev, "Invalid offset (0x%0x)\n",
496+ otg_dev->reg_offset);
497+ return sprintf(buf, "invalid offset\n" );
498+ }
499+}
500+
501+/**
502+ * Store the value in the register at the offset in the reg_offset
503+ * attribute.
504+ *
505+ */
506+static ssize_t regvalue_store( struct device *_dev, struct device_attribute *attr, const char *buf,
507+ size_t count )
508+{
509+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
510+ volatile uint32_t * addr;
511+ uint32_t val = simple_strtoul(buf, NULL, 16);
512+ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
513+ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
514+ /* Calculate the address */
515+ addr = (uint32_t*)(otg_dev->reg_offset +
516+ (uint8_t*)otg_dev->base);
517+ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr);
518+ dwc_write_reg32( addr, val );
519+ }
520+ else {
521+ dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
522+ otg_dev->reg_offset);
523+ }
524+ return count;
525+}
526+DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store);
527+
528+/*
529+ * Attributes
530+ */
531+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode");
532+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode");
533+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode");
534+
535+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
536+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
537+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected");
538+
539+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL");
540+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG");
541+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ");
542+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ");
543+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL");
544+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO");
545+DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID");
546+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID");
547+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed");
548+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed");
549+
550+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ");
551+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0");
552+
553+
554+/**
555+ * @todo Add code to initiate the HNP.
556+ */
557+/**
558+ * Show the HNP status bit
559+ */
560+static ssize_t hnp_show( struct device *_dev, struct device_attribute *attr, char *buf)
561+{
562+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
563+ gotgctl_data_t val;
564+ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
565+ return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs);
566+}
567+
568+/**
569+ * Set the HNP Request bit
570+ */
571+static ssize_t hnp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
572+ size_t count )
573+{
574+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
575+ uint32_t in = simple_strtoul(buf, NULL, 16);
576+ uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl);
577+ gotgctl_data_t mem;
578+ mem.d32 = dwc_read_reg32(addr);
579+ mem.b.hnpreq = in;
580+ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
581+ dwc_write_reg32(addr, mem.d32);
582+ return count;
583+}
584+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
585+
586+/**
587+ * @todo Add code to initiate the SRP.
588+ */
589+/**
590+ * Show the SRP status bit
591+ */
592+static ssize_t srp_show( struct device *_dev, struct device_attribute *attr, char *buf)
593+{
594+#ifndef DWC_HOST_ONLY
595+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
596+ gotgctl_data_t val;
597+ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl));
598+ return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs);
599+#else
600+ return sprintf(buf, "Host Only Mode!\n");
601+#endif
602+}
603+
604+/**
605+ * Set the SRP Request bit
606+ */
607+static ssize_t srp_store( struct device *_dev, struct device_attribute *attr, const char *buf,
608+ size_t count )
609+{
610+#ifndef DWC_HOST_ONLY
611+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
612+ dwc_otg_pcd_initiate_srp(otg_dev->pcd);
613+#endif
614+ return count;
615+}
616+DEVICE_ATTR(srp, 0644, srp_show, srp_store);
617+
618+/**
619+ * @todo Need to do more for power on/off?
620+ */
621+/**
622+ * Show the Bus Power status
623+ */
624+static ssize_t buspower_show( struct device *_dev, struct device_attribute *attr, char *buf)
625+{
626+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
627+ hprt0_data_t val;
628+ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
629+ return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr);
630+}
631+
632+
633+/**
634+ * Set the Bus Power status
635+ */
636+static ssize_t buspower_store( struct device *_dev, struct device_attribute *attr, const char *buf,
637+ size_t count )
638+{
639+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
640+ uint32_t on = simple_strtoul(buf, NULL, 16);
641+ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
642+ hprt0_data_t mem;
643+
644+ mem.d32 = dwc_read_reg32(addr);
645+ mem.b.prtpwr = on;
646+
647+ //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
648+ dwc_write_reg32(addr, mem.d32);
649+
650+ return count;
651+}
652+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
653+
654+/**
655+ * @todo Need to do more for suspend?
656+ */
657+/**
658+ * Show the Bus Suspend status
659+ */
660+static ssize_t bussuspend_show( struct device *_dev, struct device_attribute *attr, char *buf)
661+{
662+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
663+ hprt0_data_t val;
664+ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0);
665+ return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp);
666+}
667+
668+/**
669+ * Set the Bus Suspend status
670+ */
671+static ssize_t bussuspend_store( struct device *_dev, struct device_attribute *attr, const char *buf,
672+ size_t count )
673+{
674+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
675+ uint32_t in = simple_strtoul(buf, NULL, 16);
676+ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0;
677+ hprt0_data_t mem;
678+ mem.d32 = dwc_read_reg32(addr);
679+ mem.b.prtsusp = in;
680+ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32);
681+ dwc_write_reg32(addr, mem.d32);
682+ return count;
683+}
684+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
685+
686+/**
687+ * Show the status of Remote Wakeup.
688+ */
689+static ssize_t remote_wakeup_show( struct device *_dev, struct device_attribute *attr, char *buf)
690+{
691+#ifndef DWC_HOST_ONLY
692+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
693+ dctl_data_t val;
694+ val.d32 = dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl);
695+ return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n",
696+ val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable);
697+#else
698+ return sprintf(buf, "Host Only Mode!\n");
699+#endif
700+}
701+
702+/**
703+ * Initiate a remote wakeup of the host. The Device control register
704+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
705+ * flag is set.
706+ *
707+ */
708+static ssize_t remote_wakeup_store( struct device *_dev, struct device_attribute *attr, const char *buf,
709+ size_t count )
710+{
711+#ifndef DWC_HOST_ONLY
712+ uint32_t val = simple_strtoul(buf, NULL, 16);
713+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
714+ if (val&1) {
715+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
716+ }
717+ else {
718+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
719+ }
720+#endif
721+ return count;
722+}
723+DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show,
724+ remote_wakeup_store);
725+
726+/**
727+ * Dump global registers and either host or device registers (depending on the
728+ * current mode of the core).
729+ */
730+static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf)
731+{
732+#ifdef DEBUG
733+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
734+ printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev);
735+
736+ dwc_otg_dump_global_registers( otg_dev->core_if);
737+ if (dwc_otg_is_host_mode(otg_dev->core_if)) {
738+ dwc_otg_dump_host_registers( otg_dev->core_if);
739+ } else {
740+ dwc_otg_dump_dev_registers( otg_dev->core_if);
741+ }
742+#endif
743+
744+ return sprintf( buf, "Register Dump\n" );
745+}
746+
747+DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
748+
749+/**
750+ * Dump the current hcd state.
751+ */
752+static ssize_t hcddump_show( struct device *_dev, struct device_attribute *attr, char *buf)
753+{
754+#ifndef DWC_DEVICE_ONLY
755+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
756+ dwc_otg_hcd_dump_state(otg_dev->hcd);
757+#endif
758+ return sprintf( buf, "HCD Dump\n" );
759+}
760+
761+DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
762+
763+/**
764+ * Dump the average frame remaining at SOF. This can be used to
765+ * determine average interrupt latency. Frame remaining is also shown for
766+ * start transfer and two additional sample points.
767+ */
768+static ssize_t hcd_frrem_show( struct device *_dev, struct device_attribute *attr, char *buf)
769+{
770+#ifndef DWC_DEVICE_ONLY
771+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
772+ dwc_otg_hcd_dump_frrem(otg_dev->hcd);
773+#endif
774+ return sprintf( buf, "HCD Dump Frame Remaining\n" );
775+}
776+
777+DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
778+
779+/**
780+ * Displays the time required to read the GNPTXFSIZ register many times (the
781+ * output shows the number of times the register is read).
782+ */
783+#define RW_REG_COUNT 10000000
784+#define MSEC_PER_JIFFIE 1000/HZ
785+static ssize_t rd_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
786+{
787+ int i;
788+ int time;
789+ int start_jiffies;
790+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
791+
792+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
793+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
794+ start_jiffies = jiffies;
795+ for (i = 0; i < RW_REG_COUNT; i++) {
796+ dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
797+ }
798+ time = jiffies - start_jiffies;
799+ return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
800+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
801+}
802+
803+DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
804+
805+/**
806+ * Displays the time required to write the GNPTXFSIZ register many times (the
807+ * output shows the number of times the register is written).
808+ */
809+static ssize_t wr_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf)
810+{
811+ int i;
812+ int time;
813+ int start_jiffies;
814+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
815+ uint32_t reg_val;
816+
817+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
818+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
819+ reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz);
820+ start_jiffies = jiffies;
821+ for (i = 0; i < RW_REG_COUNT; i++) {
822+ dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val);
823+ }
824+ time = jiffies - start_jiffies;
825+ return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
826+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
827+}
828+
829+DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
830+/**@}*/
831+
832+/**
833+ * Create the device files
834+ */
835+void dwc_otg_attr_create (struct device *_dev)
836+{
837+ int retval;
838+
839+ retval = device_create_file(_dev, &dev_attr_regoffset);
840+ retval += device_create_file(_dev, &dev_attr_regvalue);
841+ retval += device_create_file(_dev, &dev_attr_mode);
842+ retval += device_create_file(_dev, &dev_attr_hnpcapable);
843+ retval += device_create_file(_dev, &dev_attr_srpcapable);
844+ retval += device_create_file(_dev, &dev_attr_hnp);
845+ retval += device_create_file(_dev, &dev_attr_srp);
846+ retval += device_create_file(_dev, &dev_attr_buspower);
847+ retval += device_create_file(_dev, &dev_attr_bussuspend);
848+ retval += device_create_file(_dev, &dev_attr_busconnected);
849+ retval += device_create_file(_dev, &dev_attr_gotgctl);
850+ retval += device_create_file(_dev, &dev_attr_gusbcfg);
851+ retval += device_create_file(_dev, &dev_attr_grxfsiz);
852+ retval += device_create_file(_dev, &dev_attr_gnptxfsiz);
853+ retval += device_create_file(_dev, &dev_attr_gpvndctl);
854+ retval += device_create_file(_dev, &dev_attr_ggpio);
855+ retval += device_create_file(_dev, &dev_attr_guid);
856+ retval += device_create_file(_dev, &dev_attr_gsnpsid);
857+ retval += device_create_file(_dev, &dev_attr_devspeed);
858+ retval += device_create_file(_dev, &dev_attr_enumspeed);
859+ retval += device_create_file(_dev, &dev_attr_hptxfsiz);
860+ retval += device_create_file(_dev, &dev_attr_hprt0);
861+ retval += device_create_file(_dev, &dev_attr_remote_wakeup);
862+ retval += device_create_file(_dev, &dev_attr_regdump);
863+ retval += device_create_file(_dev, &dev_attr_hcddump);
864+ retval += device_create_file(_dev, &dev_attr_hcd_frrem);
865+ retval += device_create_file(_dev, &dev_attr_rd_reg_test);
866+ retval += device_create_file(_dev, &dev_attr_wr_reg_test);
867+
868+ if(retval != 0)
869+ {
870+ DWC_PRINT("cannot create sysfs device files.\n");
871+ // DWC_PRINT("killing own sysfs device files!\n");
872+ dwc_otg_attr_remove(_dev);
873+ }
874+}
875+
876+/**
877+ * Remove the device files
878+ */
879+void dwc_otg_attr_remove (struct device *_dev)
880+{
881+ device_remove_file(_dev, &dev_attr_regoffset);
882+ device_remove_file(_dev, &dev_attr_regvalue);
883+ device_remove_file(_dev, &dev_attr_mode);
884+ device_remove_file(_dev, &dev_attr_hnpcapable);
885+ device_remove_file(_dev, &dev_attr_srpcapable);
886+ device_remove_file(_dev, &dev_attr_hnp);
887+ device_remove_file(_dev, &dev_attr_srp);
888+ device_remove_file(_dev, &dev_attr_buspower);
889+ device_remove_file(_dev, &dev_attr_bussuspend);
890+ device_remove_file(_dev, &dev_attr_busconnected);
891+ device_remove_file(_dev, &dev_attr_gotgctl);
892+ device_remove_file(_dev, &dev_attr_gusbcfg);
893+ device_remove_file(_dev, &dev_attr_grxfsiz);
894+ device_remove_file(_dev, &dev_attr_gnptxfsiz);
895+ device_remove_file(_dev, &dev_attr_gpvndctl);
896+ device_remove_file(_dev, &dev_attr_ggpio);
897+ device_remove_file(_dev, &dev_attr_guid);
898+ device_remove_file(_dev, &dev_attr_gsnpsid);
899+ device_remove_file(_dev, &dev_attr_devspeed);
900+ device_remove_file(_dev, &dev_attr_enumspeed);
901+ device_remove_file(_dev, &dev_attr_hptxfsiz);
902+ device_remove_file(_dev, &dev_attr_hprt0);
903+ device_remove_file(_dev, &dev_attr_remote_wakeup);
904+ device_remove_file(_dev, &dev_attr_regdump);
905+ device_remove_file(_dev, &dev_attr_hcddump);
906+ device_remove_file(_dev, &dev_attr_hcd_frrem);
907+ device_remove_file(_dev, &dev_attr_rd_reg_test);
908+ device_remove_file(_dev, &dev_attr_wr_reg_test);
909+}
910--- /dev/null
911+++ b/drivers/usb/dwc_otg/dwc_otg_attr.h
912@@ -0,0 +1,67 @@
913+/* ==========================================================================
914+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.h $
915+ * $Revision: 1.1.1.1 $
916+ * $Date: 2009-04-17 06:15:34 $
917+ * $Change: 510275 $
918+ *
919+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
920+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
921+ * otherwise expressly agreed to in writing between Synopsys and you.
922+ *
923+ * The Software IS NOT an item of Licensed Software or Licensed Product under
924+ * any End User Software License Agreement or Agreement for Licensed Product
925+ * with Synopsys or any supplement thereto. You are permitted to use and
926+ * redistribute this Software in source and binary forms, with or without
927+ * modification, provided that redistributions of source code must retain this
928+ * notice. You may not view, use, disclose, copy or distribute this file or
929+ * any information contained herein except pursuant to this license grant from
930+ * Synopsys. If you do not agree with this notice, including the disclaimer
931+ * below, then you are not authorized to use the Software.
932+ *
933+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
934+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
935+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
936+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
937+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
938+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
939+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
940+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
941+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
942+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
943+ * DAMAGE.
944+ * ========================================================================== */
945+
946+#if !defined(__DWC_OTG_ATTR_H__)
947+#define __DWC_OTG_ATTR_H__
948+
949+/** @file
950+ * This file contains the interface to the Linux device attributes.
951+ */
952+extern struct device_attribute dev_attr_regoffset;
953+extern struct device_attribute dev_attr_regvalue;
954+
955+extern struct device_attribute dev_attr_mode;
956+extern struct device_attribute dev_attr_hnpcapable;
957+extern struct device_attribute dev_attr_srpcapable;
958+extern struct device_attribute dev_attr_hnp;
959+extern struct device_attribute dev_attr_srp;
960+extern struct device_attribute dev_attr_buspower;
961+extern struct device_attribute dev_attr_bussuspend;
962+extern struct device_attribute dev_attr_busconnected;
963+extern struct device_attribute dev_attr_gotgctl;
964+extern struct device_attribute dev_attr_gusbcfg;
965+extern struct device_attribute dev_attr_grxfsiz;
966+extern struct device_attribute dev_attr_gnptxfsiz;
967+extern struct device_attribute dev_attr_gpvndctl;
968+extern struct device_attribute dev_attr_ggpio;
969+extern struct device_attribute dev_attr_guid;
970+extern struct device_attribute dev_attr_gsnpsid;
971+extern struct device_attribute dev_attr_devspeed;
972+extern struct device_attribute dev_attr_enumspeed;
973+extern struct device_attribute dev_attr_hptxfsiz;
974+extern struct device_attribute dev_attr_hprt0;
975+
976+void dwc_otg_attr_create (struct device *_dev);
977+void dwc_otg_attr_remove (struct device *_dev);
978+
979+#endif
980--- /dev/null
981+++ b/drivers/usb/dwc_otg/dwc_otg_cil.c
982@@ -0,0 +1,3025 @@
983+/* ==========================================================================
984+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.c $
985+ * $Revision: 1.1.1.1 $
986+ * $Date: 2009-04-17 06:15:34 $
987+ * $Change: 631780 $
988+ *
989+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
990+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
991+ * otherwise expressly agreed to in writing between Synopsys and you.
992+ *
993+ * The Software IS NOT an item of Licensed Software or Licensed Product under
994+ * any End User Software License Agreement or Agreement for Licensed Product
995+ * with Synopsys or any supplement thereto. You are permitted to use and
996+ * redistribute this Software in source and binary forms, with or without
997+ * modification, provided that redistributions of source code must retain this
998+ * notice. You may not view, use, disclose, copy or distribute this file or
999+ * any information contained herein except pursuant to this license grant from
1000+ * Synopsys. If you do not agree with this notice, including the disclaimer
1001+ * below, then you are not authorized to use the Software.
1002+ *
1003+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
1004+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1005+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1006+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
1007+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1008+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
1009+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
1010+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
1011+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1012+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
1013+ * DAMAGE.
1014+ * ========================================================================== */
1015+
1016+/** @file
1017+ *
1018+ * The Core Interface Layer provides basic services for accessing and
1019+ * managing the DWC_otg hardware. These services are used by both the
1020+ * Host Controller Driver and the Peripheral Controller Driver.
1021+ *
1022+ * The CIL manages the memory map for the core so that the HCD and PCD
1023+ * don't have to do this separately. It also handles basic tasks like
1024+ * reading/writing the registers and data FIFOs in the controller.
1025+ * Some of the data access functions provide encapsulation of several
1026+ * operations required to perform a task, such as writing multiple
1027+ * registers to start a transfer. Finally, the CIL performs basic
1028+ * services that are not specific to either the host or device modes
1029+ * of operation. These services include management of the OTG Host
1030+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
1031+ * Diagnostic API is also provided to allow testing of the controller
1032+ * hardware.
1033+ *
1034+ * The Core Interface Layer has the following requirements:
1035+ * - Provides basic controller operations.
1036+ * - Minimal use of OS services.
1037+ * - The OS services used will be abstracted by using inline functions
1038+ * or macros.
1039+ *
1040+ */
1041+#include <asm/unaligned.h>
1042+
1043+#ifdef DEBUG
1044+#include <linux/jiffies.h>
1045+#endif
1046+
1047+#include "dwc_otg_plat.h"
1048+
1049+#include "dwc_otg_regs.h"
1050+#include "dwc_otg_cil.h"
1051+
1052+/**
1053+ * This function is called to initialize the DWC_otg CSR data
1054+ * structures. The register addresses in the device and host
1055+ * structures are initialized from the base address supplied by the
1056+ * caller. The calling function must make the OS calls to get the
1057+ * base address of the DWC_otg controller registers. The core_params
1058+ * argument holds the parameters that specify how the core should be
1059+ * configured.
1060+ *
1061+ * @param[in] _reg_base_addr Base address of DWC_otg core registers
1062+ * @param[in] _core_params Pointer to the core configuration parameters
1063+ *
1064+ */
1065+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
1066+ dwc_otg_core_params_t *_core_params)
1067+{
1068+ dwc_otg_core_if_t *core_if = 0;
1069+ dwc_otg_dev_if_t *dev_if = 0;
1070+ dwc_otg_host_if_t *host_if = 0;
1071+ uint8_t *reg_base = (uint8_t *)_reg_base_addr;
1072+ int i = 0;
1073+
1074+ DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, _reg_base_addr, _core_params);
1075+
1076+ core_if = kmalloc( sizeof(dwc_otg_core_if_t), GFP_KERNEL);
1077+ if (core_if == 0) {
1078+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n");
1079+ return 0;
1080+ }
1081+ memset(core_if, 0, sizeof(dwc_otg_core_if_t));
1082+
1083+ core_if->core_params = _core_params;
1084+ core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base;
1085+ /*
1086+ * Allocate the Device Mode structures.
1087+ */
1088+ dev_if = kmalloc( sizeof(dwc_otg_dev_if_t), GFP_KERNEL);
1089+ if (dev_if == 0) {
1090+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
1091+ kfree( core_if );
1092+ return 0;
1093+ }
1094+
1095+ dev_if->dev_global_regs =
1096+ (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET);
1097+
1098+ for (i=0; i<MAX_EPS_CHANNELS; i++) {
1099+ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
1100+ (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
1101+ (i * DWC_EP_REG_OFFSET));
1102+
1103+ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
1104+ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
1105+ (i * DWC_EP_REG_OFFSET));
1106+ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
1107+ i, &dev_if->in_ep_regs[i]->diepctl);
1108+ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
1109+ i, &dev_if->out_ep_regs[i]->doepctl);
1110+ }
1111+ dev_if->speed = 0; // unknown
1112+ //dev_if->num_eps = MAX_EPS_CHANNELS;
1113+ //dev_if->num_perio_eps = 0;
1114+
1115+ core_if->dev_if = dev_if;
1116+ /*
1117+ * Allocate the Host Mode structures.
1118+ */
1119+ host_if = kmalloc( sizeof(dwc_otg_host_if_t), GFP_KERNEL);
1120+ if (host_if == 0) {
1121+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n");
1122+ kfree( dev_if );
1123+ kfree( core_if );
1124+ return 0;
1125+ }
1126+
1127+ host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
1128+ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
1129+ host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
1130+ for (i=0; i<MAX_EPS_CHANNELS; i++) {
1131+ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
1132+ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
1133+ (i * DWC_OTG_CHAN_REGS_OFFSET));
1134+ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
1135+ i, &host_if->hc_regs[i]->hcchar);
1136+ }
1137+ host_if->num_host_channels = MAX_EPS_CHANNELS;
1138+ core_if->host_if = host_if;
1139+
1140+ for (i=0; i<MAX_EPS_CHANNELS; i++) {
1141+ core_if->data_fifo[i] =
1142+ (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET +
1143+ (i * DWC_OTG_DATA_FIFO_SIZE));
1144+ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
1145+ i, (unsigned)core_if->data_fifo[i]);
1146+ } // for loop.
1147+
1148+ core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET);
1149+
1150+ /*
1151+ * Store the contents of the hardware configuration registers here for
1152+ * easy access later.
1153+ */
1154+ core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
1155+ core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
1156+ core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
1157+ core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
1158+
1159+ DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32);
1160+ DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32);
1161+ DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32);
1162+ DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32);
1163+
1164+
1165+ DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode);
1166+ DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture);
1167+ DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep);
1168+ DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan);
1169+ DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth);
1170+ DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth);
1171+ DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth);
1172+
1173+ DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth);
1174+ DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width);
1175+
1176+ /*
1177+ * Set the SRP sucess bit for FS-I2c
1178+ */
1179+ core_if->srp_success = 0;
1180+ core_if->srp_timer_started = 0;
1181+
1182+ return core_if;
1183+}
1184+/**
1185+ * This function frees the structures allocated by dwc_otg_cil_init().
1186+ *
1187+ * @param[in] _core_if The core interface pointer returned from
1188+ * dwc_otg_cil_init().
1189+ *
1190+ */
1191+void dwc_otg_cil_remove( dwc_otg_core_if_t *_core_if )
1192+{
1193+ /* Disable all interrupts */
1194+ dwc_modify_reg32( &_core_if->core_global_regs->gahbcfg, 1, 0);
1195+ dwc_write_reg32( &_core_if->core_global_regs->gintmsk, 0);
1196+
1197+ if ( _core_if->dev_if ) {
1198+ kfree( _core_if->dev_if );
1199+ }
1200+ if ( _core_if->host_if ) {
1201+ kfree( _core_if->host_if );
1202+ }
1203+ kfree( _core_if );
1204+}
1205+
1206+/**
1207+ * This function enables the controller's Global Interrupt in the AHB Config
1208+ * register.
1209+ *
1210+ * @param[in] _core_if Programming view of DWC_otg controller.
1211+ */
1212+extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if )
1213+{
1214+ gahbcfg_data_t ahbcfg = { .d32 = 0};
1215+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
1216+ dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
1217+}
1218+/**
1219+ * This function disables the controller's Global Interrupt in the AHB Config
1220+ * register.
1221+ *
1222+ * @param[in] _core_if Programming view of DWC_otg controller.
1223+ */
1224+extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if )
1225+{
1226+ gahbcfg_data_t ahbcfg = { .d32 = 0};
1227+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
1228+ dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
1229+}
1230+
1231+/**
1232+ * This function initializes the commmon interrupts, used in both
1233+ * device and host modes.
1234+ *
1235+ * @param[in] _core_if Programming view of the DWC_otg controller
1236+ *
1237+ */
1238+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *_core_if)
1239+{
1240+ dwc_otg_core_global_regs_t *global_regs =
1241+ _core_if->core_global_regs;
1242+ gintmsk_data_t intr_mask = { .d32 = 0};
1243+ /* Clear any pending OTG Interrupts */
1244+ dwc_write_reg32( &global_regs->gotgint, 0xFFFFFFFF);
1245+ /* Clear any pending interrupts */
1246+ dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF);
1247+ /*
1248+ * Enable the interrupts in the GINTMSK.
1249+ */
1250+ intr_mask.b.modemismatch = 1;
1251+ intr_mask.b.otgintr = 1;
1252+ if (!_core_if->dma_enable) {
1253+ intr_mask.b.rxstsqlvl = 1;
1254+ }
1255+ intr_mask.b.conidstschng = 1;
1256+ intr_mask.b.wkupintr = 1;
1257+ intr_mask.b.disconnect = 1;
1258+ intr_mask.b.usbsuspend = 1;
1259+ intr_mask.b.sessreqintr = 1;
1260+ dwc_write_reg32( &global_regs->gintmsk, intr_mask.d32);
1261+}
1262+
1263+/**
1264+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
1265+ * type.
1266+ */
1267+static void init_fslspclksel(dwc_otg_core_if_t *_core_if)
1268+{
1269+ uint32_t val;
1270+ hcfg_data_t hcfg;
1271+
1272+ if (((_core_if->hwcfg2.b.hs_phy_type == 2) &&
1273+ (_core_if->hwcfg2.b.fs_phy_type == 1) &&
1274+ (_core_if->core_params->ulpi_fs_ls)) ||
1275+ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS))
1276+ {
1277+ /* Full speed PHY */
1278+ val = DWC_HCFG_48_MHZ;
1279+ } else {
1280+ /* High speed PHY running at full speed or high speed */
1281+ val = DWC_HCFG_30_60_MHZ;
1282+ }
1283+
1284+ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
1285+ hcfg.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hcfg);
1286+ hcfg.b.fslspclksel = val;
1287+ dwc_write_reg32(&_core_if->host_if->host_global_regs->hcfg, hcfg.d32);
1288+}
1289+
1290+/**
1291+ * Initializes the DevSpd field of the DCFG register depending on the PHY type
1292+ * and the enumeration speed of the device.
1293+ */
1294+static void init_devspd(dwc_otg_core_if_t *_core_if)
1295+{
1296+ uint32_t val;
1297+ dcfg_data_t dcfg;
1298+
1299+ if (((_core_if->hwcfg2.b.hs_phy_type == 2) &&
1300+ (_core_if->hwcfg2.b.fs_phy_type == 1) &&
1301+ (_core_if->core_params->ulpi_fs_ls)) ||
1302+ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS))
1303+ {
1304+ /* Full speed PHY */
1305+ val = 0x3;
1306+ } else if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1307+ /* High speed PHY running at full speed */
1308+ val = 0x1;
1309+ } else {
1310+ /* High speed PHY running at high speed */
1311+ val = 0x0;
1312+ }
1313+
1314+ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
1315+ dcfg.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dcfg);
1316+ dcfg.b.devspd = val;
1317+ dwc_write_reg32(&_core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1318+}
1319+
1320+/**
1321+ * This function calculates the number of IN EPS
1322+ * using GHWCFG1 and GHWCFG2 registers values
1323+ *
1324+ * @param _pcd the pcd structure.
1325+ */
1326+static uint32_t calc_num_in_eps(dwc_otg_core_if_t * _core_if)
1327+{
1328+ uint32_t num_in_eps = 0;
1329+ uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep;
1330+ uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2;
1331+ uint32_t num_tx_fifos = _core_if->hwcfg4.b.num_in_eps;
1332+ int i;
1333+ for (i = 0; i < num_eps; ++i) {
1334+ if (!(hwcfg1 & 0x1))
1335+ num_in_eps++;
1336+ hwcfg1 >>= 2;
1337+ }
1338+ if (_core_if->hwcfg4.b.ded_fifo_en) {
1339+ num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
1340+ }
1341+ return num_in_eps;
1342+}
1343+
1344+
1345+/**
1346+ * This function calculates the number of OUT EPS
1347+ * using GHWCFG1 and GHWCFG2 registers values
1348+ *
1349+ * @param _pcd the pcd structure.
1350+ */
1351+static uint32_t calc_num_out_eps(dwc_otg_core_if_t * _core_if)
1352+{
1353+ uint32_t num_out_eps = 0;
1354+ uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep;
1355+ uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2;
1356+ int i;
1357+ for (i = 0; i < num_eps; ++i) {
1358+ if (!(hwcfg1 & 0x2))
1359+ num_out_eps++;
1360+ hwcfg1 >>= 2;
1361+ }
1362+ return num_out_eps;
1363+}
1364+/**
1365+ * This function initializes the DWC_otg controller registers and
1366+ * prepares the core for device mode or host mode operation.
1367+ *
1368+ * @param _core_if Programming view of the DWC_otg controller
1369+ *
1370+ */
1371+void dwc_otg_core_init(dwc_otg_core_if_t *_core_if)
1372+{
1373+ dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs;
1374+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1375+ int i = 0;
1376+ gahbcfg_data_t ahbcfg = { .d32 = 0};
1377+ gusbcfg_data_t usbcfg = { .d32 = 0 };
1378+ gi2cctl_data_t i2cctl = {.d32 = 0};
1379+
1380+ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n",_core_if);
1381+
1382+ /* Common Initialization */
1383+
1384+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1385+ DWC_DEBUGPL(DBG_CIL, "USB config register: 0x%08x\n", usbcfg.d32);
1386+
1387+ /* Program the ULPI External VBUS bit if needed */
1388+ //usbcfg.b.ulpi_ext_vbus_drv = 1;
1389+ //usbcfg.b.ulpi_ext_vbus_drv = 0;
1390+ usbcfg.b.ulpi_ext_vbus_drv =
1391+ (_core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1392+
1393+ /* Set external TS Dline pulsing */
1394+ usbcfg.b.term_sel_dl_pulse = (_core_if->core_params->ts_dline == 1) ? 1 : 0;
1395+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1396+
1397+ /* Reset the Controller */
1398+ dwc_otg_core_reset( _core_if );
1399+
1400+ /* Initialize parameters from Hardware configuration registers. */
1401+#if 0
1402+ dev_if->num_eps = _core_if->hwcfg2.b.num_dev_ep;
1403+ dev_if->num_perio_eps = _core_if->hwcfg4.b.num_dev_perio_in_ep;
1404+#else
1405+ dev_if->num_in_eps = calc_num_in_eps(_core_if);
1406+ dev_if->num_out_eps = calc_num_out_eps(_core_if);
1407+#endif
1408+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
1409+ _core_if->hwcfg4.b.num_dev_perio_in_ep);
1410+ DWC_DEBUGPL(DBG_CIL, "Is power optimization enabled? %s\n",
1411+ _core_if->hwcfg4.b.power_optimiz ? "Yes" : "No");
1412+ DWC_DEBUGPL(DBG_CIL, "vbus_valid filter enabled? %s\n",
1413+ _core_if->hwcfg4.b.vbus_valid_filt_en ? "Yes" : "No");
1414+ DWC_DEBUGPL(DBG_CIL, "iddig filter enabled? %s\n",
1415+ _core_if->hwcfg4.b.iddig_filt_en ? "Yes" : "No");
1416+
1417+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",_core_if->hwcfg4.b.num_dev_perio_in_ep);
1418+ for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1419+ dev_if->perio_tx_fifo_size[i] =
1420+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
1421+ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", i,
1422+ dev_if->perio_tx_fifo_size[i]);
1423+ }
1424+ for (i = 0; i < _core_if->hwcfg4.b.num_in_eps; i++) {
1425+ dev_if->tx_fifo_size[i] =
1426+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
1427+ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", i,
1428+ dev_if->perio_tx_fifo_size[i]);
1429+ }
1430+
1431+ _core_if->total_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
1432+ _core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz);
1433+ _core_if->nperio_tx_fifo_size = dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
1434+
1435+ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", _core_if->total_fifo_size);
1436+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", _core_if->rx_fifo_size);
1437+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", _core_if->nperio_tx_fifo_size);
1438+
1439+ /* This programming sequence needs to happen in FS mode before any other
1440+ * programming occurs */
1441+ if ((_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1442+ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1443+ /* If FS mode with FS PHY */
1444+
1445+ /* core_init() is now called on every switch so only call the
1446+ * following for the first time through. */
1447+ if (!_core_if->phy_init_done) {
1448+ _core_if->phy_init_done = 1;
1449+ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1450+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1451+ usbcfg.b.physel = 1;
1452+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1453+
1454+ /* Reset after a PHY select */
1455+ dwc_otg_core_reset( _core_if );
1456+ }
1457+
1458+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1459+ * do this on HNP Dev/Host mode switches (done in dev_init and
1460+ * host_init). */
1461+ if (dwc_otg_is_host_mode(_core_if)) {
1462+ DWC_DEBUGPL(DBG_CIL, "host mode\n");
1463+ init_fslspclksel(_core_if);
1464+ } else {
1465+ DWC_DEBUGPL(DBG_CIL, "device mode\n");
1466+ init_devspd(_core_if);
1467+ }
1468+
1469+ if (_core_if->core_params->i2c_enable) {
1470+ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1471+ /* Program GUSBCFG.OtgUtmifsSel to I2C */
1472+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1473+ usbcfg.b.otgutmifssel = 1;
1474+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32);
1475+
1476+ /* Program GI2CCTL.I2CEn */
1477+ i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
1478+ i2cctl.b.i2cdevaddr = 1;
1479+ i2cctl.b.i2cen = 0;
1480+ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
1481+ i2cctl.b.i2cen = 1;
1482+ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32);
1483+ }
1484+
1485+ } /* endif speed == DWC_SPEED_PARAM_FULL */
1486+ else {
1487+ /* High speed PHY. */
1488+ if (!_core_if->phy_init_done) {
1489+ _core_if->phy_init_done = 1;
1490+ DWC_DEBUGPL(DBG_CIL, "High spped PHY\n");
1491+ /* HS PHY parameters. These parameters are preserved
1492+ * during soft reset so only program the first time. Do
1493+ * a soft reset immediately after setting phyif. */
1494+ usbcfg.b.ulpi_utmi_sel = _core_if->core_params->phy_type;
1495+ if (usbcfg.b.ulpi_utmi_sel == 2) { // winder
1496+ DWC_DEBUGPL(DBG_CIL, "ULPI\n");
1497+ /* ULPI interface */
1498+ usbcfg.b.phyif = 0;
1499+ usbcfg.b.ddrsel = _core_if->core_params->phy_ulpi_ddr;
1500+ } else {
1501+ /* UTMI+ interface */
1502+ if (_core_if->core_params->phy_utmi_width == 16) {
1503+ usbcfg.b.phyif = 1;
1504+ DWC_DEBUGPL(DBG_CIL, "UTMI+ 16\n");
1505+ } else {
1506+ DWC_DEBUGPL(DBG_CIL, "UTMI+ 8\n");
1507+ usbcfg.b.phyif = 0;
1508+ }
1509+ }
1510+ dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32);
1511+
1512+ /* Reset after setting the PHY parameters */
1513+ dwc_otg_core_reset( _core_if );
1514+ }
1515+ }
1516+
1517+ if ((_core_if->hwcfg2.b.hs_phy_type == 2) &&
1518+ (_core_if->hwcfg2.b.fs_phy_type == 1) &&
1519+ (_core_if->core_params->ulpi_fs_ls))
1520+ {
1521+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1522+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1523+ usbcfg.b.ulpi_fsls = 1;
1524+ usbcfg.b.ulpi_clk_sus_m = 1;
1525+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1526+ } else {
1527+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS=0\n");
1528+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
1529+ usbcfg.b.ulpi_fsls = 0;
1530+ usbcfg.b.ulpi_clk_sus_m = 0;
1531+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
1532+ }
1533+
1534+ /* Program the GAHBCFG Register.*/
1535+ switch (_core_if->hwcfg2.b.architecture){
1536+
1537+ case DWC_SLAVE_ONLY_ARCH:
1538+ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1539+ ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1540+ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1541+ _core_if->dma_enable = 0;
1542+ break;
1543+
1544+ case DWC_EXT_DMA_ARCH:
1545+ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1546+ ahbcfg.b.hburstlen = _core_if->core_params->dma_burst_size;
1547+ _core_if->dma_enable = (_core_if->core_params->dma_enable != 0);
1548+ break;
1549+
1550+ case DWC_INT_DMA_ARCH:
1551+ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1552+ //ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
1553+ ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR4;
1554+ _core_if->dma_enable = (_core_if->core_params->dma_enable != 0);
1555+ break;
1556+ }
1557+ ahbcfg.b.dmaenable = _core_if->dma_enable;
1558+ dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
1559+ _core_if->en_multiple_tx_fifo = _core_if->hwcfg4.b.ded_fifo_en;
1560+
1561+ /*
1562+ * Program the GUSBCFG register.
1563+ */
1564+ usbcfg.d32 = dwc_read_reg32( &global_regs->gusbcfg );
1565+
1566+ switch (_core_if->hwcfg2.b.op_mode) {
1567+ case DWC_MODE_HNP_SRP_CAPABLE:
1568+ usbcfg.b.hnpcap = (_core_if->core_params->otg_cap ==
1569+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1570+ usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
1571+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1572+ break;
1573+
1574+ case DWC_MODE_SRP_ONLY_CAPABLE:
1575+ usbcfg.b.hnpcap = 0;
1576+ usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
1577+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1578+ break;
1579+
1580+ case DWC_MODE_NO_HNP_SRP_CAPABLE:
1581+ usbcfg.b.hnpcap = 0;
1582+ usbcfg.b.srpcap = 0;
1583+ break;
1584+
1585+ case DWC_MODE_SRP_CAPABLE_DEVICE:
1586+ usbcfg.b.hnpcap = 0;
1587+ usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
1588+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1589+ break;
1590+
1591+ case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1592+ usbcfg.b.hnpcap = 0;
1593+ usbcfg.b.srpcap = 0;
1594+ break;
1595+
1596+ case DWC_MODE_SRP_CAPABLE_HOST:
1597+ usbcfg.b.hnpcap = 0;
1598+ usbcfg.b.srpcap = (_core_if->core_params->otg_cap !=
1599+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1600+ break;
1601+
1602+ case DWC_MODE_NO_SRP_CAPABLE_HOST:
1603+ usbcfg.b.hnpcap = 0;
1604+ usbcfg.b.srpcap = 0;
1605+ break;
1606+ }
1607+
1608+ dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32);
1609+
1610+ /* Enable common interrupts */
1611+ dwc_otg_enable_common_interrupts( _core_if );
1612+
1613+ /* Do device or host intialization based on mode during PCD
1614+ * and HCD initialization */
1615+ if (dwc_otg_is_host_mode( _core_if )) {
1616+ DWC_DEBUGPL(DBG_ANY, "Host Mode\n" );
1617+ _core_if->op_state = A_HOST;
1618+ } else {
1619+ DWC_DEBUGPL(DBG_ANY, "Device Mode\n" );
1620+ _core_if->op_state = B_PERIPHERAL;
1621+#ifdef DWC_DEVICE_ONLY
1622+ dwc_otg_core_dev_init( _core_if );
1623+#endif
1624+ }
1625+}
1626+
1627+
1628+/**
1629+ * This function enables the Device mode interrupts.
1630+ *
1631+ * @param _core_if Programming view of DWC_otg controller
1632+ */
1633+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if)
1634+{
1635+ gintmsk_data_t intr_mask = { .d32 = 0};
1636+ dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs;
1637+
1638+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1639+
1640+ /* Disable all interrupts. */
1641+ dwc_write_reg32( &global_regs->gintmsk, 0);
1642+
1643+ /* Clear any pending interrupts */
1644+ dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF);
1645+
1646+ /* Enable the common interrupts */
1647+ dwc_otg_enable_common_interrupts( _core_if );
1648+
1649+ /* Enable interrupts */
1650+ intr_mask.b.usbreset = 1;
1651+ intr_mask.b.enumdone = 1;
1652+ //intr_mask.b.epmismatch = 1;
1653+ intr_mask.b.inepintr = 1;
1654+ intr_mask.b.outepintr = 1;
1655+ intr_mask.b.erlysuspend = 1;
1656+ if (_core_if->en_multiple_tx_fifo == 0) {
1657+ intr_mask.b.epmismatch = 1;
1658+ }
1659+
1660+ /** @todo NGS: Should this be a module parameter? */
1661+ intr_mask.b.isooutdrop = 1;
1662+ intr_mask.b.eopframe = 1;
1663+ intr_mask.b.incomplisoin = 1;
1664+ intr_mask.b.incomplisoout = 1;
1665+
1666+ dwc_modify_reg32( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1667+
1668+ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
1669+ dwc_read_reg32( &global_regs->gintmsk));
1670+}
1671+
1672+/**
1673+ * This function initializes the DWC_otg controller registers for
1674+ * device mode.
1675+ *
1676+ * @param _core_if Programming view of DWC_otg controller
1677+ *
1678+ */
1679+void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if)
1680+{
1681+ dwc_otg_core_global_regs_t *global_regs =
1682+ _core_if->core_global_regs;
1683+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1684+ dwc_otg_core_params_t *params = _core_if->core_params;
1685+ dcfg_data_t dcfg = {.d32 = 0};
1686+ grstctl_t resetctl = { .d32=0 };
1687+ int i;
1688+ uint32_t rx_fifo_size;
1689+ fifosize_data_t nptxfifosize;
1690+ fifosize_data_t txfifosize;
1691+ dthrctl_data_t dthrctl;
1692+
1693+ fifosize_data_t ptxfifosize;
1694+
1695+ /* Restart the Phy Clock */
1696+ dwc_write_reg32(_core_if->pcgcctl, 0);
1697+
1698+ /* Device configuration register */
1699+ init_devspd(_core_if);
1700+ dcfg.d32 = dwc_read_reg32( &dev_if->dev_global_regs->dcfg);
1701+ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
1702+ dwc_write_reg32( &dev_if->dev_global_regs->dcfg, dcfg.d32 );
1703+
1704+ /* Configure data FIFO sizes */
1705+ if ( _core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo ) {
1706+
1707+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", _core_if->total_fifo_size);
1708+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size);
1709+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size);
1710+
1711+ /* Rx FIFO */
1712+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
1713+ dwc_read_reg32(&global_regs->grxfsiz));
1714+ rx_fifo_size = params->dev_rx_fifo_size;
1715+ dwc_write_reg32( &global_regs->grxfsiz, rx_fifo_size );
1716+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
1717+ dwc_read_reg32(&global_regs->grxfsiz));
1718+
1719+ /** Set Periodic Tx FIFO Mask all bits 0 */
1720+ _core_if->p_tx_msk = 0;
1721+
1722+ /** Set Tx FIFO Mask all bits 0 */
1723+ _core_if->tx_msk = 0;
1724+ if (_core_if->en_multiple_tx_fifo == 0) {
1725+ /* Non-periodic Tx FIFO */
1726+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1727+ dwc_read_reg32(&global_regs->gnptxfsiz));
1728+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1729+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1730+ dwc_write_reg32( &global_regs->gnptxfsiz, nptxfifosize.d32 );
1731+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1732+ dwc_read_reg32(&global_regs->gnptxfsiz));
1733+
1734+
1735+ /**@todo NGS: Fix Periodic FIFO Sizing! */
1736+ /*
1737+ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
1738+ * Indexes of the FIFO size module parameters in the
1739+ * dev_perio_tx_fifo_size array and the FIFO size registers in
1740+ * the dptxfsiz array run from 0 to 14.
1741+ */
1742+ /** @todo Finish debug of this */
1743+ ptxfifosize.b.startaddr =
1744+ nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1745+ for (i = 0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) {
1746+ ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i];
1747+ DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n",
1748+ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1749+ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],ptxfifosize.d32);
1750+ DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n",
1751+ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1752+ ptxfifosize.b.startaddr += ptxfifosize.b.depth;
1753+ }
1754+ } else {
1755+
1756+ /*
1757+ * Tx FIFOs These FIFOs are numbered from 1 to 15.
1758+ * Indexes of the FIFO size module parameters in the
1759+ * dev_tx_fifo_size array and the FIFO size registers in
1760+ * the dptxfsiz_dieptxf array run from 0 to 14.
1761+ */
1762+
1763+ /* Non-periodic Tx FIFO */
1764+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1765+ dwc_read_reg32(&global_regs->gnptxfsiz));
1766+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1767+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1768+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
1769+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1770+ dwc_read_reg32(&global_regs->gnptxfsiz));
1771+ txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1772+ for (i = 1;i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) {
1773+ txfifosize.b.depth = params->dev_tx_fifo_size[i];
1774+ DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n",
1775+ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]));
1776+ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i - 1],txfifosize.d32);
1777+ DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n",
1778+ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1]));
1779+ txfifosize.b.startaddr += txfifosize.b.depth;
1780+ }
1781+ }
1782+ }
1783+ /* Flush the FIFOs */
1784+ dwc_otg_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */
1785+ dwc_otg_flush_rx_fifo(_core_if);
1786+
1787+ /* Flush the Learning Queue. */
1788+ resetctl.b.intknqflsh = 1;
1789+ dwc_write_reg32( &_core_if->core_global_regs->grstctl, resetctl.d32);
1790+
1791+ /* Clear all pending Device Interrupts */
1792+ dwc_write_reg32( &dev_if->dev_global_regs->diepmsk, 0 );
1793+ dwc_write_reg32( &dev_if->dev_global_regs->doepmsk, 0 );
1794+ dwc_write_reg32( &dev_if->dev_global_regs->daint, 0xFFFFFFFF );
1795+ dwc_write_reg32( &dev_if->dev_global_regs->daintmsk, 0 );
1796+
1797+ for (i = 0; i <= dev_if->num_in_eps; i++) {
1798+ depctl_data_t depctl;
1799+ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
1800+ if (depctl.b.epena) {
1801+ depctl.d32 = 0;
1802+ depctl.b.epdis = 1;
1803+ depctl.b.snak = 1;
1804+ } else {
1805+ depctl.d32 = 0;
1806+ }
1807+ dwc_write_reg32( &dev_if->in_ep_regs[i]->diepctl, depctl.d32);
1808+
1809+ dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
1810+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
1811+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
1812+ }
1813+ for (i = 0; i <= dev_if->num_out_eps; i++) {
1814+ depctl_data_t depctl;
1815+ depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
1816+ if (depctl.b.epena) {
1817+ depctl.d32 = 0;
1818+ depctl.b.epdis = 1;
1819+ depctl.b.snak = 1;
1820+ } else {
1821+ depctl.d32 = 0;
1822+ }
1823+ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepctl, depctl.d32);
1824+
1825+ //dwc_write_reg32( &dev_if->in_ep_regs[i]->dieptsiz, 0);
1826+ dwc_write_reg32( &dev_if->out_ep_regs[i]->doeptsiz, 0);
1827+ //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepdma, 0);
1828+ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepdma, 0);
1829+ //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepint, 0xFF);
1830+ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepint, 0xFF);
1831+ }
1832+
1833+ if (_core_if->en_multiple_tx_fifo && _core_if->dma_enable) {
1834+ dev_if->non_iso_tx_thr_en = _core_if->core_params->thr_ctl & 0x1;
1835+ dev_if->iso_tx_thr_en = (_core_if->core_params->thr_ctl >> 1) & 0x1;
1836+ dev_if->rx_thr_en = (_core_if->core_params->thr_ctl >> 2) & 0x1;
1837+ dev_if->rx_thr_length = _core_if->core_params->rx_thr_length;
1838+ dev_if->tx_thr_length = _core_if->core_params->tx_thr_length;
1839+ dthrctl.d32 = 0;
1840+ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
1841+ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
1842+ dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
1843+ dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
1844+ dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
1845+ dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,dthrctl.d32);
1846+ DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\n"
1847+ "Rx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
1848+ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
1849+ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
1850+ dthrctl.b.rx_thr_len);
1851+ }
1852+ dwc_otg_enable_device_interrupts( _core_if );
1853+ {
1854+ diepmsk_data_t msk = {.d32 = 0};
1855+ msk.b.txfifoundrn = 1;
1856+ dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32,msk.d32);
1857+}
1858+}
1859+
1860+/**
1861+ * This function enables the Host mode interrupts.
1862+ *
1863+ * @param _core_if Programming view of DWC_otg controller
1864+ */
1865+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if)
1866+{
1867+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
1868+ gintmsk_data_t intr_mask = {.d32 = 0};
1869+
1870+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1871+
1872+ /* Disable all interrupts. */
1873+ dwc_write_reg32(&global_regs->gintmsk, 0);
1874+
1875+ /* Clear any pending interrupts. */
1876+ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
1877+
1878+ /* Enable the common interrupts */
1879+ dwc_otg_enable_common_interrupts(_core_if);
1880+
1881+ /*
1882+ * Enable host mode interrupts without disturbing common
1883+ * interrupts.
1884+ */
1885+ intr_mask.b.sofintr = 1;
1886+ intr_mask.b.portintr = 1;
1887+ intr_mask.b.hcintr = 1;
1888+
1889+ //dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1890+ //dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
1891+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1892+}
1893+
1894+/**
1895+ * This function disables the Host Mode interrupts.
1896+ *
1897+ * @param _core_if Programming view of DWC_otg controller
1898+ */
1899+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if)
1900+{
1901+ dwc_otg_core_global_regs_t *global_regs =
1902+ _core_if->core_global_regs;
1903+ gintmsk_data_t intr_mask = {.d32 = 0};
1904+
1905+ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
1906+
1907+ /*
1908+ * Disable host mode interrupts without disturbing common
1909+ * interrupts.
1910+ */
1911+ intr_mask.b.sofintr = 1;
1912+ intr_mask.b.portintr = 1;
1913+ intr_mask.b.hcintr = 1;
1914+ intr_mask.b.ptxfempty = 1;
1915+ intr_mask.b.nptxfempty = 1;
1916+
1917+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
1918+}
1919+
1920+#if 0
1921+/* currently not used, keep it here as if needed later */
1922+static int phy_read(dwc_otg_core_if_t * _core_if, int addr)
1923+{
1924+ u32 val;
1925+ int timeout = 10;
1926+
1927+ dwc_write_reg32(&_core_if->core_global_regs->gpvndctl,
1928+ 0x02000000 | (addr << 16));
1929+ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
1930+ while (((val & 0x08000000) == 0) && (timeout--)) {
1931+ udelay(1000);
1932+ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
1933+ }
1934+ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl);
1935+ printk("%s: addr=%02x regval=%02x\n", __func__, addr, val & 0x000000ff);
1936+
1937+ return 0;
1938+}
1939+#endif
1940+
1941+/**
1942+ * This function initializes the DWC_otg controller registers for
1943+ * host mode.
1944+ *
1945+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
1946+ * request queues. Host channels are reset to ensure that they are ready for
1947+ * performing transfers.
1948+ *
1949+ * @param _core_if Programming view of DWC_otg controller
1950+ *
1951+ */
1952+void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if)
1953+{
1954+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
1955+ dwc_otg_host_if_t *host_if = _core_if->host_if;
1956+ dwc_otg_core_params_t *params = _core_if->core_params;
1957+ hprt0_data_t hprt0 = {.d32 = 0};
1958+ fifosize_data_t nptxfifosize;
1959+ fifosize_data_t ptxfifosize;
1960+ int i;
1961+ hcchar_data_t hcchar;
1962+ hcfg_data_t hcfg;
1963+ dwc_otg_hc_regs_t *hc_regs;
1964+ int num_channels;
1965+ gotgctl_data_t gotgctl = {.d32 = 0};
1966+
1967+ DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, _core_if);
1968+
1969+ /* Restart the Phy Clock */
1970+ dwc_write_reg32(_core_if->pcgcctl, 0);
1971+
1972+ /* Initialize Host Configuration Register */
1973+ init_fslspclksel(_core_if);
1974+ if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1975+ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
1976+ hcfg.b.fslssupp = 1;
1977+ dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
1978+ }
1979+
1980+ /* Configure data FIFO sizes */
1981+ if (_core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
1982+ DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", _core_if->total_fifo_size);
1983+ DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size);
1984+ DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size);
1985+ DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size);
1986+
1987+ /* Rx FIFO */
1988+ DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
1989+ dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size);
1990+ DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz));
1991+
1992+ /* Non-periodic Tx FIFO */
1993+ DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
1994+ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
1995+ nptxfifosize.b.startaddr = params->host_rx_fifo_size;
1996+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
1997+ DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz));
1998+
1999+ /* Periodic Tx FIFO */
2000+ DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
2001+ ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
2002+ ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2003+ dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
2004+ DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz));
2005+ }
2006+
2007+ /* Clear Host Set HNP Enable in the OTG Control Register */
2008+ gotgctl.b.hstsethnpen = 1;
2009+ dwc_modify_reg32( &global_regs->gotgctl, gotgctl.d32, 0);
2010+
2011+ /* Make sure the FIFOs are flushed. */
2012+ dwc_otg_flush_tx_fifo(_core_if, 0x10 /* all Tx FIFOs */);
2013+ dwc_otg_flush_rx_fifo(_core_if);
2014+
2015+ /* Flush out any leftover queued requests. */
2016+ num_channels = _core_if->core_params->host_channels;
2017+ for (i = 0; i < num_channels; i++) {
2018+ hc_regs = _core_if->host_if->hc_regs[i];
2019+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2020+ hcchar.b.chen = 0;
2021+ hcchar.b.chdis = 1;
2022+ hcchar.b.epdir = 0;
2023+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2024+ }
2025+
2026+ /* Halt all channels to put them into a known state. */
2027+ for (i = 0; i < num_channels; i++) {
2028+ int count = 0;
2029+ hc_regs = _core_if->host_if->hc_regs[i];
2030+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2031+ hcchar.b.chen = 1;
2032+ hcchar.b.chdis = 1;
2033+ hcchar.b.epdir = 0;
2034+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2035+ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
2036+ do {
2037+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2038+ if (++count > 200) {
2039+ DWC_ERROR("%s: Unable to clear halt on channel %d\n",
2040+ __func__, i);
2041+ break;
2042+ }
2043+ udelay(100);
2044+ } while (hcchar.b.chen);
2045+ }
2046+
2047+ /* Turn on the vbus power. */
2048+ DWC_PRINT("Init: Port Power? op_state=%d\n", _core_if->op_state);
2049+ if (_core_if->op_state == A_HOST){
2050+ hprt0.d32 = dwc_otg_read_hprt0(_core_if);
2051+ DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2052+ if (hprt0.b.prtpwr == 0 ) {
2053+ hprt0.b.prtpwr = 1;
2054+ dwc_write_reg32(host_if->hprt0, hprt0.d32);
2055+ }
2056+ }
2057+
2058+ dwc_otg_enable_host_interrupts( _core_if );
2059+}
2060+
2061+/**
2062+ * Prepares a host channel for transferring packets to/from a specific
2063+ * endpoint. The HCCHARn register is set up with the characteristics specified
2064+ * in _hc. Host channel interrupts that may need to be serviced while this
2065+ * transfer is in progress are enabled.
2066+ *
2067+ * @param _core_if Programming view of DWC_otg controller
2068+ * @param _hc Information needed to initialize the host channel
2069+ */
2070+void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2071+{
2072+ uint32_t intr_enable;
2073+ hcintmsk_data_t hc_intr_mask;
2074+ gintmsk_data_t gintmsk = {.d32 = 0};
2075+ hcchar_data_t hcchar;
2076+ hcsplt_data_t hcsplt;
2077+
2078+ uint8_t hc_num = _hc->hc_num;
2079+ dwc_otg_host_if_t *host_if = _core_if->host_if;
2080+ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
2081+
2082+ /* Clear old interrupt conditions for this host channel. */
2083+ hc_intr_mask.d32 = 0xFFFFFFFF;
2084+ hc_intr_mask.b.reserved = 0;
2085+ dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
2086+
2087+ /* Enable channel interrupts required for this transfer. */
2088+ hc_intr_mask.d32 = 0;
2089+ hc_intr_mask.b.chhltd = 1;
2090+ if (_core_if->dma_enable) {
2091+ hc_intr_mask.b.ahberr = 1;
2092+ if (_hc->error_state && !_hc->do_split &&
2093+ _hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
2094+ hc_intr_mask.b.ack = 1;
2095+ if (_hc->ep_is_in) {
2096+ hc_intr_mask.b.datatglerr = 1;
2097+ if (_hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
2098+ hc_intr_mask.b.nak = 1;
2099+ }
2100+ }
2101+ }
2102+ } else {
2103+ switch (_hc->ep_type) {
2104+ case DWC_OTG_EP_TYPE_CONTROL:
2105+ case DWC_OTG_EP_TYPE_BULK:
2106+ hc_intr_mask.b.xfercompl = 1;
2107+ hc_intr_mask.b.stall = 1;
2108+ hc_intr_mask.b.xacterr = 1;
2109+ hc_intr_mask.b.datatglerr = 1;
2110+ if (_hc->ep_is_in) {
2111+ hc_intr_mask.b.bblerr = 1;
2112+ } else {
2113+ hc_intr_mask.b.nak = 1;
2114+ hc_intr_mask.b.nyet = 1;
2115+ if (_hc->do_ping) {
2116+ hc_intr_mask.b.ack = 1;
2117+ }
2118+ }
2119+
2120+ if (_hc->do_split) {
2121+ hc_intr_mask.b.nak = 1;
2122+ if (_hc->complete_split) {
2123+ hc_intr_mask.b.nyet = 1;
2124+ }
2125+ else {
2126+ hc_intr_mask.b.ack = 1;
2127+ }
2128+ }
2129+
2130+ if (_hc->error_state) {
2131+ hc_intr_mask.b.ack = 1;
2132+ }
2133+ break;
2134+ case DWC_OTG_EP_TYPE_INTR:
2135+ hc_intr_mask.b.xfercompl = 1;
2136+ hc_intr_mask.b.nak = 1;
2137+ hc_intr_mask.b.stall = 1;
2138+ hc_intr_mask.b.xacterr = 1;
2139+ hc_intr_mask.b.datatglerr = 1;
2140+ hc_intr_mask.b.frmovrun = 1;
2141+
2142+ if (_hc->ep_is_in) {
2143+ hc_intr_mask.b.bblerr = 1;
2144+ }
2145+ if (_hc->error_state) {
2146+ hc_intr_mask.b.ack = 1;
2147+ }
2148+ if (_hc->do_split) {
2149+ if (_hc->complete_split) {
2150+ hc_intr_mask.b.nyet = 1;
2151+ }
2152+ else {
2153+ hc_intr_mask.b.ack = 1;
2154+ }
2155+ }
2156+ break;
2157+ case DWC_OTG_EP_TYPE_ISOC:
2158+ hc_intr_mask.b.xfercompl = 1;
2159+ hc_intr_mask.b.frmovrun = 1;
2160+ hc_intr_mask.b.ack = 1;
2161+
2162+ if (_hc->ep_is_in) {
2163+ hc_intr_mask.b.xacterr = 1;
2164+ hc_intr_mask.b.bblerr = 1;
2165+ }
2166+ break;
2167+ }
2168+ }
2169+ dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
2170+
2171+ /* Enable the top level host channel interrupt. */
2172+ intr_enable = (1 << hc_num);
2173+ dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
2174+
2175+ /* Make sure host channel interrupts are enabled. */
2176+ gintmsk.b.hcintr = 1;
2177+ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
2178+
2179+ /*
2180+ * Program the HCCHARn register with the endpoint characteristics for
2181+ * the current transfer.
2182+ */
2183+ hcchar.d32 = 0;
2184+ hcchar.b.devaddr = _hc->dev_addr;
2185+ hcchar.b.epnum = _hc->ep_num;
2186+ hcchar.b.epdir = _hc->ep_is_in;
2187+ hcchar.b.lspddev = (_hc->speed == DWC_OTG_EP_SPEED_LOW);
2188+ hcchar.b.eptype = _hc->ep_type;
2189+ hcchar.b.mps = _hc->max_packet;
2190+
2191+ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
2192+
2193+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2194+ DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr);
2195+ DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum);
2196+ DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir);
2197+ DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev);
2198+ DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype);
2199+ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2200+ DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt);
2201+
2202+ /*
2203+ * Program the HCSPLIT register for SPLITs
2204+ */
2205+ hcsplt.d32 = 0;
2206+ if (_hc->do_split) {
2207+ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", _hc->hc_num,
2208+ _hc->complete_split ? "CSPLIT" : "SSPLIT");
2209+ hcsplt.b.compsplt = _hc->complete_split;
2210+ hcsplt.b.xactpos = _hc->xact_pos;
2211+ hcsplt.b.hubaddr = _hc->hub_addr;
2212+ hcsplt.b.prtaddr = _hc->port_addr;
2213+ DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", _hc->complete_split);
2214+ DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", _hc->xact_pos);
2215+ DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", _hc->hub_addr);
2216+ DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", _hc->port_addr);
2217+ DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", _hc->ep_is_in);
2218+ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2219+ DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", _hc->xfer_len);
2220+ }
2221+ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
2222+
2223+}
2224+
2225+/**
2226+ * Attempts to halt a host channel. This function should only be called in
2227+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
2228+ * normal circumstances in DMA mode, the controller halts the channel when the
2229+ * transfer is complete or a condition occurs that requires application
2230+ * intervention.
2231+ *
2232+ * In slave mode, checks for a free request queue entry, then sets the Channel
2233+ * Enable and Channel Disable bits of the Host Channel Characteristics
2234+ * register of the specified channel to intiate the halt. If there is no free
2235+ * request queue entry, sets only the Channel Disable bit of the HCCHARn
2236+ * register to flush requests for this channel. In the latter case, sets a
2237+ * flag to indicate that the host channel needs to be halted when a request
2238+ * queue slot is open.
2239+ *
2240+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2241+ * HCCHARn register. The controller ensures there is space in the request
2242+ * queue before submitting the halt request.
2243+ *
2244+ * Some time may elapse before the core flushes any posted requests for this
2245+ * host channel and halts. The Channel Halted interrupt handler completes the
2246+ * deactivation of the host channel.
2247+ *
2248+ * @param _core_if Controller register interface.
2249+ * @param _hc Host channel to halt.
2250+ * @param _halt_status Reason for halting the channel.
2251+ */
2252+void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
2253+ dwc_hc_t *_hc,
2254+ dwc_otg_halt_status_e _halt_status)
2255+{
2256+ gnptxsts_data_t nptxsts;
2257+ hptxsts_data_t hptxsts;
2258+ hcchar_data_t hcchar;
2259+ dwc_otg_hc_regs_t *hc_regs;
2260+ dwc_otg_core_global_regs_t *global_regs;
2261+ dwc_otg_host_global_regs_t *host_global_regs;
2262+
2263+ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2264+ global_regs = _core_if->core_global_regs;
2265+ host_global_regs = _core_if->host_if->host_global_regs;
2266+
2267+ WARN_ON(_halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS);
2268+
2269+ if (_halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
2270+ _halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
2271+ /*
2272+ * Disable all channel interrupts except Ch Halted. The QTD
2273+ * and QH state associated with this transfer has been cleared
2274+ * (in the case of URB_DEQUEUE), so the channel needs to be
2275+ * shut down carefully to prevent crashes.
2276+ */
2277+ hcintmsk_data_t hcintmsk;
2278+ hcintmsk.d32 = 0;
2279+ hcintmsk.b.chhltd = 1;
2280+ dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
2281+
2282+ /*
2283+ * Make sure no other interrupts besides halt are currently
2284+ * pending. Handling another interrupt could cause a crash due
2285+ * to the QTD and QH state.
2286+ */
2287+ dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
2288+
2289+ /*
2290+ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2291+ * even if the channel was already halted for some other
2292+ * reason.
2293+ */
2294+ _hc->halt_status = _halt_status;
2295+
2296+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2297+ if (hcchar.b.chen == 0) {
2298+ /*
2299+ * The channel is either already halted or it hasn't
2300+ * started yet. In DMA mode, the transfer may halt if
2301+ * it finishes normally or a condition occurs that
2302+ * requires driver intervention. Don't want to halt
2303+ * the channel again. In either Slave or DMA mode,
2304+ * it's possible that the transfer has been assigned
2305+ * to a channel, but not started yet when an URB is
2306+ * dequeued. Don't want to halt a channel that hasn't
2307+ * started yet.
2308+ */
2309+ return;
2310+ }
2311+ }
2312+
2313+ if (_hc->halt_pending) {
2314+ /*
2315+ * A halt has already been issued for this channel. This might
2316+ * happen when a transfer is aborted by a higher level in
2317+ * the stack.
2318+ */
2319+#ifdef DEBUG
2320+ DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n",
2321+ __func__, _hc->hc_num);
2322+
2323+/* dwc_otg_dump_global_registers(_core_if); */
2324+/* dwc_otg_dump_host_registers(_core_if); */
2325+#endif
2326+ return;
2327+ }
2328+
2329+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2330+ hcchar.b.chen = 1;
2331+ hcchar.b.chdis = 1;
2332+
2333+ if (!_core_if->dma_enable) {
2334+ /* Check for space in the request queue to issue the halt. */
2335+ if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
2336+ _hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
2337+ nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2338+ if (nptxsts.b.nptxqspcavail == 0) {
2339+ hcchar.b.chen = 0;
2340+ }
2341+ } else {
2342+ hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts);
2343+ if ((hptxsts.b.ptxqspcavail == 0) || (_core_if->queuing_high_bandwidth)) {
2344+ hcchar.b.chen = 0;
2345+ }
2346+ }
2347+ }
2348+
2349+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2350+
2351+ _hc->halt_status = _halt_status;
2352+
2353+ if (hcchar.b.chen) {
2354+ _hc->halt_pending = 1;
2355+ _hc->halt_on_queue = 0;
2356+ } else {
2357+ _hc->halt_on_queue = 1;
2358+ }
2359+
2360+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2361+ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
2362+ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", _hc->halt_pending);
2363+ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", _hc->halt_on_queue);
2364+ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", _hc->halt_status);
2365+
2366+ return;
2367+}
2368+
2369+/**
2370+ * Clears the transfer state for a host channel. This function is normally
2371+ * called after a transfer is done and the host channel is being released.
2372+ *
2373+ * @param _core_if Programming view of DWC_otg controller.
2374+ * @param _hc Identifies the host channel to clean up.
2375+ */
2376+void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2377+{
2378+ dwc_otg_hc_regs_t *hc_regs;
2379+
2380+ _hc->xfer_started = 0;
2381+
2382+ /*
2383+ * Clear channel interrupt enables and any unhandled channel interrupt
2384+ * conditions.
2385+ */
2386+ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2387+ dwc_write_reg32(&hc_regs->hcintmsk, 0);
2388+ dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
2389+
2390+#ifdef DEBUG
2391+ del_timer(&_core_if->hc_xfer_timer[_hc->hc_num]);
2392+ {
2393+ hcchar_data_t hcchar;
2394+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2395+ if (hcchar.b.chdis) {
2396+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2397+ __func__, _hc->hc_num, hcchar.d32);
2398+ }
2399+ }
2400+#endif
2401+}
2402+
2403+/**
2404+ * Sets the channel property that indicates in which frame a periodic transfer
2405+ * should occur. This is always set to the _next_ frame. This function has no
2406+ * effect on non-periodic transfers.
2407+ *
2408+ * @param _core_if Programming view of DWC_otg controller.
2409+ * @param _hc Identifies the host channel to set up and its properties.
2410+ * @param _hcchar Current value of the HCCHAR register for the specified host
2411+ * channel.
2412+ */
2413+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *_core_if,
2414+ dwc_hc_t *_hc,
2415+ hcchar_data_t *_hcchar)
2416+{
2417+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2418+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2419+ hfnum_data_t hfnum;
2420+ hfnum.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hfnum);
2421+ /* 1 if _next_ frame is odd, 0 if it's even */
2422+ _hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2423+#ifdef DEBUG
2424+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR && _hc->do_split && !_hc->complete_split) {
2425+ switch (hfnum.b.frnum & 0x7) {
2426+ case 7:
2427+ _core_if->hfnum_7_samples++;
2428+ _core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
2429+ break;
2430+ case 0:
2431+ _core_if->hfnum_0_samples++;
2432+ _core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
2433+ break;
2434+ default:
2435+ _core_if->hfnum_other_samples++;
2436+ _core_if->hfnum_other_frrem_accum += hfnum.b.frrem;
2437+ break;
2438+ }
2439+ }
2440+#endif
2441+ }
2442+}
2443+
2444+#ifdef DEBUG
2445+static void hc_xfer_timeout(unsigned long _ptr)
2446+{
2447+ hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr;
2448+ int hc_num = xfer_info->hc->hc_num;
2449+ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
2450+ DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]);
2451+}
2452+#endif
2453+
2454+/*
2455+ * This function does the setup for a data transfer for a host channel and
2456+ * starts the transfer. May be called in either Slave mode or DMA mode. In
2457+ * Slave mode, the caller must ensure that there is sufficient space in the
2458+ * request queue and Tx Data FIFO.
2459+ *
2460+ * For an OUT transfer in Slave mode, it loads a data packet into the
2461+ * appropriate FIFO. If necessary, additional data packets will be loaded in
2462+ * the Host ISR.
2463+ *
2464+ * For an IN transfer in Slave mode, a data packet is requested. The data
2465+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
2466+ * additional data packets are requested in the Host ISR.
2467+ *
2468+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
2469+ * register along with a packet count of 1 and the channel is enabled. This
2470+ * causes a single PING transaction to occur. Other fields in HCTSIZ are
2471+ * simply set to 0 since no data transfer occurs in this case.
2472+ *
2473+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
2474+ * all the information required to perform the subsequent data transfer. In
2475+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
2476+ * controller performs the entire PING protocol, then starts the data
2477+ * transfer.
2478+ *
2479+ * @param _core_if Programming view of DWC_otg controller.
2480+ * @param _hc Information needed to initialize the host channel. The xfer_len
2481+ * value may be reduced to accommodate the max widths of the XferSize and
2482+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
2483+ * to reflect the final xfer_len value.
2484+ */
2485+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2486+{
2487+ hcchar_data_t hcchar;
2488+ hctsiz_data_t hctsiz;
2489+ uint16_t num_packets;
2490+ uint32_t max_hc_xfer_size = _core_if->core_params->max_transfer_size;
2491+ uint16_t max_hc_pkt_count = _core_if->core_params->max_packet_count;
2492+ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2493+
2494+ hctsiz.d32 = 0;
2495+
2496+ if (_hc->do_ping) {
2497+ if (!_core_if->dma_enable) {
2498+ dwc_otg_hc_do_ping(_core_if, _hc);
2499+ _hc->xfer_started = 1;
2500+ return;
2501+ } else {
2502+ hctsiz.b.dopng = 1;
2503+ }
2504+ }
2505+
2506+ if (_hc->do_split) {
2507+ num_packets = 1;
2508+
2509+ if (_hc->complete_split && !_hc->ep_is_in) {
2510+ /* For CSPLIT OUT Transfer, set the size to 0 so the
2511+ * core doesn't expect any data written to the FIFO */
2512+ _hc->xfer_len = 0;
2513+ } else if (_hc->ep_is_in || (_hc->xfer_len > _hc->max_packet)) {
2514+ _hc->xfer_len = _hc->max_packet;
2515+ } else if (!_hc->ep_is_in && (_hc->xfer_len > 188)) {
2516+ _hc->xfer_len = 188;
2517+ }
2518+
2519+ hctsiz.b.xfersize = _hc->xfer_len;
2520+ } else {
2521+ /*
2522+ * Ensure that the transfer length and packet count will fit
2523+ * in the widths allocated for them in the HCTSIZn register.
2524+ */
2525+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2526+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2527+ /*
2528+ * Make sure the transfer size is no larger than one
2529+ * (micro)frame's worth of data. (A check was done
2530+ * when the periodic transfer was accepted to ensure
2531+ * that a (micro)frame's worth of data can be
2532+ * programmed into a channel.)
2533+ */
2534+ uint32_t max_periodic_len = _hc->multi_count * _hc->max_packet;
2535+ if (_hc->xfer_len > max_periodic_len) {
2536+ _hc->xfer_len = max_periodic_len;
2537+ } else {
2538+ }
2539+ } else if (_hc->xfer_len > max_hc_xfer_size) {
2540+ /* Make sure that xfer_len is a multiple of max packet size. */
2541+ _hc->xfer_len = max_hc_xfer_size - _hc->max_packet + 1;
2542+ }
2543+
2544+ if (_hc->xfer_len > 0) {
2545+ num_packets = (_hc->xfer_len + _hc->max_packet - 1) / _hc->max_packet;
2546+ if (num_packets > max_hc_pkt_count) {
2547+ num_packets = max_hc_pkt_count;
2548+ _hc->xfer_len = num_packets * _hc->max_packet;
2549+ }
2550+ } else {
2551+ /* Need 1 packet for transfer length of 0. */
2552+ num_packets = 1;
2553+ }
2554+
2555+ if (_hc->ep_is_in) {
2556+ /* Always program an integral # of max packets for IN transfers. */
2557+ _hc->xfer_len = num_packets * _hc->max_packet;
2558+ }
2559+
2560+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2561+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2562+ /*
2563+ * Make sure that the multi_count field matches the
2564+ * actual transfer length.
2565+ */
2566+ _hc->multi_count = num_packets;
2567+
2568+ }
2569+
2570+ if (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2571+ /* Set up the initial PID for the transfer. */
2572+ if (_hc->speed == DWC_OTG_EP_SPEED_HIGH) {
2573+ if (_hc->ep_is_in) {
2574+ if (_hc->multi_count == 1) {
2575+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2576+ } else if (_hc->multi_count == 2) {
2577+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2578+ } else {
2579+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
2580+ }
2581+ } else {
2582+ if (_hc->multi_count == 1) {
2583+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2584+ } else {
2585+ _hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
2586+ }
2587+ }
2588+ } else {
2589+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2590+ }
2591+ }
2592+
2593+ hctsiz.b.xfersize = _hc->xfer_len;
2594+ }
2595+
2596+ _hc->start_pkt_count = num_packets;
2597+ hctsiz.b.pktcnt = num_packets;
2598+ hctsiz.b.pid = _hc->data_pid_start;
2599+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2600+
2601+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2602+ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
2603+ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
2604+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
2605+
2606+ if (_core_if->dma_enable) {
2607+#ifdef DEBUG
2608+if(((uint32_t)_hc->xfer_buff)%4)
2609+printk("dwc_otg_hc_start_transfer _hc->xfer_buff not 4 byte alignment\n");
2610+#endif
2611+ dwc_write_reg32(&hc_regs->hcdma, (uint32_t)_hc->xfer_buff);
2612+ }
2613+
2614+ /* Start the split */
2615+ if (_hc->do_split) {
2616+ hcsplt_data_t hcsplt;
2617+ hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt);
2618+ hcsplt.b.spltena = 1;
2619+ dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
2620+ }
2621+
2622+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2623+ hcchar.b.multicnt = _hc->multi_count;
2624+ hc_set_even_odd_frame(_core_if, _hc, &hcchar);
2625+#ifdef DEBUG
2626+ _core_if->start_hcchar_val[_hc->hc_num] = hcchar.d32;
2627+ if (hcchar.b.chdis) {
2628+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2629+ __func__, _hc->hc_num, hcchar.d32);
2630+ }
2631+#endif
2632+
2633+ /* Set host channel enable after all other setup is complete. */
2634+ hcchar.b.chen = 1;
2635+ hcchar.b.chdis = 0;
2636+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2637+
2638+ _hc->xfer_started = 1;
2639+ _hc->requests++;
2640+
2641+ if (!_core_if->dma_enable && !_hc->ep_is_in && _hc->xfer_len > 0) {
2642+ /* Load OUT packet into the appropriate Tx FIFO. */
2643+ dwc_otg_hc_write_packet(_core_if, _hc);
2644+ }
2645+
2646+#ifdef DEBUG
2647+ /* Start a timer for this transfer. */
2648+ _core_if->hc_xfer_timer[_hc->hc_num].function = hc_xfer_timeout;
2649+ _core_if->hc_xfer_info[_hc->hc_num].core_if = _core_if;
2650+ _core_if->hc_xfer_info[_hc->hc_num].hc = _hc;
2651+ _core_if->hc_xfer_timer[_hc->hc_num].data = (unsigned long)(&_core_if->hc_xfer_info[_hc->hc_num]);
2652+ _core_if->hc_xfer_timer[_hc->hc_num].expires = jiffies + (HZ*10);
2653+ add_timer(&_core_if->hc_xfer_timer[_hc->hc_num]);
2654+#endif
2655+}
2656+
2657+/**
2658+ * This function continues a data transfer that was started by previous call
2659+ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
2660+ * sufficient space in the request queue and Tx Data FIFO. This function
2661+ * should only be called in Slave mode. In DMA mode, the controller acts
2662+ * autonomously to complete transfers programmed to a host channel.
2663+ *
2664+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
2665+ * if there is any data remaining to be queued. For an IN transfer, another
2666+ * data packet is always requested. For the SETUP phase of a control transfer,
2667+ * this function does nothing.
2668+ *
2669+ * @return 1 if a new request is queued, 0 if no more requests are required
2670+ * for this transfer.
2671+ */
2672+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2673+{
2674+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2675+
2676+ if (_hc->do_split) {
2677+ /* SPLITs always queue just once per channel */
2678+ return 0;
2679+ } else if (_hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2680+ /* SETUPs are queued only once since they can't be NAKed. */
2681+ return 0;
2682+ } else if (_hc->ep_is_in) {
2683+ /*
2684+ * Always queue another request for other IN transfers. If
2685+ * back-to-back INs are issued and NAKs are received for both,
2686+ * the driver may still be processing the first NAK when the
2687+ * second NAK is received. When the interrupt handler clears
2688+ * the NAK interrupt for the first NAK, the second NAK will
2689+ * not be seen. So we can't depend on the NAK interrupt
2690+ * handler to requeue a NAKed request. Instead, IN requests
2691+ * are issued each time this function is called. When the
2692+ * transfer completes, the extra requests for the channel will
2693+ * be flushed.
2694+ */
2695+ hcchar_data_t hcchar;
2696+ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2697+
2698+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2699+ hc_set_even_odd_frame(_core_if, _hc, &hcchar);
2700+ hcchar.b.chen = 1;
2701+ hcchar.b.chdis = 0;
2702+ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32);
2703+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2704+ _hc->requests++;
2705+ return 1;
2706+ } else {
2707+ /* OUT transfers. */
2708+ if (_hc->xfer_count < _hc->xfer_len) {
2709+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2710+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2711+ hcchar_data_t hcchar;
2712+ dwc_otg_hc_regs_t *hc_regs;
2713+ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2714+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2715+ hc_set_even_odd_frame(_core_if, _hc, &hcchar);
2716+ }
2717+
2718+ /* Load OUT packet into the appropriate Tx FIFO. */
2719+ dwc_otg_hc_write_packet(_core_if, _hc);
2720+ _hc->requests++;
2721+ return 1;
2722+ } else {
2723+ return 0;
2724+ }
2725+ }
2726+}
2727+
2728+/**
2729+ * Starts a PING transfer. This function should only be called in Slave mode.
2730+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
2731+ */
2732+void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2733+{
2734+ hcchar_data_t hcchar;
2735+ hctsiz_data_t hctsiz;
2736+ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num];
2737+
2738+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num);
2739+
2740+ hctsiz.d32 = 0;
2741+ hctsiz.b.dopng = 1;
2742+ hctsiz.b.pktcnt = 1;
2743+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2744+
2745+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2746+ hcchar.b.chen = 1;
2747+ hcchar.b.chdis = 0;
2748+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2749+}
2750+
2751+/*
2752+ * This function writes a packet into the Tx FIFO associated with the Host
2753+ * Channel. For a channel associated with a non-periodic EP, the non-periodic
2754+ * Tx FIFO is written. For a channel associated with a periodic EP, the
2755+ * periodic Tx FIFO is written. This function should only be called in Slave
2756+ * mode.
2757+ *
2758+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
2759+ * then number of bytes written to the Tx FIFO.
2760+ */
2761+void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
2762+{
2763+ uint32_t i;
2764+ uint32_t remaining_count;
2765+ uint32_t byte_count;
2766+ uint32_t dword_count;
2767+
2768+ uint32_t *data_buff = (uint32_t *)(_hc->xfer_buff);
2769+ uint32_t *data_fifo = _core_if->data_fifo[_hc->hc_num];
2770+
2771+ remaining_count = _hc->xfer_len - _hc->xfer_count;
2772+ if (remaining_count > _hc->max_packet) {
2773+ byte_count = _hc->max_packet;
2774+ } else {
2775+ byte_count = remaining_count;
2776+ }
2777+
2778+ dword_count = (byte_count + 3) / 4;
2779+
2780+ if ((((unsigned long)data_buff) & 0x3) == 0) {
2781+ /* xfer_buff is DWORD aligned. */
2782+ for (i = 0; i < dword_count; i++, data_buff++) {
2783+ dwc_write_reg32(data_fifo, *data_buff);
2784+ }
2785+ } else {
2786+ /* xfer_buff is not DWORD aligned. */
2787+ for (i = 0; i < dword_count; i++, data_buff++) {
2788+ dwc_write_reg32(data_fifo, get_unaligned(data_buff));
2789+ }
2790+ }
2791+
2792+ _hc->xfer_count += byte_count;
2793+ _hc->xfer_buff += byte_count;
2794+}
2795+
2796+/**
2797+ * Gets the current USB frame number. This is the frame number from the last
2798+ * SOF packet.
2799+ */
2800+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if)
2801+{
2802+ dsts_data_t dsts;
2803+ dsts.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts);
2804+
2805+ /* read current frame/microfreme number from DSTS register */
2806+ return dsts.b.soffn;
2807+}
2808+
2809+/**
2810+ * This function reads a setup packet from the Rx FIFO into the destination
2811+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
2812+ * Interrupt routine when a SETUP packet has been received in Slave mode.
2813+ *
2814+ * @param _core_if Programming view of DWC_otg controller.
2815+ * @param _dest Destination buffer for packet data.
2816+ */
2817+void dwc_otg_read_setup_packet(dwc_otg_core_if_t *_core_if, uint32_t *_dest)
2818+{
2819+ /* Get the 8 bytes of a setup transaction data */
2820+
2821+ /* Pop 2 DWORDS off the receive data FIFO into memory */
2822+ _dest[0] = dwc_read_reg32(_core_if->data_fifo[0]);
2823+ _dest[1] = dwc_read_reg32(_core_if->data_fifo[0]);
2824+ //_dest[0] = dwc_read_datafifo32(_core_if->data_fifo[0]);
2825+ //_dest[1] = dwc_read_datafifo32(_core_if->data_fifo[0]);
2826+}
2827+
2828+
2829+/**
2830+ * This function enables EP0 OUT to receive SETUP packets and configures EP0
2831+ * IN for transmitting packets. It is normally called when the
2832+ * "Enumeration Done" interrupt occurs.
2833+ *
2834+ * @param _core_if Programming view of DWC_otg controller.
2835+ * @param _ep The EP0 data.
2836+ */
2837+void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2838+{
2839+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
2840+ dsts_data_t dsts;
2841+ depctl_data_t diepctl;
2842+ depctl_data_t doepctl;
2843+ dctl_data_t dctl ={.d32=0};
2844+
2845+ /* Read the Device Status and Endpoint 0 Control registers */
2846+ dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
2847+ diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
2848+ doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
2849+
2850+ /* Set the MPS of the IN EP based on the enumeration speed */
2851+ switch (dsts.b.enumspd) {
2852+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
2853+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
2854+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
2855+ diepctl.b.mps = DWC_DEP0CTL_MPS_64;
2856+ break;
2857+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
2858+ diepctl.b.mps = DWC_DEP0CTL_MPS_8;
2859+ break;
2860+ }
2861+
2862+ dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
2863+
2864+ /* Enable OUT EP for receive */
2865+ doepctl.b.epena = 1;
2866+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
2867+
2868+#ifdef VERBOSE
2869+ DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n",
2870+ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
2871+ DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n",
2872+ dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
2873+#endif
2874+ dctl.b.cgnpinnak = 1;
2875+ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
2876+ DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n",
2877+ dwc_read_reg32(&dev_if->dev_global_regs->dctl));
2878+}
2879+
2880+/**
2881+ * This function activates an EP. The Device EP control register for
2882+ * the EP is configured as defined in the ep structure. Note: This
2883+ * function is not used for EP0.
2884+ *
2885+ * @param _core_if Programming view of DWC_otg controller.
2886+ * @param _ep The EP to activate.
2887+ */
2888+void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2889+{
2890+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
2891+ depctl_data_t depctl;
2892+ volatile uint32_t *addr;
2893+ daint_data_t daintmsk = {.d32=0};
2894+
2895+ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, _ep->num,
2896+ (_ep->is_in?"IN":"OUT"));
2897+
2898+ /* Read DEPCTLn register */
2899+ if (_ep->is_in == 1) {
2900+ addr = &dev_if->in_ep_regs[_ep->num]->diepctl;
2901+ daintmsk.ep.in = 1<<_ep->num;
2902+ } else {
2903+ addr = &dev_if->out_ep_regs[_ep->num]->doepctl;
2904+ daintmsk.ep.out = 1<<_ep->num;
2905+ }
2906+
2907+ /* If the EP is already active don't change the EP Control
2908+ * register. */
2909+ depctl.d32 = dwc_read_reg32(addr);
2910+ if (!depctl.b.usbactep) {
2911+ depctl.b.mps = _ep->maxpacket;
2912+ depctl.b.eptype = _ep->type;
2913+ depctl.b.txfnum = _ep->tx_fifo_num;
2914+
2915+ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
2916+ depctl.b.setd0pid = 1; // ???
2917+ } else {
2918+ depctl.b.setd0pid = 1;
2919+ }
2920+ depctl.b.usbactep = 1;
2921+
2922+ dwc_write_reg32(addr, depctl.d32);
2923+ DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr));
2924+ }
2925+
2926+
2927+ /* Enable the Interrupt for this EP */
2928+ dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
2929+ 0, daintmsk.d32);
2930+ DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n",
2931+ dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
2932+ _ep->stall_clear_flag = 0;
2933+ return;
2934+}
2935+
2936+/**
2937+ * This function deactivates an EP. This is done by clearing the USB Active
2938+ * EP bit in the Device EP control register. Note: This function is not used
2939+ * for EP0. EP0 cannot be deactivated.
2940+ *
2941+ * @param _core_if Programming view of DWC_otg controller.
2942+ * @param _ep The EP to deactivate.
2943+ */
2944+void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2945+{
2946+ depctl_data_t depctl ={.d32 = 0};
2947+ volatile uint32_t *addr;
2948+ daint_data_t daintmsk = {.d32=0};
2949+
2950+ /* Read DEPCTLn register */
2951+ if (_ep->is_in == 1) {
2952+ addr = &_core_if->dev_if->in_ep_regs[_ep->num]->diepctl;
2953+ daintmsk.ep.in = 1<<_ep->num;
2954+ } else {
2955+ addr = &_core_if->dev_if->out_ep_regs[_ep->num]->doepctl;
2956+ daintmsk.ep.out = 1<<_ep->num;
2957+ }
2958+
2959+ depctl.b.usbactep = 0;
2960+ dwc_write_reg32(addr, depctl.d32);
2961+
2962+ /* Disable the Interrupt for this EP */
2963+ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->daintmsk,
2964+ daintmsk.d32, 0);
2965+
2966+ return;
2967+}
2968+
2969+/**
2970+ * This function does the setup for a data transfer for an EP and
2971+ * starts the transfer. For an IN transfer, the packets will be
2972+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
2973+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
2974+ *
2975+ * @param _core_if Programming view of DWC_otg controller.
2976+ * @param _ep The EP to start the transfer on.
2977+ */
2978+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
2979+{
2980+ /** @todo Refactor this funciton to check the transfer size
2981+ * count value does not execed the number bits in the Transfer
2982+ * count register. */
2983+ depctl_data_t depctl;
2984+ deptsiz_data_t deptsiz;
2985+ gintmsk_data_t intr_mask = { .d32 = 0};
2986+
2987+#ifdef CHECK_PACKET_COUNTER_WIDTH
2988+ const uint32_t MAX_XFER_SIZE =
2989+ _core_if->core_params->max_transfer_size;
2990+ const uint32_t MAX_PKT_COUNT =
2991+ _core_if->core_params->max_packet_count;
2992+ uint32_t num_packets;
2993+ uint32_t transfer_len;
2994+ dwc_otg_dev_out_ep_regs_t *out_regs =
2995+ _core_if->dev_if->out_ep_regs[_ep->num];
2996+ dwc_otg_dev_in_ep_regs_t *in_regs =
2997+ _core_if->dev_if->in_ep_regs[_ep->num];
2998+ gnptxsts_data_t txstatus;
2999+
3000+ int lvl = SET_DEBUG_LEVEL(DBG_PCD);
3001+
3002+
3003+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3004+ "xfer_buff=%p start_xfer_buff=%p\n",
3005+ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
3006+ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff);
3007+
3008+ transfer_len = _ep->xfer_len - _ep->xfer_count;
3009+ if (transfer_len > MAX_XFER_SIZE) {
3010+ transfer_len = MAX_XFER_SIZE;
3011+ }
3012+ if (transfer_len == 0) {
3013+ num_packets = 1;
3014+ /* OUT EP to recieve Zero-length packet set transfer
3015+ * size to maxpacket size. */
3016+ if (!_ep->is_in) {
3017+ transfer_len = _ep->maxpacket;
3018+ }
3019+ } else {
3020+ num_packets =
3021+ (transfer_len + _ep->maxpacket - 1) / _ep->maxpacket;
3022+ if (num_packets > MAX_PKT_COUNT) {
3023+ num_packets = MAX_PKT_COUNT;
3024+ }
3025+ }
3026+ DWC_DEBUGPL(DBG_PCD, "transfer_len=%d #pckt=%d\n", transfer_len,
3027+ num_packets);
3028+
3029+ deptsiz.b.xfersize = transfer_len;
3030+ deptsiz.b.pktcnt = num_packets;
3031+
3032+ /* IN endpoint */
3033+ if (_ep->is_in == 1) {
3034+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3035+ } else {/* OUT endpoint */
3036+ depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
3037+ }
3038+
3039+ /* EP enable, IN data in FIFO */
3040+ depctl.b.cnak = 1;
3041+ depctl.b.epena = 1;
3042+ /* IN endpoint */
3043+ if (_ep->is_in == 1) {
3044+ txstatus.d32 =
3045+ dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
3046+ if (txstatus.b.nptxqspcavail == 0) {
3047+ DWC_DEBUGPL(DBG_ANY, "TX Queue Full (0x%0x)\n",
3048+ txstatus.d32);
3049+ return;
3050+ }
3051+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3052+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3053+ /**
3054+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
3055+ * data will be written into the fifo by the ISR.
3056+ */
3057+ if (_core_if->dma_enable) {
3058+ dwc_write_reg32(&in_regs->diepdma, (uint32_t) _ep->xfer_buff);
3059+ } else {
3060+ if (_core_if->en_multiple_tx_fifo == 0) {
3061+ intr_mask.b.nptxfempty = 1;
3062+ dwc_modify_reg32( &_core_if->core_global_regs->gintsts,
3063+ intr_mask.d32, 0);
3064+ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
3065+ intr_mask.d32, intr_mask.d32);
3066+ } else {
3067+ /* Enable the Tx FIFO Empty Interrupt for this EP */
3068+ if (_ep->xfer_len > 0 &&
3069+ _ep->type != DWC_OTG_EP_TYPE_ISOC) {
3070+ uint32_t fifoemptymsk = 0;
3071+ fifoemptymsk = (0x1 << _ep->num);
3072+ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->
3073+ dtknqr4_fifoemptymsk,0, fifoemptymsk);
3074+ }
3075+ }
3076+ }
3077+ } else { /* OUT endpoint */
3078+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3079+ dwc_write_reg32(&out_regs->doepctl, depctl.d32);
3080+ if (_core_if->dma_enable) {
3081+ dwc_write_reg32(&out_regs->doepdma,(uint32_t) _ep->xfer_buff);
3082+ }
3083+ }
3084+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
3085+ dwc_read_reg32(&out_regs->doepctl),
3086+ dwc_read_reg32(&out_regs->doeptsiz));
3087+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3088+ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk),
3089+ dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
3090+
3091+ SET_DEBUG_LEVEL(lvl);
3092+#endif
3093+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
3094+
3095+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3096+ "xfer_buff=%p start_xfer_buff=%p\n",
3097+ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
3098+ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff);
3099+
3100+ /* IN endpoint */
3101+ if (_ep->is_in == 1) {
3102+ dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[_ep->num];
3103+ gnptxsts_data_t gtxstatus;
3104+ gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
3105+ if (_core_if->en_multiple_tx_fifo == 0 &&
3106+ gtxstatus.b.nptxqspcavail == 0) {
3107+#ifdef DEBUG
3108+ DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32);
3109+#endif
3110+ //return;
3111+ MDELAY(100); //james
3112+ }
3113+
3114+ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
3115+ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
3116+
3117+ /* Zero Length Packet? */
3118+ if (_ep->xfer_len == 0) {
3119+ deptsiz.b.xfersize = 0;
3120+ deptsiz.b.pktcnt = 1;
3121+ } else {
3122+
3123+ /* Program the transfer size and packet count
3124+ * as follows: xfersize = N * maxpacket +
3125+ * short_packet pktcnt = N + (short_packet
3126+ * exist ? 1 : 0)
3127+ */
3128+ deptsiz.b.xfersize = _ep->xfer_len;
3129+ deptsiz.b.pktcnt = (_ep->xfer_len - 1 + _ep->maxpacket) / _ep->maxpacket;
3130+ }
3131+
3132+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3133+
3134+ /* Write the DMA register */
3135+ if (_core_if->dma_enable) {
3136+#if 1 // winder
3137+ dma_cache_wback_inv((unsigned long) _ep->xfer_buff, _ep->xfer_len); // winder
3138+ dwc_write_reg32 (&(in_regs->diepdma),
3139+ CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder
3140+#else
3141+ dwc_write_reg32 (&(in_regs->diepdma),
3142+ (uint32_t)_ep->dma_addr);
3143+#endif
3144+ } else {
3145+ if (_ep->type != DWC_OTG_EP_TYPE_ISOC) {
3146+ /**
3147+ * Enable the Non-Periodic Tx FIFO empty interrupt,
3148+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
3149+ * the data will be written into the fifo by the ISR.
3150+ */
3151+ if (_core_if->en_multiple_tx_fifo == 0) {
3152+ intr_mask.b.nptxfempty = 1;
3153+ dwc_modify_reg32( &_core_if->core_global_regs->gintsts,
3154+ intr_mask.d32, 0);
3155+ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
3156+ intr_mask.d32, intr_mask.d32);
3157+ } else {
3158+ /* Enable the Tx FIFO Empty Interrupt for this EP */
3159+ if (_ep->xfer_len > 0) {
3160+ uint32_t fifoemptymsk = 0;
3161+ fifoemptymsk = 1 << _ep->num;
3162+ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->
3163+ dtknqr4_fifoemptymsk,0,fifoemptymsk);
3164+ }
3165+ }
3166+ }
3167+ }
3168+
3169+ /* EP enable, IN data in FIFO */
3170+ depctl.b.cnak = 1;
3171+ depctl.b.epena = 1;
3172+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3173+
3174+ if (_core_if->dma_enable) {
3175+ depctl.d32 = dwc_read_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl);
3176+ depctl.b.nextep = _ep->num;
3177+ dwc_write_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32);
3178+
3179+ }
3180+ } else {
3181+ /* OUT endpoint */
3182+ dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num];
3183+
3184+ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
3185+ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
3186+
3187+ /* Program the transfer size and packet count as follows:
3188+ *
3189+ * pktcnt = N
3190+ * xfersize = N * maxpacket
3191+ */
3192+ if (_ep->xfer_len == 0) {
3193+ /* Zero Length Packet */
3194+ deptsiz.b.xfersize = _ep->maxpacket;
3195+ deptsiz.b.pktcnt = 1;
3196+ } else {
3197+ deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket;
3198+ deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket;
3199+ }
3200+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3201+
3202+ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
3203+ _ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
3204+
3205+ if (_core_if->dma_enable) {
3206+#if 1 // winder
3207+ dwc_write_reg32 (&(out_regs->doepdma),
3208+ CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder
3209+#else
3210+ dwc_write_reg32 (&(out_regs->doepdma),
3211+ (uint32_t)_ep->dma_addr);
3212+#endif
3213+ }
3214+
3215+ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
3216+ /** @todo NGS: dpid is read-only. Use setd0pid
3217+ * or setd1pid. */
3218+ if (_ep->even_odd_frame) {
3219+ depctl.b.setd1pid = 1;
3220+ } else {
3221+ depctl.b.setd0pid = 1;
3222+ }
3223+ }
3224+
3225+ /* EP enable */
3226+ depctl.b.cnak = 1;
3227+ depctl.b.epena = 1;
3228+
3229+ dwc_write_reg32(&out_regs->doepctl, depctl.d32);
3230+
3231+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
3232+ dwc_read_reg32(&out_regs->doepctl),
3233+ dwc_read_reg32(&out_regs->doeptsiz));
3234+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
3235+ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk),
3236+ dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
3237+ }
3238+}
3239+
3240+
3241+/**
3242+ * This function does the setup for a data transfer for EP0 and starts
3243+ * the transfer. For an IN transfer, the packets will be loaded into
3244+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
3245+ * unloaded from the Rx FIFO in the ISR.
3246+ *
3247+ * @param _core_if Programming view of DWC_otg controller.
3248+ * @param _ep The EP0 data.
3249+ */
3250+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3251+{
3252+ volatile depctl_data_t depctl;
3253+ volatile deptsiz0_data_t deptsiz;
3254+ gintmsk_data_t intr_mask = { .d32 = 0};
3255+
3256+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3257+ "xfer_buff=%p start_xfer_buff=%p total_len=%d\n",
3258+ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len,
3259+ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff,
3260+ _ep->total_len);
3261+ _ep->total_len = _ep->xfer_len;
3262+
3263+ /* IN endpoint */
3264+ if (_ep->is_in == 1) {
3265+ dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[0];
3266+ gnptxsts_data_t gtxstatus;
3267+ gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
3268+ if (_core_if->en_multiple_tx_fifo == 0 &&
3269+ gtxstatus.b.nptxqspcavail == 0) {
3270+#ifdef DEBUG
3271+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3272+ DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n",
3273+ dwc_read_reg32(&in_regs->diepctl));
3274+ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
3275+ deptsiz.d32, deptsiz.b.xfersize,deptsiz.b.pktcnt);
3276+ DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n", gtxstatus.d32);
3277+#endif /* */
3278+ printk("TX Queue or FIFO Full!!!!\n"); // test-only
3279+ //return;
3280+ MDELAY(100); //james
3281+ }
3282+
3283+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3284+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3285+
3286+ /* Zero Length Packet? */
3287+ if (_ep->xfer_len == 0) {
3288+ deptsiz.b.xfersize = 0;
3289+ deptsiz.b.pktcnt = 1;
3290+ } else {
3291+ /* Program the transfer size and packet count
3292+ * as follows: xfersize = N * maxpacket +
3293+ * short_packet pktcnt = N + (short_packet
3294+ * exist ? 1 : 0)
3295+ */
3296+ if (_ep->xfer_len > _ep->maxpacket) {
3297+ _ep->xfer_len = _ep->maxpacket;
3298+ deptsiz.b.xfersize = _ep->maxpacket;
3299+ }
3300+ else {
3301+ deptsiz.b.xfersize = _ep->xfer_len;
3302+ }
3303+ deptsiz.b.pktcnt = 1;
3304+
3305+ }
3306+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3307+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
3308+ _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt, deptsiz.d32);
3309+
3310+ /* Write the DMA register */
3311+ if (_core_if->dma_enable) {
3312+ dwc_write_reg32(&(in_regs->diepdma), (uint32_t) _ep->dma_addr);
3313+ }
3314+
3315+ /* EP enable, IN data in FIFO */
3316+ depctl.b.cnak = 1;
3317+ depctl.b.epena = 1;
3318+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3319+
3320+ /**
3321+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
3322+ * data will be written into the fifo by the ISR.
3323+ */
3324+ if (!_core_if->dma_enable) {
3325+ if (_core_if->en_multiple_tx_fifo == 0) {
3326+ intr_mask.b.nptxfempty = 1;
3327+ dwc_modify_reg32(&_core_if->core_global_regs->gintsts, intr_mask.d32, 0);
3328+ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, intr_mask.d32,
3329+ intr_mask.d32);
3330+ } else {
3331+ /* Enable the Tx FIFO Empty Interrupt for this EP */
3332+ if (_ep->xfer_len > 0) {
3333+ uint32_t fifoemptymsk = 0;
3334+ fifoemptymsk |= 1 << _ep->num;
3335+ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3336+ 0, fifoemptymsk);
3337+ }
3338+
3339+ }
3340+ }
3341+ } else {
3342+ /* OUT endpoint */
3343+ dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num];
3344+
3345+ depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
3346+ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
3347+
3348+ /* Program the transfer size and packet count as follows:
3349+ * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
3350+ * pktcnt = N */
3351+ if (_ep->xfer_len == 0) {
3352+ /* Zero Length Packet */
3353+ deptsiz.b.xfersize = _ep->maxpacket;
3354+ deptsiz.b.pktcnt = 1;
3355+ } else {
3356+ deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket;
3357+ deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket;
3358+ }
3359+
3360+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
3361+ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
3362+ _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt);
3363+
3364+ if (_core_if->dma_enable) {
3365+ dwc_write_reg32(&(out_regs->doepdma), (uint32_t) _ep->dma_addr);
3366+ }
3367+
3368+ /* EP enable */
3369+ depctl.b.cnak = 1;
3370+ depctl.b.epena = 1;
3371+ dwc_write_reg32 (&(out_regs->doepctl), depctl.d32);
3372+ }
3373+}
3374+
3375+/**
3376+ * This function continues control IN transfers started by
3377+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
3378+ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
3379+ * bit for the packet count.
3380+ *
3381+ * @param _core_if Programming view of DWC_otg controller.
3382+ * @param _ep The EP0 data.
3383+ */
3384+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3385+{
3386+ depctl_data_t depctl;
3387+ deptsiz0_data_t deptsiz;
3388+ gintmsk_data_t intr_mask = { .d32 = 0};
3389+
3390+ if (_ep->is_in == 1) {
3391+ dwc_otg_dev_in_ep_regs_t *in_regs =
3392+ _core_if->dev_if->in_ep_regs[0];
3393+ gnptxsts_data_t tx_status = {.d32 = 0};
3394+
3395+ tx_status.d32 = dwc_read_reg32( &_core_if->core_global_regs->gnptxsts );
3396+ /** @todo Should there be check for room in the Tx
3397+ * Status Queue. If not remove the code above this comment. */
3398+
3399+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
3400+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
3401+
3402+ /* Program the transfer size and packet count
3403+ * as follows: xfersize = N * maxpacket +
3404+ * short_packet pktcnt = N + (short_packet
3405+ * exist ? 1 : 0)
3406+ */
3407+ deptsiz.b.xfersize = (_ep->total_len - _ep->xfer_count) > _ep->maxpacket ? _ep->maxpacket :
3408+ (_ep->total_len - _ep->xfer_count);
3409+ deptsiz.b.pktcnt = 1;
3410+ _ep->xfer_len += deptsiz.b.xfersize;
3411+
3412+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
3413+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
3414+ _ep->xfer_len,
3415+ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32);
3416+
3417+ /* Write the DMA register */
3418+ if (_core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
3419+ dwc_write_reg32 (&(in_regs->diepdma),
3420+ CPHYSADDR((uint32_t)_ep->dma_addr)); // winder
3421+ }
3422+
3423+ /* EP enable, IN data in FIFO */
3424+ depctl.b.cnak = 1;
3425+ depctl.b.epena = 1;
3426+ dwc_write_reg32(&in_regs->diepctl, depctl.d32);
3427+
3428+ /**
3429+ * Enable the Non-Periodic Tx FIFO empty interrupt, the
3430+ * data will be written into the fifo by the ISR.
3431+ */
3432+ if (!_core_if->dma_enable) {
3433+ /* First clear it from GINTSTS */
3434+ intr_mask.b.nptxfempty = 1;
3435+ dwc_write_reg32( &_core_if->core_global_regs->gintsts,
3436+ intr_mask.d32 );
3437+
3438+ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk,
3439+ intr_mask.d32, intr_mask.d32);
3440+ }
3441+
3442+ }
3443+
3444+}
3445+
3446+#ifdef DEBUG
3447+void dump_msg(const u8 *buf, unsigned int length)
3448+{
3449+ unsigned int start, num, i;
3450+ char line[52], *p;
3451+
3452+ if (length >= 512)
3453+ return;
3454+ start = 0;
3455+ while (length > 0) {
3456+ num = min(length, 16u);
3457+ p = line;
3458+ for (i = 0; i < num; ++i) {
3459+ if (i == 8)
3460+ *p++ = ' ';
3461+ sprintf(p, " %02x", buf[i]);
3462+ p += 3;
3463+ }
3464+ *p = 0;
3465+ DWC_PRINT( "%6x: %s\n", start, line);
3466+ buf += num;
3467+ start += num;
3468+ length -= num;
3469+ }
3470+}
3471+#else
3472+static inline void dump_msg(const u8 *buf, unsigned int length)
3473+{
3474+}
3475+#endif
3476+
3477+/**
3478+ * This function writes a packet into the Tx FIFO associated with the
3479+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
3480+ * periodic EPs the periodic Tx FIFO associated with the EP is written
3481+ * with all packets for the next micro-frame.
3482+ *
3483+ * @param _core_if Programming view of DWC_otg controller.
3484+ * @param _ep The EP to write packet for.
3485+ * @param _dma Indicates if DMA is being used.
3486+ */
3487+void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)
3488+{
3489+ /**
3490+ * The buffer is padded to DWORD on a per packet basis in
3491+ * slave/dma mode if the MPS is not DWORD aligned. The last
3492+ * packet, if short, is also padded to a multiple of DWORD.
3493+ *
3494+ * ep->xfer_buff always starts DWORD aligned in memory and is a
3495+ * multiple of DWORD in length
3496+ *
3497+ * ep->xfer_len can be any number of bytes
3498+ *
3499+ * ep->xfer_count is a multiple of ep->maxpacket until the last
3500+ * packet
3501+ *
3502+ * FIFO access is DWORD */
3503+
3504+ uint32_t i;
3505+ uint32_t byte_count;
3506+ uint32_t dword_count;
3507+ uint32_t *fifo;
3508+ uint32_t *data_buff = (uint32_t *)_ep->xfer_buff;
3509+
3510+ //DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, _core_if, _ep);
3511+ if (_ep->xfer_count >= _ep->xfer_len) {
3512+ DWC_WARN("%s() No data for EP%d!!!\n", __func__, _ep->num);
3513+ return;
3514+ }
3515+
3516+ /* Find the byte length of the packet either short packet or MPS */
3517+ if ((_ep->xfer_len - _ep->xfer_count) < _ep->maxpacket) {
3518+ byte_count = _ep->xfer_len - _ep->xfer_count;
3519+ }
3520+ else {
3521+ byte_count = _ep->maxpacket;
3522+ }
3523+
3524+ /* Find the DWORD length, padded by extra bytes as neccessary if MPS
3525+ * is not a multiple of DWORD */
3526+ dword_count = (byte_count + 3) / 4;
3527+
3528+#ifdef VERBOSE
3529+ dump_msg(_ep->xfer_buff, byte_count);
3530+#endif
3531+ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) {
3532+ /**@todo NGS Where are the Periodic Tx FIFO addresses
3533+ * intialized? What should this be? */
3534+ fifo = _core_if->data_fifo[_ep->tx_fifo_num];
3535+ } else {
3536+ fifo = _core_if->data_fifo[_ep->num];
3537+ }
3538+
3539+ DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
3540+ fifo, data_buff, *data_buff, byte_count);
3541+
3542+
3543+ if (!_dma) {
3544+ for (i=0; i<dword_count; i++, data_buff++) {
3545+ dwc_write_reg32( fifo, *data_buff );
3546+ }
3547+ }
3548+
3549+ _ep->xfer_count += byte_count;
3550+ _ep->xfer_buff += byte_count;
3551+#if 1 // winder, why do we need this??
3552+ _ep->dma_addr += byte_count;
3553+#endif
3554+}
3555+
3556+/**
3557+ * Set the EP STALL.
3558+ *
3559+ * @param _core_if Programming view of DWC_otg controller.
3560+ * @param _ep The EP to set the stall on.
3561+ */
3562+void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3563+{
3564+ depctl_data_t depctl;
3565+ volatile uint32_t *depctl_addr;
3566+
3567+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num,
3568+ (_ep->is_in?"IN":"OUT"));
3569+
3570+ if (_ep->is_in == 1) {
3571+ depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl);
3572+ depctl.d32 = dwc_read_reg32(depctl_addr);
3573+
3574+ /* set the disable and stall bits */
3575+ if (depctl.b.epena) {
3576+ depctl.b.epdis = 1;
3577+ }
3578+ depctl.b.stall = 1;
3579+ dwc_write_reg32(depctl_addr, depctl.d32);
3580+
3581+ } else {
3582+ depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl);
3583+ depctl.d32 = dwc_read_reg32(depctl_addr);
3584+
3585+ /* set the stall bit */
3586+ depctl.b.stall = 1;
3587+ dwc_write_reg32(depctl_addr, depctl.d32);
3588+ }
3589+ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
3590+ return;
3591+}
3592+
3593+/**
3594+ * Clear the EP STALL.
3595+ *
3596+ * @param _core_if Programming view of DWC_otg controller.
3597+ * @param _ep The EP to clear stall from.
3598+ */
3599+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
3600+{
3601+ depctl_data_t depctl;
3602+ volatile uint32_t *depctl_addr;
3603+
3604+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num,
3605+ (_ep->is_in?"IN":"OUT"));
3606+
3607+ if (_ep->is_in == 1) {
3608+ depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl);
3609+ } else {
3610+ depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl);
3611+ }
3612+
3613+ depctl.d32 = dwc_read_reg32(depctl_addr);
3614+
3615+ /* clear the stall bits */
3616+ depctl.b.stall = 0;
3617+
3618+ /*
3619+ * USB Spec 9.4.5: For endpoints using data toggle, regardless
3620+ * of whether an endpoint has the Halt feature set, a
3621+ * ClearFeature(ENDPOINT_HALT) request always results in the
3622+ * data toggle being reinitialized to DATA0.
3623+ */
3624+ if (_ep->type == DWC_OTG_EP_TYPE_INTR ||
3625+ _ep->type == DWC_OTG_EP_TYPE_BULK) {
3626+ depctl.b.setd0pid = 1; /* DATA0 */
3627+ }
3628+
3629+ dwc_write_reg32(depctl_addr, depctl.d32);
3630+ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr));
3631+ return;
3632+}
3633+
3634+/**
3635+ * This function reads a packet from the Rx FIFO into the destination
3636+ * buffer. To read SETUP data use dwc_otg_read_setup_packet.
3637+ *
3638+ * @param _core_if Programming view of DWC_otg controller.
3639+ * @param _dest Destination buffer for the packet.
3640+ * @param _bytes Number of bytes to copy to the destination.
3641+ */
3642+void dwc_otg_read_packet(dwc_otg_core_if_t *_core_if,
3643+ uint8_t *_dest,
3644+ uint16_t _bytes)
3645+{
3646+ int i;
3647+ int word_count = (_bytes + 3) / 4;
3648+
3649+ volatile uint32_t *fifo = _core_if->data_fifo[0];
3650+ uint32_t *data_buff = (uint32_t *)_dest;
3651+
3652+ /**
3653+ * @todo Account for the case where _dest is not dword aligned. This
3654+ * requires reading data from the FIFO into a uint32_t temp buffer,
3655+ * then moving it into the data buffer.
3656+ */
3657+
3658+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
3659+ _core_if, _dest, _bytes);
3660+
3661+ for (i=0; i<word_count; i++, data_buff++) {
3662+ *data_buff = dwc_read_reg32(fifo);
3663+ }
3664+
3665+ return;
3666+}
3667+
3668+
3669+#ifdef DEBUG
3670+/**
3671+ * This functions reads the device registers and prints them
3672+ *
3673+ * @param _core_if Programming view of DWC_otg controller.
3674+ */
3675+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if)
3676+{
3677+ int i;
3678+ volatile uint32_t *addr;
3679+
3680+ DWC_PRINT("Device Global Registers\n");
3681+ addr=&_core_if->dev_if->dev_global_regs->dcfg;
3682+ DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3683+ addr=&_core_if->dev_if->dev_global_regs->dctl;
3684+ DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3685+ addr=&_core_if->dev_if->dev_global_regs->dsts;
3686+ DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3687+ addr=&_core_if->dev_if->dev_global_regs->diepmsk;
3688+ DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3689+ addr=&_core_if->dev_if->dev_global_regs->doepmsk;
3690+ DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3691+ addr=&_core_if->dev_if->dev_global_regs->daint;
3692+ DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3693+ addr=&_core_if->dev_if->dev_global_regs->dtknqr1;
3694+ DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3695+ if (_core_if->hwcfg2.b.dev_token_q_depth > 6) {
3696+ addr=&_core_if->dev_if->dev_global_regs->dtknqr2;
3697+ DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n",
3698+ (uint32_t)addr,dwc_read_reg32(addr));
3699+ }
3700+
3701+ addr=&_core_if->dev_if->dev_global_regs->dvbusdis;
3702+ DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3703+
3704+ addr=&_core_if->dev_if->dev_global_regs->dvbuspulse;
3705+ DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n",
3706+ (uint32_t)addr,dwc_read_reg32(addr));
3707+
3708+ if (_core_if->hwcfg2.b.dev_token_q_depth > 14) {
3709+ addr = &_core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
3710+ DWC_PRINT("DTKNQR3 @0x%08X : 0x%08X\n",
3711+ (uint32_t)addr, dwc_read_reg32(addr));
3712+ }
3713+
3714+ if (_core_if->hwcfg2.b.dev_token_q_depth > 22) {
3715+ addr = &_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
3716+ DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t) addr,
3717+ dwc_read_reg32(addr));
3718+ }
3719+ for (i = 0; i <= _core_if->dev_if->num_in_eps; i++) {
3720+ DWC_PRINT("Device IN EP %d Registers\n", i);
3721+ addr=&_core_if->dev_if->in_ep_regs[i]->diepctl;
3722+ DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3723+ addr=&_core_if->dev_if->in_ep_regs[i]->diepint;
3724+ DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3725+ addr=&_core_if->dev_if->in_ep_regs[i]->dieptsiz;
3726+ DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3727+ addr=&_core_if->dev_if->in_ep_regs[i]->diepdma;
3728+ DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3729+
3730+addr = &_core_if->dev_if->in_ep_regs[i]->dtxfsts;
3731+ DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n", (uint32_t) addr,
3732+ dwc_read_reg32(addr));
3733+ }
3734+ for (i = 0; i <= _core_if->dev_if->num_out_eps; i++) {
3735+ DWC_PRINT("Device OUT EP %d Registers\n", i);
3736+ addr=&_core_if->dev_if->out_ep_regs[i]->doepctl;
3737+ DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3738+ addr=&_core_if->dev_if->out_ep_regs[i]->doepfn;
3739+ DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3740+ addr=&_core_if->dev_if->out_ep_regs[i]->doepint;
3741+ DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3742+ addr=&_core_if->dev_if->out_ep_regs[i]->doeptsiz;
3743+ DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3744+ addr=&_core_if->dev_if->out_ep_regs[i]->doepdma;
3745+ DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3746+ }
3747+ return;
3748+}
3749+
3750+/**
3751+ * This function reads the host registers and prints them
3752+ *
3753+ * @param _core_if Programming view of DWC_otg controller.
3754+ */
3755+void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if)
3756+{
3757+ int i;
3758+ volatile uint32_t *addr;
3759+
3760+ DWC_PRINT("Host Global Registers\n");
3761+ addr=&_core_if->host_if->host_global_regs->hcfg;
3762+ DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3763+ addr=&_core_if->host_if->host_global_regs->hfir;
3764+ DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3765+ addr=&_core_if->host_if->host_global_regs->hfnum;
3766+ DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3767+ addr=&_core_if->host_if->host_global_regs->hptxsts;
3768+ DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3769+ addr=&_core_if->host_if->host_global_regs->haint;
3770+ DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3771+ addr=&_core_if->host_if->host_global_regs->haintmsk;
3772+ DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3773+ addr=_core_if->host_if->hprt0;
3774+ DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3775+
3776+ for (i=0; i<_core_if->core_params->host_channels; i++) {
3777+ DWC_PRINT("Host Channel %d Specific Registers\n", i);
3778+ addr=&_core_if->host_if->hc_regs[i]->hcchar;
3779+ DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3780+ addr=&_core_if->host_if->hc_regs[i]->hcsplt;
3781+ DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3782+ addr=&_core_if->host_if->hc_regs[i]->hcint;
3783+ DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3784+ addr=&_core_if->host_if->hc_regs[i]->hcintmsk;
3785+ DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3786+ addr=&_core_if->host_if->hc_regs[i]->hctsiz;
3787+ DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3788+ addr=&_core_if->host_if->hc_regs[i]->hcdma;
3789+ DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3790+
3791+ }
3792+ return;
3793+}
3794+
3795+/**
3796+ * This function reads the core global registers and prints them
3797+ *
3798+ * @param _core_if Programming view of DWC_otg controller.
3799+ */
3800+void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if)
3801+{
3802+ int i;
3803+ volatile uint32_t *addr;
3804+
3805+ DWC_PRINT("Core Global Registers\n");
3806+ addr=&_core_if->core_global_regs->gotgctl;
3807+ DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3808+ addr=&_core_if->core_global_regs->gotgint;
3809+ DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3810+ addr=&_core_if->core_global_regs->gahbcfg;
3811+ DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3812+ addr=&_core_if->core_global_regs->gusbcfg;
3813+ DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3814+ addr=&_core_if->core_global_regs->grstctl;
3815+ DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3816+ addr=&_core_if->core_global_regs->gintsts;
3817+ DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3818+ addr=&_core_if->core_global_regs->gintmsk;
3819+ DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3820+ addr=&_core_if->core_global_regs->grxstsr;
3821+ DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3822+ //addr=&_core_if->core_global_regs->grxstsp;
3823+ //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3824+ addr=&_core_if->core_global_regs->grxfsiz;
3825+ DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3826+ addr=&_core_if->core_global_regs->gnptxfsiz;
3827+ DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3828+ addr=&_core_if->core_global_regs->gnptxsts;
3829+ DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3830+ addr=&_core_if->core_global_regs->gi2cctl;
3831+ DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3832+ addr=&_core_if->core_global_regs->gpvndctl;
3833+ DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3834+ addr=&_core_if->core_global_regs->ggpio;
3835+ DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3836+ addr=&_core_if->core_global_regs->guid;
3837+ DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3838+ addr=&_core_if->core_global_regs->gsnpsid;
3839+ DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3840+ addr=&_core_if->core_global_regs->ghwcfg1;
3841+ DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3842+ addr=&_core_if->core_global_regs->ghwcfg2;
3843+ DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3844+ addr=&_core_if->core_global_regs->ghwcfg3;
3845+ DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3846+ addr=&_core_if->core_global_regs->ghwcfg4;
3847+ DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3848+ addr=&_core_if->core_global_regs->hptxfsiz;
3849+ DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr));
3850+
3851+ for (i=0; i<_core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
3852+ addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
3853+ DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr));
3854+ }
3855+
3856+}
3857+#endif
3858+
3859+/**
3860+ * Flush a Tx FIFO.
3861+ *
3862+ * @param _core_if Programming view of DWC_otg controller.
3863+ * @param _num Tx FIFO to flush.
3864+ */
3865+extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
3866+ const int _num )
3867+{
3868+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
3869+ volatile grstctl_t greset = { .d32 = 0};
3870+ int count = 0;
3871+
3872+ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num);
3873+
3874+ greset.b.txfflsh = 1;
3875+ greset.b.txfnum = _num;
3876+ dwc_write_reg32( &global_regs->grstctl, greset.d32 );
3877+
3878+ do {
3879+ greset.d32 = dwc_read_reg32( &global_regs->grstctl);
3880+ if (++count > 10000){
3881+ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
3882+ __func__, greset.d32,
3883+ dwc_read_reg32( &global_regs->gnptxsts));
3884+ break;
3885+ }
3886+
3887+ udelay(1);
3888+ } while (greset.b.txfflsh == 1);
3889+ /* Wait for 3 PHY Clocks*/
3890+ UDELAY(1);
3891+}
3892+
3893+/**
3894+ * Flush Rx FIFO.
3895+ *
3896+ * @param _core_if Programming view of DWC_otg controller.
3897+ */
3898+extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if )
3899+{
3900+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
3901+ volatile grstctl_t greset = { .d32 = 0};
3902+ int count = 0;
3903+
3904+ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
3905+ /*
3906+ *
3907+ */
3908+ greset.b.rxfflsh = 1;
3909+ dwc_write_reg32( &global_regs->grstctl, greset.d32 );
3910+
3911+ do {
3912+ greset.d32 = dwc_read_reg32( &global_regs->grstctl);
3913+ if (++count > 10000){
3914+ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
3915+ greset.d32);
3916+ break;
3917+ }
3918+ } while (greset.b.rxfflsh == 1);
3919+ /* Wait for 3 PHY Clocks*/
3920+ UDELAY(1);
3921+}
3922+
3923+/**
3924+ * Do core a soft reset of the core. Be careful with this because it
3925+ * resets all the internal state machines of the core.
3926+ */
3927+
3928+void dwc_otg_core_reset(dwc_otg_core_if_t *_core_if)
3929+{
3930+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs;
3931+ volatile grstctl_t greset = { .d32 = 0};
3932+ int count = 0;
3933+
3934+ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
3935+ /* Wait for AHB master IDLE state. */
3936+ do {
3937+ UDELAY(10);
3938+ greset.d32 = dwc_read_reg32( &global_regs->grstctl);
3939+ if (++count > 100000){
3940+ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__,
3941+ greset.d32, greset.b.ahbidle);
3942+ return;
3943+ }
3944+ } while (greset.b.ahbidle == 0);
3945+
3946+// winder add.
3947+#if 1
3948+ /* Note: Actually, I don't exactly why we need to put delay here. */
3949+ MDELAY(100);
3950+#endif
3951+ /* Core Soft Reset */
3952+ count = 0;
3953+ greset.b.csftrst = 1;
3954+ dwc_write_reg32( &global_regs->grstctl, greset.d32 );
3955+// winder add.
3956+#if 1
3957+ /* Note: Actually, I don't exactly why we need to put delay here. */
3958+ MDELAY(100);
3959+#endif
3960+ do {
3961+ greset.d32 = dwc_read_reg32( &global_regs->grstctl);
3962+ if (++count > 10000){
3963+ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__,
3964+ greset.d32);
3965+ break;
3966+ }
3967+ udelay(1);
3968+ } while (greset.b.csftrst == 1);
3969+ /* Wait for 3 PHY Clocks*/
3970+ //DWC_PRINT("100ms\n");
3971+ MDELAY(100);
3972+}
3973+
3974+
3975+
3976+/**
3977+ * Register HCD callbacks. The callbacks are used to start and stop
3978+ * the HCD for interrupt processing.
3979+ *
3980+ * @param _core_if Programming view of DWC_otg controller.
3981+ * @param _cb the HCD callback structure.
3982+ * @param _p pointer to be passed to callback function (usb_hcd*).
3983+ */
3984+extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
3985+ dwc_otg_cil_callbacks_t *_cb,
3986+ void *_p)
3987+{
3988+ _core_if->hcd_cb = _cb;
3989+ _cb->p = _p;
3990+}
3991+
3992+/**
3993+ * Register PCD callbacks. The callbacks are used to start and stop
3994+ * the PCD for interrupt processing.
3995+ *
3996+ * @param _core_if Programming view of DWC_otg controller.
3997+ * @param _cb the PCD callback structure.
3998+ * @param _p pointer to be passed to callback function (pcd*).
3999+ */
4000+extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
4001+ dwc_otg_cil_callbacks_t *_cb,
4002+ void *_p)
4003+{
4004+ _core_if->pcd_cb = _cb;
4005+ _cb->p = _p;
4006+}
4007+
4008--- /dev/null
4009+++ b/drivers/usb/dwc_otg/dwc_otg_cil.h
4010@@ -0,0 +1,911 @@
4011+/* ==========================================================================
4012+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $
4013+ * $Revision: 1.1.1.1 $
4014+ * $Date: 2009-04-17 06:15:34 $
4015+ * $Change: 631780 $
4016+ *
4017+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
4018+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
4019+ * otherwise expressly agreed to in writing between Synopsys and you.
4020+ *
4021+ * The Software IS NOT an item of Licensed Software or Licensed Product under
4022+ * any End User Software License Agreement or Agreement for Licensed Product
4023+ * with Synopsys or any supplement thereto. You are permitted to use and
4024+ * redistribute this Software in source and binary forms, with or without
4025+ * modification, provided that redistributions of source code must retain this
4026+ * notice. You may not view, use, disclose, copy or distribute this file or
4027+ * any information contained herein except pursuant to this license grant from
4028+ * Synopsys. If you do not agree with this notice, including the disclaimer
4029+ * below, then you are not authorized to use the Software.
4030+ *
4031+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
4032+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4033+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4034+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
4035+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4036+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
4037+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
4038+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
4039+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
4040+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
4041+ * DAMAGE.
4042+ * ========================================================================== */
4043+
4044+#if !defined(__DWC_CIL_H__)
4045+#define __DWC_CIL_H__
4046+
4047+#include "dwc_otg_plat.h"
4048+
4049+#include "dwc_otg_regs.h"
4050+#ifdef DEBUG
4051+#include "linux/timer.h"
4052+#endif
4053+
4054+/* the OTG capabilities. */
4055+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
4056+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
4057+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
4058+/* the maximum speed of operation in host and device mode. */
4059+#define DWC_SPEED_PARAM_HIGH 0
4060+#define DWC_SPEED_PARAM_FULL 1
4061+/* the PHY clock rate in low power mode when connected to a
4062+ * Low Speed device in host mode. */
4063+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
4064+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
4065+/* the type of PHY interface to use. */
4066+#define DWC_PHY_TYPE_PARAM_FS 0
4067+#define DWC_PHY_TYPE_PARAM_UTMI 1
4068+#define DWC_PHY_TYPE_PARAM_ULPI 2
4069+/* whether to use the internal or external supply to
4070+ * drive the vbus with a ULPI phy. */
4071+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
4072+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
4073+/* EP type. */
4074+
4075+/**
4076+ * @file
4077+ * This file contains the interface to the Core Interface Layer.
4078+ */
4079+
4080+/**
4081+ * The <code>dwc_ep</code> structure represents the state of a single
4082+ * endpoint when acting in device mode. It contains the data items
4083+ * needed for an endpoint to be activated and transfer packets.
4084+ */
4085+typedef struct dwc_ep {
4086+ /** EP number used for register address lookup */
4087+ uint8_t num;
4088+ /** EP direction 0 = OUT */
4089+ unsigned is_in : 1;
4090+ /** EP active. */
4091+ unsigned active : 1;
4092+
4093+ /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
4094+ If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
4095+ unsigned tx_fifo_num : 4;
4096+ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
4097+ unsigned type : 2;
4098+#define DWC_OTG_EP_TYPE_CONTROL 0
4099+#define DWC_OTG_EP_TYPE_ISOC 1
4100+#define DWC_OTG_EP_TYPE_BULK 2
4101+#define DWC_OTG_EP_TYPE_INTR 3
4102+
4103+ /** DATA start PID for INTR and BULK EP */
4104+ unsigned data_pid_start : 1;
4105+ /** Frame (even/odd) for ISOC EP */
4106+ unsigned even_odd_frame : 1;
4107+ /** Max Packet bytes */
4108+ unsigned maxpacket : 11;
4109+
4110+ /** @name Transfer state */
4111+ /** @{ */
4112+
4113+ /**
4114+ * Pointer to the beginning of the transfer buffer -- do not modify
4115+ * during transfer.
4116+ */
4117+
4118+ uint32_t dma_addr;
4119+
4120+ uint8_t *start_xfer_buff;
4121+ /** pointer to the transfer buffer */
4122+ uint8_t *xfer_buff;
4123+ /** Number of bytes to transfer */
4124+ unsigned xfer_len : 19;
4125+ /** Number of bytes transferred. */
4126+ unsigned xfer_count : 19;
4127+ /** Sent ZLP */
4128+ unsigned sent_zlp : 1;
4129+ /** Total len for control transfer */
4130+ unsigned total_len : 19;
4131+
4132+ /** stall clear flag */
4133+ unsigned stall_clear_flag : 1;
4134+
4135+ /** @} */
4136+} dwc_ep_t;
4137+
4138+/*
4139+ * Reasons for halting a host channel.
4140+ */
4141+typedef enum dwc_otg_halt_status {
4142+ DWC_OTG_HC_XFER_NO_HALT_STATUS,
4143+ DWC_OTG_HC_XFER_COMPLETE,
4144+ DWC_OTG_HC_XFER_URB_COMPLETE,
4145+ DWC_OTG_HC_XFER_ACK,
4146+ DWC_OTG_HC_XFER_NAK,
4147+ DWC_OTG_HC_XFER_NYET,
4148+ DWC_OTG_HC_XFER_STALL,
4149+ DWC_OTG_HC_XFER_XACT_ERR,
4150+ DWC_OTG_HC_XFER_FRAME_OVERRUN,
4151+ DWC_OTG_HC_XFER_BABBLE_ERR,
4152+ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
4153+ DWC_OTG_HC_XFER_AHB_ERR,
4154+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
4155+ DWC_OTG_HC_XFER_URB_DEQUEUE
4156+} dwc_otg_halt_status_e;
4157+
4158+/**
4159+ * Host channel descriptor. This structure represents the state of a single
4160+ * host channel when acting in host mode. It contains the data items needed to
4161+ * transfer packets to an endpoint via a host channel.
4162+ */
4163+typedef struct dwc_hc {
4164+ /** Host channel number used for register address lookup */
4165+ uint8_t hc_num;
4166+
4167+ /** Device to access */
4168+ unsigned dev_addr : 7;
4169+
4170+ /** EP to access */
4171+ unsigned ep_num : 4;
4172+
4173+ /** EP direction. 0: OUT, 1: IN */
4174+ unsigned ep_is_in : 1;
4175+
4176+ /**
4177+ * EP speed.
4178+ * One of the following values:
4179+ * - DWC_OTG_EP_SPEED_LOW
4180+ * - DWC_OTG_EP_SPEED_FULL
4181+ * - DWC_OTG_EP_SPEED_HIGH
4182+ */
4183+ unsigned speed : 2;
4184+#define DWC_OTG_EP_SPEED_LOW 0
4185+#define DWC_OTG_EP_SPEED_FULL 1
4186+#define DWC_OTG_EP_SPEED_HIGH 2
4187+
4188+ /**
4189+ * Endpoint type.
4190+ * One of the following values:
4191+ * - DWC_OTG_EP_TYPE_CONTROL: 0
4192+ * - DWC_OTG_EP_TYPE_ISOC: 1
4193+ * - DWC_OTG_EP_TYPE_BULK: 2
4194+ * - DWC_OTG_EP_TYPE_INTR: 3
4195+ */
4196+ unsigned ep_type : 2;
4197+
4198+ /** Max packet size in bytes */
4199+ unsigned max_packet : 11;
4200+
4201+ /**
4202+ * PID for initial transaction.
4203+ * 0: DATA0,<br>
4204+ * 1: DATA2,<br>
4205+ * 2: DATA1,<br>
4206+ * 3: MDATA (non-Control EP),
4207+ * SETUP (Control EP)
4208+ */
4209+ unsigned data_pid_start : 2;
4210+#define DWC_OTG_HC_PID_DATA0 0
4211+#define DWC_OTG_HC_PID_DATA2 1
4212+#define DWC_OTG_HC_PID_DATA1 2
4213+#define DWC_OTG_HC_PID_MDATA 3
4214+#define DWC_OTG_HC_PID_SETUP 3
4215+
4216+ /** Number of periodic transactions per (micro)frame */
4217+ unsigned multi_count: 2;
4218+
4219+ /** @name Transfer State */
4220+ /** @{ */
4221+
4222+ /** Pointer to the current transfer buffer position. */
4223+ uint8_t *xfer_buff;
4224+ /** Total number of bytes to transfer. */
4225+ uint32_t xfer_len;
4226+ /** Number of bytes transferred so far. */
4227+ uint32_t xfer_count;
4228+ /** Packet count at start of transfer.*/
4229+ uint16_t start_pkt_count;
4230+
4231+ /**
4232+ * Flag to indicate whether the transfer has been started. Set to 1 if
4233+ * it has been started, 0 otherwise.
4234+ */
4235+ uint8_t xfer_started;
4236+
4237+ /**
4238+ * Set to 1 to indicate that a PING request should be issued on this
4239+ * channel. If 0, process normally.
4240+ */
4241+ uint8_t do_ping;
4242+
4243+ /**
4244+ * Set to 1 to indicate that the error count for this transaction is
4245+ * non-zero. Set to 0 if the error count is 0.
4246+ */
4247+ uint8_t error_state;
4248+
4249+ /**
4250+ * Set to 1 to indicate that this channel should be halted the next
4251+ * time a request is queued for the channel. This is necessary in
4252+ * slave mode if no request queue space is available when an attempt
4253+ * is made to halt the channel.
4254+ */
4255+ uint8_t halt_on_queue;
4256+
4257+ /**
4258+ * Set to 1 if the host channel has been halted, but the core is not
4259+ * finished flushing queued requests. Otherwise 0.
4260+ */
4261+ uint8_t halt_pending;
4262+
4263+ /**
4264+ * Reason for halting the host channel.
4265+ */
4266+ dwc_otg_halt_status_e halt_status;
4267+
4268+ /*
4269+ * Split settings for the host channel
4270+ */
4271+ uint8_t do_split; /**< Enable split for the channel */
4272+ uint8_t complete_split; /**< Enable complete split */
4273+ uint8_t hub_addr; /**< Address of high speed hub */
4274+
4275+ uint8_t port_addr; /**< Port of the low/full speed device */
4276+ /** Split transaction position
4277+ * One of the following values:
4278+ * - DWC_HCSPLIT_XACTPOS_MID
4279+ * - DWC_HCSPLIT_XACTPOS_BEGIN
4280+ * - DWC_HCSPLIT_XACTPOS_END
4281+ * - DWC_HCSPLIT_XACTPOS_ALL */
4282+ uint8_t xact_pos;
4283+
4284+ /** Set when the host channel does a short read. */
4285+ uint8_t short_read;
4286+
4287+ /**
4288+ * Number of requests issued for this channel since it was assigned to
4289+ * the current transfer (not counting PINGs).
4290+ */
4291+ uint8_t requests;
4292+
4293+ /**
4294+ * Queue Head for the transfer being processed by this channel.
4295+ */
4296+ struct dwc_otg_qh *qh;
4297+
4298+ /** @} */
4299+
4300+ /** Entry in list of host channels. */
4301+ struct list_head hc_list_entry;
4302+} dwc_hc_t;
4303+
4304+/**
4305+ * The following parameters may be specified when starting the module. These
4306+ * parameters define how the DWC_otg controller should be configured.
4307+ * Parameter values are passed to the CIL initialization function
4308+ * dwc_otg_cil_init.
4309+ */
4310+
4311+typedef struct dwc_otg_core_params
4312+{
4313+ int32_t opt;
4314+//#define dwc_param_opt_default 1
4315+ /**
4316+ * Specifies the OTG capabilities. The driver will automatically
4317+ * detect the value for this parameter if none is specified.
4318+ * 0 - HNP and SRP capable (default)
4319+ * 1 - SRP Only capable
4320+ * 2 - No HNP/SRP capable
4321+ */
4322+ int32_t otg_cap;
4323+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
4324+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
4325+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
4326+//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
4327+ /**
4328+ * Specifies whether to use slave or DMA mode for accessing the data
4329+ * FIFOs. The driver will automatically detect the value for this
4330+ * parameter if none is specified.
4331+ * 0 - Slave
4332+ * 1 - DMA (default, if available)
4333+ */
4334+ int32_t dma_enable;
4335+//#define dwc_param_dma_enable_default 1
4336+ /** The DMA Burst size (applicable only for External DMA
4337+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
4338+ */
4339+ int32_t dma_burst_size; /* Translate this to GAHBCFG values */
4340+//#define dwc_param_dma_burst_size_default 32
4341+ /**
4342+ * Specifies the maximum speed of operation in host and device mode.
4343+ * The actual speed depends on the speed of the attached device and
4344+ * the value of phy_type. The actual speed depends on the speed of the
4345+ * attached device.
4346+ * 0 - High Speed (default)
4347+ * 1 - Full Speed
4348+ */
4349+ int32_t speed;
4350+//#define dwc_param_speed_default 0
4351+#define DWC_SPEED_PARAM_HIGH 0
4352+#define DWC_SPEED_PARAM_FULL 1
4353+
4354+ /** Specifies whether low power mode is supported when attached
4355+ * to a Full Speed or Low Speed device in host mode.
4356+ * 0 - Don't support low power mode (default)
4357+ * 1 - Support low power mode
4358+ */
4359+ int32_t host_support_fs_ls_low_power;
4360+//#define dwc_param_host_support_fs_ls_low_power_default 0
4361+ /** Specifies the PHY clock rate in low power mode when connected to a
4362+ * Low Speed device in host mode. This parameter is applicable only if
4363+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
4364+ * then defaults to 6 MHZ otherwise 48 MHZ.
4365+ *
4366+ * 0 - 48 MHz
4367+ * 1 - 6 MHz
4368+ */
4369+ int32_t host_ls_low_power_phy_clk;
4370+//#define dwc_param_host_ls_low_power_phy_clk_default 0
4371+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
4372+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
4373+ /**
4374+ * 0 - Use cC FIFO size parameters
4375+ * 1 - Allow dynamic FIFO sizing (default)
4376+ */
4377+ int32_t enable_dynamic_fifo;
4378+//#define dwc_param_enable_dynamic_fifo_default 1
4379+ /** Total number of 4-byte words in the data FIFO memory. This
4380+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
4381+ * Tx FIFOs.
4382+ * 32 to 32768 (default 8192)
4383+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
4384+ */
4385+ int32_t data_fifo_size;
4386+//#define dwc_param_data_fifo_size_default 8192
4387+ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
4388+ * FIFO sizing is enabled.
4389+ * 16 to 32768 (default 1064)
4390+ */
4391+ int32_t dev_rx_fifo_size;
4392+//#define dwc_param_dev_rx_fifo_size_default 1064
4393+ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
4394+ * when dynamic FIFO sizing is enabled.
4395+ * 16 to 32768 (default 1024)
4396+ */
4397+ int32_t dev_nperio_tx_fifo_size;
4398+//#define dwc_param_dev_nperio_tx_fifo_size_default 1024
4399+ /** Number of 4-byte words in each of the periodic Tx FIFOs in device
4400+ * mode when dynamic FIFO sizing is enabled.
4401+ * 4 to 768 (default 256)
4402+ */
4403+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
4404+//#define dwc_param_dev_perio_tx_fifo_size_default 256
4405+ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
4406+ * FIFO sizing is enabled.
4407+ * 16 to 32768 (default 1024)
4408+ */
4409+ int32_t host_rx_fifo_size;
4410+//#define dwc_param_host_rx_fifo_size_default 1024
4411+ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
4412+ * when Dynamic FIFO sizing is enabled in the core.
4413+ * 16 to 32768 (default 1024)
4414+ */
4415+ int32_t host_nperio_tx_fifo_size;
4416+//#define dwc_param_host_nperio_tx_fifo_size_default 1024
4417+ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
4418+ * FIFO sizing is enabled.
4419+ * 16 to 32768 (default 1024)
4420+ */
4421+ int32_t host_perio_tx_fifo_size;
4422+//#define dwc_param_host_perio_tx_fifo_size_default 1024
4423+ /** The maximum transfer size supported in bytes.
4424+ * 2047 to 65,535 (default 65,535)
4425+ */
4426+ int32_t max_transfer_size;
4427+//#define dwc_param_max_transfer_size_default 65535
4428+ /** The maximum number of packets in a transfer.
4429+ * 15 to 511 (default 511)
4430+ */
4431+ int32_t max_packet_count;
4432+//#define dwc_param_max_packet_count_default 511
4433+ /** The number of host channel registers to use.
4434+ * 1 to 16 (default 12)
4435+ * Note: The FPGA configuration supports a maximum of 12 host channels.
4436+ */
4437+ int32_t host_channels;
4438+//#define dwc_param_host_channels_default 12
4439+ /** The number of endpoints in addition to EP0 available for device
4440+ * mode operations.
4441+ * 1 to 15 (default 6 IN and OUT)
4442+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
4443+ * endpoints in addition to EP0.
4444+ */
4445+ int32_t dev_endpoints;
4446+//#define dwc_param_dev_endpoints_default 6
4447+ /**
4448+ * Specifies the type of PHY interface to use. By default, the driver
4449+ * will automatically detect the phy_type.
4450+ *
4451+ * 0 - Full Speed PHY
4452+ * 1 - UTMI+ (default)
4453+ * 2 - ULPI
4454+ */
4455+ int32_t phy_type;
4456+#define DWC_PHY_TYPE_PARAM_FS 0
4457+#define DWC_PHY_TYPE_PARAM_UTMI 1
4458+#define DWC_PHY_TYPE_PARAM_ULPI 2
4459+//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
4460+ /**
4461+ * Specifies the UTMI+ Data Width. This parameter is
4462+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
4463+ * PHY_TYPE, this parameter indicates the data width between
4464+ * the MAC and the ULPI Wrapper.) Also, this parameter is
4465+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
4466+ * to "8 and 16 bits", meaning that the core has been
4467+ * configured to work at either data path width.
4468+ *
4469+ * 8 or 16 bits (default 16)
4470+ */
4471+ int32_t phy_utmi_width;
4472+//#define dwc_param_phy_utmi_width_default 16
4473+ /**
4474+ * Specifies whether the ULPI operates at double or single
4475+ * data rate. This parameter is only applicable if PHY_TYPE is
4476+ * ULPI.
4477+ *
4478+ * 0 - single data rate ULPI interface with 8 bit wide data
4479+ * bus (default)
4480+ * 1 - double data rate ULPI interface with 4 bit wide data
4481+ * bus
4482+ */
4483+ int32_t phy_ulpi_ddr;
4484+//#define dwc_param_phy_ulpi_ddr_default 0
4485+ /**
4486+ * Specifies whether to use the internal or external supply to
4487+ * drive the vbus with a ULPI phy.
4488+ */
4489+ int32_t phy_ulpi_ext_vbus;
4490+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
4491+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
4492+//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
4493+ /**
4494+ * Specifies whether to use the I2Cinterface for full speed PHY. This
4495+ * parameter is only applicable if PHY_TYPE is FS.
4496+ * 0 - No (default)
4497+ * 1 - Yes
4498+ */
4499+ int32_t i2c_enable;
4500+//#define dwc_param_i2c_enable_default 0
4501+
4502+ int32_t ulpi_fs_ls;
4503+//#define dwc_param_ulpi_fs_ls_default 0
4504+
4505+ int32_t ts_dline;
4506+//#define dwc_param_ts_dline_default 0
4507+
4508+ /**
4509+ * Specifies whether dedicated transmit FIFOs are
4510+ * enabled for non periodic IN endpoints in device mode
4511+ * 0 - No
4512+ * 1 - Yes
4513+ */
4514+ int32_t en_multiple_tx_fifo;
4515+#define dwc_param_en_multiple_tx_fifo_default 1
4516+
4517+ /** Number of 4-byte words in each of the Tx FIFOs in device
4518+ * mode when dynamic FIFO sizing is enabled.
4519+ * 4 to 768 (default 256)
4520+ */
4521+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
4522+#define dwc_param_dev_tx_fifo_size_default 256
4523+
4524+ /** Thresholding enable flag-
4525+ * bit 0 - enable non-ISO Tx thresholding
4526+ * bit 1 - enable ISO Tx thresholding
4527+ * bit 2 - enable Rx thresholding
4528+ */
4529+ uint32_t thr_ctl;
4530+#define dwc_param_thr_ctl_default 0
4531+
4532+ /** Thresholding length for Tx
4533+ * FIFOs in 32 bit DWORDs
4534+ */
4535+ uint32_t tx_thr_length;
4536+#define dwc_param_tx_thr_length_default 64
4537+
4538+ /** Thresholding length for Rx
4539+ * FIFOs in 32 bit DWORDs
4540+ */
4541+ uint32_t rx_thr_length;
4542+#define dwc_param_rx_thr_length_default 64
4543+} dwc_otg_core_params_t;
4544+
4545+#ifdef DEBUG
4546+struct dwc_otg_core_if;
4547+typedef struct hc_xfer_info
4548+{
4549+ struct dwc_otg_core_if *core_if;
4550+ dwc_hc_t *hc;
4551+} hc_xfer_info_t;
4552+#endif
4553+
4554+/**
4555+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
4556+ * the DWC_otg controller acting in either host or device mode. It
4557+ * represents the programming view of the controller as a whole.
4558+ */
4559+typedef struct dwc_otg_core_if
4560+{
4561+ /** Parameters that define how the core should be configured.*/
4562+ dwc_otg_core_params_t *core_params;
4563+
4564+ /** Core Global registers starting at offset 000h. */
4565+ dwc_otg_core_global_regs_t *core_global_regs;
4566+
4567+ /** Device-specific information */
4568+ dwc_otg_dev_if_t *dev_if;
4569+ /** Host-specific information */
4570+ dwc_otg_host_if_t *host_if;
4571+
4572+ /*
4573+ * Set to 1 if the core PHY interface bits in USBCFG have been
4574+ * initialized.
4575+ */
4576+ uint8_t phy_init_done;
4577+
4578+ /*
4579+ * SRP Success flag, set by srp success interrupt in FS I2C mode
4580+ */
4581+ uint8_t srp_success;
4582+ uint8_t srp_timer_started;
4583+
4584+ /* Common configuration information */
4585+ /** Power and Clock Gating Control Register */
4586+ volatile uint32_t *pcgcctl;
4587+#define DWC_OTG_PCGCCTL_OFFSET 0xE00
4588+
4589+ /** Push/pop addresses for endpoints or host channels.*/
4590+ uint32_t *data_fifo[MAX_EPS_CHANNELS];
4591+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
4592+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
4593+
4594+ /** Total RAM for FIFOs (Bytes) */
4595+ uint16_t total_fifo_size;
4596+ /** Size of Rx FIFO (Bytes) */
4597+ uint16_t rx_fifo_size;
4598+ /** Size of Non-periodic Tx FIFO (Bytes) */
4599+ uint16_t nperio_tx_fifo_size;
4600+
4601+ /** 1 if DMA is enabled, 0 otherwise. */
4602+ uint8_t dma_enable;
4603+
4604+ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
4605+ uint8_t en_multiple_tx_fifo;
4606+
4607+ /** Set to 1 if multiple packets of a high-bandwidth transfer is in
4608+ * process of being queued */
4609+ uint8_t queuing_high_bandwidth;
4610+
4611+ /** Hardware Configuration -- stored here for convenience.*/
4612+ hwcfg1_data_t hwcfg1;
4613+ hwcfg2_data_t hwcfg2;
4614+ hwcfg3_data_t hwcfg3;
4615+ hwcfg4_data_t hwcfg4;
4616+
4617+ /** The operational State, during transations
4618+ * (a_host>>a_peripherial and b_device=>b_host) this may not
4619+ * match the core but allows the software to determine
4620+ * transitions.
4621+ */
4622+ uint8_t op_state;
4623+
4624+ /**
4625+ * Set to 1 if the HCD needs to be restarted on a session request
4626+ * interrupt. This is required if no connector ID status change has
4627+ * occurred since the HCD was last disconnected.
4628+ */
4629+ uint8_t restart_hcd_on_session_req;
4630+
4631+ /** HCD callbacks */
4632+ /** A-Device is a_host */
4633+#define A_HOST (1)
4634+ /** A-Device is a_suspend */
4635+#define A_SUSPEND (2)
4636+ /** A-Device is a_peripherial */
4637+#define A_PERIPHERAL (3)
4638+ /** B-Device is operating as a Peripheral. */
4639+#define B_PERIPHERAL (4)
4640+ /** B-Device is operating as a Host. */
4641+#define B_HOST (5)
4642+
4643+ /** HCD callbacks */
4644+ struct dwc_otg_cil_callbacks *hcd_cb;
4645+ /** PCD callbacks */
4646+ struct dwc_otg_cil_callbacks *pcd_cb;
4647+
4648+ /** Device mode Periodic Tx FIFO Mask */
4649+ uint32_t p_tx_msk;
4650+ /** Device mode Periodic Tx FIFO Mask */
4651+ uint32_t tx_msk;
4652+
4653+#ifdef DEBUG
4654+ uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
4655+
4656+ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
4657+ struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS];
4658+
4659+#if 1 // winder
4660+ uint32_t hfnum_7_samples;
4661+ uint32_t hfnum_7_frrem_accum;
4662+ uint32_t hfnum_0_samples;
4663+ uint32_t hfnum_0_frrem_accum;
4664+ uint32_t hfnum_other_samples;
4665+ uint32_t hfnum_other_frrem_accum;
4666+#else
4667+ uint32_t hfnum_7_samples;
4668+ uint64_t hfnum_7_frrem_accum;
4669+ uint32_t hfnum_0_samples;
4670+ uint64_t hfnum_0_frrem_accum;
4671+ uint32_t hfnum_other_samples;
4672+ uint64_t hfnum_other_frrem_accum;
4673+#endif
4674+ resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */
4675+#endif
4676+
4677+} dwc_otg_core_if_t;
4678+
4679+/*
4680+ * The following functions support initialization of the CIL driver component
4681+ * and the DWC_otg controller.
4682+ */
4683+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
4684+ dwc_otg_core_params_t *_core_params);
4685+extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
4686+extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
4687+extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
4688+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
4689+extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
4690+extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
4691+
4692+/** @name Device CIL Functions
4693+ * The following functions support managing the DWC_otg controller in device
4694+ * mode.
4695+ */
4696+/**@{*/
4697+extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
4698+extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
4699+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
4700+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4701+extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4702+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4703+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4704+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4705+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4706+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
4707+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4708+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
4709+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
4710+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
4711+/**@}*/
4712+
4713+/** @name Host CIL Functions
4714+ * The following functions support managing the DWC_otg controller in host
4715+ * mode.
4716+ */
4717+/**@{*/
4718+extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4719+extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
4720+ dwc_hc_t *_hc,
4721+ dwc_otg_halt_status_e _halt_status);
4722+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4723+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4724+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4725+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4726+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
4727+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
4728+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
4729+
4730+/**
4731+ * This function Reads HPRT0 in preparation to modify. It keeps the
4732+ * WC bits 0 so that if they are read as 1, they won't clear when you
4733+ * write it back
4734+ */
4735+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
4736+{
4737+ hprt0_data_t hprt0;
4738+ hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
4739+ hprt0.b.prtena = 0;
4740+ hprt0.b.prtconndet = 0;
4741+ hprt0.b.prtenchng = 0;
4742+ hprt0.b.prtovrcurrchng = 0;
4743+ return hprt0.d32;
4744+}
4745+
4746+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
4747+/**@}*/
4748+
4749+/** @name Common CIL Functions
4750+ * The following functions support managing the DWC_otg controller in either
4751+ * device or host mode.
4752+ */
4753+/**@{*/
4754+
4755+extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
4756+ uint8_t *dest,
4757+ uint16_t bytes);
4758+
4759+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
4760+
4761+extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
4762+ const int _num );
4763+extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
4764+extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
4765+
4766+#define NP_TXFIFO_EMPTY -1
4767+#define MAX_NP_TXREQUEST_Q_SLOTS 8
4768+/**
4769+ * This function returns the endpoint number of the request at
4770+ * the top of non-periodic TX FIFO, or -1 if the request FIFO is
4771+ * empty.
4772+ */
4773+static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) {
4774+ gnptxsts_data_t txstatus = {.d32 = 0};
4775+
4776+ txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts);
4777+ return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ?
4778+ -1 : txstatus.b.nptxqtop_chnep);
4779+}
4780+/**
4781+ * This function returns the Core Interrupt register.
4782+ */
4783+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) {
4784+ return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
4785+ dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
4786+}
4787+
4788+/**
4789+ * This function returns the OTG Interrupt register.
4790+ */
4791+static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) {
4792+ return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
4793+}
4794+
4795+/**
4796+ * This function reads the Device All Endpoints Interrupt register and
4797+ * returns the IN endpoint interrupt bits.
4798+ */
4799+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) {
4800+ uint32_t v;
4801+ v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
4802+ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
4803+ return (v & 0xffff);
4804+
4805+}
4806+
4807+/**
4808+ * This function reads the Device All Endpoints Interrupt register and
4809+ * returns the OUT endpoint interrupt bits.
4810+ */
4811+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) {
4812+ uint32_t v;
4813+ v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) &
4814+ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk);
4815+ return ((v & 0xffff0000) >> 16);
4816+}
4817+
4818+/**
4819+ * This function returns the Device IN EP Interrupt register
4820+ */
4821+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if,
4822+ dwc_ep_t *_ep)
4823+{
4824+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
4825+ uint32_t v, msk, emp;
4826+ msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
4827+ emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
4828+ msk |= ((emp >> _ep->num) & 0x1) << 7;
4829+ v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk;
4830+/*
4831+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
4832+ uint32_t v;
4833+ v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) &
4834+ dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
4835+*/
4836+ return v;
4837+}
4838+/**
4839+ * This function returns the Device OUT EP Interrupt register
4840+ */
4841+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
4842+ dwc_ep_t *_ep)
4843+{
4844+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
4845+ uint32_t v;
4846+ v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) &
4847+ dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
4848+ return v;
4849+}
4850+
4851+/**
4852+ * This function returns the Host All Channel Interrupt register
4853+ */
4854+static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
4855+{
4856+ return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
4857+}
4858+
4859+static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
4860+{
4861+ return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
4862+}
4863+
4864+
4865+/**
4866+ * This function returns the mode of the operation, host or device.
4867+ *
4868+ * @return 0 - Device Mode, 1 - Host Mode
4869+ */
4870+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) {
4871+ return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
4872+}
4873+
4874+static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
4875+{
4876+ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
4877+}
4878+static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
4879+{
4880+ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
4881+}
4882+
4883+extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
4884+
4885+
4886+/**@}*/
4887+
4888+/**
4889+ * DWC_otg CIL callback structure. This structure allows the HCD and
4890+ * PCD to register functions used for starting and stopping the PCD
4891+ * and HCD for role change on for a DRD.
4892+ */
4893+typedef struct dwc_otg_cil_callbacks
4894+{
4895+ /** Start function for role change */
4896+ int (*start) (void *_p);
4897+ /** Stop Function for role change */
4898+ int (*stop) (void *_p);
4899+ /** Disconnect Function for role change */
4900+ int (*disconnect) (void *_p);
4901+ /** Resume/Remote wakeup Function */
4902+ int (*resume_wakeup) (void *_p);
4903+ /** Suspend function */
4904+ int (*suspend) (void *_p);
4905+ /** Session Start (SRP) */
4906+ int (*session_start) (void *_p);
4907+ /** Pointer passed to start() and stop() */
4908+ void *p;
4909+} dwc_otg_cil_callbacks_t;
4910+
4911+
4912+
4913+extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
4914+ dwc_otg_cil_callbacks_t *_cb,
4915+ void *_p);
4916+extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
4917+ dwc_otg_cil_callbacks_t *_cb,
4918+ void *_p);
4919+
4920+
4921+#endif
4922--- /dev/null
4923+++ b/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h
4924@@ -0,0 +1,58 @@
4925+/******************************************************************************
4926+**
4927+** FILE NAME : dwc_otg_cil_ifx.h
4928+** PROJECT : Twinpass/Danube
4929+** MODULES : DWC OTG USB
4930+**
4931+** DATE : 07 Sep. 2007
4932+** AUTHOR : Sung Winder
4933+** DESCRIPTION : Default param value.
4934+** COPYRIGHT : Copyright (c) 2007
4935+** Infineon Technologies AG
4936+** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
4937+** Hsin-chu City, 300 Taiwan.
4938+**
4939+** This program is free software; you can redistribute it and/or modify
4940+** it under the terms of the GNU General Public License as published by
4941+** the Free Software Foundation; either version 2 of the License, or
4942+** (at your option) any later version.
4943+**
4944+** HISTORY
4945+** $Date $Author $Comment
4946+** 12 April 2007 Sung Winder Initiate Version
4947+*******************************************************************************/
4948+#if !defined(__DWC_OTG_CIL_IFX_H__)
4949+#define __DWC_OTG_CIL_IFX_H__
4950+
4951+/* ================ Default param value ================== */
4952+#define dwc_param_opt_default 1
4953+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE
4954+#define dwc_param_dma_enable_default 1
4955+#define dwc_param_dma_burst_size_default 32
4956+#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH
4957+#define dwc_param_host_support_fs_ls_low_power_default 0
4958+#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ
4959+#define dwc_param_enable_dynamic_fifo_default 1
4960+#define dwc_param_data_fifo_size_default 2048
4961+#define dwc_param_dev_rx_fifo_size_default 1024
4962+#define dwc_param_dev_nperio_tx_fifo_size_default 1024
4963+#define dwc_param_dev_perio_tx_fifo_size_default 768
4964+#define dwc_param_host_rx_fifo_size_default 640
4965+#define dwc_param_host_nperio_tx_fifo_size_default 640
4966+#define dwc_param_host_perio_tx_fifo_size_default 768
4967+#define dwc_param_max_transfer_size_default 65535
4968+#define dwc_param_max_packet_count_default 511
4969+#define dwc_param_host_channels_default 16
4970+#define dwc_param_dev_endpoints_default 6
4971+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
4972+#define dwc_param_phy_utmi_width_default 16
4973+#define dwc_param_phy_ulpi_ddr_default 0
4974+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
4975+#define dwc_param_i2c_enable_default 0
4976+#define dwc_param_ulpi_fs_ls_default 0
4977+#define dwc_param_ts_dline_default 0
4978+
4979+/* ======================================================= */
4980+
4981+#endif // __DWC_OTG_CIL_IFX_H__
4982+
4983--- /dev/null
4984+++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
4985@@ -0,0 +1,708 @@
4986+/* ==========================================================================
4987+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil_intr.c $
4988+ * $Revision: 1.1.1.1 $
4989+ * $Date: 2009-04-17 06:15:34 $
4990+ * $Change: 553126 $
4991+ *
4992+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
4993+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
4994+ * otherwise expressly agreed to in writing between Synopsys and you.
4995+ *
4996+ * The Software IS NOT an item of Licensed Software or Licensed Product under
4997+ * any End User Software License Agreement or Agreement for Licensed Product
4998+ * with Synopsys or any supplement thereto. You are permitted to use and
4999+ * redistribute this Software in source and binary forms, with or without
5000+ * modification, provided that redistributions of source code must retain this
5001+ * notice. You may not view, use, disclose, copy or distribute this file or
5002+ * any information contained herein except pursuant to this license grant from
5003+ * Synopsys. If you do not agree with this notice, including the disclaimer
5004+ * below, then you are not authorized to use the Software.
5005+ *
5006+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
5007+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
5008+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
5009+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
5010+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5011+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
5012+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
5013+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
5014+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
5015+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5016+ * DAMAGE.
5017+ * ========================================================================== */
5018+
5019+/** @file
5020+ *
5021+ * The Core Interface Layer provides basic services for accessing and
5022+ * managing the DWC_otg hardware. These services are used by both the
5023+ * Host Controller Driver and the Peripheral Controller Driver.
5024+ *
5025+ * This file contains the Common Interrupt handlers.
5026+ */
5027+#include "dwc_otg_plat.h"
5028+#include "dwc_otg_regs.h"
5029+#include "dwc_otg_cil.h"
5030+
5031+#ifdef DEBUG
5032+inline const char *op_state_str( dwc_otg_core_if_t *_core_if )
5033+{
5034+ return (_core_if->op_state==A_HOST?"a_host":
5035+ (_core_if->op_state==A_SUSPEND?"a_suspend":
5036+ (_core_if->op_state==A_PERIPHERAL?"a_peripheral":
5037+ (_core_if->op_state==B_PERIPHERAL?"b_peripheral":
5038+ (_core_if->op_state==B_HOST?"b_host":
5039+ "unknown")))));
5040+}
5041+#endif
5042+
5043+/** This function will log a debug message
5044+ *
5045+ * @param _core_if Programming view of DWC_otg controller.
5046+ */
5047+int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *_core_if)
5048+{
5049+ gintsts_data_t gintsts;
5050+ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
5051+ dwc_otg_mode(_core_if) ? "Host" : "Device");
5052+
5053+ /* Clear interrupt */
5054+ gintsts.d32 = 0;
5055+ gintsts.b.modemismatch = 1;
5056+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5057+ return 1;
5058+}
5059+
5060+/** Start the HCD. Helper function for using the HCD callbacks.
5061+ *
5062+ * @param _core_if Programming view of DWC_otg controller.
5063+ */
5064+static inline void hcd_start( dwc_otg_core_if_t *_core_if )
5065+{
5066+ if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
5067+ _core_if->hcd_cb->start( _core_if->hcd_cb->p );
5068+ }
5069+}
5070+/** Stop the HCD. Helper function for using the HCD callbacks.
5071+ *
5072+ * @param _core_if Programming view of DWC_otg controller.
5073+ */
5074+static inline void hcd_stop( dwc_otg_core_if_t *_core_if )
5075+{
5076+ if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
5077+ _core_if->hcd_cb->stop( _core_if->hcd_cb->p );
5078+ }
5079+}
5080+/** Disconnect the HCD. Helper function for using the HCD callbacks.
5081+ *
5082+ * @param _core_if Programming view of DWC_otg controller.
5083+ */
5084+static inline void hcd_disconnect( dwc_otg_core_if_t *_core_if )
5085+{
5086+ if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
5087+ _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
5088+ }
5089+}
5090+/** Inform the HCD the a New Session has begun. Helper function for
5091+ * using the HCD callbacks.
5092+ *
5093+ * @param _core_if Programming view of DWC_otg controller.
5094+ */
5095+static inline void hcd_session_start( dwc_otg_core_if_t *_core_if )
5096+{
5097+ if (_core_if->hcd_cb && _core_if->hcd_cb->session_start) {
5098+ _core_if->hcd_cb->session_start( _core_if->hcd_cb->p );
5099+ }
5100+}
5101+
5102+/** Start the PCD. Helper function for using the PCD callbacks.
5103+ *
5104+ * @param _core_if Programming view of DWC_otg controller.
5105+ */
5106+static inline void pcd_start( dwc_otg_core_if_t *_core_if )
5107+{
5108+ if (_core_if->pcd_cb && _core_if->pcd_cb->start ) {
5109+ _core_if->pcd_cb->start( _core_if->pcd_cb->p );
5110+ }
5111+}
5112+/** Stop the PCD. Helper function for using the PCD callbacks.
5113+ *
5114+ * @param _core_if Programming view of DWC_otg controller.
5115+ */
5116+static inline void pcd_stop( dwc_otg_core_if_t *_core_if )
5117+{
5118+ if (_core_if->pcd_cb && _core_if->pcd_cb->stop ) {
5119+ _core_if->pcd_cb->stop( _core_if->pcd_cb->p );
5120+ }
5121+}
5122+/** Suspend the PCD. Helper function for using the PCD callbacks.
5123+ *
5124+ * @param _core_if Programming view of DWC_otg controller.
5125+ */
5126+static inline void pcd_suspend( dwc_otg_core_if_t *_core_if )
5127+{
5128+ if (_core_if->pcd_cb && _core_if->pcd_cb->suspend ) {
5129+ _core_if->pcd_cb->suspend( _core_if->pcd_cb->p );
5130+ }
5131+}
5132+/** Resume the PCD. Helper function for using the PCD callbacks.
5133+ *
5134+ * @param _core_if Programming view of DWC_otg controller.
5135+ */
5136+static inline void pcd_resume( dwc_otg_core_if_t *_core_if )
5137+{
5138+ if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup ) {
5139+ _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
5140+ }
5141+}
5142+
5143+/**
5144+ * This function handles the OTG Interrupts. It reads the OTG
5145+ * Interrupt Register (GOTGINT) to determine what interrupt has
5146+ * occurred.
5147+ *
5148+ * @param _core_if Programming view of DWC_otg controller.
5149+ */
5150+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *_core_if)
5151+{
5152+ dwc_otg_core_global_regs_t *global_regs =
5153+ _core_if->core_global_regs;
5154+ gotgint_data_t gotgint;
5155+ gotgctl_data_t gotgctl;
5156+ gintmsk_data_t gintmsk;
5157+
5158+ gotgint.d32 = dwc_read_reg32( &global_regs->gotgint);
5159+ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
5160+ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
5161+ op_state_str(_core_if));
5162+ //DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32 );
5163+
5164+ if (gotgint.b.sesenddet) {
5165+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5166+ "Session End Detected++ (%s)\n",
5167+ op_state_str(_core_if));
5168+ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
5169+
5170+ if (_core_if->op_state == B_HOST) {
5171+ pcd_start( _core_if );
5172+ _core_if->op_state = B_PERIPHERAL;
5173+ } else {
5174+ /* If not B_HOST and Device HNP still set. HNP
5175+ * Did not succeed!*/
5176+ if (gotgctl.b.devhnpen) {
5177+ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
5178+ DWC_ERROR( "Device Not Connected/Responding!\n" );
5179+ }
5180+
5181+ /* If Session End Detected the B-Cable has
5182+ * been disconnected. */
5183+ /* Reset PCD and Gadget driver to a
5184+ * clean state. */
5185+ pcd_stop(_core_if);
5186+ }
5187+ gotgctl.d32 = 0;
5188+ gotgctl.b.devhnpen = 1;
5189+ dwc_modify_reg32( &global_regs->gotgctl,
5190+ gotgctl.d32, 0);
5191+ }
5192+ if (gotgint.b.sesreqsucstschng) {
5193+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5194+ "Session Reqeust Success Status Change++\n");
5195+ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl);
5196+ if (gotgctl.b.sesreqscs) {
5197+ if ((_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
5198+ (_core_if->core_params->i2c_enable)) {
5199+ _core_if->srp_success = 1;
5200+ }
5201+ else {
5202+ pcd_resume( _core_if );
5203+ /* Clear Session Request */
5204+ gotgctl.d32 = 0;
5205+ gotgctl.b.sesreq = 1;
5206+ dwc_modify_reg32( &global_regs->gotgctl,
5207+ gotgctl.d32, 0);
5208+ }
5209+ }
5210+ }
5211+ if (gotgint.b.hstnegsucstschng) {
5212+ /* Print statements during the HNP interrupt handling
5213+ * can cause it to fail.*/
5214+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
5215+ if (gotgctl.b.hstnegscs) {
5216+ if (dwc_otg_is_host_mode(_core_if) ) {
5217+ _core_if->op_state = B_HOST;
5218+ /*
5219+ * Need to disable SOF interrupt immediately.
5220+ * When switching from device to host, the PCD
5221+ * interrupt handler won't handle the
5222+ * interrupt if host mode is already set. The
5223+ * HCD interrupt handler won't get called if
5224+ * the HCD state is HALT. This means that the
5225+ * interrupt does not get handled and Linux
5226+ * complains loudly.
5227+ */
5228+ gintmsk.d32 = 0;
5229+ gintmsk.b.sofintr = 1;
5230+ dwc_modify_reg32(&global_regs->gintmsk,
5231+ gintmsk.d32, 0);
5232+ pcd_stop(_core_if);
5233+ /*
5234+ * Initialize the Core for Host mode.
5235+ */
5236+ hcd_start( _core_if );
5237+ _core_if->op_state = B_HOST;
5238+ }
5239+ } else {
5240+ gotgctl.d32 = 0;
5241+ gotgctl.b.hnpreq = 1;
5242+ gotgctl.b.devhnpen = 1;
5243+ dwc_modify_reg32( &global_regs->gotgctl,
5244+ gotgctl.d32, 0);
5245+ DWC_DEBUGPL( DBG_ANY, "HNP Failed\n");
5246+ DWC_ERROR( "Device Not Connected/Responding\n" );
5247+ }
5248+ }
5249+ if (gotgint.b.hstnegdet) {
5250+ /* The disconnect interrupt is set at the same time as
5251+ * Host Negotiation Detected. During the mode
5252+ * switch all interrupts are cleared so the disconnect
5253+ * interrupt handler will not get executed.
5254+ */
5255+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5256+ "Host Negotiation Detected++ (%s)\n",
5257+ (dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
5258+ if (dwc_otg_is_device_mode(_core_if)){
5259+ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",_core_if->op_state);
5260+ hcd_disconnect( _core_if );
5261+ pcd_start( _core_if );
5262+ _core_if->op_state = A_PERIPHERAL;
5263+ } else {
5264+ /*
5265+ * Need to disable SOF interrupt immediately. When
5266+ * switching from device to host, the PCD interrupt
5267+ * handler won't handle the interrupt if host mode is
5268+ * already set. The HCD interrupt handler won't get
5269+ * called if the HCD state is HALT. This means that
5270+ * the interrupt does not get handled and Linux
5271+ * complains loudly.
5272+ */
5273+ gintmsk.d32 = 0;
5274+ gintmsk.b.sofintr = 1;
5275+ dwc_modify_reg32(&global_regs->gintmsk,
5276+ gintmsk.d32, 0);
5277+ pcd_stop( _core_if );
5278+ hcd_start( _core_if );
5279+ _core_if->op_state = A_HOST;
5280+ }
5281+ }
5282+ if (gotgint.b.adevtoutchng) {
5283+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5284+ "A-Device Timeout Change++\n");
5285+ }
5286+ if (gotgint.b.debdone) {
5287+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
5288+ "Debounce Done++\n");
5289+ }
5290+
5291+ /* Clear GOTGINT */
5292+ dwc_write_reg32 (&_core_if->core_global_regs->gotgint, gotgint.d32);
5293+
5294+ return 1;
5295+}
5296+
5297+/**
5298+ * This function handles the Connector ID Status Change Interrupt. It
5299+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this
5300+ * is a Device to Host Mode transition or a Host Mode to Device
5301+ * Transition.
5302+ *
5303+ * This only occurs when the cable is connected/removed from the PHY
5304+ * connector.
5305+ *
5306+ * @param _core_if Programming view of DWC_otg controller.
5307+ */
5308+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *_core_if)
5309+{
5310+ uint32_t count = 0;
5311+
5312+ gintsts_data_t gintsts = { .d32 = 0 };
5313+ gintmsk_data_t gintmsk = { .d32 = 0 };
5314+ gotgctl_data_t gotgctl = { .d32 = 0 };
5315+
5316+ /*
5317+ * Need to disable SOF interrupt immediately. If switching from device
5318+ * to host, the PCD interrupt handler won't handle the interrupt if
5319+ * host mode is already set. The HCD interrupt handler won't get
5320+ * called if the HCD state is HALT. This means that the interrupt does
5321+ * not get handled and Linux complains loudly.
5322+ */
5323+ gintmsk.b.sofintr = 1;
5324+ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
5325+
5326+ DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n",
5327+ (dwc_otg_is_host_mode(_core_if)?"Host":"Device"));
5328+ gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
5329+ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
5330+ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
5331+
5332+ /* B-Device connector (Device Mode) */
5333+ if (gotgctl.b.conidsts) {
5334+ /* Wait for switch to device mode. */
5335+ while (!dwc_otg_is_device_mode(_core_if) ){
5336+ DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n",
5337+ (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
5338+ MDELAY(100);
5339+ if (++count > 10000) *(uint32_t*)NULL=0;
5340+ }
5341+ _core_if->op_state = B_PERIPHERAL;
5342+ dwc_otg_core_init(_core_if);
5343+ dwc_otg_enable_global_interrupts(_core_if);
5344+ pcd_start( _core_if );
5345+ } else {
5346+ /* A-Device connector (Host Mode) */
5347+ while (!dwc_otg_is_host_mode(_core_if) ) {
5348+ DWC_PRINT("Waiting for Host Mode, Mode=%s\n",
5349+ (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral"));
5350+ MDELAY(100);
5351+ if (++count > 10000) *(uint32_t*)NULL=0;
5352+ }
5353+ _core_if->op_state = A_HOST;
5354+ /*
5355+ * Initialize the Core for Host mode.
5356+ */
5357+ dwc_otg_core_init(_core_if);
5358+ dwc_otg_enable_global_interrupts(_core_if);
5359+ hcd_start( _core_if );
5360+ }
5361+
5362+ /* Set flag and clear interrupt */
5363+ gintsts.b.conidstschng = 1;
5364+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5365+
5366+ return 1;
5367+}
5368+
5369+/**
5370+ * This interrupt indicates that a device is initiating the Session
5371+ * Request Protocol to request the host to turn on bus power so a new
5372+ * session can begin. The handler responds by turning on bus power. If
5373+ * the DWC_otg controller is in low power mode, the handler brings the
5374+ * controller out of low power mode before turning on bus power.
5375+ *
5376+ * @param _core_if Programming view of DWC_otg controller.
5377+ */
5378+int32_t dwc_otg_handle_session_req_intr( dwc_otg_core_if_t *_core_if )
5379+{
5380+#ifndef DWC_HOST_ONLY // winder
5381+ hprt0_data_t hprt0;
5382+#endif
5383+ gintsts_data_t gintsts;
5384+
5385+#ifndef DWC_HOST_ONLY
5386+ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
5387+
5388+ if (dwc_otg_is_device_mode(_core_if) ) {
5389+ DWC_PRINT("SRP: Device mode\n");
5390+ } else {
5391+ DWC_PRINT("SRP: Host mode\n");
5392+
5393+ /* Turn on the port power bit. */
5394+ hprt0.d32 = dwc_otg_read_hprt0( _core_if );
5395+ hprt0.b.prtpwr = 1;
5396+ dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
5397+
5398+ /* Start the Connection timer. So a message can be displayed
5399+ * if connect does not occur within 10 seconds. */
5400+ hcd_session_start( _core_if );
5401+ }
5402+#endif
5403+
5404+ /* Clear interrupt */
5405+ gintsts.d32 = 0;
5406+ gintsts.b.sessreqintr = 1;
5407+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5408+
5409+ return 1;
5410+}
5411+
5412+/**
5413+ * This interrupt indicates that the DWC_otg controller has detected a
5414+ * resume or remote wakeup sequence. If the DWC_otg controller is in
5415+ * low power mode, the handler must brings the controller out of low
5416+ * power mode. The controller automatically begins resume
5417+ * signaling. The handler schedules a time to stop resume signaling.
5418+ */
5419+int32_t dwc_otg_handle_wakeup_detected_intr( dwc_otg_core_if_t *_core_if )
5420+{
5421+ gintsts_data_t gintsts;
5422+
5423+ DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");
5424+
5425+ if (dwc_otg_is_device_mode(_core_if) ) {
5426+ dctl_data_t dctl = {.d32=0};
5427+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
5428+ dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts));
5429+#ifdef PARTIAL_POWER_DOWN
5430+ if (_core_if->hwcfg4.b.power_optimiz) {
5431+ pcgcctl_data_t power = {.d32=0};
5432+
5433+ power.d32 = dwc_read_reg32( _core_if->pcgcctl );
5434+ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);
5435+
5436+ power.b.stoppclk = 0;
5437+ dwc_write_reg32( _core_if->pcgcctl, power.d32);
5438+
5439+ power.b.pwrclmp = 0;
5440+ dwc_write_reg32( _core_if->pcgcctl, power.d32);
5441+
5442+ power.b.rstpdwnmodule = 0;
5443+ dwc_write_reg32( _core_if->pcgcctl, power.d32);
5444+ }
5445+#endif
5446+ /* Clear the Remote Wakeup Signalling */
5447+ dctl.b.rmtwkupsig = 1;
5448+ dwc_modify_reg32( &_core_if->dev_if->dev_global_regs->dctl,
5449+ dctl.d32, 0 );
5450+
5451+ if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) {
5452+ _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p );
5453+ }
5454+
5455+ } else {
5456+ /*
5457+ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
5458+ * so that OPT tests pass with all PHYs).
5459+ */
5460+ hprt0_data_t hprt0 = {.d32=0};
5461+ pcgcctl_data_t pcgcctl = {.d32=0};
5462+ /* Restart the Phy Clock */
5463+ pcgcctl.b.stoppclk = 1;
5464+ dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0);
5465+ UDELAY(10);
5466+
5467+ /* Now wait for 70 ms. */
5468+ hprt0.d32 = dwc_otg_read_hprt0( _core_if );
5469+ DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32);
5470+ MDELAY(70);
5471+ hprt0.b.prtres = 0; /* Resume */
5472+ dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
5473+ DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(_core_if->host_if->hprt0));
5474+ }
5475+
5476+ /* Clear interrupt */
5477+ gintsts.d32 = 0;
5478+ gintsts.b.wkupintr = 1;
5479+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5480+
5481+ return 1;
5482+}
5483+
5484+/**
5485+ * This interrupt indicates that a device has been disconnected from
5486+ * the root port.
5487+ */
5488+int32_t dwc_otg_handle_disconnect_intr( dwc_otg_core_if_t *_core_if)
5489+{
5490+ gintsts_data_t gintsts;
5491+
5492+ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
5493+ (dwc_otg_is_host_mode(_core_if)?"Host":"Device"),
5494+ op_state_str(_core_if));
5495+
5496+/** @todo Consolidate this if statement. */
5497+#ifndef DWC_HOST_ONLY
5498+ if (_core_if->op_state == B_HOST) {
5499+ /* If in device mode Disconnect and stop the HCD, then
5500+ * start the PCD. */
5501+ hcd_disconnect( _core_if );
5502+ pcd_start( _core_if );
5503+ _core_if->op_state = B_PERIPHERAL;
5504+ } else if (dwc_otg_is_device_mode(_core_if)) {
5505+ gotgctl_data_t gotgctl = { .d32 = 0 };
5506+ gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
5507+ if (gotgctl.b.hstsethnpen==1) {
5508+ /* Do nothing, if HNP in process the OTG
5509+ * interrupt "Host Negotiation Detected"
5510+ * interrupt will do the mode switch.
5511+ */
5512+ } else if (gotgctl.b.devhnpen == 0) {
5513+ /* If in device mode Disconnect and stop the HCD, then
5514+ * start the PCD. */
5515+ hcd_disconnect( _core_if );
5516+ pcd_start( _core_if );
5517+ _core_if->op_state = B_PERIPHERAL;
5518+ } else {
5519+ DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n");
5520+ }
5521+ } else {
5522+ if (_core_if->op_state == A_HOST) {
5523+ /* A-Cable still connected but device disconnected. */
5524+ hcd_disconnect( _core_if );
5525+ }
5526+ }
5527+#endif
5528+/* Without OTG, we should use the disconnect function!? winder added.*/
5529+#if 1 // NO OTG, so host only!!
5530+ hcd_disconnect( _core_if );
5531+#endif
5532+
5533+ gintsts.d32 = 0;
5534+ gintsts.b.disconnect = 1;
5535+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32);
5536+ return 1;
5537+}
5538+/**
5539+ * This interrupt indicates that SUSPEND state has been detected on
5540+ * the USB.
5541+ *
5542+ * For HNP the USB Suspend interrupt signals the change from
5543+ * "a_peripheral" to "a_host".
5544+ *
5545+ * When power management is enabled the core will be put in low power
5546+ * mode.
5547+ */
5548+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *_core_if )
5549+{
5550+ dsts_data_t dsts;
5551+ gintsts_data_t gintsts;
5552+
5553+ //805141:<IFTW-fchang>.removed DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n");
5554+
5555+ if (dwc_otg_is_device_mode( _core_if ) ) {
5556+ /* Check the Device status register to determine if the Suspend
5557+ * state is active. */
5558+ dsts.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts);
5559+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
5560+ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
5561+ "HWCFG4.power Optimize=%d\n",
5562+ dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz);
5563+
5564+
5565+#ifdef PARTIAL_POWER_DOWN
5566+/** @todo Add a module parameter for power management. */
5567+
5568+ if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) {
5569+ pcgcctl_data_t power = {.d32=0};
5570+ DWC_DEBUGPL(DBG_CIL, "suspend\n");
5571+
5572+ power.b.pwrclmp = 1;
5573+ dwc_write_reg32( _core_if->pcgcctl, power.d32);
5574+
5575+ power.b.rstpdwnmodule = 1;
5576+ dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
5577+
5578+ power.b.stoppclk = 1;
5579+ dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32);
5580+
5581+ } else {
5582+ DWC_DEBUGPL(DBG_ANY,"disconnect?\n");
5583+ }
5584+#endif
5585+ /* PCD callback for suspend. */
5586+ pcd_suspend(_core_if);
5587+ } else {
5588+ if (_core_if->op_state == A_PERIPHERAL) {
5589+ DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n");
5590+ /* Clear the a_peripheral flag, back to a_host. */
5591+ pcd_stop( _core_if );
5592+ hcd_start( _core_if );
5593+ _core_if->op_state = A_HOST;
5594+ }
5595+ }
5596+
5597+ /* Clear interrupt */
5598+ gintsts.d32 = 0;
5599+ gintsts.b.usbsuspend = 1;
5600+ dwc_write_reg32( &_core_if->core_global_regs->gintsts, gintsts.d32);
5601+
5602+ return 1;
5603+}
5604+
5605+
5606+/**
5607+ * This function returns the Core Interrupt register.
5608+ */
5609+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *_core_if)
5610+{
5611+ gintsts_data_t gintsts;
5612+ gintmsk_data_t gintmsk;
5613+ gintmsk_data_t gintmsk_common = {.d32=0};
5614+ gintmsk_common.b.wkupintr = 1;
5615+ gintmsk_common.b.sessreqintr = 1;
5616+ gintmsk_common.b.conidstschng = 1;
5617+ gintmsk_common.b.otgintr = 1;
5618+ gintmsk_common.b.modemismatch = 1;
5619+ gintmsk_common.b.disconnect = 1;
5620+ gintmsk_common.b.usbsuspend = 1;
5621+ /** @todo: The port interrupt occurs while in device
5622+ * mode. Added code to CIL to clear the interrupt for now!
5623+ */
5624+ gintmsk_common.b.portintr = 1;
5625+
5626+ gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts);
5627+ gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk);
5628+#ifdef DEBUG
5629+ /* if any common interrupts set */
5630+ if (gintsts.d32 & gintmsk_common.d32) {
5631+ DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
5632+ gintsts.d32, gintmsk.d32);
5633+ }
5634+#endif
5635+
5636+ return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
5637+
5638+}
5639+
5640+/**
5641+ * Common interrupt handler.
5642+ *
5643+ * The common interrupts are those that occur in both Host and Device mode.
5644+ * This handler handles the following interrupts:
5645+ * - Mode Mismatch Interrupt
5646+ * - Disconnect Interrupt
5647+ * - OTG Interrupt
5648+ * - Connector ID Status Change Interrupt
5649+ * - Session Request Interrupt.
5650+ * - Resume / Remote Wakeup Detected Interrupt.
5651+ *
5652+ */
5653+extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if )
5654+{
5655+ int retval = 0;
5656+ gintsts_data_t gintsts;
5657+
5658+ gintsts.d32 = dwc_otg_read_common_intr(_core_if);
5659+
5660+ if (gintsts.b.modemismatch) {
5661+ retval |= dwc_otg_handle_mode_mismatch_intr( _core_if );
5662+ }
5663+ if (gintsts.b.otgintr) {
5664+ retval |= dwc_otg_handle_otg_intr( _core_if );
5665+ }
5666+ if (gintsts.b.conidstschng) {
5667+ retval |= dwc_otg_handle_conn_id_status_change_intr( _core_if );
5668+ }
5669+ if (gintsts.b.disconnect) {
5670+ retval |= dwc_otg_handle_disconnect_intr( _core_if );
5671+ }
5672+ if (gintsts.b.sessreqintr) {
5673+ retval |= dwc_otg_handle_session_req_intr( _core_if );
5674+ }
5675+ if (gintsts.b.wkupintr) {
5676+ retval |= dwc_otg_handle_wakeup_detected_intr( _core_if );
5677+ }
5678+ if (gintsts.b.usbsuspend) {
5679+ retval |= dwc_otg_handle_usb_suspend_intr( _core_if );
5680+ }
5681+ if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) {
5682+ /* The port interrupt occurs while in device mode with HPRT0
5683+ * Port Enable/Disable.
5684+ */
5685+ gintsts.d32 = 0;
5686+ gintsts.b.portintr = 1;
5687+ dwc_write_reg32(&_core_if->core_global_regs->gintsts,
5688+ gintsts.d32);
5689+ retval |= 1;
5690+
5691+ }
5692+ return retval;
5693+}
5694--- /dev/null
5695+++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
5696@@ -0,0 +1,1274 @@
5697+/* ==========================================================================
5698+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
5699+ * $Revision: 1.1.1.1 $
5700+ * $Date: 2009-04-17 06:15:34 $
5701+ * $Change: 631780 $
5702+ *
5703+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
5704+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
5705+ * otherwise expressly agreed to in writing between Synopsys and you.
5706+ *
5707+ * The Software IS NOT an item of Licensed Software or Licensed Product under
5708+ * any End User Software License Agreement or Agreement for Licensed Product
5709+ * with Synopsys or any supplement thereto. You are permitted to use and
5710+ * redistribute this Software in source and binary forms, with or without
5711+ * modification, provided that redistributions of source code must retain this
5712+ * notice. You may not view, use, disclose, copy or distribute this file or
5713+ * any information contained herein except pursuant to this license grant from
5714+ * Synopsys. If you do not agree with this notice, including the disclaimer
5715+ * below, then you are not authorized to use the Software.
5716+ *
5717+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
5718+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
5719+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
5720+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
5721+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5722+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
5723+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
5724+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
5725+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
5726+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5727+ * DAMAGE.
5728+ * ========================================================================== */
5729+
5730+/** @file
5731+ * The dwc_otg_driver module provides the initialization and cleanup entry
5732+ * points for the DWC_otg driver. This module will be dynamically installed
5733+ * after Linux is booted using the insmod command. When the module is
5734+ * installed, the dwc_otg_init function is called. When the module is
5735+ * removed (using rmmod), the dwc_otg_cleanup function is called.
5736+ *
5737+ * This module also defines a data structure for the dwc_otg_driver, which is
5738+ * used in conjunction with the standard ARM lm_device structure. These
5739+ * structures allow the OTG driver to comply with the standard Linux driver
5740+ * model in which devices and drivers are registered with a bus driver. This
5741+ * has the benefit that Linux can expose attributes of the driver and device
5742+ * in its special sysfs file system. Users can then read or write files in
5743+ * this file system to perform diagnostics on the driver components or the
5744+ * device.
5745+ */
5746+
5747+#include <linux/kernel.h>
5748+#include <linux/module.h>
5749+#include <linux/moduleparam.h>
5750+#include <linux/init.h>
5751+#include <linux/gpio.h>
5752+
5753+#include <linux/device.h>
5754+#include <linux/platform_device.h>
5755+
5756+#include <linux/errno.h>
5757+#include <linux/types.h>
5758+#include <linux/stat.h> /* permission constants */
5759+#include <linux/irq.h>
5760+#include <asm/io.h>
5761+
5762+#include "dwc_otg_plat.h"
5763+#include "dwc_otg_attr.h"
5764+#include "dwc_otg_driver.h"
5765+#include "dwc_otg_cil.h"
5766+#include "dwc_otg_cil_ifx.h"
5767+
5768+// #include "dwc_otg_pcd.h" // device
5769+#include "dwc_otg_hcd.h" // host
5770+
5771+#include "dwc_otg_ifx.h" // for Infineon platform specific.
5772+
5773+#define DWC_DRIVER_VERSION "2.60a 22-NOV-2006"
5774+#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
5775+
5776+const char dwc_driver_name[] = "dwc_otg";
5777+
5778+static unsigned long dwc_iomem_base = IFX_USB_IOMEM_BASE;
5779+int dwc_irq = LTQ_USB_INT;
5780+//int dwc_irq = 54;
5781+//int dwc_irq = IFXMIPS_USB_OC_INT;
5782+
5783+extern int ifx_usb_hc_init(unsigned long base_addr, int irq);
5784+extern void ifx_usb_hc_remove(void);
5785+
5786+/*-------------------------------------------------------------------------*/
5787+/* Encapsulate the module parameter settings */
5788+
5789+static dwc_otg_core_params_t dwc_otg_module_params = {
5790+ .opt = -1,
5791+ .otg_cap = -1,
5792+ .dma_enable = -1,
5793+ .dma_burst_size = -1,
5794+ .speed = -1,
5795+ .host_support_fs_ls_low_power = -1,
5796+ .host_ls_low_power_phy_clk = -1,
5797+ .enable_dynamic_fifo = -1,
5798+ .data_fifo_size = -1,
5799+ .dev_rx_fifo_size = -1,
5800+ .dev_nperio_tx_fifo_size = -1,
5801+ .dev_perio_tx_fifo_size = /* dev_perio_tx_fifo_size_1 */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 15 */
5802+ .host_rx_fifo_size = -1,
5803+ .host_nperio_tx_fifo_size = -1,
5804+ .host_perio_tx_fifo_size = -1,
5805+ .max_transfer_size = -1,
5806+ .max_packet_count = -1,
5807+ .host_channels = -1,
5808+ .dev_endpoints = -1,
5809+ .phy_type = -1,
5810+ .phy_utmi_width = -1,
5811+ .phy_ulpi_ddr = -1,
5812+ .phy_ulpi_ext_vbus = -1,
5813+ .i2c_enable = -1,
5814+ .ulpi_fs_ls = -1,
5815+ .ts_dline = -1,
5816+ .en_multiple_tx_fifo = -1,
5817+ .dev_tx_fifo_size = { /* dev_tx_fifo_size */
5818+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
5819+ }, /* 15 */
5820+ .thr_ctl = -1,
5821+ .tx_thr_length = -1,
5822+ .rx_thr_length = -1,
5823+};
5824+
5825+/**
5826+ * This function shows the Driver Version.
5827+ */
5828+static ssize_t version_show(struct device_driver *dev, char *buf)
5829+{
5830+ return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n",
5831+ DWC_DRIVER_VERSION);
5832+}
5833+static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
5834+
5835+/**
5836+ * Global Debug Level Mask.
5837+ */
5838+uint32_t g_dbg_lvl = 0xff; /* OFF */
5839+
5840+/**
5841+ * This function shows the driver Debug Level.
5842+ */
5843+static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf)
5844+{
5845+ return sprintf(_buf, "0x%0x\n", g_dbg_lvl);
5846+}
5847+/**
5848+ * This function stores the driver Debug Level.
5849+ */
5850+static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf,
5851+ size_t _count)
5852+{
5853+ g_dbg_lvl = simple_strtoul(_buf, NULL, 16);
5854+ return _count;
5855+}
5856+static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
5857+
5858+/**
5859+ * This function is called during module intialization to verify that
5860+ * the module parameters are in a valid state.
5861+ */
5862+static int check_parameters(dwc_otg_core_if_t *core_if)
5863+{
5864+ int i;
5865+ int retval = 0;
5866+
5867+/* Checks if the parameter is outside of its valid range of values */
5868+#define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \
5869+ ((dwc_otg_module_params._param_ < (_low_)) || \
5870+ (dwc_otg_module_params._param_ > (_high_)))
5871+
5872+/* If the parameter has been set by the user, check that the parameter value is
5873+ * within the value range of values. If not, report a module error. */
5874+#define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \
5875+ do { \
5876+ if (dwc_otg_module_params._param_ != -1) { \
5877+ if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \
5878+ DWC_ERROR("`%d' invalid for parameter `%s'\n", \
5879+ dwc_otg_module_params._param_, _string_); \
5880+ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
5881+ retval ++; \
5882+ } \
5883+ } \
5884+ } while (0)
5885+
5886+ DWC_OTG_PARAM_ERR(opt,0,1,"opt");
5887+ DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
5888+ DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
5889+ DWC_OTG_PARAM_ERR(speed,0,1,"speed");
5890+ DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
5891+ DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
5892+ DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
5893+ DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
5894+ DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
5895+ DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
5896+ DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
5897+ DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
5898+ DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
5899+ DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
5900+ DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
5901+ DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
5902+ DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
5903+ DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
5904+ DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
5905+ DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
5906+ DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
5907+ DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
5908+ DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
5909+
5910+ if (dwc_otg_module_params.dma_burst_size != -1) {
5911+ if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
5912+ DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
5913+ DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
5914+ DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
5915+ DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
5916+ DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
5917+ DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
5918+ DWC_OTG_PARAM_TEST(dma_burst_size,256,256))
5919+ {
5920+ DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
5921+ dwc_otg_module_params.dma_burst_size);
5922+ dwc_otg_module_params.dma_burst_size = 32;
5923+ retval ++;
5924+ }
5925+ }
5926+
5927+ if (dwc_otg_module_params.phy_utmi_width != -1) {
5928+ if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) &&
5929+ DWC_OTG_PARAM_TEST(phy_utmi_width,16,16))
5930+ {
5931+ DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
5932+ dwc_otg_module_params.phy_utmi_width);
5933+ //dwc_otg_module_params.phy_utmi_width = 16;
5934+ dwc_otg_module_params.phy_utmi_width = 8;
5935+ retval ++;
5936+ }
5937+ }
5938+
5939+ for (i=0; i<15; i++) {
5940+ /** @todo should be like above */
5941+ //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size");
5942+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
5943+ if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768)) {
5944+ DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
5945+ dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
5946+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
5947+ retval ++;
5948+ }
5949+ }
5950+ }
5951+
5952+ DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
5953+ for (i = 0; i < 15; i++) {
5954+ /** @todo should be like above */
5955+ //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size");
5956+ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
5957+ if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
5958+ DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
5959+ dwc_otg_module_params.dev_tx_fifo_size[i],
5960+ "dev_tx_fifo_size", i);
5961+ dwc_otg_module_params.dev_tx_fifo_size[i] =
5962+ dwc_param_dev_tx_fifo_size_default;
5963+ retval++;
5964+ }
5965+ }
5966+ }
5967+ DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
5968+ DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
5969+ DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
5970+
5971+ /* At this point, all module parameters that have been set by the user
5972+ * are valid, and those that have not are left unset. Now set their
5973+ * default values and/or check the parameters against the hardware
5974+ * configurations of the OTG core. */
5975+
5976+
5977+
5978+/* This sets the parameter to the default value if it has not been set by the
5979+ * user */
5980+#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
5981+ ({ \
5982+ int changed = 1; \
5983+ if (dwc_otg_module_params._param_ == -1) { \
5984+ changed = 0; \
5985+ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
5986+ } \
5987+ changed; \
5988+ })
5989+
5990+/* This checks the macro agains the hardware configuration to see if it is
5991+ * valid. It is possible that the default value could be invalid. In this
5992+ * case, it will report a module error if the user touched the parameter.
5993+ * Otherwise it will adjust the value without any error. */
5994+#define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \
5995+ ({ \
5996+ int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
5997+ int error = 0; \
5998+ if (!(_is_valid_)) { \
5999+ if (changed) { \
6000+ DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_,_str_); \
6001+ error = 1; \
6002+ } \
6003+ dwc_otg_module_params._param_ = (_set_valid_); \
6004+ } \
6005+ error; \
6006+ })
6007+
6008+ /* OTG Cap */
6009+ retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap",
6010+ ({
6011+ int valid;
6012+ valid = 1;
6013+ switch (dwc_otg_module_params.otg_cap) {
6014+ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
6015+ if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0;
6016+ break;
6017+ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
6018+ if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
6019+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
6020+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
6021+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST))
6022+ {
6023+ valid = 0;
6024+ }
6025+ break;
6026+ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
6027+ /* always valid */
6028+ break;
6029+ }
6030+ valid;
6031+ }),
6032+ (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
6033+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
6034+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
6035+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
6036+ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
6037+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
6038+
6039+ retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable",
6040+ ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
6041+ 0);
6042+
6043+ retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt",
6044+ 1,
6045+ 0);
6046+
6047+ DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
6048+
6049+ retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
6050+ "host_support_fs_ls_low_power",
6051+ 1, 0);
6052+
6053+ retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
6054+ "enable_dynamic_fifo",
6055+ ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
6056+ (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
6057+
6058+
6059+ retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
6060+ "data_fifo_size",
6061+ (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
6062+ core_if->hwcfg3.b.dfifo_depth);
6063+
6064+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
6065+ "dev_rx_fifo_size",
6066+ (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
6067+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
6068+
6069+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
6070+ "dev_nperio_tx_fifo_size",
6071+ (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
6072+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
6073+
6074+ retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
6075+ "host_rx_fifo_size",
6076+ (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
6077+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
6078+
6079+
6080+ retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
6081+ "host_nperio_tx_fifo_size",
6082+ (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
6083+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
6084+
6085+ retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
6086+ "host_perio_tx_fifo_size",
6087+ (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
6088+ ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
6089+
6090+ retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
6091+ "max_transfer_size",
6092+ (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
6093+ ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
6094+
6095+ retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
6096+ "max_packet_count",
6097+ (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
6098+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
6099+
6100+ retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
6101+ "host_channels",
6102+ (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
6103+ (core_if->hwcfg2.b.num_host_chan + 1));
6104+
6105+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
6106+ "dev_endpoints",
6107+ (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
6108+ core_if->hwcfg2.b.num_dev_ep);
6109+
6110+/*
6111+ * Define the following to disable the FS PHY Hardware checking. This is for
6112+ * internal testing only.
6113+ *
6114+ * #define NO_FS_PHY_HW_CHECKS
6115+ */
6116+
6117+#ifdef NO_FS_PHY_HW_CHECKS
6118+ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
6119+ "phy_type", 1, 0);
6120+#else
6121+ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
6122+ "phy_type",
6123+ ({
6124+ int valid = 0;
6125+ if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
6126+ ((core_if->hwcfg2.b.hs_phy_type == 1) ||
6127+ (core_if->hwcfg2.b.hs_phy_type == 3)))
6128+ {
6129+ valid = 1;
6130+ }
6131+ else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
6132+ ((core_if->hwcfg2.b.hs_phy_type == 2) ||
6133+ (core_if->hwcfg2.b.hs_phy_type == 3)))
6134+ {
6135+ valid = 1;
6136+ }
6137+ else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
6138+ (core_if->hwcfg2.b.fs_phy_type == 1))
6139+ {
6140+ valid = 1;
6141+ }
6142+ valid;
6143+ }),
6144+ ({
6145+ int set = DWC_PHY_TYPE_PARAM_FS;
6146+ if (core_if->hwcfg2.b.hs_phy_type) {
6147+ if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
6148+ (core_if->hwcfg2.b.hs_phy_type == 1)) {
6149+ set = DWC_PHY_TYPE_PARAM_UTMI;
6150+ }
6151+ else {
6152+ set = DWC_PHY_TYPE_PARAM_ULPI;
6153+ }
6154+ }
6155+ set;
6156+ }));
6157+#endif
6158+
6159+ retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed",
6160+ (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
6161+ dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
6162+
6163+ retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
6164+ "host_ls_low_power_phy_clk",
6165+ ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
6166+ ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
6167+
6168+ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
6169+ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
6170+ DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
6171+ DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
6172+ DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
6173+
6174+#ifdef NO_FS_PHY_HW_CHECKS
6175+ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
6176+ "i2c_enable", 1, 0);
6177+#else
6178+ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
6179+ "i2c_enable",
6180+ (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
6181+ 0);
6182+#endif
6183+
6184+ for (i=0; i<16; i++) {
6185+
6186+ int changed = 1;
6187+ int error = 0;
6188+
6189+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
6190+ changed = 0;
6191+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
6192+ }
6193+ if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
6194+ if (changed) {
6195+ DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i],i);
6196+ error = 1;
6197+ }
6198+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
6199+ }
6200+ retval += error;
6201+ }
6202+
6203+ retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo,
6204+ "en_multiple_tx_fifo",
6205+ ((dwc_otg_module_params.en_multiple_tx_fifo == 1) &&
6206+ (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, 0);
6207+
6208+ for (i = 0; i < 16; i++) {
6209+ int changed = 1;
6210+ int error = 0;
6211+ if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
6212+ changed = 0;
6213+ dwc_otg_module_params.dev_tx_fifo_size[i] =
6214+ dwc_param_dev_tx_fifo_size_default;
6215+ }
6216+ if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <=
6217+ (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
6218+ if (changed) {
6219+ DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'."
6220+ "Check HW configuration.\n",dwc_otg_module_params.dev_tx_fifo_size[i],i);
6221+ error = 1;
6222+ }
6223+ dwc_otg_module_params.dev_tx_fifo_size[i] =
6224+ dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
6225+ }
6226+ retval += error;
6227+ }
6228+ DWC_OTG_PARAM_SET_DEFAULT(thr_ctl);
6229+ DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
6230+ DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
6231+ return retval;
6232+} // check_parameters
6233+
6234+
6235+/**
6236+ * This function is the top level interrupt handler for the Common
6237+ * (Device and host modes) interrupts.
6238+ */
6239+static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev)
6240+{
6241+ dwc_otg_device_t *otg_dev = _dev;
6242+ int32_t retval = IRQ_NONE;
6243+
6244+ retval = dwc_otg_handle_common_intr( otg_dev->core_if );
6245+
6246+ mask_and_ack_ifx_irq (_irq);
6247+
6248+ return IRQ_RETVAL(retval);
6249+}
6250+
6251+
6252+/**
6253+ * This function is called when a DWC_OTG device is unregistered with the
6254+ * dwc_otg_driver. This happens, for example, when the rmmod command is
6255+ * executed. The device may or may not be electrically present. If it is
6256+ * present, the driver stops device processing. Any resources used on behalf
6257+ * of this device are freed.
6258+ *
6259+ * @return
6260+ */
6261+static int
6262+dwc_otg_driver_remove(struct platform_device *_dev)
6263+{
6264+ //dwc_otg_device_t *otg_dev = dev_get_drvdata(&_dev->dev);
6265+ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
6266+
6267+ DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
6268+
6269+ if (otg_dev == NULL) {
6270+ /* Memory allocation for the dwc_otg_device failed. */
6271+ return 0;
6272+ }
6273+
6274+ /*
6275+ * Free the IRQ
6276+ */
6277+ if (otg_dev->common_irq_installed) {
6278+ free_irq( otg_dev->irq, otg_dev );
6279+ }
6280+
6281+#ifndef DWC_DEVICE_ONLY
6282+ if (otg_dev->hcd != NULL) {
6283+ dwc_otg_hcd_remove(&_dev->dev);
6284+ }
6285+#endif
6286+ printk("after removehcd\n");
6287+
6288+// Note: Integrate HOST and DEVICE(Gadget) is not planned yet.
6289+#ifndef DWC_HOST_ONLY
6290+ if (otg_dev->pcd != NULL) {
6291+ dwc_otg_pcd_remove(otg_dev);
6292+ }
6293+#endif
6294+ if (otg_dev->core_if != NULL) {
6295+ dwc_otg_cil_remove( otg_dev->core_if );
6296+ }
6297+ printk("after removecil\n");
6298+
6299+ /*
6300+ * Remove the device attributes
6301+ */
6302+ dwc_otg_attr_remove(&_dev->dev);
6303+ printk("after removeattr\n");
6304+
6305+ /*
6306+ * Return the memory.
6307+ */
6308+ if (otg_dev->base != NULL) {
6309+ iounmap(otg_dev->base);
6310+ }
6311+ if (otg_dev->phys_addr != 0) {
6312+ release_mem_region(otg_dev->phys_addr, otg_dev->base_len);
6313+ }
6314+ kfree(otg_dev);
6315+
6316+ /*
6317+ * Clear the drvdata pointer.
6318+ */
6319+ //dev_set_drvdata(&_dev->dev, 0);
6320+ platform_set_drvdata(_dev, 0);
6321+ return 0;
6322+}
6323+
6324+/**
6325+ * This function is called when an DWC_OTG device is bound to a
6326+ * dwc_otg_driver. It creates the driver components required to
6327+ * control the device (CIL, HCD, and PCD) and it initializes the
6328+ * device. The driver components are stored in a dwc_otg_device
6329+ * structure. A reference to the dwc_otg_device is saved in the
6330+ * lm_device. This allows the driver to access the dwc_otg_device
6331+ * structure on subsequent calls to driver methods for this device.
6332+ *
6333+ * @return
6334+ */
6335+static int __devinit
6336+dwc_otg_driver_probe(struct platform_device *_dev)
6337+{
6338+ int retval = 0;
6339+ dwc_otg_device_t *dwc_otg_device;
6340+ int pin = (int)_dev->dev.platform_data;
6341+ int32_t snpsid;
6342+ struct resource *res;
6343+ gusbcfg_data_t usbcfg = {.d32 = 0};
6344+
6345+ // GPIOs
6346+ if(pin >= 0)
6347+ {
6348+ gpio_request(pin, "usb_power");
6349+ gpio_direction_output(pin, 1);
6350+ gpio_set_value(pin, 1);
6351+ gpio_export(pin, 0);
6352+ }
6353+ dev_dbg(&_dev->dev, "dwc_otg_driver_probe (%p)\n", _dev);
6354+
6355+ dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
6356+ if (dwc_otg_device == 0) {
6357+ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
6358+ retval = -ENOMEM;
6359+ goto fail;
6360+ }
6361+ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
6362+ dwc_otg_device->reg_offset = 0xFFFFFFFF;
6363+
6364+ /*
6365+ * Retrieve the memory and IRQ resources.
6366+ */
6367+ dwc_otg_device->irq = platform_get_irq(_dev, 0);
6368+ if (dwc_otg_device->irq == 0) {
6369+ dev_err(&_dev->dev, "no device irq\n");
6370+ retval = -ENODEV;
6371+ goto fail;
6372+ }
6373+ dev_dbg(&_dev->dev, "OTG - device irq: %d\n", dwc_otg_device->irq);
6374+ res = platform_get_resource(_dev, IORESOURCE_MEM, 0);
6375+ if (res == NULL) {
6376+ dev_err(&_dev->dev, "no CSR address\n");
6377+ retval = -ENODEV;
6378+ goto fail;
6379+ }
6380+ dev_dbg(&_dev->dev, "OTG - ioresource_mem start0x%08x: end:0x%08x\n",
6381+ (unsigned)res->start, (unsigned)res->end);
6382+ dwc_otg_device->phys_addr = res->start;
6383+ dwc_otg_device->base_len = res->end - res->start + 1;
6384+ if (request_mem_region(dwc_otg_device->phys_addr, dwc_otg_device->base_len,
6385+ dwc_driver_name) == NULL) {
6386+ dev_err(&_dev->dev, "request_mem_region failed\n");
6387+ retval = -EBUSY;
6388+ goto fail;
6389+ }
6390+
6391+ /*
6392+ * Map the DWC_otg Core memory into virtual address space.
6393+ */
6394+ dwc_otg_device->base = ioremap_nocache(dwc_otg_device->phys_addr, dwc_otg_device->base_len);
6395+ if (dwc_otg_device->base == NULL) {
6396+ dev_err(&_dev->dev, "ioremap() failed\n");
6397+ retval = -ENOMEM;
6398+ goto fail;
6399+ }
6400+ dev_dbg(&_dev->dev, "mapped base=0x%08x\n", (unsigned)dwc_otg_device->base);
6401+
6402+ /*
6403+ * Attempt to ensure this device is really a DWC_otg Controller.
6404+ * Read and verify the SNPSID register contents. The value should be
6405+ * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
6406+ */
6407+ snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
6408+ if ((snpsid & 0xFFFFF000) != 0x4F542000) {
6409+ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
6410+ retval = -EINVAL;
6411+ goto fail;
6412+ }
6413+
6414+ /*
6415+ * Initialize driver data to point to the global DWC_otg
6416+ * Device structure.
6417+ */
6418+ platform_set_drvdata(_dev, dwc_otg_device);
6419+ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
6420+ dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base, &dwc_otg_module_params);
6421+ if (dwc_otg_device->core_if == 0) {
6422+ dev_err(&_dev->dev, "CIL initialization failed!\n");
6423+ retval = -ENOMEM;
6424+ goto fail;
6425+ }
6426+
6427+ /*
6428+ * Validate parameter values.
6429+ */
6430+ if (check_parameters(dwc_otg_device->core_if) != 0) {
6431+ retval = -EINVAL;
6432+ goto fail;
6433+ }
6434+
6435+ /* Added for PLB DMA phys virt mapping */
6436+ //dwc_otg_device->core_if->phys_addr = dwc_otg_device->phys_addr;
6437+ /*
6438+ * Create Device Attributes in sysfs
6439+ */
6440+ dwc_otg_attr_create (&_dev->dev);
6441+
6442+ /*
6443+ * Disable the global interrupt until all the interrupt
6444+ * handlers are installed.
6445+ */
6446+ dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
6447+ /*
6448+ * Install the interrupt handler for the common interrupts before
6449+ * enabling common interrupts in core_init below.
6450+ */
6451+ DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n", dwc_otg_device->irq);
6452+
6453+ retval = request_irq((unsigned int)dwc_otg_device->irq, dwc_otg_common_irq,
6454+ //SA_INTERRUPT|SA_SHIRQ, "dwc_otg", (void *)dwc_otg_device );
6455+ IRQF_SHARED, "dwc_otg", (void *)dwc_otg_device );
6456+ //IRQF_DISABLED, "dwc_otg", (void *)dwc_otg_device );
6457+ if (retval != 0) {
6458+ DWC_ERROR("request of irq%d failed retval: %d\n", dwc_otg_device->irq, retval);
6459+ retval = -EBUSY;
6460+ goto fail;
6461+ } else {
6462+ dwc_otg_device->common_irq_installed = 1;
6463+ }
6464+
6465+ /*
6466+ * Initialize the DWC_otg core.
6467+ */
6468+ dwc_otg_core_init( dwc_otg_device->core_if );
6469+
6470+
6471+#ifndef DWC_HOST_ONLY // otg device mode. (gadget.)
6472+ /*
6473+ * Initialize the PCD
6474+ */
6475+ retval = dwc_otg_pcd_init(dwc_otg_device);
6476+ if (retval != 0) {
6477+ DWC_ERROR("dwc_otg_pcd_init failed\n");
6478+ dwc_otg_device->pcd = NULL;
6479+ goto fail;
6480+ }
6481+#endif // DWC_HOST_ONLY
6482+
6483+#ifndef DWC_DEVICE_ONLY // otg host mode. (HCD)
6484+ /*
6485+ * Initialize the HCD
6486+ */
6487+#if 1 /*fscz*/
6488+ /* force_host_mode */
6489+ usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg);
6490+ usbcfg.b.force_host_mode = 1;
6491+ dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32);
6492+#endif
6493+ retval = dwc_otg_hcd_init(&_dev->dev, dwc_otg_device);
6494+ if (retval != 0) {
6495+ DWC_ERROR("dwc_otg_hcd_init failed\n");
6496+ dwc_otg_device->hcd = NULL;
6497+ goto fail;
6498+ }
6499+#endif // DWC_DEVICE_ONLY
6500+
6501+ /*
6502+ * Enable the global interrupt after all the interrupt
6503+ * handlers are installed.
6504+ */
6505+ dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
6506+#if 0 /*fscz*/
6507+ usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg);
6508+ usbcfg.b.force_host_mode = 0;
6509+ dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32);
6510+#endif
6511+
6512+
6513+ return 0;
6514+
6515+fail:
6516+ dwc_otg_driver_remove(_dev);
6517+ return retval;
6518+}
6519+
6520+/**
6521+ * This structure defines the methods to be called by a bus driver
6522+ * during the lifecycle of a device on that bus. Both drivers and
6523+ * devices are registered with a bus driver. The bus driver matches
6524+ * devices to drivers based on information in the device and driver
6525+ * structures.
6526+ *
6527+ * The probe function is called when the bus driver matches a device
6528+ * to this driver. The remove function is called when a device is
6529+ * unregistered with the bus driver.
6530+ */
6531+struct platform_driver dwc_otg_driver = {
6532+ .probe = dwc_otg_driver_probe,
6533+ .remove = dwc_otg_driver_remove,
6534+// .suspend = dwc_otg_driver_suspend,
6535+// .resume = dwc_otg_driver_resume,
6536+ .driver = {
6537+ .name = dwc_driver_name,
6538+ .owner = THIS_MODULE,
6539+ },
6540+};
6541+EXPORT_SYMBOL(dwc_otg_driver);
6542+
6543+/**
6544+ * This function is called when the dwc_otg_driver is installed with the
6545+ * insmod command. It registers the dwc_otg_driver structure with the
6546+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function
6547+ * to be called. In addition, the bus driver will automatically expose
6548+ * attributes defined for the device and driver in the special sysfs file
6549+ * system.
6550+ *
6551+ * @return
6552+ */
6553+static int __init dwc_otg_init(void)
6554+{
6555+ int retval = 0;
6556+
6557+ printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
6558+
6559+ // ifxmips setup
6560+ retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq);
6561+ if (retval < 0)
6562+ {
6563+ printk(KERN_ERR "%s retval=%d\n", __func__, retval);
6564+ return retval;
6565+ }
6566+ dwc_otg_power_on(); // ifx only!!
6567+
6568+
6569+ retval = platform_driver_register(&dwc_otg_driver);
6570+
6571+ if (retval < 0) {
6572+ printk(KERN_ERR "%s retval=%d\n", __func__, retval);
6573+ goto error1;
6574+ }
6575+
6576+ retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
6577+ if (retval < 0)
6578+ {
6579+ printk(KERN_ERR "%s retval=%d\n", __func__, retval);
6580+ goto error2;
6581+ }
6582+ retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
6583+ if (retval < 0)
6584+ {
6585+ printk(KERN_ERR "%s retval=%d\n", __func__, retval);
6586+ goto error3;
6587+ }
6588+ return retval;
6589+
6590+
6591+error3:
6592+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
6593+error2:
6594+ driver_unregister(&dwc_otg_driver.driver);
6595+error1:
6596+ ifx_usb_hc_remove();
6597+ return retval;
6598+}
6599+module_init(dwc_otg_init);
6600+
6601+/**
6602+ * This function is called when the driver is removed from the kernel
6603+ * with the rmmod command. The driver unregisters itself with its bus
6604+ * driver.
6605+ *
6606+ */
6607+static void __exit dwc_otg_cleanup(void)
6608+{
6609+ printk(KERN_DEBUG "dwc_otg_cleanup()\n");
6610+
6611+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
6612+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
6613+
6614+ platform_driver_unregister(&dwc_otg_driver);
6615+ ifx_usb_hc_remove();
6616+
6617+ printk(KERN_INFO "%s module removed\n", dwc_driver_name);
6618+}
6619+module_exit(dwc_otg_cleanup);
6620+
6621+MODULE_DESCRIPTION(DWC_DRIVER_DESC);
6622+MODULE_AUTHOR("Synopsys Inc.");
6623+MODULE_LICENSE("GPL");
6624+
6625+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
6626+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
6627+module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
6628+MODULE_PARM_DESC(opt, "OPT Mode");
6629+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
6630+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
6631+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
6632+MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
6633+module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
6634+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
6635+module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
6636+MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
6637+module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
6638+MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
6639+module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
6640+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
6641+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
6642+MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
6643+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
6644+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
6645+module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
6646+MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
6647+module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
6648+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
6649+module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
6650+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
6651+module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
6652+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
6653+module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
6654+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
6655+module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
6656+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
6657+module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
6658+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
6659+module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
6660+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
6661+module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
6662+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
6663+module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
6664+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
6665+module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
6666+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
6667+module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
6668+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
6669+module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
6670+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
6671+module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
6672+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
6673+module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
6674+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
6675+module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
6676+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
6677+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
6678+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
6679+module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
6680+MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
6681+module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
6682+MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
6683+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
6684+/** @todo Set the max to 512K, modify checks */
6685+MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
6686+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
6687+MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
6688+module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
6689+MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
6690+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
6691+MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
6692+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
6693+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
6694+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
6695+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
6696+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
6697+MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
6698+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
6699+MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
6700+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
6701+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
6702+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
6703+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
6704+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
6705+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
6706+module_param_named(debug, g_dbg_lvl, int, 0444);
6707+MODULE_PARM_DESC(debug, "0");
6708+module_param_named(en_multiple_tx_fifo,
6709+ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
6710+MODULE_PARM_DESC(en_multiple_tx_fifo,
6711+ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
6712+module_param_named(dev_tx_fifo_size_1,
6713+ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
6714+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
6715+module_param_named(dev_tx_fifo_size_2,
6716+ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
6717+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
6718+module_param_named(dev_tx_fifo_size_3,
6719+ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
6720+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
6721+module_param_named(dev_tx_fifo_size_4,
6722+ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
6723+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
6724+module_param_named(dev_tx_fifo_size_5,
6725+ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
6726+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
6727+module_param_named(dev_tx_fifo_size_6,
6728+ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
6729+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
6730+module_param_named(dev_tx_fifo_size_7,
6731+ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
6732+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
6733+module_param_named(dev_tx_fifo_size_8,
6734+ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
6735+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
6736+module_param_named(dev_tx_fifo_size_9,
6737+ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
6738+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
6739+module_param_named(dev_tx_fifo_size_10,
6740+ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
6741+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
6742+module_param_named(dev_tx_fifo_size_11,
6743+ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
6744+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
6745+module_param_named(dev_tx_fifo_size_12,
6746+ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
6747+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
6748+module_param_named(dev_tx_fifo_size_13,
6749+ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
6750+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
6751+module_param_named(dev_tx_fifo_size_14,
6752+ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
6753+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
6754+module_param_named(dev_tx_fifo_size_15,
6755+ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
6756+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
6757+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
6758+MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit"
6759+ "0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
6760+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
6761+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
6762+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
6763+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
6764+module_param_named (iomem_base, dwc_iomem_base, ulong, 0444);
6765+MODULE_PARM_DESC (dwc_iomem_base, "The base address of the DWC_OTG register.");
6766+module_param_named (irq, dwc_irq, int, 0444);
6767+MODULE_PARM_DESC (dwc_irq, "The interrupt number");
6768+
6769+/** @page "Module Parameters"
6770+ *
6771+ * The following parameters may be specified when starting the module.
6772+ * These parameters define how the DWC_otg controller should be
6773+ * configured. Parameter values are passed to the CIL initialization
6774+ * function dwc_otg_cil_init
6775+ *
6776+ * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
6777+ *
6778+
6779+ <table>
6780+ <tr><td>Parameter Name</td><td>Meaning</td></tr>
6781+
6782+ <tr>
6783+ <td>otg_cap</td>
6784+ <td>Specifies the OTG capabilities. The driver will automatically detect the
6785+ value for this parameter if none is specified.
6786+ - 0: HNP and SRP capable (default, if available)
6787+ - 1: SRP Only capable
6788+ - 2: No HNP/SRP capable
6789+ </td></tr>
6790+
6791+ <tr>
6792+ <td>dma_enable</td>
6793+ <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
6794+ The driver will automatically detect the value for this parameter if none is
6795+ specified.
6796+ - 0: Slave
6797+ - 1: DMA (default, if available)
6798+ </td></tr>
6799+
6800+ <tr>
6801+ <td>dma_burst_size</td>
6802+ <td>The DMA Burst size (applicable only for External DMA Mode).
6803+ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
6804+ </td></tr>
6805+
6806+ <tr>
6807+ <td>speed</td>
6808+ <td>Specifies the maximum speed of operation in host and device mode. The
6809+ actual speed depends on the speed of the attached device and the value of
6810+ phy_type.
6811+ - 0: High Speed (default)
6812+ - 1: Full Speed
6813+ </td></tr>
6814+
6815+ <tr>
6816+ <td>host_support_fs_ls_low_power</td>
6817+ <td>Specifies whether low power mode is supported when attached to a Full
6818+ Speed or Low Speed device in host mode.
6819+ - 0: Don't support low power mode (default)
6820+ - 1: Support low power mode
6821+ </td></tr>
6822+
6823+ <tr>
6824+ <td>host_ls_low_power_phy_clk</td>
6825+ <td>Specifies the PHY clock rate in low power mode when connected to a Low
6826+ Speed device in host mode. This parameter is applicable only if
6827+ HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
6828+ - 0: 48 MHz (default)
6829+ - 1: 6 MHz
6830+ </td></tr>
6831+
6832+ <tr>
6833+ <td>enable_dynamic_fifo</td>
6834+ <td> Specifies whether FIFOs may be resized by the driver software.
6835+ - 0: Use cC FIFO size parameters
6836+ - 1: Allow dynamic FIFO sizing (default)
6837+ </td></tr>
6838+
6839+ <tr>
6840+ <td>data_fifo_size</td>
6841+ <td>Total number of 4-byte words in the data FIFO memory. This memory
6842+ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
6843+ - Values: 32 to 32768 (default 8192)
6844+
6845+ Note: The total FIFO memory depth in the FPGA configuration is 8192.
6846+ </td></tr>
6847+
6848+ <tr>
6849+ <td>dev_rx_fifo_size</td>
6850+ <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
6851+ FIFO sizing is enabled.
6852+ - Values: 16 to 32768 (default 1064)
6853+ </td></tr>
6854+
6855+ <tr>
6856+ <td>dev_nperio_tx_fifo_size</td>
6857+ <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
6858+ dynamic FIFO sizing is enabled.
6859+ - Values: 16 to 32768 (default 1024)
6860+ </td></tr>
6861+
6862+ <tr>
6863+ <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
6864+ <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
6865+ when dynamic FIFO sizing is enabled.
6866+ - Values: 4 to 768 (default 256)
6867+ </td></tr>
6868+
6869+ <tr>
6870+ <td>host_rx_fifo_size</td>
6871+ <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
6872+ sizing is enabled.
6873+ - Values: 16 to 32768 (default 1024)
6874+ </td></tr>
6875+
6876+ <tr>
6877+ <td>host_nperio_tx_fifo_size</td>
6878+ <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
6879+ dynamic FIFO sizing is enabled in the core.
6880+ - Values: 16 to 32768 (default 1024)
6881+ </td></tr>
6882+
6883+ <tr>
6884+ <td>host_perio_tx_fifo_size</td>
6885+ <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
6886+ sizing is enabled.
6887+ - Values: 16 to 32768 (default 1024)
6888+ </td></tr>
6889+
6890+ <tr>
6891+ <td>max_transfer_size</td>
6892+ <td>The maximum transfer size supported in bytes.
6893+ - Values: 2047 to 65,535 (default 65,535)
6894+ </td></tr>
6895+
6896+ <tr>
6897+ <td>max_packet_count</td>
6898+ <td>The maximum number of packets in a transfer.
6899+ - Values: 15 to 511 (default 511)
6900+ </td></tr>
6901+
6902+ <tr>
6903+ <td>host_channels</td>
6904+ <td>The number of host channel registers to use.
6905+ - Values: 1 to 16 (default 12)
6906+
6907+ Note: The FPGA configuration supports a maximum of 12 host channels.
6908+ </td></tr>
6909+
6910+ <tr>
6911+ <td>dev_endpoints</td>
6912+ <td>The number of endpoints in addition to EP0 available for device mode
6913+ operations.
6914+ - Values: 1 to 15 (default 6 IN and OUT)
6915+
6916+ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
6917+ addition to EP0.
6918+ </td></tr>
6919+
6920+ <tr>
6921+ <td>phy_type</td>
6922+ <td>Specifies the type of PHY interface to use. By default, the driver will
6923+ automatically detect the phy_type.
6924+ - 0: Full Speed
6925+ - 1: UTMI+ (default, if available)
6926+ - 2: ULPI
6927+ </td></tr>
6928+
6929+ <tr>
6930+ <td>phy_utmi_width</td>
6931+ <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
6932+ phy_type of UTMI+. Also, this parameter is applicable only if the
6933+ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
6934+ core has been configured to work at either data path width.
6935+ - Values: 8 or 16 bits (default 16)
6936+ </td></tr>
6937+
6938+ <tr>
6939+ <td>phy_ulpi_ddr</td>
6940+ <td>Specifies whether the ULPI operates at double or single data rate. This
6941+ parameter is only applicable if phy_type is ULPI.
6942+ - 0: single data rate ULPI interface with 8 bit wide data bus (default)
6943+ - 1: double data rate ULPI interface with 4 bit wide data bus
6944+ </td></tr>
6945+
6946+ <tr>
6947+ <td>i2c_enable</td>
6948+ <td>Specifies whether to use the I2C interface for full speed PHY. This
6949+ parameter is only applicable if PHY_TYPE is FS.
6950+ - 0: Disabled (default)
6951+ - 1: Enabled
6952+ </td></tr>
6953+
6954+ <tr>
6955+ <td>otg_en_multiple_tx_fifo</td>
6956+ <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
6957+ The driver will automatically detect the value for this parameter if none is
6958+ specified.
6959+ - 0: Disabled
6960+ - 1: Enabled (default, if available)
6961+ </td></tr>
6962+
6963+ <tr>
6964+ <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
6965+ <td>Number of 4-byte words in each of the Tx FIFOs in device mode
6966+ when dynamic FIFO sizing is enabled.
6967+ - Values: 4 to 768 (default 256)
6968+ </td></tr>
6969+
6970+*/
6971--- /dev/null
6972+++ b/drivers/usb/dwc_otg/dwc_otg_driver.h
6973@@ -0,0 +1,84 @@
6974+/* ==========================================================================
6975+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.h $
6976+ * $Revision: 1.1.1.1 $
6977+ * $Date: 2009-04-17 06:15:34 $
6978+ * $Change: 510275 $
6979+ *
6980+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
6981+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
6982+ * otherwise expressly agreed to in writing between Synopsys and you.
6983+ *
6984+ * The Software IS NOT an item of Licensed Software or Licensed Product under
6985+ * any End User Software License Agreement or Agreement for Licensed Product
6986+ * with Synopsys or any supplement thereto. You are permitted to use and
6987+ * redistribute this Software in source and binary forms, with or without
6988+ * modification, provided that redistributions of source code must retain this
6989+ * notice. You may not view, use, disclose, copy or distribute this file or
6990+ * any information contained herein except pursuant to this license grant from
6991+ * Synopsys. If you do not agree with this notice, including the disclaimer
6992+ * below, then you are not authorized to use the Software.
6993+ *
6994+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
6995+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
6996+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
6997+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
6998+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
6999+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7000+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7001+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7002+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7003+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7004+ * DAMAGE.
7005+ * ========================================================================== */
7006+
7007+#if !defined(__DWC_OTG_DRIVER_H__)
7008+#define __DWC_OTG_DRIVER_H__
7009+
7010+/** @file
7011+ * This file contains the interface to the Linux driver.
7012+ */
7013+#include "dwc_otg_cil.h"
7014+
7015+/* Type declarations */
7016+struct dwc_otg_pcd;
7017+struct dwc_otg_hcd;
7018+
7019+/**
7020+ * This structure is a wrapper that encapsulates the driver components used to
7021+ * manage a single DWC_otg controller.
7022+ */
7023+typedef struct dwc_otg_device
7024+{
7025+ /** Base address returned from ioremap() */
7026+ void *base;
7027+
7028+ /** Pointer to the core interface structure. */
7029+ dwc_otg_core_if_t *core_if;
7030+
7031+ /** Register offset for Diagnostic API.*/
7032+ uint32_t reg_offset;
7033+
7034+ /** Pointer to the PCD structure. */
7035+ struct dwc_otg_pcd *pcd;
7036+
7037+ /** Pointer to the HCD structure. */
7038+ struct dwc_otg_hcd *hcd;
7039+
7040+ /** Flag to indicate whether the common IRQ handler is installed. */
7041+ uint8_t common_irq_installed;
7042+
7043+ /** Interrupt request number. */
7044+ unsigned int irq;
7045+
7046+ /** Physical address of Control and Status registers, used by
7047+ * release_mem_region().
7048+ */
7049+ resource_size_t phys_addr;
7050+
7051+ /** Length of memory region, used by release_mem_region(). */
7052+ unsigned long base_len;
7053+} dwc_otg_device_t;
7054+
7055+//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg)
7056+
7057+#endif
7058--- /dev/null
7059+++ b/drivers/usb/dwc_otg/dwc_otg_hcd.c
7060@@ -0,0 +1,2870 @@
7061+/* ==========================================================================
7062+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
7063+ * $Revision: 1.1.1.1 $
7064+ * $Date: 2009-04-17 06:15:34 $
7065+ * $Change: 631780 $
7066+ *
7067+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
7068+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
7069+ * otherwise expressly agreed to in writing between Synopsys and you.
7070+ *
7071+ * The Software IS NOT an item of Licensed Software or Licensed Product under
7072+ * any End User Software License Agreement or Agreement for Licensed Product
7073+ * with Synopsys or any supplement thereto. You are permitted to use and
7074+ * redistribute this Software in source and binary forms, with or without
7075+ * modification, provided that redistributions of source code must retain this
7076+ * notice. You may not view, use, disclose, copy or distribute this file or
7077+ * any information contained herein except pursuant to this license grant from
7078+ * Synopsys. If you do not agree with this notice, including the disclaimer
7079+ * below, then you are not authorized to use the Software.
7080+ *
7081+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
7082+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
7083+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
7084+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
7085+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
7086+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
7087+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7088+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
7089+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
7090+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
7091+ * DAMAGE.
7092+ * ========================================================================== */
7093+#ifndef DWC_DEVICE_ONLY
7094+
7095+/**
7096+ * @file
7097+ *
7098+ * This file contains the implementation of the HCD. In Linux, the HCD
7099+ * implements the hc_driver API.
7100+ */
7101+#include <linux/kernel.h>
7102+#include <linux/module.h>
7103+#include <linux/moduleparam.h>
7104+#include <linux/init.h>
7105+
7106+#include <linux/device.h>
7107+
7108+#include <linux/errno.h>
7109+#include <linux/list.h>
7110+#include <linux/interrupt.h>
7111+#include <linux/string.h>
7112+
7113+#include <linux/dma-mapping.h>
7114+
7115+#include "dwc_otg_driver.h"
7116+#include "dwc_otg_hcd.h"
7117+#include "dwc_otg_regs.h"
7118+
7119+#include <asm/irq.h>
7120+#include "dwc_otg_ifx.h" // for Infineon platform specific.
7121+extern atomic_t release_later;
7122+
7123+static u64 dma_mask = DMA_BIT_MASK(32);
7124+
7125+static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
7126+static const struct hc_driver dwc_otg_hc_driver =
7127+{
7128+ .description = dwc_otg_hcd_name,
7129+ .product_desc = "DWC OTG Controller",
7130+ .hcd_priv_size = sizeof(dwc_otg_hcd_t),
7131+ .irq = dwc_otg_hcd_irq,
7132+ .flags = HCD_MEMORY | HCD_USB2,
7133+ //.reset =
7134+ .start = dwc_otg_hcd_start,
7135+ //.suspend =
7136+ //.resume =
7137+ .stop = dwc_otg_hcd_stop,
7138+ .urb_enqueue = dwc_otg_hcd_urb_enqueue,
7139+ .urb_dequeue = dwc_otg_hcd_urb_dequeue,
7140+ .endpoint_disable = dwc_otg_hcd_endpoint_disable,
7141+ .get_frame_number = dwc_otg_hcd_get_frame_number,
7142+ .hub_status_data = dwc_otg_hcd_hub_status_data,
7143+ .hub_control = dwc_otg_hcd_hub_control,
7144+ //.hub_suspend =
7145+ //.hub_resume =
7146+};
7147+
7148+
7149+/**
7150+ * Work queue function for starting the HCD when A-Cable is connected.
7151+ * The dwc_otg_hcd_start() must be called in a process context.
7152+ */
7153+static void hcd_start_func(struct work_struct *work)
7154+{
7155+ struct dwc_otg_hcd *priv =
7156+ container_of(work, struct dwc_otg_hcd, start_work);
7157+ struct usb_hcd *usb_hcd = (struct usb_hcd *)priv->_p;
7158+ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd);
7159+ if (usb_hcd) {
7160+ dwc_otg_hcd_start(usb_hcd);
7161+ }
7162+}
7163+
7164+
7165+/**
7166+ * HCD Callback function for starting the HCD when A-Cable is
7167+ * connected.
7168+ *
7169+ * @param _p void pointer to the <code>struct usb_hcd</code>
7170+ */
7171+static int32_t dwc_otg_hcd_start_cb(void *_p)
7172+{
7173+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
7174+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
7175+ hprt0_data_t hprt0;
7176+ if (core_if->op_state == B_HOST) {
7177+ /*
7178+ * Reset the port. During a HNP mode switch the reset
7179+ * needs to occur within 1ms and have a duration of at
7180+ * least 50ms.
7181+ */
7182+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
7183+ hprt0.b.prtrst = 1;
7184+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
7185+ ((struct usb_hcd *)_p)->self.is_b_host = 1;
7186+ } else {
7187+ ((struct usb_hcd *)_p)->self.is_b_host = 0;
7188+ }
7189+ /* Need to start the HCD in a non-interrupt context. */
7190+ INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
7191+ dwc_otg_hcd->_p = _p;
7192+ schedule_work(&dwc_otg_hcd->start_work);
7193+ return 1;
7194+}
7195+
7196+
7197+/**
7198+ * HCD Callback function for stopping the HCD.
7199+ *
7200+ * @param _p void pointer to the <code>struct usb_hcd</code>
7201+ */
7202+static int32_t dwc_otg_hcd_stop_cb( void *_p )
7203+{
7204+ struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
7205+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
7206+ dwc_otg_hcd_stop( usb_hcd );
7207+ return 1;
7208+}
7209+static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
7210+{
7211+#ifdef DEBUG
7212+ int i;
7213+ int num_channels = _hcd->core_if->core_params->host_channels;
7214+ for (i = 0; i < num_channels; i++) {
7215+ del_timer(&_hcd->core_if->hc_xfer_timer[i]);
7216+ }
7217+#endif /* */
7218+}
7219+
7220+static void del_timers(dwc_otg_hcd_t *_hcd)
7221+{
7222+ del_xfer_timers(_hcd);
7223+ del_timer(&_hcd->conn_timer);
7224+}
7225+
7226+/**
7227+ * Processes all the URBs in a single list of QHs. Completes them with
7228+ * -ETIMEDOUT and frees the QTD.
7229+ */
7230+static void kill_urbs_in_qh_list(dwc_otg_hcd_t * _hcd,
7231+ struct list_head *_qh_list)
7232+{
7233+ struct list_head *qh_item;
7234+ dwc_otg_qh_t *qh;
7235+ struct list_head *qtd_item;
7236+ dwc_otg_qtd_t *qtd;
7237+
7238+ list_for_each(qh_item, _qh_list) {
7239+ qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
7240+ for (qtd_item = qh->qtd_list.next; qtd_item != &qh->qtd_list;
7241+ qtd_item = qh->qtd_list.next) {
7242+ qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
7243+ if (qtd->urb != NULL) {
7244+ dwc_otg_hcd_complete_urb(_hcd, qtd->urb,-ETIMEDOUT);
7245+ }
7246+ dwc_otg_hcd_qtd_remove_and_free(qtd);
7247+ }
7248+ }
7249+}
7250+
7251+/**
7252+ * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
7253+ * and periodic schedules. The QTD associated with each URB is removed from
7254+ * the schedule and freed. This function may be called when a disconnect is
7255+ * detected or when the HCD is being stopped.
7256+ */
7257+static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
7258+{
7259+ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_deferred);
7260+ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
7261+ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
7262+ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
7263+ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
7264+ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
7265+ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
7266+}
7267+
7268+/**
7269+ * HCD Callback function for disconnect of the HCD.
7270+ *
7271+ * @param _p void pointer to the <code>struct usb_hcd</code>
7272+ */
7273+static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
7274+{
7275+ gintsts_data_t intr;
7276+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
7277+
7278+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
7279+
7280+ /*
7281+ * Set status flags for the hub driver.
7282+ */
7283+ dwc_otg_hcd->flags.b.port_connect_status_change = 1;
7284+ dwc_otg_hcd->flags.b.port_connect_status = 0;
7285+
7286+ /*
7287+ * Shutdown any transfers in process by clearing the Tx FIFO Empty
7288+ * interrupt mask and status bits and disabling subsequent host
7289+ * channel interrupts.
7290+ */
7291+ intr.d32 = 0;
7292+ intr.b.nptxfempty = 1;
7293+ intr.b.ptxfempty = 1;
7294+ intr.b.hcintr = 1;
7295+ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
7296+ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
7297+
7298+ del_timers(dwc_otg_hcd);
7299+
7300+ /*
7301+ * Turn off the vbus power only if the core has transitioned to device
7302+ * mode. If still in host mode, need to keep power on to detect a
7303+ * reconnection.
7304+ */
7305+ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
7306+ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
7307+ hprt0_data_t hprt0 = { .d32=0 };
7308+ DWC_PRINT("Disconnect: PortPower off\n");
7309+ hprt0.b.prtpwr = 0;
7310+ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
7311+ }
7312+
7313+ dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
7314+ }
7315+
7316+ /* Respond with an error status to all URBs in the schedule. */
7317+ kill_all_urbs(dwc_otg_hcd);
7318+
7319+ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
7320+ /* Clean up any host channels that were in use. */
7321+ int num_channels;
7322+ int i;
7323+ dwc_hc_t *channel;
7324+ dwc_otg_hc_regs_t *hc_regs;
7325+ hcchar_data_t hcchar;
7326+
7327+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
7328+
7329+ if (!dwc_otg_hcd->core_if->dma_enable) {
7330+ /* Flush out any channel requests in slave mode. */
7331+ for (i = 0; i < num_channels; i++) {
7332+ channel = dwc_otg_hcd->hc_ptr_array[i];
7333+ if (list_empty(&channel->hc_list_entry)) {
7334+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
7335+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
7336+ if (hcchar.b.chen) {
7337+ hcchar.b.chen = 0;
7338+ hcchar.b.chdis = 1;
7339+ hcchar.b.epdir = 0;
7340+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
7341+ }
7342+ }
7343+ }
7344+ }
7345+
7346+ for (i = 0; i < num_channels; i++) {
7347+ channel = dwc_otg_hcd->hc_ptr_array[i];
7348+ if (list_empty(&channel->hc_list_entry)) {
7349+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
7350+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
7351+ if (hcchar.b.chen) {
7352+ /* Halt the channel. */
7353+ hcchar.b.chdis = 1;
7354+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
7355+ }
7356+
7357+ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
7358+ list_add_tail(&channel->hc_list_entry,
7359+ &dwc_otg_hcd->free_hc_list);
7360+ }
7361+ }
7362+ }
7363+
7364+ /* A disconnect will end the session so the B-Device is no
7365+ * longer a B-host. */
7366+ ((struct usb_hcd *)_p)->self.is_b_host = 0;
7367+
7368+ return 1;
7369+}
7370+
7371+/**
7372+ * Connection timeout function. An OTG host is required to display a
7373+ * message if the device does not connect within 10 seconds.
7374+ */
7375+void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
7376+{
7377+ DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
7378+ DWC_PRINT( "Connect Timeout\n");
7379+ DWC_ERROR( "Device Not Connected/Responding\n" );
7380+}
7381+
7382+/**
7383+ * Start the connection timer. An OTG host is required to display a
7384+ * message if the device does not connect within 10 seconds. The
7385+ * timer is deleted if a port connect interrupt occurs before the
7386+ * timer expires.
7387+ */
7388+static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
7389+{
7390+ init_timer( &_hcd->conn_timer );
7391+ _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
7392+ _hcd->conn_timer.data = (unsigned long)0;
7393+ _hcd->conn_timer.expires = jiffies + (HZ*10);
7394+ add_timer( &_hcd->conn_timer );
7395+}
7396+
7397+/**
7398+ * HCD Callback function for disconnect of the HCD.
7399+ *
7400+ * @param _p void pointer to the <code>struct usb_hcd</code>
7401+ */
7402+static int32_t dwc_otg_hcd_session_start_cb( void *_p )
7403+{
7404+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
7405+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
7406+ dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
7407+ return 1;
7408+}
7409+
7410+/**
7411+ * HCD Callback structure for handling mode switching.
7412+ */
7413+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
7414+ .start = dwc_otg_hcd_start_cb,
7415+ .stop = dwc_otg_hcd_stop_cb,
7416+ .disconnect = dwc_otg_hcd_disconnect_cb,
7417+ .session_start = dwc_otg_hcd_session_start_cb,
7418+ .p = 0,
7419+};
7420+
7421+
7422+/**
7423+ * Reset tasklet function
7424+ */
7425+static void reset_tasklet_func (unsigned long data)
7426+{
7427+ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
7428+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
7429+ hprt0_data_t hprt0;
7430+
7431+ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
7432+
7433+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
7434+ hprt0.b.prtrst = 1;
7435+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
7436+ mdelay (60);
7437+
7438+ hprt0.b.prtrst = 0;
7439+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
7440+ dwc_otg_hcd->flags.b.port_reset_change = 1;
7441+
7442+ return;
7443+}
7444+
7445+static struct tasklet_struct reset_tasklet = {
7446+ .next = NULL,
7447+ .state = 0,
7448+ .count = ATOMIC_INIT(0),
7449+ .func = reset_tasklet_func,
7450+ .data = 0,
7451+};
7452+
7453+/**
7454+ * Initializes the HCD. This function allocates memory for and initializes the
7455+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
7456+ * USB bus with the core and calls the hc_driver->start() function. It returns
7457+ * a negative error on failure.
7458+ */
7459+int init_hcd_usecs(dwc_otg_hcd_t *_hcd);
7460+
7461+int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device)
7462+{
7463+ struct usb_hcd *hcd = NULL;
7464+ dwc_otg_hcd_t *dwc_otg_hcd = NULL;
7465+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
7466+
7467+ int num_channels;
7468+ int i;
7469+ dwc_hc_t *channel;
7470+
7471+ int retval = 0;
7472+
7473+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
7474+
7475+ /*
7476+ * Allocate memory for the base HCD plus the DWC OTG HCD.
7477+ * Initialize the base HCD.
7478+ */
7479+ hcd = usb_create_hcd(&dwc_otg_hc_driver, _dev, dev_name(_dev));
7480+ if (hcd == NULL) {
7481+ retval = -ENOMEM;
7482+ goto error1;
7483+ }
7484+ dev_set_drvdata(_dev, dwc_otg_device); /* fscz restore */
7485+ hcd->regs = otg_dev->base;
7486+ hcd->rsrc_start = (int)otg_dev->base;
7487+
7488+ hcd->self.otg_port = 1;
7489+
7490+ /* Initialize the DWC OTG HCD. */
7491+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
7492+ dwc_otg_hcd->core_if = otg_dev->core_if;
7493+ otg_dev->hcd = dwc_otg_hcd;
7494+
7495+ /* Register the HCD CIL Callbacks */
7496+ dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
7497+ &hcd_cil_callbacks, hcd);
7498+
7499+ /* Initialize the non-periodic schedule. */
7500+ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
7501+ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
7502+ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_deferred);
7503+
7504+ /* Initialize the periodic schedule. */
7505+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
7506+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
7507+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
7508+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
7509+
7510+ /*
7511+ * Create a host channel descriptor for each host channel implemented
7512+ * in the controller. Initialize the channel descriptor array.
7513+ */
7514+ INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
7515+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
7516+ for (i = 0; i < num_channels; i++) {
7517+ channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
7518+ if (channel == NULL) {
7519+ retval = -ENOMEM;
7520+ DWC_ERROR("%s: host channel allocation failed\n", __func__);
7521+ goto error2;
7522+ }
7523+ memset(channel, 0, sizeof(dwc_hc_t));
7524+ channel->hc_num = i;
7525+ dwc_otg_hcd->hc_ptr_array[i] = channel;
7526+#ifdef DEBUG
7527+ init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
7528+#endif
7529+
7530+ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
7531+ }
7532+
7533+ /* Initialize the Connection timeout timer. */
7534+ init_timer( &dwc_otg_hcd->conn_timer );
7535+
7536+ /* Initialize reset tasklet. */
7537+ reset_tasklet.data = (unsigned long) dwc_otg_hcd;
7538+ dwc_otg_hcd->reset_tasklet = &reset_tasklet;
7539+
7540+ /* Set device flags indicating whether the HCD supports DMA. */
7541+ if (otg_dev->core_if->dma_enable) {
7542+ DWC_PRINT("Using DMA mode\n");
7543+ //_dev->dma_mask = (void *)~0;
7544+ //_dev->coherent_dma_mask = ~0;
7545+ _dev->dma_mask = &dma_mask;
7546+ _dev->coherent_dma_mask = DMA_BIT_MASK(32);
7547+ } else {
7548+ DWC_PRINT("Using Slave mode\n");
7549+ _dev->dma_mask = (void *)0;
7550+ _dev->coherent_dma_mask = 0;
7551+ }
7552+
7553+ init_hcd_usecs(dwc_otg_hcd);
7554+ /*
7555+ * Finish generic HCD initialization and start the HCD. This function
7556+ * allocates the DMA buffer pool, registers the USB bus, requests the
7557+ * IRQ line, and calls dwc_otg_hcd_start method.
7558+ */
7559+ retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED);
7560+ if (retval < 0) {
7561+ goto error2;
7562+ }
7563+
7564+ /*
7565+ * Allocate space for storing data on status transactions. Normally no
7566+ * data is sent, but this space acts as a bit bucket. This must be
7567+ * done after usb_add_hcd since that function allocates the DMA buffer
7568+ * pool.
7569+ */
7570+ if (otg_dev->core_if->dma_enable) {
7571+ dwc_otg_hcd->status_buf =
7572+ dma_alloc_coherent(_dev,
7573+ DWC_OTG_HCD_STATUS_BUF_SIZE,
7574+ &dwc_otg_hcd->status_buf_dma,
7575+ GFP_KERNEL | GFP_DMA);
7576+ } else {
7577+ dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
7578+ GFP_KERNEL);
7579+ }
7580+ if (dwc_otg_hcd->status_buf == NULL) {
7581+ retval = -ENOMEM;
7582+ DWC_ERROR("%s: status_buf allocation failed\n", __func__);
7583+ goto error3;
7584+ }
7585+
7586+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
7587+ dev_name(_dev), hcd->self.busnum);
7588+
7589+ return 0;
7590+
7591+ /* Error conditions */
7592+error3:
7593+ usb_remove_hcd(hcd);
7594+error2:
7595+ dwc_otg_hcd_free(hcd);
7596+ usb_put_hcd(hcd);
7597+error1:
7598+ return retval;
7599+}
7600+
7601+/**
7602+ * Removes the HCD.
7603+ * Frees memory and resources associated with the HCD and deregisters the bus.
7604+ */
7605+void dwc_otg_hcd_remove(struct device *_dev)
7606+{
7607+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
7608+ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
7609+ struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
7610+
7611+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
7612+
7613+ /* Turn off all interrupts */
7614+ dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
7615+ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
7616+
7617+ usb_remove_hcd(hcd);
7618+
7619+ dwc_otg_hcd_free(hcd);
7620+
7621+ usb_put_hcd(hcd);
7622+
7623+ return;
7624+}
7625+
7626+
7627+/* =========================================================================
7628+ * Linux HC Driver Functions
7629+ * ========================================================================= */
7630+
7631+/**
7632+ * Initializes dynamic portions of the DWC_otg HCD state.
7633+ */
7634+static void hcd_reinit(dwc_otg_hcd_t *_hcd)
7635+{
7636+ struct list_head *item;
7637+ int num_channels;
7638+ int i;
7639+ dwc_hc_t *channel;
7640+
7641+ _hcd->flags.d32 = 0;
7642+
7643+ _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
7644+ _hcd->available_host_channels = _hcd->core_if->core_params->host_channels;
7645+
7646+ /*
7647+ * Put all channels in the free channel list and clean up channel
7648+ * states.
7649+ */
7650+ item = _hcd->free_hc_list.next;
7651+ while (item != &_hcd->free_hc_list) {
7652+ list_del(item);
7653+ item = _hcd->free_hc_list.next;
7654+ }
7655+ num_channels = _hcd->core_if->core_params->host_channels;
7656+ for (i = 0; i < num_channels; i++) {
7657+ channel = _hcd->hc_ptr_array[i];
7658+ list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
7659+ dwc_otg_hc_cleanup(_hcd->core_if, channel);
7660+ }
7661+
7662+ /* Initialize the DWC core for host mode operation. */
7663+ dwc_otg_core_host_init(_hcd->core_if);
7664+}
7665+
7666+/** Initializes the DWC_otg controller and its root hub and prepares it for host
7667+ * mode operation. Activates the root port. Returns 0 on success and a negative
7668+ * error code on failure. */
7669+int dwc_otg_hcd_start(struct usb_hcd *_hcd)
7670+{
7671+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
7672+ dwc_otg_core_if_t * core_if = dwc_otg_hcd->core_if;
7673+ struct usb_bus *bus;
7674+
7675+ // int retval;
7676+
7677+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
7678+
7679+ bus = hcd_to_bus(_hcd);
7680+
7681+ /* Initialize the bus state. If the core is in Device Mode
7682+ * HALT the USB bus and return. */
7683+ if (dwc_otg_is_device_mode (core_if)) {
7684+ _hcd->state = HC_STATE_HALT;
7685+ return 0;
7686+ }
7687+ _hcd->state = HC_STATE_RUNNING;
7688+
7689+ /* Initialize and connect root hub if one is not already attached */
7690+ if (bus->root_hub) {
7691+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
7692+ /* Inform the HUB driver to resume. */
7693+ usb_hcd_resume_root_hub(_hcd);
7694+ }
7695+ else {
7696+#if 0
7697+ struct usb_device *udev;
7698+ udev = usb_alloc_dev(NULL, bus, 0);
7699+ if (!udev) {
7700+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
7701+ return -ENODEV;
7702+ }
7703+ udev->speed = USB_SPEED_HIGH;
7704+ /* Not needed - VJ
7705+ if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
7706+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
7707+ return -ENODEV;
7708+ }
7709+ */
7710+#else
7711+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
7712+#endif
7713+ }
7714+
7715+ hcd_reinit(dwc_otg_hcd);
7716+
7717+ return 0;
7718+}
7719+
7720+static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
7721+{
7722+ struct list_head *item;
7723+ dwc_otg_qh_t *qh;
7724+
7725+ if (_qh_list->next == NULL) {
7726+ /* The list hasn't been initialized yet. */
7727+ return;
7728+ }
7729+
7730+ /* Ensure there are no QTDs or URBs left. */
7731+ kill_urbs_in_qh_list(_hcd, _qh_list);
7732+
7733+ for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
7734+ qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
7735+ dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
7736+ }
7737+}
7738+
7739+/**
7740+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
7741+ * stopped.
7742+ */
7743+void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
7744+{
7745+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
7746+ hprt0_data_t hprt0 = { .d32=0 };
7747+
7748+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
7749+
7750+ /* Turn off all host-specific interrupts. */
7751+ dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
7752+
7753+ /*
7754+ * The root hub should be disconnected before this function is called.
7755+ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
7756+ * and the QH lists (via ..._hcd_endpoint_disable).
7757+ */
7758+
7759+ /* Turn off the vbus power */
7760+ DWC_PRINT("PortPower off\n");
7761+ hprt0.b.prtpwr = 0;
7762+ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
7763+
7764+ return;
7765+}
7766+
7767+
7768+/** Returns the current frame number. */
7769+int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
7770+{
7771+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
7772+ hfnum_data_t hfnum;
7773+
7774+ hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
7775+ host_if->host_global_regs->hfnum);
7776+
7777+#ifdef DEBUG_SOF
7778+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
7779+#endif
7780+ return hfnum.b.frnum;
7781+}
7782+
7783+/**
7784+ * Frees secondary storage associated with the dwc_otg_hcd structure contained
7785+ * in the struct usb_hcd field.
7786+ */
7787+void dwc_otg_hcd_free(struct usb_hcd *_hcd)
7788+{
7789+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
7790+ int i;
7791+
7792+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
7793+
7794+ del_timers(dwc_otg_hcd);
7795+
7796+ /* Free memory for QH/QTD lists */
7797+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
7798+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_deferred);
7799+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
7800+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
7801+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
7802+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
7803+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
7804+
7805+ /* Free memory for the host channels. */
7806+ for (i = 0; i < MAX_EPS_CHANNELS; i++) {
7807+ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
7808+ if (hc != NULL) {
7809+ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
7810+ kfree(hc);
7811+ }
7812+ }
7813+
7814+ if (dwc_otg_hcd->core_if->dma_enable) {
7815+ if (dwc_otg_hcd->status_buf_dma) {
7816+ dma_free_coherent(_hcd->self.controller,
7817+ DWC_OTG_HCD_STATUS_BUF_SIZE,
7818+ dwc_otg_hcd->status_buf,
7819+ dwc_otg_hcd->status_buf_dma);
7820+ }
7821+ } else if (dwc_otg_hcd->status_buf != NULL) {
7822+ kfree(dwc_otg_hcd->status_buf);
7823+ }
7824+
7825+ return;
7826+}
7827+
7828+
7829+#ifdef DEBUG
7830+static void dump_urb_info(struct urb *_urb, char* _fn_name)
7831+{
7832+ DWC_PRINT("%s, urb %p\n", _fn_name, _urb);
7833+ DWC_PRINT(" Device address: %d\n", usb_pipedevice(_urb->pipe));
7834+ DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
7835+ (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
7836+ DWC_PRINT(" Endpoint type: %s\n",
7837+ ({char *pipetype;
7838+ switch (usb_pipetype(_urb->pipe)) {
7839+ case PIPE_CONTROL: pipetype = "CONTROL"; break;
7840+ case PIPE_BULK: pipetype = "BULK"; break;
7841+ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
7842+ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
7843+ default: pipetype = "UNKNOWN"; break;
7844+ }; pipetype;}));
7845+ DWC_PRINT(" Speed: %s\n",
7846+ ({char *speed;
7847+ switch (_urb->dev->speed) {
7848+ case USB_SPEED_HIGH: speed = "HIGH"; break;
7849+ case USB_SPEED_FULL: speed = "FULL"; break;
7850+ case USB_SPEED_LOW: speed = "LOW"; break;
7851+ default: speed = "UNKNOWN"; break;
7852+ }; speed;}));
7853+ DWC_PRINT(" Max packet size: %d\n",
7854+ usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
7855+ DWC_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length);
7856+ DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n",
7857+ _urb->transfer_buffer, (void *)_urb->transfer_dma);
7858+ DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n",
7859+ _urb->setup_packet, (void *)_urb->setup_dma);
7860+ DWC_PRINT(" Interval: %d\n", _urb->interval);
7861+ if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
7862+ int i;
7863+ for (i = 0; i < _urb->number_of_packets; i++) {
7864+ DWC_PRINT(" ISO Desc %d:\n", i);
7865+ DWC_PRINT(" offset: %d, length %d\n",
7866+ _urb->iso_frame_desc[i].offset,
7867+ _urb->iso_frame_desc[i].length);
7868+ }
7869+ }
7870+}
7871+
7872+static void dump_channel_info(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *qh)
7873+{
7874+ if (qh->channel != NULL) {
7875+ dwc_hc_t *hc = qh->channel;
7876+ struct list_head *item;
7877+ dwc_otg_qh_t *qh_item;
7878+ int num_channels = _hcd->core_if->core_params->host_channels;
7879+ int i;
7880+
7881+ dwc_otg_hc_regs_t *hc_regs;
7882+ hcchar_data_t hcchar;
7883+ hcsplt_data_t hcsplt;
7884+ hctsiz_data_t hctsiz;
7885+ uint32_t hcdma;
7886+
7887+ hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
7888+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
7889+ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
7890+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
7891+ hcdma = dwc_read_reg32(&hc_regs->hcdma);
7892+
7893+ DWC_PRINT(" Assigned to channel %p:\n", hc);
7894+ DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
7895+ DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
7896+ DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
7897+ hc->dev_addr, hc->ep_num, hc->ep_is_in);
7898+ DWC_PRINT(" ep_type: %d\n", hc->ep_type);
7899+ DWC_PRINT(" max_packet: %d\n", hc->max_packet);
7900+ DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
7901+ DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
7902+ DWC_PRINT(" halt_status: %d\n", hc->halt_status);
7903+ DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
7904+ DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
7905+ DWC_PRINT(" qh: %p\n", hc->qh);
7906+ DWC_PRINT(" NP inactive sched:\n");
7907+ list_for_each(item, &_hcd->non_periodic_sched_inactive) {
7908+ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
7909+ DWC_PRINT(" %p\n", qh_item);
7910+ } DWC_PRINT(" NP active sched:\n");
7911+ list_for_each(item, &_hcd->non_periodic_sched_deferred) {
7912+ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
7913+ DWC_PRINT(" %p\n", qh_item);
7914+ } DWC_PRINT(" NP deferred sched:\n");
7915+ list_for_each(item, &_hcd->non_periodic_sched_active) {
7916+ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
7917+ DWC_PRINT(" %p\n", qh_item);
7918+ } DWC_PRINT(" Channels: \n");
7919+ for (i = 0; i < num_channels; i++) {
7920+ dwc_hc_t *hc = _hcd->hc_ptr_array[i];
7921+ DWC_PRINT(" %2d: %p\n", i, hc);
7922+ }
7923+ }
7924+}
7925+#endif // DEBUG
7926+
7927+/** Starts processing a USB transfer request specified by a USB Request Block
7928+ * (URB). mem_flags indicates the type of memory allocation to use while
7929+ * processing this URB. */
7930+int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
7931+ struct urb *_urb,
7932+ gfp_t _mem_flags)
7933+{
7934+ unsigned long flags;
7935+ int retval;
7936+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
7937+ dwc_otg_qtd_t *qtd;
7938+
7939+ local_irq_save(flags);
7940+ retval = usb_hcd_link_urb_to_ep(_hcd, _urb);
7941+ if (retval) {
7942+ local_irq_restore(flags);
7943+ return retval;
7944+ }
7945+#ifdef DEBUG
7946+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
7947+ dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
7948+ }
7949+#endif // DEBUG
7950+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
7951+ /* No longer connected. */
7952+ local_irq_restore(flags);
7953+ return -ENODEV;
7954+ }
7955+
7956+ qtd = dwc_otg_hcd_qtd_create (_urb);
7957+ if (qtd == NULL) {
7958+ local_irq_restore(flags);
7959+ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
7960+ return -ENOMEM;
7961+ }
7962+
7963+ retval = dwc_otg_hcd_qtd_add (qtd, dwc_otg_hcd);
7964+ if (retval < 0) {
7965+ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
7966+ "Error status %d\n", retval);
7967+ dwc_otg_hcd_qtd_free(qtd);
7968+ }
7969+
7970+ local_irq_restore (flags);
7971+ return retval;
7972+}
7973+
7974+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
7975+ * success. */
7976+int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
7977+{
7978+ unsigned long flags;
7979+ dwc_otg_hcd_t *dwc_otg_hcd;
7980+ dwc_otg_qtd_t *urb_qtd;
7981+ dwc_otg_qh_t *qh;
7982+ int retval;
7983+ //struct usb_host_endpoint *_ep = NULL;
7984+
7985+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
7986+
7987+ local_irq_save(flags);
7988+
7989+ retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status);
7990+ if (retval) {
7991+ local_irq_restore(flags);
7992+ return retval;
7993+ }
7994+
7995+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
7996+ urb_qtd = (dwc_otg_qtd_t *)_urb->hcpriv;
7997+ if (urb_qtd == NULL) {
7998+ printk("urb_qtd is NULL for _urb %08x\n",(unsigned)_urb);
7999+ goto done;
8000+ }
8001+ qh = (dwc_otg_qh_t *) urb_qtd->qtd_qh_ptr;
8002+ if (qh == NULL) {
8003+ goto done;
8004+ }
8005+
8006+#ifdef DEBUG
8007+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8008+ dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
8009+ if (urb_qtd == qh->qtd_in_process) {
8010+ dump_channel_info(dwc_otg_hcd, qh);
8011+ }
8012+ }
8013+#endif // DEBUG
8014+
8015+ if (urb_qtd == qh->qtd_in_process) {
8016+ /* The QTD is in process (it has been assigned to a channel). */
8017+
8018+ if (dwc_otg_hcd->flags.b.port_connect_status) {
8019+ /*
8020+ * If still connected (i.e. in host mode), halt the
8021+ * channel so it can be used for other transfers. If
8022+ * no longer connected, the host registers can't be
8023+ * written to halt the channel since the core is in
8024+ * device mode.
8025+ */
8026+ dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
8027+ DWC_OTG_HC_XFER_URB_DEQUEUE);
8028+ }
8029+ }
8030+
8031+ /*
8032+ * Free the QTD and clean up the associated QH. Leave the QH in the
8033+ * schedule if it has any remaining QTDs.
8034+ */
8035+ dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
8036+ if (urb_qtd == qh->qtd_in_process) {
8037+ dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
8038+ qh->channel = NULL;
8039+ qh->qtd_in_process = NULL;
8040+ } else if (list_empty(&qh->qtd_list)) {
8041+ dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
8042+ }
8043+
8044+done:
8045+ local_irq_restore(flags);
8046+ _urb->hcpriv = NULL;
8047+
8048+ /* Higher layer software sets URB status. */
8049+ usb_hcd_unlink_urb_from_ep(_hcd, _urb);
8050+ usb_hcd_giveback_urb(_hcd, _urb, _status);
8051+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
8052+ DWC_PRINT("Called usb_hcd_giveback_urb()\n");
8053+ DWC_PRINT(" urb->status = %d\n", _urb->status);
8054+ }
8055+
8056+ return 0;
8057+}
8058+
8059+
8060+/** Frees resources in the DWC_otg controller related to a given endpoint. Also
8061+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint
8062+ * must already be dequeued. */
8063+void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
8064+ struct usb_host_endpoint *_ep)
8065+
8066+{
8067+ dwc_otg_qh_t *qh;
8068+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
8069+
8070+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
8071+ "endpoint=%d\n", _ep->desc.bEndpointAddress,
8072+ dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
8073+
8074+ qh = (dwc_otg_qh_t *)(_ep->hcpriv);
8075+ if (qh != NULL) {
8076+#ifdef DEBUG
8077+ /** Check that the QTD list is really empty */
8078+ if (!list_empty(&qh->qtd_list)) {
8079+ DWC_WARN("DWC OTG HCD EP DISABLE:"
8080+ " QTD List for this endpoint is not empty\n");
8081+ }
8082+#endif // DEBUG
8083+
8084+ dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
8085+ _ep->hcpriv = NULL;
8086+ }
8087+
8088+ return;
8089+}
8090+extern int dwc_irq;
8091+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
8092+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
8093+ * interrupt.
8094+ *
8095+ * This function is called by the USB core when an interrupt occurs */
8096+irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
8097+{
8098+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
8099+
8100+ mask_and_ack_ifx_irq (dwc_irq);
8101+ return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
8102+}
8103+
8104+/** Creates Status Change bitmap for the root hub and root port. The bitmap is
8105+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
8106+ * is the status change indicator for the single root port. Returns 1 if either
8107+ * change indicator is 1, otherwise returns 0. */
8108+int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd, char *_buf)
8109+{
8110+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
8111+
8112+ _buf[0] = 0;
8113+ _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
8114+ dwc_otg_hcd->flags.b.port_reset_change ||
8115+ dwc_otg_hcd->flags.b.port_enable_change ||
8116+ dwc_otg_hcd->flags.b.port_suspend_change ||
8117+ dwc_otg_hcd->flags.b.port_over_current_change) << 1;
8118+
8119+#ifdef DEBUG
8120+ if (_buf[0]) {
8121+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
8122+ " Root port status changed\n");
8123+ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
8124+ dwc_otg_hcd->flags.b.port_connect_status_change);
8125+ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
8126+ dwc_otg_hcd->flags.b.port_reset_change);
8127+ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
8128+ dwc_otg_hcd->flags.b.port_enable_change);
8129+ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
8130+ dwc_otg_hcd->flags.b.port_suspend_change);
8131+ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
8132+ dwc_otg_hcd->flags.b.port_over_current_change);
8133+ }
8134+#endif // DEBUG
8135+ return (_buf[0] != 0);
8136+}
8137+
8138+#ifdef DWC_HS_ELECT_TST
8139+/*
8140+ * Quick and dirty hack to implement the HS Electrical Test
8141+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
8142+ *
8143+ * This code was copied from our userspace app "hset". It sends a
8144+ * Get Device Descriptor control sequence in two parts, first the
8145+ * Setup packet by itself, followed some time later by the In and
8146+ * Ack packets. Rather than trying to figure out how to add this
8147+ * functionality to the normal driver code, we just hijack the
8148+ * hardware, using these two function to drive the hardware
8149+ * directly.
8150+ */
8151+
8152+dwc_otg_core_global_regs_t *global_regs;
8153+dwc_otg_host_global_regs_t *hc_global_regs;
8154+dwc_otg_hc_regs_t *hc_regs;
8155+uint32_t *data_fifo;
8156+
8157+static void do_setup(void)
8158+{
8159+ gintsts_data_t gintsts;
8160+ hctsiz_data_t hctsiz;
8161+ hcchar_data_t hcchar;
8162+ haint_data_t haint;
8163+ hcint_data_t hcint;
8164+
8165+ /* Enable HAINTs */
8166+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
8167+
8168+ /* Enable HCINTs */
8169+ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
8170+
8171+ /* Read GINTSTS */
8172+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8173+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8174+
8175+ /* Read HAINT */
8176+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8177+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8178+
8179+ /* Read HCINT */
8180+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8181+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8182+
8183+ /* Read HCCHAR */
8184+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8185+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8186+
8187+ /* Clear HCINT */
8188+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8189+
8190+ /* Clear HAINT */
8191+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8192+
8193+ /* Clear GINTSTS */
8194+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8195+
8196+ /* Read GINTSTS */
8197+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8198+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8199+
8200+ /*
8201+ * Send Setup packet (Get Device Descriptor)
8202+ */
8203+
8204+ /* Make sure channel is disabled */
8205+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8206+ if (hcchar.b.chen) {
8207+ //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
8208+ hcchar.b.chdis = 1;
8209+ // hcchar.b.chen = 1;
8210+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8211+ //sleep(1);
8212+ MDELAY(1000);
8213+
8214+ /* Read GINTSTS */
8215+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8216+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8217+
8218+ /* Read HAINT */
8219+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8220+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8221+
8222+ /* Read HCINT */
8223+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8224+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8225+
8226+ /* Read HCCHAR */
8227+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8228+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8229+
8230+ /* Clear HCINT */
8231+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8232+
8233+ /* Clear HAINT */
8234+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8235+
8236+ /* Clear GINTSTS */
8237+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8238+
8239+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8240+ //if (hcchar.b.chen) {
8241+ // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
8242+ //}
8243+ }
8244+
8245+ /* Set HCTSIZ */
8246+ hctsiz.d32 = 0;
8247+ hctsiz.b.xfersize = 8;
8248+ hctsiz.b.pktcnt = 1;
8249+ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
8250+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
8251+
8252+ /* Set HCCHAR */
8253+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8254+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
8255+ hcchar.b.epdir = 0;
8256+ hcchar.b.epnum = 0;
8257+ hcchar.b.mps = 8;
8258+ hcchar.b.chen = 1;
8259+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8260+
8261+ /* Fill FIFO with Setup data for Get Device Descriptor */
8262+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
8263+ dwc_write_reg32(data_fifo++, 0x01000680);
8264+ dwc_write_reg32(data_fifo++, 0x00080000);
8265+
8266+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8267+ //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
8268+
8269+ /* Wait for host channel interrupt */
8270+ do {
8271+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8272+ } while (gintsts.b.hcintr == 0);
8273+
8274+ //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
8275+
8276+ /* Disable HCINTs */
8277+ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
8278+
8279+ /* Disable HAINTs */
8280+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
8281+
8282+ /* Read HAINT */
8283+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8284+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8285+
8286+ /* Read HCINT */
8287+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8288+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8289+
8290+ /* Read HCCHAR */
8291+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8292+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8293+
8294+ /* Clear HCINT */
8295+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8296+
8297+ /* Clear HAINT */
8298+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8299+
8300+ /* Clear GINTSTS */
8301+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8302+
8303+ /* Read GINTSTS */
8304+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8305+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8306+}
8307+
8308+static void do_in_ack(void)
8309+{
8310+ gintsts_data_t gintsts;
8311+ hctsiz_data_t hctsiz;
8312+ hcchar_data_t hcchar;
8313+ haint_data_t haint;
8314+ hcint_data_t hcint;
8315+ host_grxsts_data_t grxsts;
8316+
8317+ /* Enable HAINTs */
8318+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
8319+
8320+ /* Enable HCINTs */
8321+ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
8322+
8323+ /* Read GINTSTS */
8324+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8325+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8326+
8327+ /* Read HAINT */
8328+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8329+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8330+
8331+ /* Read HCINT */
8332+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8333+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8334+
8335+ /* Read HCCHAR */
8336+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8337+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8338+
8339+ /* Clear HCINT */
8340+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8341+
8342+ /* Clear HAINT */
8343+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8344+
8345+ /* Clear GINTSTS */
8346+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8347+
8348+ /* Read GINTSTS */
8349+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8350+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8351+
8352+ /*
8353+ * Receive Control In packet
8354+ */
8355+
8356+ /* Make sure channel is disabled */
8357+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8358+ if (hcchar.b.chen) {
8359+ //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
8360+ hcchar.b.chdis = 1;
8361+ hcchar.b.chen = 1;
8362+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8363+ //sleep(1);
8364+ MDELAY(1000);
8365+
8366+ /* Read GINTSTS */
8367+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8368+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8369+
8370+ /* Read HAINT */
8371+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8372+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8373+
8374+ /* Read HCINT */
8375+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8376+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8377+
8378+ /* Read HCCHAR */
8379+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8380+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8381+
8382+ /* Clear HCINT */
8383+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8384+
8385+ /* Clear HAINT */
8386+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8387+
8388+ /* Clear GINTSTS */
8389+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8390+
8391+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8392+ //if (hcchar.b.chen) {
8393+ // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
8394+ //}
8395+ }
8396+
8397+ /* Set HCTSIZ */
8398+ hctsiz.d32 = 0;
8399+ hctsiz.b.xfersize = 8;
8400+ hctsiz.b.pktcnt = 1;
8401+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
8402+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
8403+
8404+ /* Set HCCHAR */
8405+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8406+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
8407+ hcchar.b.epdir = 1;
8408+ hcchar.b.epnum = 0;
8409+ hcchar.b.mps = 8;
8410+ hcchar.b.chen = 1;
8411+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8412+
8413+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8414+ //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
8415+
8416+ /* Wait for receive status queue interrupt */
8417+ do {
8418+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8419+ } while (gintsts.b.rxstsqlvl == 0);
8420+
8421+ //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
8422+
8423+ /* Read RXSTS */
8424+ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
8425+ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
8426+
8427+ /* Clear RXSTSQLVL in GINTSTS */
8428+ gintsts.d32 = 0;
8429+ gintsts.b.rxstsqlvl = 1;
8430+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8431+
8432+ switch (grxsts.b.pktsts) {
8433+ case DWC_GRXSTS_PKTSTS_IN:
8434+ /* Read the data into the host buffer */
8435+ if (grxsts.b.bcnt > 0) {
8436+ int i;
8437+ int word_count = (grxsts.b.bcnt + 3) / 4;
8438+
8439+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
8440+
8441+ for (i = 0; i < word_count; i++) {
8442+ (void)dwc_read_reg32(data_fifo++);
8443+ }
8444+ }
8445+
8446+ //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
8447+ break;
8448+
8449+ default:
8450+ //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
8451+ break;
8452+ }
8453+
8454+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8455+ //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
8456+
8457+ /* Wait for receive status queue interrupt */
8458+ do {
8459+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8460+ } while (gintsts.b.rxstsqlvl == 0);
8461+
8462+ //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
8463+
8464+ /* Read RXSTS */
8465+ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
8466+ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
8467+
8468+ /* Clear RXSTSQLVL in GINTSTS */
8469+ gintsts.d32 = 0;
8470+ gintsts.b.rxstsqlvl = 1;
8471+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8472+
8473+ switch (grxsts.b.pktsts) {
8474+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
8475+ break;
8476+
8477+ default:
8478+ //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
8479+ break;
8480+ }
8481+
8482+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8483+ //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
8484+
8485+ /* Wait for host channel interrupt */
8486+ do {
8487+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8488+ } while (gintsts.b.hcintr == 0);
8489+
8490+ //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
8491+
8492+ /* Read HAINT */
8493+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8494+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8495+
8496+ /* Read HCINT */
8497+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8498+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8499+
8500+ /* Read HCCHAR */
8501+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8502+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8503+
8504+ /* Clear HCINT */
8505+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8506+
8507+ /* Clear HAINT */
8508+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8509+
8510+ /* Clear GINTSTS */
8511+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8512+
8513+ /* Read GINTSTS */
8514+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8515+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8516+
8517+ // usleep(100000);
8518+ // mdelay(100);
8519+ MDELAY(1);
8520+
8521+ /*
8522+ * Send handshake packet
8523+ */
8524+
8525+ /* Read HAINT */
8526+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8527+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8528+
8529+ /* Read HCINT */
8530+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8531+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8532+
8533+ /* Read HCCHAR */
8534+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8535+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8536+
8537+ /* Clear HCINT */
8538+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8539+
8540+ /* Clear HAINT */
8541+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8542+
8543+ /* Clear GINTSTS */
8544+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8545+
8546+ /* Read GINTSTS */
8547+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8548+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8549+
8550+ /* Make sure channel is disabled */
8551+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8552+ if (hcchar.b.chen) {
8553+ //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
8554+ hcchar.b.chdis = 1;
8555+ hcchar.b.chen = 1;
8556+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8557+ //sleep(1);
8558+ MDELAY(1000);
8559+
8560+ /* Read GINTSTS */
8561+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8562+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8563+
8564+ /* Read HAINT */
8565+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8566+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8567+
8568+ /* Read HCINT */
8569+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8570+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8571+
8572+ /* Read HCCHAR */
8573+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8574+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8575+
8576+ /* Clear HCINT */
8577+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8578+
8579+ /* Clear HAINT */
8580+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8581+
8582+ /* Clear GINTSTS */
8583+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8584+
8585+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8586+ //if (hcchar.b.chen) {
8587+ // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
8588+ //}
8589+ }
8590+
8591+ /* Set HCTSIZ */
8592+ hctsiz.d32 = 0;
8593+ hctsiz.b.xfersize = 0;
8594+ hctsiz.b.pktcnt = 1;
8595+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
8596+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
8597+
8598+ /* Set HCCHAR */
8599+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8600+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
8601+ hcchar.b.epdir = 0;
8602+ hcchar.b.epnum = 0;
8603+ hcchar.b.mps = 8;
8604+ hcchar.b.chen = 1;
8605+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
8606+
8607+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8608+ //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
8609+
8610+ /* Wait for host channel interrupt */
8611+ do {
8612+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8613+ } while (gintsts.b.hcintr == 0);
8614+
8615+ //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
8616+
8617+ /* Disable HCINTs */
8618+ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
8619+
8620+ /* Disable HAINTs */
8621+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
8622+
8623+ /* Read HAINT */
8624+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
8625+ //fprintf(stderr, "HAINT: %08x\n", haint.d32);
8626+
8627+ /* Read HCINT */
8628+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
8629+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
8630+
8631+ /* Read HCCHAR */
8632+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
8633+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
8634+
8635+ /* Clear HCINT */
8636+ dwc_write_reg32(&hc_regs->hcint, hcint.d32);
8637+
8638+ /* Clear HAINT */
8639+ dwc_write_reg32(&hc_global_regs->haint, haint.d32);
8640+
8641+ /* Clear GINTSTS */
8642+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
8643+
8644+ /* Read GINTSTS */
8645+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
8646+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
8647+}
8648+#endif /* DWC_HS_ELECT_TST */
8649+
8650+/** Handles hub class-specific requests.*/
8651+int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
8652+ u16 _typeReq,
8653+ u16 _wValue,
8654+ u16 _wIndex,
8655+ char *_buf,
8656+ u16 _wLength)
8657+{
8658+ int retval = 0;
8659+
8660+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
8661+ dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
8662+ struct usb_hub_descriptor *desc;
8663+ hprt0_data_t hprt0 = {.d32 = 0};
8664+
8665+ uint32_t port_status;
8666+
8667+ switch (_typeReq) {
8668+ case ClearHubFeature:
8669+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8670+ "ClearHubFeature 0x%x\n", _wValue);
8671+ switch (_wValue) {
8672+ case C_HUB_LOCAL_POWER:
8673+ case C_HUB_OVER_CURRENT:
8674+ /* Nothing required here */
8675+ break;
8676+ default:
8677+ retval = -EINVAL;
8678+ DWC_ERROR ("DWC OTG HCD - "
8679+ "ClearHubFeature request %xh unknown\n", _wValue);
8680+ }
8681+ break;
8682+ case ClearPortFeature:
8683+ if (!_wIndex || _wIndex > 1)
8684+ goto error;
8685+
8686+ switch (_wValue) {
8687+ case USB_PORT_FEAT_ENABLE:
8688+ DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
8689+ "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
8690+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8691+ hprt0.b.prtena = 1;
8692+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8693+ break;
8694+ case USB_PORT_FEAT_SUSPEND:
8695+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8696+ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
8697+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8698+ hprt0.b.prtres = 1;
8699+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8700+ /* Clear Resume bit */
8701+ mdelay (100);
8702+ hprt0.b.prtres = 0;
8703+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8704+ break;
8705+ case USB_PORT_FEAT_POWER:
8706+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8707+ "ClearPortFeature USB_PORT_FEAT_POWER\n");
8708+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8709+ hprt0.b.prtpwr = 0;
8710+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8711+ break;
8712+ case USB_PORT_FEAT_INDICATOR:
8713+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8714+ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
8715+ /* Port inidicator not supported */
8716+ break;
8717+ case USB_PORT_FEAT_C_CONNECTION:
8718+ /* Clears drivers internal connect status change
8719+ * flag */
8720+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8721+ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
8722+ dwc_otg_hcd->flags.b.port_connect_status_change = 0;
8723+ break;
8724+ case USB_PORT_FEAT_C_RESET:
8725+ /* Clears the driver's internal Port Reset Change
8726+ * flag */
8727+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8728+ "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
8729+ dwc_otg_hcd->flags.b.port_reset_change = 0;
8730+ break;
8731+ case USB_PORT_FEAT_C_ENABLE:
8732+ /* Clears the driver's internal Port
8733+ * Enable/Disable Change flag */
8734+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8735+ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
8736+ dwc_otg_hcd->flags.b.port_enable_change = 0;
8737+ break;
8738+ case USB_PORT_FEAT_C_SUSPEND:
8739+ /* Clears the driver's internal Port Suspend
8740+ * Change flag, which is set when resume signaling on
8741+ * the host port is complete */
8742+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8743+ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
8744+ dwc_otg_hcd->flags.b.port_suspend_change = 0;
8745+ break;
8746+ case USB_PORT_FEAT_C_OVER_CURRENT:
8747+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8748+ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
8749+ dwc_otg_hcd->flags.b.port_over_current_change = 0;
8750+ break;
8751+ default:
8752+ retval = -EINVAL;
8753+ DWC_ERROR ("DWC OTG HCD - "
8754+ "ClearPortFeature request %xh "
8755+ "unknown or unsupported\n", _wValue);
8756+ }
8757+ break;
8758+ case GetHubDescriptor:
8759+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8760+ "GetHubDescriptor\n");
8761+ desc = (struct usb_hub_descriptor *)_buf;
8762+ desc->bDescLength = 9;
8763+ desc->bDescriptorType = 0x29;
8764+ desc->bNbrPorts = 1;
8765+ desc->wHubCharacteristics = 0x08;
8766+ desc->bPwrOn2PwrGood = 1;
8767+ desc->bHubContrCurrent = 0;
8768+ desc->bitmap[0] = 0;
8769+ desc->bitmap[1] = 0xff;
8770+ break;
8771+ case GetHubStatus:
8772+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8773+ "GetHubStatus\n");
8774+ memset (_buf, 0, 4);
8775+ break;
8776+ case GetPortStatus:
8777+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8778+ "GetPortStatus\n");
8779+
8780+ if (!_wIndex || _wIndex > 1)
8781+ goto error;
8782+
8783+ port_status = 0;
8784+
8785+ if (dwc_otg_hcd->flags.b.port_connect_status_change)
8786+ port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
8787+
8788+ if (dwc_otg_hcd->flags.b.port_enable_change)
8789+ port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
8790+
8791+ if (dwc_otg_hcd->flags.b.port_suspend_change)
8792+ port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
8793+
8794+ if (dwc_otg_hcd->flags.b.port_reset_change)
8795+ port_status |= (1 << USB_PORT_FEAT_C_RESET);
8796+
8797+ if (dwc_otg_hcd->flags.b.port_over_current_change) {
8798+ DWC_ERROR("Device Not Supported\n");
8799+ port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
8800+ }
8801+
8802+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
8803+ printk("DISCONNECTED PORT\n");
8804+ /*
8805+ * The port is disconnected, which means the core is
8806+ * either in device mode or it soon will be. Just
8807+ * return 0's for the remainder of the port status
8808+ * since the port register can't be read if the core
8809+ * is in device mode.
8810+ */
8811+#if 1 // winder.
8812+ *((u32 *) _buf) = cpu_to_le32(port_status);
8813+#else
8814+ *((__le32 *) _buf) = cpu_to_le32(port_status);
8815+#endif
8816+ break;
8817+ }
8818+
8819+ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
8820+ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
8821+
8822+ if (hprt0.b.prtconnsts)
8823+ port_status |= (1 << USB_PORT_FEAT_CONNECTION);
8824+
8825+ if (hprt0.b.prtena)
8826+ port_status |= (1 << USB_PORT_FEAT_ENABLE);
8827+
8828+ if (hprt0.b.prtsusp)
8829+ port_status |= (1 << USB_PORT_FEAT_SUSPEND);
8830+
8831+ if (hprt0.b.prtovrcurract)
8832+ port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
8833+
8834+ if (hprt0.b.prtrst)
8835+ port_status |= (1 << USB_PORT_FEAT_RESET);
8836+
8837+ if (hprt0.b.prtpwr)
8838+ port_status |= (1 << USB_PORT_FEAT_POWER);
8839+
8840+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
8841+ port_status |= USB_PORT_STAT_HIGH_SPEED;
8842+
8843+ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
8844+ port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
8845+
8846+ if (hprt0.b.prttstctl)
8847+ port_status |= (1 << USB_PORT_FEAT_TEST);
8848+
8849+ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
8850+#if 1 // winder.
8851+ *((u32 *) _buf) = cpu_to_le32(port_status);
8852+#else
8853+ *((__le32 *) _buf) = cpu_to_le32(port_status);
8854+#endif
8855+
8856+ break;
8857+ case SetHubFeature:
8858+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8859+ "SetHubFeature\n");
8860+ /* No HUB features supported */
8861+ break;
8862+ case SetPortFeature:
8863+ if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
8864+ goto error;
8865+
8866+ if (!dwc_otg_hcd->flags.b.port_connect_status) {
8867+ /*
8868+ * The port is disconnected, which means the core is
8869+ * either in device mode or it soon will be. Just
8870+ * return without doing anything since the port
8871+ * register can't be written if the core is in device
8872+ * mode.
8873+ */
8874+ break;
8875+ }
8876+
8877+ switch (_wValue) {
8878+ case USB_PORT_FEAT_SUSPEND:
8879+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8880+ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
8881+ if (_hcd->self.otg_port == _wIndex
8882+ && _hcd->self.b_hnp_enable) {
8883+ gotgctl_data_t gotgctl = {.d32=0};
8884+ gotgctl.b.hstsethnpen = 1;
8885+ dwc_modify_reg32(&core_if->core_global_regs->
8886+ gotgctl, 0, gotgctl.d32);
8887+ core_if->op_state = A_SUSPEND;
8888+ }
8889+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8890+ hprt0.b.prtsusp = 1;
8891+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8892+ //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
8893+ /* Suspend the Phy Clock */
8894+ {
8895+ pcgcctl_data_t pcgcctl = {.d32=0};
8896+ pcgcctl.b.stoppclk = 1;
8897+ dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
8898+ }
8899+
8900+ /* For HNP the bus must be suspended for at least 200ms.*/
8901+ if (_hcd->self.b_hnp_enable) {
8902+ mdelay(200);
8903+ //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
8904+ }
8905+ break;
8906+ case USB_PORT_FEAT_POWER:
8907+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8908+ "SetPortFeature - USB_PORT_FEAT_POWER\n");
8909+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8910+ hprt0.b.prtpwr = 1;
8911+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8912+ break;
8913+ case USB_PORT_FEAT_RESET:
8914+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8915+ "SetPortFeature - USB_PORT_FEAT_RESET\n");
8916+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8917+ /* TODO: Is this for OTG protocol??
8918+ * We shoudl remove OTG totally for Danube system.
8919+ * But, in the future, maybe we need this.
8920+ */
8921+#if 1 // winder
8922+ hprt0.b.prtrst = 1;
8923+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8924+#else
8925+ /* When B-Host the Port reset bit is set in
8926+ * the Start HCD Callback function, so that
8927+ * the reset is started within 1ms of the HNP
8928+ * success interrupt. */
8929+ if (!_hcd->self.is_b_host) {
8930+ hprt0.b.prtrst = 1;
8931+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8932+ }
8933+#endif
8934+ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
8935+ MDELAY (60);
8936+ hprt0.b.prtrst = 0;
8937+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8938+ break;
8939+
8940+#ifdef DWC_HS_ELECT_TST
8941+ case USB_PORT_FEAT_TEST:
8942+ {
8943+ uint32_t t;
8944+ gintmsk_data_t gintmsk;
8945+
8946+ t = (_wIndex >> 8); /* MSB wIndex USB */
8947+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
8948+ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
8949+ printk("USB_PORT_FEAT_TEST %d\n", t);
8950+ if (t < 6) {
8951+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8952+ hprt0.b.prttstctl = t;
8953+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8954+ } else {
8955+ /* Setup global vars with reg addresses (quick and
8956+ * dirty hack, should be cleaned up)
8957+ */
8958+ global_regs = core_if->core_global_regs;
8959+ hc_global_regs = core_if->host_if->host_global_regs;
8960+ hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
8961+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
8962+
8963+ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
8964+ /* Save current interrupt mask */
8965+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
8966+
8967+ /* Disable all interrupts while we muck with
8968+ * the hardware directly
8969+ */
8970+ dwc_write_reg32(&global_regs->gintmsk, 0);
8971+
8972+ /* 15 second delay per the test spec */
8973+ mdelay(15000);
8974+
8975+ /* Drive suspend on the root port */
8976+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8977+ hprt0.b.prtsusp = 1;
8978+ hprt0.b.prtres = 0;
8979+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8980+
8981+ /* 15 second delay per the test spec */
8982+ mdelay(15000);
8983+
8984+ /* Drive resume on the root port */
8985+ hprt0.d32 = dwc_otg_read_hprt0 (core_if);
8986+ hprt0.b.prtsusp = 0;
8987+ hprt0.b.prtres = 1;
8988+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8989+ mdelay(100);
8990+
8991+ /* Clear the resume bit */
8992+ hprt0.b.prtres = 0;
8993+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
8994+
8995+ /* Restore interrupts */
8996+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
8997+ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
8998+ /* Save current interrupt mask */
8999+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9000+
9001+ /* Disable all interrupts while we muck with
9002+ * the hardware directly
9003+ */
9004+ dwc_write_reg32(&global_regs->gintmsk, 0);
9005+
9006+ /* 15 second delay per the test spec */
9007+ mdelay(15000);
9008+
9009+ /* Send the Setup packet */
9010+ do_setup();
9011+
9012+ /* 15 second delay so nothing else happens for awhile */
9013+ mdelay(15000);
9014+
9015+ /* Restore interrupts */
9016+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9017+ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
9018+ /* Save current interrupt mask */
9019+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
9020+
9021+ /* Disable all interrupts while we muck with
9022+ * the hardware directly
9023+ */
9024+ dwc_write_reg32(&global_regs->gintmsk, 0);
9025+
9026+ /* Send the Setup packet */
9027+ do_setup();
9028+
9029+ /* 15 second delay so nothing else happens for awhile */
9030+ mdelay(15000);
9031+
9032+ /* Send the In and Ack packets */
9033+ do_in_ack();
9034+
9035+ /* 15 second delay so nothing else happens for awhile */
9036+ mdelay(15000);
9037+
9038+ /* Restore interrupts */
9039+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
9040+ }
9041+ }
9042+ break;
9043+ }
9044+#endif /* DWC_HS_ELECT_TST */
9045+
9046+ case USB_PORT_FEAT_INDICATOR:
9047+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
9048+ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
9049+ /* Not supported */
9050+ break;
9051+ default:
9052+ retval = -EINVAL;
9053+ DWC_ERROR ("DWC OTG HCD - "
9054+ "SetPortFeature request %xh "
9055+ "unknown or unsupported\n", _wValue);
9056+ break;
9057+ }
9058+ break;
9059+ default:
9060+error:
9061+ retval = -EINVAL;
9062+ DWC_WARN ("DWC OTG HCD - "
9063+ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
9064+ _typeReq, _wIndex, _wValue);
9065+ break;
9066+ }
9067+
9068+ return retval;
9069+}
9070+
9071+
9072+/**
9073+ * Assigns transactions from a QTD to a free host channel and initializes the
9074+ * host channel to perform the transactions. The host channel is removed from
9075+ * the free list.
9076+ *
9077+ * @param _hcd The HCD state structure.
9078+ * @param _qh Transactions from the first QTD for this QH are selected and
9079+ * assigned to a free host channel.
9080+ */
9081+static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
9082+{
9083+ dwc_hc_t *hc;
9084+ dwc_otg_qtd_t *qtd;
9085+ struct urb *urb;
9086+
9087+ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
9088+
9089+ hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
9090+
9091+ /* Remove the host channel from the free list. */
9092+ list_del_init(&hc->hc_list_entry);
9093+
9094+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
9095+ urb = qtd->urb;
9096+ _qh->channel = hc;
9097+ _qh->qtd_in_process = qtd;
9098+
9099+ /*
9100+ * Use usb_pipedevice to determine device address. This address is
9101+ * 0 before the SET_ADDRESS command and the correct address afterward.
9102+ */
9103+ hc->dev_addr = usb_pipedevice(urb->pipe);
9104+ hc->ep_num = usb_pipeendpoint(urb->pipe);
9105+
9106+ if (urb->dev->speed == USB_SPEED_LOW) {
9107+ hc->speed = DWC_OTG_EP_SPEED_LOW;
9108+ } else if (urb->dev->speed == USB_SPEED_FULL) {
9109+ hc->speed = DWC_OTG_EP_SPEED_FULL;
9110+ } else {
9111+ hc->speed = DWC_OTG_EP_SPEED_HIGH;
9112+ }
9113+ hc->max_packet = dwc_max_packet(_qh->maxp);
9114+
9115+ hc->xfer_started = 0;
9116+ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
9117+ hc->error_state = (qtd->error_count > 0);
9118+ hc->halt_on_queue = 0;
9119+ hc->halt_pending = 0;
9120+ hc->requests = 0;
9121+
9122+ /*
9123+ * The following values may be modified in the transfer type section
9124+ * below. The xfer_len value may be reduced when the transfer is
9125+ * started to accommodate the max widths of the XferSize and PktCnt
9126+ * fields in the HCTSIZn register.
9127+ */
9128+ hc->do_ping = _qh->ping_state;
9129+ hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
9130+ hc->data_pid_start = _qh->data_toggle;
9131+ hc->multi_count = 1;
9132+
9133+ if (_hcd->core_if->dma_enable) {
9134+ hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma + urb->actual_length;
9135+ } else {
9136+ hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
9137+ }
9138+ hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
9139+ hc->xfer_count = 0;
9140+
9141+ /*
9142+ * Set the split attributes
9143+ */
9144+ hc->do_split = 0;
9145+ if (_qh->do_split) {
9146+ hc->do_split = 1;
9147+ hc->xact_pos = qtd->isoc_split_pos;
9148+ hc->complete_split = qtd->complete_split;
9149+ hc->hub_addr = urb->dev->tt->hub->devnum;
9150+ hc->port_addr = urb->dev->ttport;
9151+ }
9152+
9153+ switch (usb_pipetype(urb->pipe)) {
9154+ case PIPE_CONTROL:
9155+ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
9156+ switch (qtd->control_phase) {
9157+ case DWC_OTG_CONTROL_SETUP:
9158+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
9159+ hc->do_ping = 0;
9160+ hc->ep_is_in = 0;
9161+ hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
9162+ if (_hcd->core_if->dma_enable) {
9163+ hc->xfer_buff = (uint8_t *)(u32)urb->setup_dma;
9164+ } else {
9165+ hc->xfer_buff = (uint8_t *)urb->setup_packet;
9166+ }
9167+ hc->xfer_len = 8;
9168+ break;
9169+ case DWC_OTG_CONTROL_DATA:
9170+ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
9171+ hc->data_pid_start = qtd->data_toggle;
9172+ break;
9173+ case DWC_OTG_CONTROL_STATUS:
9174+ /*
9175+ * Direction is opposite of data direction or IN if no
9176+ * data.
9177+ */
9178+ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
9179+ if (urb->transfer_buffer_length == 0) {
9180+ hc->ep_is_in = 1;
9181+ } else {
9182+ hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
9183+ }
9184+ if (hc->ep_is_in) {
9185+ hc->do_ping = 0;
9186+ }
9187+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
9188+ hc->xfer_len = 0;
9189+ if (_hcd->core_if->dma_enable) {
9190+ hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
9191+ } else {
9192+ hc->xfer_buff = (uint8_t *)_hcd->status_buf;
9193+ }
9194+ break;
9195+ }
9196+ break;
9197+ case PIPE_BULK:
9198+ hc->ep_type = DWC_OTG_EP_TYPE_BULK;
9199+ break;
9200+ case PIPE_INTERRUPT:
9201+ hc->ep_type = DWC_OTG_EP_TYPE_INTR;
9202+ break;
9203+ case PIPE_ISOCHRONOUS:
9204+ {
9205+ struct usb_iso_packet_descriptor *frame_desc;
9206+ frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
9207+ hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
9208+ if (_hcd->core_if->dma_enable) {
9209+ hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma;
9210+ } else {
9211+ hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
9212+ }
9213+ hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
9214+ hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
9215+
9216+ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
9217+ if (hc->xfer_len <= 188) {
9218+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
9219+ }
9220+ else {
9221+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
9222+ }
9223+ }
9224+ }
9225+ break;
9226+ }
9227+
9228+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
9229+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
9230+ /*
9231+ * This value may be modified when the transfer is started to
9232+ * reflect the actual transfer length.
9233+ */
9234+ hc->multi_count = dwc_hb_mult(_qh->maxp);
9235+ }
9236+
9237+ dwc_otg_hc_init(_hcd->core_if, hc);
9238+ hc->qh = _qh;
9239+}
9240+#define DEBUG_HOST_CHANNELS
9241+#ifdef DEBUG_HOST_CHANNELS
9242+static int last_sel_trans_num_per_scheduled = 0;
9243+module_param(last_sel_trans_num_per_scheduled, int, 0444);
9244+
9245+static int last_sel_trans_num_nonper_scheduled = 0;
9246+module_param(last_sel_trans_num_nonper_scheduled, int, 0444);
9247+
9248+static int last_sel_trans_num_avail_hc_at_start = 0;
9249+module_param(last_sel_trans_num_avail_hc_at_start, int, 0444);
9250+
9251+static int last_sel_trans_num_avail_hc_at_end = 0;
9252+module_param(last_sel_trans_num_avail_hc_at_end, int, 0444);
9253+#endif /* DEBUG_HOST_CHANNELS */
9254+
9255+/**
9256+ * This function selects transactions from the HCD transfer schedule and
9257+ * assigns them to available host channels. It is called from HCD interrupt
9258+ * handler functions.
9259+ *
9260+ * @param _hcd The HCD state structure.
9261+ *
9262+ * @return The types of new transactions that were assigned to host channels.
9263+ */
9264+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
9265+{
9266+ struct list_head *qh_ptr;
9267+ dwc_otg_qh_t *qh;
9268+ int num_channels;
9269+ unsigned long flags;
9270+ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
9271+
9272+#ifdef DEBUG_SOF
9273+ DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
9274+#endif /* */
9275+
9276+#ifdef DEBUG_HOST_CHANNELS
9277+ last_sel_trans_num_per_scheduled = 0;
9278+ last_sel_trans_num_nonper_scheduled = 0;
9279+ last_sel_trans_num_avail_hc_at_start = _hcd->available_host_channels;
9280+#endif /* DEBUG_HOST_CHANNELS */
9281+
9282+ /* Process entries in the periodic ready list. */
9283+ num_channels = _hcd->core_if->core_params->host_channels;
9284+ qh_ptr = _hcd->periodic_sched_ready.next;
9285+ while (qh_ptr != &_hcd->periodic_sched_ready
9286+ && !list_empty(&_hcd->free_hc_list)) {
9287+
9288+ // Make sure we leave one channel for non periodic transactions.
9289+ local_irq_save(flags);
9290+ if (_hcd->available_host_channels <= 1) {
9291+ local_irq_restore(flags);
9292+ break;
9293+ }
9294+ _hcd->available_host_channels--;
9295+ local_irq_restore(flags);
9296+#ifdef DEBUG_HOST_CHANNELS
9297+ last_sel_trans_num_per_scheduled++;
9298+#endif /* DEBUG_HOST_CHANNELS */
9299+
9300+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
9301+ assign_and_init_hc(_hcd, qh);
9302+
9303+ /*
9304+ * Move the QH from the periodic ready schedule to the
9305+ * periodic assigned schedule.
9306+ */
9307+ qh_ptr = qh_ptr->next;
9308+ local_irq_save(flags);
9309+ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
9310+ local_irq_restore(flags);
9311+ ret_val = DWC_OTG_TRANSACTION_PERIODIC;
9312+ }
9313+
9314+ /*
9315+ * Process entries in the deferred portion of the non-periodic list.
9316+ * A NAK put them here and, at the right time, they need to be
9317+ * placed on the sched_inactive list.
9318+ */
9319+ qh_ptr = _hcd->non_periodic_sched_deferred.next;
9320+ while (qh_ptr != &_hcd->non_periodic_sched_deferred) {
9321+ uint16_t frame_number =
9322+ dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
9323+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
9324+ qh_ptr = qh_ptr->next;
9325+
9326+ if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
9327+ // NAK did this
9328+ /*
9329+ * Move the QH from the non periodic deferred schedule to
9330+ * the non periodic inactive schedule.
9331+ */
9332+ local_irq_save(flags);
9333+ list_move(&qh->qh_list_entry,
9334+ &_hcd->non_periodic_sched_inactive);
9335+ local_irq_restore(flags);
9336+ }
9337+ }
9338+
9339+ /*
9340+ * Process entries in the inactive portion of the non-periodic
9341+ * schedule. Some free host channels may not be used if they are
9342+ * reserved for periodic transfers.
9343+ */
9344+ qh_ptr = _hcd->non_periodic_sched_inactive.next;
9345+ num_channels = _hcd->core_if->core_params->host_channels;
9346+ while (qh_ptr != &_hcd->non_periodic_sched_inactive
9347+ && !list_empty(&_hcd->free_hc_list)) {
9348+
9349+ local_irq_save(flags);
9350+ if (_hcd->available_host_channels < 1) {
9351+ local_irq_restore(flags);
9352+ break;
9353+ }
9354+ _hcd->available_host_channels--;
9355+ local_irq_restore(flags);
9356+#ifdef DEBUG_HOST_CHANNELS
9357+ last_sel_trans_num_nonper_scheduled++;
9358+#endif /* DEBUG_HOST_CHANNELS */
9359+
9360+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
9361+ assign_and_init_hc(_hcd, qh);
9362+
9363+ /*
9364+ * Move the QH from the non-periodic inactive schedule to the
9365+ * non-periodic active schedule.
9366+ */
9367+ qh_ptr = qh_ptr->next;
9368+ local_irq_save(flags);
9369+ list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
9370+ local_irq_restore(flags);
9371+
9372+ if (ret_val == DWC_OTG_TRANSACTION_NONE) {
9373+ ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
9374+ } else {
9375+ ret_val = DWC_OTG_TRANSACTION_ALL;
9376+ }
9377+
9378+ }
9379+#ifdef DEBUG_HOST_CHANNELS
9380+ last_sel_trans_num_avail_hc_at_end = _hcd->available_host_channels;
9381+#endif /* DEBUG_HOST_CHANNELS */
9382+
9383+ return ret_val;
9384+}
9385+
9386+/**
9387+ * Attempts to queue a single transaction request for a host channel
9388+ * associated with either a periodic or non-periodic transfer. This function
9389+ * assumes that there is space available in the appropriate request queue. For
9390+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
9391+ * is available in the appropriate Tx FIFO.
9392+ *
9393+ * @param _hcd The HCD state structure.
9394+ * @param _hc Host channel descriptor associated with either a periodic or
9395+ * non-periodic transfer.
9396+ * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
9397+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
9398+ * transfers.
9399+ *
9400+ * @return 1 if a request is queued and more requests may be needed to
9401+ * complete the transfer, 0 if no more requests are required for this
9402+ * transfer, -1 if there is insufficient space in the Tx FIFO.
9403+ */
9404+static int queue_transaction(dwc_otg_hcd_t *_hcd,
9405+ dwc_hc_t *_hc,
9406+ uint16_t _fifo_dwords_avail)
9407+{
9408+ int retval;
9409+
9410+ if (_hcd->core_if->dma_enable) {
9411+ if (!_hc->xfer_started) {
9412+ dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
9413+ _hc->qh->ping_state = 0;
9414+ }
9415+ retval = 0;
9416+ } else if (_hc->halt_pending) {
9417+ /* Don't queue a request if the channel has been halted. */
9418+ retval = 0;
9419+ } else if (_hc->halt_on_queue) {
9420+ dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
9421+ retval = 0;
9422+ } else if (_hc->do_ping) {
9423+ if (!_hc->xfer_started) {
9424+ dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
9425+ }
9426+ retval = 0;
9427+ } else if (!_hc->ep_is_in ||
9428+ _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
9429+ if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
9430+ if (!_hc->xfer_started) {
9431+ dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
9432+ retval = 1;
9433+ } else {
9434+ retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
9435+ }
9436+ } else {
9437+ retval = -1;
9438+ }
9439+ } else {
9440+ if (!_hc->xfer_started) {
9441+ dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
9442+ retval = 1;
9443+ } else {
9444+ retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
9445+ }
9446+ }
9447+
9448+ return retval;
9449+}
9450+
9451+/**
9452+ * Processes active non-periodic channels and queues transactions for these
9453+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx
9454+ * FIFO Empty interrupt is enabled if there are more transactions to queue as
9455+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
9456+ * FIFO Empty interrupt is disabled.
9457+ */
9458+static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
9459+{
9460+ gnptxsts_data_t tx_status;
9461+ struct list_head *orig_qh_ptr;
9462+ dwc_otg_qh_t *qh;
9463+ int status;
9464+ int no_queue_space = 0;
9465+ int no_fifo_space = 0;
9466+ int more_to_do = 0;
9467+
9468+ dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
9469+
9470+ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
9471+#ifdef DEBUG
9472+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
9473+ DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n",
9474+ tx_status.b.nptxqspcavail);
9475+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
9476+ tx_status.b.nptxfspcavail);
9477+#endif
9478+ /*
9479+ * Keep track of the starting point. Skip over the start-of-list
9480+ * entry.
9481+ */
9482+ if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
9483+ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
9484+ }
9485+ orig_qh_ptr = _hcd->non_periodic_qh_ptr;
9486+
9487+ /*
9488+ * Process once through the active list or until no more space is
9489+ * available in the request queue or the Tx FIFO.
9490+ */
9491+ do {
9492+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
9493+ if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
9494+ no_queue_space = 1;
9495+ break;
9496+ }
9497+
9498+ qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
9499+ status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
9500+
9501+ if (status > 0) {
9502+ more_to_do = 1;
9503+ } else if (status < 0) {
9504+ no_fifo_space = 1;
9505+ break;
9506+ }
9507+
9508+ /* Advance to next QH, skipping start-of-list entry. */
9509+ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
9510+ if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
9511+ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
9512+ }
9513+
9514+ } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
9515+
9516+ if (!_hcd->core_if->dma_enable) {
9517+ gintmsk_data_t intr_mask = {.d32 = 0};
9518+ intr_mask.b.nptxfempty = 1;
9519+
9520+#ifdef DEBUG
9521+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
9522+ DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n",
9523+ tx_status.b.nptxqspcavail);
9524+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n",
9525+ tx_status.b.nptxfspcavail);
9526+#endif
9527+ if (more_to_do || no_queue_space || no_fifo_space) {
9528+ /*
9529+ * May need to queue more transactions as the request
9530+ * queue or Tx FIFO empties. Enable the non-periodic
9531+ * Tx FIFO empty interrupt. (Always use the half-empty
9532+ * level to ensure that new requests are loaded as
9533+ * soon as possible.)
9534+ */
9535+ dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
9536+ } else {
9537+ /*
9538+ * Disable the Tx FIFO empty interrupt since there are
9539+ * no more transactions that need to be queued right
9540+ * now. This function is called from interrupt
9541+ * handlers to queue more transactions as transfer
9542+ * states change.
9543+ */
9544+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
9545+ }
9546+ }
9547+}
9548+
9549+/**
9550+ * Processes periodic channels for the next frame and queues transactions for
9551+ * these channels to the DWC_otg controller. After queueing transactions, the
9552+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
9553+ * to queue as Periodic Tx FIFO or request queue space becomes available.
9554+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
9555+ */
9556+static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
9557+{
9558+ hptxsts_data_t tx_status;
9559+ struct list_head *qh_ptr;
9560+ dwc_otg_qh_t *qh;
9561+ int status;
9562+ int no_queue_space = 0;
9563+ int no_fifo_space = 0;
9564+
9565+ dwc_otg_host_global_regs_t *host_regs;
9566+ host_regs = _hcd->core_if->host_if->host_global_regs;
9567+
9568+ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
9569+#ifdef DEBUG
9570+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
9571+ DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n",
9572+ tx_status.b.ptxqspcavail);
9573+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
9574+ tx_status.b.ptxfspcavail);
9575+#endif
9576+
9577+ qh_ptr = _hcd->periodic_sched_assigned.next;
9578+ while (qh_ptr != &_hcd->periodic_sched_assigned) {
9579+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
9580+ if (tx_status.b.ptxqspcavail == 0) {
9581+ no_queue_space = 1;
9582+ break;
9583+ }
9584+
9585+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
9586+
9587+ /*
9588+ * Set a flag if we're queuing high-bandwidth in slave mode.
9589+ * The flag prevents any halts to get into the request queue in
9590+ * the middle of multiple high-bandwidth packets getting queued.
9591+ */
9592+ if ((!_hcd->core_if->dma_enable) &&
9593+ (qh->channel->multi_count > 1))
9594+ {
9595+ _hcd->core_if->queuing_high_bandwidth = 1;
9596+ }
9597+
9598+ status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
9599+ if (status < 0) {
9600+ no_fifo_space = 1;
9601+ break;
9602+ }
9603+
9604+ /*
9605+ * In Slave mode, stay on the current transfer until there is
9606+ * nothing more to do or the high-bandwidth request count is
9607+ * reached. In DMA mode, only need to queue one request. The
9608+ * controller automatically handles multiple packets for
9609+ * high-bandwidth transfers.
9610+ */
9611+ if (_hcd->core_if->dma_enable ||
9612+ (status == 0 ||
9613+ qh->channel->requests == qh->channel->multi_count)) {
9614+ qh_ptr = qh_ptr->next;
9615+ /*
9616+ * Move the QH from the periodic assigned schedule to
9617+ * the periodic queued schedule.
9618+ */
9619+ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
9620+
9621+ /* done queuing high bandwidth */
9622+ _hcd->core_if->queuing_high_bandwidth = 0;
9623+ }
9624+ }
9625+
9626+ if (!_hcd->core_if->dma_enable) {
9627+ dwc_otg_core_global_regs_t *global_regs;
9628+ gintmsk_data_t intr_mask = {.d32 = 0};
9629+
9630+ global_regs = _hcd->core_if->core_global_regs;
9631+ intr_mask.b.ptxfempty = 1;
9632+#ifdef DEBUG
9633+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
9634+ DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n",
9635+ tx_status.b.ptxqspcavail);
9636+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n",
9637+ tx_status.b.ptxfspcavail);
9638+#endif
9639+ if (!(list_empty(&_hcd->periodic_sched_assigned)) ||
9640+ no_queue_space || no_fifo_space) {
9641+ /*
9642+ * May need to queue more transactions as the request
9643+ * queue or Tx FIFO empties. Enable the periodic Tx
9644+ * FIFO empty interrupt. (Always use the half-empty
9645+ * level to ensure that new requests are loaded as
9646+ * soon as possible.)
9647+ */
9648+ dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
9649+ } else {
9650+ /*
9651+ * Disable the Tx FIFO empty interrupt since there are
9652+ * no more transactions that need to be queued right
9653+ * now. This function is called from interrupt
9654+ * handlers to queue more transactions as transfer
9655+ * states change.
9656+ */
9657+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
9658+ }
9659+ }
9660+}
9661+
9662+/**
9663+ * This function processes the currently active host channels and queues
9664+ * transactions for these channels to the DWC_otg controller. It is called
9665+ * from HCD interrupt handler functions.
9666+ *
9667+ * @param _hcd The HCD state structure.
9668+ * @param _tr_type The type(s) of transactions to queue (non-periodic,
9669+ * periodic, or both).
9670+ */
9671+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
9672+ dwc_otg_transaction_type_e _tr_type)
9673+{
9674+#ifdef DEBUG_SOF
9675+ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
9676+#endif
9677+ /* Process host channels associated with periodic transfers. */
9678+ if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
9679+ _tr_type == DWC_OTG_TRANSACTION_ALL) &&
9680+ !list_empty(&_hcd->periodic_sched_assigned)) {
9681+
9682+ process_periodic_channels(_hcd);
9683+ }
9684+
9685+ /* Process host channels associated with non-periodic transfers. */
9686+ if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
9687+ _tr_type == DWC_OTG_TRANSACTION_ALL)) {
9688+ if (!list_empty(&_hcd->non_periodic_sched_active)) {
9689+ process_non_periodic_channels(_hcd);
9690+ } else {
9691+ /*
9692+ * Ensure NP Tx FIFO empty interrupt is disabled when
9693+ * there are no non-periodic transfers to process.
9694+ */
9695+ gintmsk_data_t gintmsk = {.d32 = 0};
9696+ gintmsk.b.nptxfempty = 1;
9697+ dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
9698+ }
9699+ }
9700+}
9701+
9702+/**
9703+ * Sets the final status of an URB and returns it to the device driver. Any
9704+ * required cleanup of the URB is performed.
9705+ */
9706+void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
9707+ int _status)
9708+ __releases(_hcd->lock)
9709+__acquires(_hcd->lock)
9710+{
9711+#ifdef DEBUG
9712+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
9713+ DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
9714+ __func__, _urb, usb_pipedevice(_urb->pipe),
9715+ usb_pipeendpoint(_urb->pipe),
9716+ usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
9717+ if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
9718+ int i;
9719+ for (i = 0; i < _urb->number_of_packets; i++) {
9720+ DWC_PRINT(" ISO Desc %d status: %d\n",
9721+ i, _urb->iso_frame_desc[i].status);
9722+ }
9723+ }
9724+ }
9725+#endif
9726+
9727+ _urb->status = _status;
9728+ _urb->hcpriv = NULL;
9729+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb);
9730+ spin_unlock(&_hcd->lock);
9731+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
9732+ spin_lock(&_hcd->lock);
9733+}
9734+
9735+/*
9736+ * Returns the Queue Head for an URB.
9737+ */
9738+dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb)
9739+{
9740+ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
9741+ return (dwc_otg_qh_t *)ep->hcpriv;
9742+}
9743+
9744+#ifdef DEBUG
9745+void dwc_print_setup_data (uint8_t *setup)
9746+{
9747+ int i;
9748+ if (CHK_DEBUG_LEVEL(DBG_HCD)){
9749+ DWC_PRINT("Setup Data = MSB ");
9750+ for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
9751+ DWC_PRINT("\n");
9752+ DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
9753+ DWC_PRINT(" bmRequestType Type = ");
9754+ switch ((setup[0]&0x60) >> 5) {
9755+ case 0: DWC_PRINT("Standard\n"); break;
9756+ case 1: DWC_PRINT("Class\n"); break;
9757+ case 2: DWC_PRINT("Vendor\n"); break;
9758+ case 3: DWC_PRINT("Reserved\n"); break;
9759+ }
9760+ DWC_PRINT(" bmRequestType Recipient = ");
9761+ switch (setup[0]&0x1f) {
9762+ case 0: DWC_PRINT("Device\n"); break;
9763+ case 1: DWC_PRINT("Interface\n"); break;
9764+ case 2: DWC_PRINT("Endpoint\n"); break;
9765+ case 3: DWC_PRINT("Other\n"); break;
9766+ default: DWC_PRINT("Reserved\n"); break;
9767+ }
9768+ DWC_PRINT(" bRequest = 0x%0x\n", setup[1]);
9769+ DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
9770+ DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
9771+ DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
9772+ }
9773+}
9774+#endif
9775+
9776+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
9777+#ifdef DEBUG
9778+#if 0
9779+ DWC_PRINT("Frame remaining at SOF:\n");
9780+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9781+ _hcd->frrem_samples, _hcd->frrem_accum,
9782+ (_hcd->frrem_samples > 0) ?
9783+ _hcd->frrem_accum/_hcd->frrem_samples : 0);
9784+
9785+ DWC_PRINT("\n");
9786+ DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
9787+ DWC_PRINT(" samples %u, accum %u, avg %u\n",
9788+ _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
9789+ (_hcd->core_if->hfnum_7_samples > 0) ?
9790+ _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
9791+ DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
9792+ DWC_PRINT(" samples %u, accum %u, avg %u\n",
9793+ _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
9794+ (_hcd->core_if->hfnum_0_samples > 0) ?
9795+ _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
9796+ DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
9797+ DWC_PRINT(" samples %u, accum %u, avg %u\n",
9798+ _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
9799+ (_hcd->core_if->hfnum_other_samples > 0) ?
9800+ _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
9801+
9802+ DWC_PRINT("\n");
9803+ DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
9804+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9805+ _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
9806+ (_hcd->hfnum_7_samples_a > 0) ?
9807+ _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
9808+ DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
9809+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9810+ _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
9811+ (_hcd->hfnum_0_samples_a > 0) ?
9812+ _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
9813+ DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
9814+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9815+ _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
9816+ (_hcd->hfnum_other_samples_a > 0) ?
9817+ _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
9818+
9819+ DWC_PRINT("\n");
9820+ DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
9821+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9822+ _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
9823+ (_hcd->hfnum_7_samples_b > 0) ?
9824+ _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
9825+ DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
9826+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9827+ _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
9828+ (_hcd->hfnum_0_samples_b > 0) ?
9829+ _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
9830+ DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
9831+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
9832+ _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
9833+ (_hcd->hfnum_other_samples_b > 0) ?
9834+ _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
9835+#endif
9836+#endif
9837+}
9838+
9839+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
9840+{
9841+#ifdef DEBUG
9842+ int num_channels;
9843+ int i;
9844+ gnptxsts_data_t np_tx_status;
9845+ hptxsts_data_t p_tx_status;
9846+
9847+ num_channels = _hcd->core_if->core_params->host_channels;
9848+ DWC_PRINT("\n");
9849+ DWC_PRINT("************************************************************\n");
9850+ DWC_PRINT("HCD State:\n");
9851+ DWC_PRINT(" Num channels: %d\n", num_channels);
9852+ for (i = 0; i < num_channels; i++) {
9853+ dwc_hc_t *hc = _hcd->hc_ptr_array[i];
9854+ DWC_PRINT(" Channel %d:\n", i);
9855+ DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
9856+ hc->dev_addr, hc->ep_num, hc->ep_is_in);
9857+ DWC_PRINT(" speed: %d\n", hc->speed);
9858+ DWC_PRINT(" ep_type: %d\n", hc->ep_type);
9859+ DWC_PRINT(" max_packet: %d\n", hc->max_packet);
9860+ DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
9861+ DWC_PRINT(" multi_count: %d\n", hc->multi_count);
9862+ DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
9863+ DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
9864+ DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
9865+ DWC_PRINT(" xfer_count: %d\n", hc->xfer_count);
9866+ DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue);
9867+ DWC_PRINT(" halt_pending: %d\n", hc->halt_pending);
9868+ DWC_PRINT(" halt_status: %d\n", hc->halt_status);
9869+ DWC_PRINT(" do_split: %d\n", hc->do_split);
9870+ DWC_PRINT(" complete_split: %d\n", hc->complete_split);
9871+ DWC_PRINT(" hub_addr: %d\n", hc->hub_addr);
9872+ DWC_PRINT(" port_addr: %d\n", hc->port_addr);
9873+ DWC_PRINT(" xact_pos: %d\n", hc->xact_pos);
9874+ DWC_PRINT(" requests: %d\n", hc->requests);
9875+ DWC_PRINT(" qh: %p\n", hc->qh);
9876+ if (hc->xfer_started) {
9877+ hfnum_data_t hfnum;
9878+ hcchar_data_t hcchar;
9879+ hctsiz_data_t hctsiz;
9880+ hcint_data_t hcint;
9881+ hcintmsk_data_t hcintmsk;
9882+ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
9883+ hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
9884+ hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
9885+ hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
9886+ hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
9887+ DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32);
9888+ DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32);
9889+ DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32);
9890+ DWC_PRINT(" hcint: 0x%08x\n", hcint.d32);
9891+ DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32);
9892+ }
9893+ if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
9894+ dwc_otg_qtd_t *qtd;
9895+ struct urb *urb;
9896+ qtd = hc->qh->qtd_in_process;
9897+ urb = qtd->urb;
9898+ DWC_PRINT(" URB Info:\n");
9899+ DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb);
9900+ if (urb != NULL) {
9901+ DWC_PRINT(" Dev: %d, EP: %d %s\n",
9902+ usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
9903+ usb_pipein(urb->pipe) ? "IN" : "OUT");
9904+ DWC_PRINT(" Max packet size: %d\n",
9905+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
9906+ DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer);
9907+ DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma);
9908+ DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length);
9909+ DWC_PRINT(" actual_length: %d\n", urb->actual_length);
9910+ }
9911+ }
9912+ }
9913+ //DWC_PRINT(" non_periodic_channels: %d\n", _hcd->non_periodic_channels);
9914+ //DWC_PRINT(" periodic_channels: %d\n", _hcd->periodic_channels);
9915+ DWC_PRINT(" available_channels: %d\n", _hcd->available_host_channels);
9916+ DWC_PRINT(" periodic_usecs: %d\n", _hcd->periodic_usecs);
9917+ np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
9918+ DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
9919+ DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
9920+ p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
9921+ DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
9922+ DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
9923+ dwc_otg_hcd_dump_frrem(_hcd);
9924+ dwc_otg_dump_global_registers(_hcd->core_if);
9925+ dwc_otg_dump_host_registers(_hcd->core_if);
9926+ DWC_PRINT("************************************************************\n");
9927+ DWC_PRINT("\n");
9928+#endif
9929+}
9930+#endif /* DWC_DEVICE_ONLY */
9931--- /dev/null
9932+++ b/drivers/usb/dwc_otg/dwc_otg_hcd.h
9933@@ -0,0 +1,677 @@
9934+/* ==========================================================================
9935+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.h $
9936+ * $Revision: 1.1.1.1 $
9937+ * $Date: 2009-04-17 06:15:34 $
9938+ * $Change: 537387 $
9939+ *
9940+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
9941+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9942+ * otherwise expressly agreed to in writing between Synopsys and you.
9943+ *
9944+ * The Software IS NOT an item of Licensed Software or Licensed Product under
9945+ * any End User Software License Agreement or Agreement for Licensed Product
9946+ * with Synopsys or any supplement thereto. You are permitted to use and
9947+ * redistribute this Software in source and binary forms, with or without
9948+ * modification, provided that redistributions of source code must retain this
9949+ * notice. You may not view, use, disclose, copy or distribute this file or
9950+ * any information contained herein except pursuant to this license grant from
9951+ * Synopsys. If you do not agree with this notice, including the disclaimer
9952+ * below, then you are not authorized to use the Software.
9953+ *
9954+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
9955+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
9956+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9957+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
9958+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9959+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
9960+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
9961+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
9962+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
9963+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
9964+ * DAMAGE.
9965+ * ========================================================================== */
9966+#ifndef DWC_DEVICE_ONLY
9967+#if !defined(__DWC_HCD_H__)
9968+#define __DWC_HCD_H__
9969+
9970+#include <linux/list.h>
9971+#include <linux/usb.h>
9972+//#include <linux/usb/hcd.h>
9973+#include "../core/hcd.h"
9974+
9975+struct lm_device;
9976+struct dwc_otg_device;
9977+
9978+#include "dwc_otg_cil.h"
9979+//#include "dwc_otg_ifx.h" // winder
9980+
9981+
9982+/**
9983+ * @file
9984+ *
9985+ * This file contains the structures, constants, and interfaces for
9986+ * the Host Contoller Driver (HCD).
9987+ *
9988+ * The Host Controller Driver (HCD) is responsible for translating requests
9989+ * from the USB Driver into the appropriate actions on the DWC_otg controller.
9990+ * It isolates the USBD from the specifics of the controller by providing an
9991+ * API to the USBD.
9992+ */
9993+
9994+/**
9995+ * Phases for control transfers.
9996+ */
9997+typedef enum dwc_otg_control_phase {
9998+ DWC_OTG_CONTROL_SETUP,
9999+ DWC_OTG_CONTROL_DATA,
10000+ DWC_OTG_CONTROL_STATUS
10001+} dwc_otg_control_phase_e;
10002+
10003+/** Transaction types. */
10004+typedef enum dwc_otg_transaction_type {
10005+ DWC_OTG_TRANSACTION_NONE,
10006+ DWC_OTG_TRANSACTION_PERIODIC,
10007+ DWC_OTG_TRANSACTION_NON_PERIODIC,
10008+ DWC_OTG_TRANSACTION_ALL
10009+} dwc_otg_transaction_type_e;
10010+
10011+/**
10012+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
10013+ * interrupt, or isochronous transfer. A single QTD is created for each URB
10014+ * (of one of these types) submitted to the HCD. The transfer associated with
10015+ * a QTD may require one or multiple transactions.
10016+ *
10017+ * A QTD is linked to a Queue Head, which is entered in either the
10018+ * non-periodic or periodic schedule for execution. When a QTD is chosen for
10019+ * execution, some or all of its transactions may be executed. After
10020+ * execution, the state of the QTD is updated. The QTD may be retired if all
10021+ * its transactions are complete or if an error occurred. Otherwise, it
10022+ * remains in the schedule so more transactions can be executed later.
10023+ */
10024+struct dwc_otg_qh;
10025+typedef struct dwc_otg_qtd {
10026+ /**
10027+ * Determines the PID of the next data packet for the data phase of
10028+ * control transfers. Ignored for other transfer types.<br>
10029+ * One of the following values:
10030+ * - DWC_OTG_HC_PID_DATA0
10031+ * - DWC_OTG_HC_PID_DATA1
10032+ */
10033+ uint8_t data_toggle;
10034+
10035+ /** Current phase for control transfers (Setup, Data, or Status). */
10036+ dwc_otg_control_phase_e control_phase;
10037+
10038+ /** Keep track of the current split type
10039+ * for FS/LS endpoints on a HS Hub */
10040+ uint8_t complete_split;
10041+
10042+ /** How many bytes transferred during SSPLIT OUT */
10043+ uint32_t ssplit_out_xfer_count;
10044+
10045+ /**
10046+ * Holds the number of bus errors that have occurred for a transaction
10047+ * within this transfer.
10048+ */
10049+ uint8_t error_count;
10050+
10051+ /**
10052+ * Index of the next frame descriptor for an isochronous transfer. A
10053+ * frame descriptor describes the buffer position and length of the
10054+ * data to be transferred in the next scheduled (micro)frame of an
10055+ * isochronous transfer. It also holds status for that transaction.
10056+ * The frame index starts at 0.
10057+ */
10058+ int isoc_frame_index;
10059+
10060+ /** Position of the ISOC split on full/low speed */
10061+ uint8_t isoc_split_pos;
10062+
10063+ /** Position of the ISOC split in the buffer for the current frame */
10064+ uint16_t isoc_split_offset;
10065+
10066+ /** URB for this transfer */
10067+ struct urb *urb;
10068+
10069+ /** This list of QTDs */
10070+ struct list_head qtd_list_entry;
10071+
10072+ /* Field to track the qh pointer */
10073+ struct dwc_otg_qh *qtd_qh_ptr;
10074+} dwc_otg_qtd_t;
10075+
10076+/**
10077+ * A Queue Head (QH) holds the static characteristics of an endpoint and
10078+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
10079+ * be entered in either the non-periodic or periodic schedule.
10080+ */
10081+typedef struct dwc_otg_qh {
10082+ /**
10083+ * Endpoint type.
10084+ * One of the following values:
10085+ * - USB_ENDPOINT_XFER_CONTROL
10086+ * - USB_ENDPOINT_XFER_ISOC
10087+ * - USB_ENDPOINT_XFER_BULK
10088+ * - USB_ENDPOINT_XFER_INT
10089+ */
10090+ uint8_t ep_type;
10091+ uint8_t ep_is_in;
10092+
10093+ /** wMaxPacketSize Field of Endpoint Descriptor. */
10094+ uint16_t maxp;
10095+
10096+ /**
10097+ * Determines the PID of the next data packet for non-control
10098+ * transfers. Ignored for control transfers.<br>
10099+ * One of the following values:
10100+ * - DWC_OTG_HC_PID_DATA0
10101+ * - DWC_OTG_HC_PID_DATA1
10102+ */
10103+ uint8_t data_toggle;
10104+
10105+ /** Ping state if 1. */
10106+ uint8_t ping_state;
10107+
10108+ /**
10109+ * List of QTDs for this QH.
10110+ */
10111+ struct list_head qtd_list;
10112+
10113+ /** Host channel currently processing transfers for this QH. */
10114+ dwc_hc_t *channel;
10115+
10116+ /** QTD currently assigned to a host channel for this QH. */
10117+ dwc_otg_qtd_t *qtd_in_process;
10118+
10119+ /** Full/low speed endpoint on high-speed hub requires split. */
10120+ uint8_t do_split;
10121+
10122+ /** @name Periodic schedule information */
10123+ /** @{ */
10124+
10125+ /** Bandwidth in microseconds per (micro)frame. */
10126+ uint8_t usecs;
10127+
10128+ /** Interval between transfers in (micro)frames. */
10129+ uint16_t interval;
10130+
10131+ /**
10132+ * (micro)frame to initialize a periodic transfer. The transfer
10133+ * executes in the following (micro)frame.
10134+ */
10135+ uint16_t sched_frame;
10136+
10137+ /** (micro)frame at which last start split was initialized. */
10138+ uint16_t start_split_frame;
10139+
10140+ /** @} */
10141+
10142+ uint16_t speed;
10143+ uint16_t frame_usecs[8];
10144+ /** Entry for QH in either the periodic or non-periodic schedule. */
10145+ struct list_head qh_list_entry;
10146+} dwc_otg_qh_t;
10147+
10148+/**
10149+ * This structure holds the state of the HCD, including the non-periodic and
10150+ * periodic schedules.
10151+ */
10152+typedef struct dwc_otg_hcd {
10153+ spinlock_t lock;
10154+
10155+ /** DWC OTG Core Interface Layer */
10156+ dwc_otg_core_if_t *core_if;
10157+
10158+ /** Internal DWC HCD Flags */
10159+ volatile union dwc_otg_hcd_internal_flags {
10160+ uint32_t d32;
10161+ struct {
10162+ unsigned port_connect_status_change : 1;
10163+ unsigned port_connect_status : 1;
10164+ unsigned port_reset_change : 1;
10165+ unsigned port_enable_change : 1;
10166+ unsigned port_suspend_change : 1;
10167+ unsigned port_over_current_change : 1;
10168+ unsigned reserved : 27;
10169+ } b;
10170+ } flags;
10171+
10172+ /**
10173+ * Inactive items in the non-periodic schedule. This is a list of
10174+ * Queue Heads. Transfers associated with these Queue Heads are not
10175+ * currently assigned to a host channel.
10176+ */
10177+ struct list_head non_periodic_sched_inactive;
10178+
10179+ /**
10180+ * Deferred items in the non-periodic schedule. This is a list of
10181+ * Queue Heads. Transfers associated with these Queue Heads are not
10182+ * currently assigned to a host channel.
10183+ * When we get an NAK, the QH goes here.
10184+ */
10185+ struct list_head non_periodic_sched_deferred;
10186+
10187+ /**
10188+ * Active items in the non-periodic schedule. This is a list of
10189+ * Queue Heads. Transfers associated with these Queue Heads are
10190+ * currently assigned to a host channel.
10191+ */
10192+ struct list_head non_periodic_sched_active;
10193+
10194+ /**
10195+ * Pointer to the next Queue Head to process in the active
10196+ * non-periodic schedule.
10197+ */
10198+ struct list_head *non_periodic_qh_ptr;
10199+
10200+ /**
10201+ * Inactive items in the periodic schedule. This is a list of QHs for
10202+ * periodic transfers that are _not_ scheduled for the next frame.
10203+ * Each QH in the list has an interval counter that determines when it
10204+ * needs to be scheduled for execution. This scheduling mechanism
10205+ * allows only a simple calculation for periodic bandwidth used (i.e.
10206+ * must assume that all periodic transfers may need to execute in the
10207+ * same frame). However, it greatly simplifies scheduling and should
10208+ * be sufficient for the vast majority of OTG hosts, which need to
10209+ * connect to a small number of peripherals at one time.
10210+ *
10211+ * Items move from this list to periodic_sched_ready when the QH
10212+ * interval counter is 0 at SOF.
10213+ */
10214+ struct list_head periodic_sched_inactive;
10215+
10216+ /**
10217+ * List of periodic QHs that are ready for execution in the next
10218+ * frame, but have not yet been assigned to host channels.
10219+ *
10220+ * Items move from this list to periodic_sched_assigned as host
10221+ * channels become available during the current frame.
10222+ */
10223+ struct list_head periodic_sched_ready;
10224+
10225+ /**
10226+ * List of periodic QHs to be executed in the next frame that are
10227+ * assigned to host channels.
10228+ *
10229+ * Items move from this list to periodic_sched_queued as the
10230+ * transactions for the QH are queued to the DWC_otg controller.
10231+ */
10232+ struct list_head periodic_sched_assigned;
10233+
10234+ /**
10235+ * List of periodic QHs that have been queued for execution.
10236+ *
10237+ * Items move from this list to either periodic_sched_inactive or
10238+ * periodic_sched_ready when the channel associated with the transfer
10239+ * is released. If the interval for the QH is 1, the item moves to
10240+ * periodic_sched_ready because it must be rescheduled for the next
10241+ * frame. Otherwise, the item moves to periodic_sched_inactive.
10242+ */
10243+ struct list_head periodic_sched_queued;
10244+
10245+ /**
10246+ * Total bandwidth claimed so far for periodic transfers. This value
10247+ * is in microseconds per (micro)frame. The assumption is that all
10248+ * periodic transfers may occur in the same (micro)frame.
10249+ */
10250+ uint16_t periodic_usecs;
10251+
10252+ /**
10253+ * Total bandwidth claimed so far for all periodic transfers
10254+ * in a frame.
10255+ * This will include a mixture of HS and FS transfers.
10256+ * Units are microseconds per (micro)frame.
10257+ * We have a budget per frame and have to schedule
10258+ * transactions accordingly.
10259+ * Watch out for the fact that things are actually scheduled for the
10260+ * "next frame".
10261+ */
10262+ uint16_t frame_usecs[8];
10263+
10264+ /**
10265+ * Frame number read from the core at SOF. The value ranges from 0 to
10266+ * DWC_HFNUM_MAX_FRNUM.
10267+ */
10268+ uint16_t frame_number;
10269+
10270+ /**
10271+ * Free host channels in the controller. This is a list of
10272+ * dwc_hc_t items.
10273+ */
10274+ struct list_head free_hc_list;
10275+
10276+ /**
10277+ * Number of available host channels.
10278+ */
10279+ int available_host_channels;
10280+
10281+ /**
10282+ * Array of pointers to the host channel descriptors. Allows accessing
10283+ * a host channel descriptor given the host channel number. This is
10284+ * useful in interrupt handlers.
10285+ */
10286+ dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
10287+
10288+ /**
10289+ * Buffer to use for any data received during the status phase of a
10290+ * control transfer. Normally no data is transferred during the status
10291+ * phase. This buffer is used as a bit bucket.
10292+ */
10293+ uint8_t *status_buf;
10294+
10295+ /**
10296+ * DMA address for status_buf.
10297+ */
10298+ dma_addr_t status_buf_dma;
10299+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
10300+
10301+ /**
10302+ * Structure to allow starting the HCD in a non-interrupt context
10303+ * during an OTG role change.
10304+ */
10305+ struct work_struct start_work;
10306+ struct usb_hcd *_p;
10307+
10308+ /**
10309+ * Connection timer. An OTG host must display a message if the device
10310+ * does not connect. Started when the VBus power is turned on via
10311+ * sysfs attribute "buspower".
10312+ */
10313+ struct timer_list conn_timer;
10314+
10315+ /* Tasket to do a reset */
10316+ struct tasklet_struct *reset_tasklet;
10317+
10318+#ifdef DEBUG
10319+ uint32_t frrem_samples;
10320+ uint64_t frrem_accum;
10321+
10322+ uint32_t hfnum_7_samples_a;
10323+ uint64_t hfnum_7_frrem_accum_a;
10324+ uint32_t hfnum_0_samples_a;
10325+ uint64_t hfnum_0_frrem_accum_a;
10326+ uint32_t hfnum_other_samples_a;
10327+ uint64_t hfnum_other_frrem_accum_a;
10328+
10329+ uint32_t hfnum_7_samples_b;
10330+ uint64_t hfnum_7_frrem_accum_b;
10331+ uint32_t hfnum_0_samples_b;
10332+ uint64_t hfnum_0_frrem_accum_b;
10333+ uint32_t hfnum_other_samples_b;
10334+ uint64_t hfnum_other_frrem_accum_b;
10335+#endif
10336+
10337+} dwc_otg_hcd_t;
10338+
10339+/** Gets the dwc_otg_hcd from a struct usb_hcd */
10340+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
10341+{
10342+ return (dwc_otg_hcd_t *)(hcd->hcd_priv);
10343+}
10344+
10345+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
10346+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
10347+{
10348+ return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
10349+}
10350+
10351+/** @name HCD Create/Destroy Functions */
10352+/** @{ */
10353+extern int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device);
10354+extern void dwc_otg_hcd_remove(struct device *_dev);
10355+/** @} */
10356+
10357+/** @name Linux HC Driver API Functions */
10358+/** @{ */
10359+
10360+extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
10361+extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
10362+extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
10363+extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
10364+
10365+extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
10366+ struct urb *urb,
10367+ gfp_t mem_flags);
10368+extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
10369+ struct urb *urb,
10370+ int status);
10371+extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
10372+
10373+extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
10374+ struct usb_host_endpoint *ep);
10375+
10376+extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
10377+ char *buf);
10378+extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
10379+ u16 typeReq,
10380+ u16 wValue,
10381+ u16 wIndex,
10382+ char *buf,
10383+ u16 wLength);
10384+
10385+/** @} */
10386+
10387+/** @name Transaction Execution Functions */
10388+/** @{ */
10389+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd);
10390+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
10391+ dwc_otg_transaction_type_e _tr_type);
10392+extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *_urb,
10393+ int _status);
10394+/** @} */
10395+
10396+/** @name Interrupt Handler Functions */
10397+/** @{ */
10398+extern int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10399+extern int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10400+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10401+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10402+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10403+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *_dwc_otg_hcd);
10404+extern int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10405+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10406+extern int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10407+extern int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10408+extern int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num);
10409+extern int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10410+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *_dwc_otg_hcd);
10411+/** @} */
10412+
10413+
10414+/** @name Schedule Queue Functions */
10415+/** @{ */
10416+
10417+/* Implemented in dwc_otg_hcd_queue.c */
10418+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb);
10419+extern void dwc_otg_hcd_qh_init (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb);
10420+extern void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh);
10421+extern int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
10422+extern void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh);
10423+extern void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_csplit);
10424+extern int dwc_otg_hcd_qh_deferr (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int delay);
10425+
10426+/** Remove and free a QH */
10427+static inline void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *_hcd,
10428+ dwc_otg_qh_t *_qh)
10429+{
10430+ dwc_otg_hcd_qh_remove (_hcd, _qh);
10431+ dwc_otg_hcd_qh_free (_qh);
10432+}
10433+
10434+/** Allocates memory for a QH structure.
10435+ * @return Returns the memory allocate or NULL on error. */
10436+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc (void)
10437+{
10438+#ifdef _SC_BUILD_
10439+ return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_ATOMIC);
10440+#else
10441+ return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_KERNEL);
10442+#endif
10443+}
10444+
10445+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb);
10446+extern void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb);
10447+extern int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
10448+
10449+/** Allocates memory for a QTD structure.
10450+ * @return Returns the memory allocate or NULL on error. */
10451+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc (void)
10452+{
10453+#ifdef _SC_BUILD_
10454+ return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_ATOMIC);
10455+#else
10456+ return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_KERNEL);
10457+#endif
10458+}
10459+
10460+/** Frees the memory for a QTD structure. QTD should already be removed from
10461+ * list.
10462+ * @param[in] _qtd QTD to free.*/
10463+static inline void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *_qtd)
10464+{
10465+ kfree (_qtd);
10466+}
10467+
10468+/** Removes a QTD from list.
10469+ * @param[in] _qtd QTD to remove from list. */
10470+static inline void dwc_otg_hcd_qtd_remove (dwc_otg_qtd_t *_qtd)
10471+{
10472+ unsigned long flags;
10473+ local_irq_save (flags);
10474+ list_del (&_qtd->qtd_list_entry);
10475+ local_irq_restore (flags);
10476+}
10477+
10478+/** Remove and free a QTD */
10479+static inline void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_qtd_t *_qtd)
10480+{
10481+ dwc_otg_hcd_qtd_remove (_qtd);
10482+ dwc_otg_hcd_qtd_free (_qtd);
10483+}
10484+
10485+/** @} */
10486+
10487+
10488+/** @name Internal Functions */
10489+/** @{ */
10490+dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb);
10491+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd);
10492+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd);
10493+/** @} */
10494+
10495+
10496+/** Gets the usb_host_endpoint associated with an URB. */
10497+static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *_urb)
10498+{
10499+ struct usb_device *dev = _urb->dev;
10500+ int ep_num = usb_pipeendpoint(_urb->pipe);
10501+ if (usb_pipein(_urb->pipe))
10502+ return dev->ep_in[ep_num];
10503+ else
10504+ return dev->ep_out[ep_num];
10505+}
10506+
10507+/**
10508+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
10509+ * qualified with its direction (possible 32 endpoints per device).
10510+ */
10511+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) \
10512+ ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
10513+ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
10514+
10515+/** Gets the QH that contains the list_head */
10516+#define dwc_list_to_qh(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qh_t,qh_list_entry))
10517+
10518+/** Gets the QTD that contains the list_head */
10519+#define dwc_list_to_qtd(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qtd_t,qtd_list_entry))
10520+
10521+/** Check if QH is non-periodic */
10522+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
10523+ (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
10524+
10525+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
10526+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
10527+
10528+/** Packet size for any kind of endpoint descriptor */
10529+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
10530+
10531+/**
10532+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is
10533+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
10534+ * frame number when the max frame number is reached.
10535+ */
10536+static inline int dwc_frame_num_le(uint16_t _frame1, uint16_t _frame2)
10537+{
10538+ return ((_frame2 - _frame1) & DWC_HFNUM_MAX_FRNUM) <=
10539+ (DWC_HFNUM_MAX_FRNUM >> 1);
10540+}
10541+
10542+/**
10543+ * Returns true if _frame1 is greater than _frame2. The comparison is done
10544+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
10545+ * number when the max frame number is reached.
10546+ */
10547+static inline int dwc_frame_num_gt(uint16_t _frame1, uint16_t _frame2)
10548+{
10549+ return (_frame1 != _frame2) &&
10550+ (((_frame1 - _frame2) & DWC_HFNUM_MAX_FRNUM) <
10551+ (DWC_HFNUM_MAX_FRNUM >> 1));
10552+}
10553+
10554+/**
10555+ * Increments _frame by the amount specified by _inc. The addition is done
10556+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
10557+ */
10558+static inline uint16_t dwc_frame_num_inc(uint16_t _frame, uint16_t _inc)
10559+{
10560+ return (_frame + _inc) & DWC_HFNUM_MAX_FRNUM;
10561+}
10562+
10563+static inline uint16_t dwc_full_frame_num (uint16_t _frame)
10564+{
10565+ return ((_frame) & DWC_HFNUM_MAX_FRNUM) >> 3;
10566+}
10567+
10568+static inline uint16_t dwc_micro_frame_num (uint16_t _frame)
10569+{
10570+ return (_frame) & 0x7;
10571+}
10572+
10573+#ifdef DEBUG
10574+/**
10575+ * Macro to sample the remaining PHY clocks left in the current frame. This
10576+ * may be used during debugging to determine the average time it takes to
10577+ * execute sections of code. There are two possible sample points, "a" and
10578+ * "b", so the _letter argument must be one of these values.
10579+ *
10580+ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
10581+ * example, "cat /sys/devices/lm0/hcd_frrem".
10582+ */
10583+#define dwc_sample_frrem(_hcd, _qh, _letter) \
10584+{ \
10585+ hfnum_data_t hfnum; \
10586+ dwc_otg_qtd_t *qtd; \
10587+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
10588+ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
10589+ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
10590+ switch (hfnum.b.frnum & 0x7) { \
10591+ case 7: \
10592+ _hcd->hfnum_7_samples_##_letter++; \
10593+ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
10594+ break; \
10595+ case 0: \
10596+ _hcd->hfnum_0_samples_##_letter++; \
10597+ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
10598+ break; \
10599+ default: \
10600+ _hcd->hfnum_other_samples_##_letter++; \
10601+ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
10602+ break; \
10603+ } \
10604+ } \
10605+}
10606+#else // DEBUG
10607+#define dwc_sample_frrem(_hcd, _qh, _letter)
10608+#endif // DEBUG
10609+#endif // __DWC_HCD_H__
10610+#endif /* DWC_DEVICE_ONLY */
10611--- /dev/null
10612+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
10613@@ -0,0 +1,1841 @@
10614+/* ==========================================================================
10615+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_intr.c $
10616+ * $Revision: 1.1.1.1 $
10617+ * $Date: 2009-04-17 06:15:34 $
10618+ * $Change: 553126 $
10619+ *
10620+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
10621+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
10622+ * otherwise expressly agreed to in writing between Synopsys and you.
10623+ *
10624+ * The Software IS NOT an item of Licensed Software or Licensed Product under
10625+ * any End User Software License Agreement or Agreement for Licensed Product
10626+ * with Synopsys or any supplement thereto. You are permitted to use and
10627+ * redistribute this Software in source and binary forms, with or without
10628+ * modification, provided that redistributions of source code must retain this
10629+ * notice. You may not view, use, disclose, copy or distribute this file or
10630+ * any information contained herein except pursuant to this license grant from
10631+ * Synopsys. If you do not agree with this notice, including the disclaimer
10632+ * below, then you are not authorized to use the Software.
10633+ *
10634+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
10635+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10636+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10637+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
10638+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10639+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
10640+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
10641+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
10642+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
10643+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10644+ * DAMAGE.
10645+ * ========================================================================== */
10646+#ifndef DWC_DEVICE_ONLY
10647+
10648+#include "dwc_otg_driver.h"
10649+#include "dwc_otg_hcd.h"
10650+#include "dwc_otg_regs.h"
10651+
10652+const int erratum_usb09_patched = 0;
10653+const int deferral_on = 1;
10654+const int nak_deferral_delay = 8;
10655+const int nyet_deferral_delay = 1;
10656+/** @file
10657+ * This file contains the implementation of the HCD Interrupt handlers.
10658+ */
10659+
10660+/** This function handles interrupts for the HCD. */
10661+int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10662+{
10663+ int retval = 0;
10664+
10665+ dwc_otg_core_if_t *core_if = _dwc_otg_hcd->core_if;
10666+ gintsts_data_t gintsts;
10667+#ifdef DEBUG
10668+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
10669+#endif
10670+
10671+ /* Check if HOST Mode */
10672+ if (dwc_otg_is_host_mode(core_if)) {
10673+ gintsts.d32 = dwc_otg_read_core_intr(core_if);
10674+ if (!gintsts.d32) {
10675+ return 0;
10676+ }
10677+
10678+#ifdef DEBUG
10679+ /* Don't print debug message in the interrupt handler on SOF */
10680+# ifndef DEBUG_SOF
10681+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
10682+# endif
10683+ DWC_DEBUGPL (DBG_HCD, "\n");
10684+#endif
10685+
10686+#ifdef DEBUG
10687+# ifndef DEBUG_SOF
10688+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
10689+# endif
10690+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32);
10691+#endif
10692+
10693+ if (gintsts.b.sofintr) {
10694+ retval |= dwc_otg_hcd_handle_sof_intr (_dwc_otg_hcd);
10695+ }
10696+ if (gintsts.b.rxstsqlvl) {
10697+ retval |= dwc_otg_hcd_handle_rx_status_q_level_intr (_dwc_otg_hcd);
10698+ }
10699+ if (gintsts.b.nptxfempty) {
10700+ retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr (_dwc_otg_hcd);
10701+ }
10702+ if (gintsts.b.i2cintr) {
10703+ /** @todo Implement i2cintr handler. */
10704+ }
10705+ if (gintsts.b.portintr) {
10706+ retval |= dwc_otg_hcd_handle_port_intr (_dwc_otg_hcd);
10707+ }
10708+ if (gintsts.b.hcintr) {
10709+ retval |= dwc_otg_hcd_handle_hc_intr (_dwc_otg_hcd);
10710+ }
10711+ if (gintsts.b.ptxfempty) {
10712+ retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (_dwc_otg_hcd);
10713+ }
10714+#ifdef DEBUG
10715+# ifndef DEBUG_SOF
10716+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
10717+# endif
10718+ {
10719+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n");
10720+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
10721+ dwc_read_reg32(&global_regs->gintsts));
10722+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
10723+ dwc_read_reg32(&global_regs->gintmsk));
10724+ }
10725+#endif
10726+
10727+#ifdef DEBUG
10728+# ifndef DEBUG_SOF
10729+ if (gintsts.d32 != DWC_SOF_INTR_MASK)
10730+# endif
10731+ DWC_DEBUGPL (DBG_HCD, "\n");
10732+#endif
10733+
10734+ }
10735+
10736+ return retval;
10737+}
10738+
10739+#ifdef DWC_TRACK_MISSED_SOFS
10740+#warning Compiling code to track missed SOFs
10741+#define FRAME_NUM_ARRAY_SIZE 1000
10742+/**
10743+ * This function is for debug only.
10744+ */
10745+static inline void track_missed_sofs(uint16_t _curr_frame_number) {
10746+ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
10747+ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
10748+ static int frame_num_idx = 0;
10749+ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
10750+ static int dumped_frame_num_array = 0;
10751+
10752+ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
10753+ if ((((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != _curr_frame_number)) {
10754+ frame_num_array[frame_num_idx] = _curr_frame_number;
10755+ last_frame_num_array[frame_num_idx++] = last_frame_num;
10756+ }
10757+ } else if (!dumped_frame_num_array) {
10758+ int i;
10759+ printk(KERN_EMERG USB_DWC "Frame Last Frame\n");
10760+ printk(KERN_EMERG USB_DWC "----- ----------\n");
10761+ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
10762+ printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n",
10763+ frame_num_array[i], last_frame_num_array[i]);
10764+ }
10765+ dumped_frame_num_array = 1;
10766+ }
10767+ last_frame_num = _curr_frame_number;
10768+}
10769+#endif
10770+
10771+/**
10772+ * Handles the start-of-frame interrupt in host mode. Non-periodic
10773+ * transactions may be queued to the DWC_otg controller for the current
10774+ * (micro)frame. Periodic transactions may be queued to the controller for the
10775+ * next (micro)frame.
10776+ */
10777+int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_hcd)
10778+{
10779+ hfnum_data_t hfnum;
10780+ struct list_head *qh_entry;
10781+ dwc_otg_qh_t *qh;
10782+ dwc_otg_transaction_type_e tr_type;
10783+ gintsts_data_t gintsts = {.d32 = 0};
10784+
10785+ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
10786+
10787+#ifdef DEBUG_SOF
10788+ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
10789+#endif
10790+
10791+ _hcd->frame_number = hfnum.b.frnum;
10792+
10793+#ifdef DEBUG
10794+ _hcd->frrem_accum += hfnum.b.frrem;
10795+ _hcd->frrem_samples++;
10796+#endif
10797+
10798+#ifdef DWC_TRACK_MISSED_SOFS
10799+ track_missed_sofs(_hcd->frame_number);
10800+#endif
10801+
10802+ /* Determine whether any periodic QHs should be executed. */
10803+ qh_entry = _hcd->periodic_sched_inactive.next;
10804+ while (qh_entry != &_hcd->periodic_sched_inactive) {
10805+ qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
10806+ qh_entry = qh_entry->next;
10807+ if (dwc_frame_num_le(qh->sched_frame, _hcd->frame_number)) {
10808+ /*
10809+ * Move QH to the ready list to be executed next
10810+ * (micro)frame.
10811+ */
10812+ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_ready);
10813+ }
10814+ }
10815+
10816+ tr_type = dwc_otg_hcd_select_transactions(_hcd);
10817+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
10818+ dwc_otg_hcd_queue_transactions(_hcd, tr_type);
10819+ }
10820+
10821+ /* Clear interrupt */
10822+ gintsts.b.sofintr = 1;
10823+ dwc_write_reg32(&_hcd->core_if->core_global_regs->gintsts, gintsts.d32);
10824+
10825+ return 1;
10826+}
10827+
10828+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
10829+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
10830+ * memory if the DWC_otg controller is operating in Slave mode. */
10831+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10832+{
10833+ host_grxsts_data_t grxsts;
10834+ dwc_hc_t *hc = NULL;
10835+
10836+ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
10837+
10838+ grxsts.d32 = dwc_read_reg32(&_dwc_otg_hcd->core_if->core_global_regs->grxstsp);
10839+
10840+ hc = _dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
10841+
10842+ /* Packet Status */
10843+ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
10844+ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
10845+ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start);
10846+ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
10847+
10848+ switch (grxsts.b.pktsts) {
10849+ case DWC_GRXSTS_PKTSTS_IN:
10850+ /* Read the data into the host buffer. */
10851+ if (grxsts.b.bcnt > 0) {
10852+ dwc_otg_read_packet(_dwc_otg_hcd->core_if,
10853+ hc->xfer_buff,
10854+ grxsts.b.bcnt);
10855+
10856+ /* Update the HC fields for the next packet received. */
10857+ hc->xfer_count += grxsts.b.bcnt;
10858+ hc->xfer_buff += grxsts.b.bcnt;
10859+ }
10860+
10861+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
10862+ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
10863+ case DWC_GRXSTS_PKTSTS_CH_HALTED:
10864+ /* Handled in interrupt, just ignore data */
10865+ break;
10866+ default:
10867+ DWC_ERROR ("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts);
10868+ break;
10869+ }
10870+
10871+ return 1;
10872+}
10873+
10874+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
10875+ * data packets may be written to the FIFO for OUT transfers. More requests
10876+ * may be written to the non-periodic request queue for IN transfers. This
10877+ * interrupt is enabled only in Slave mode. */
10878+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10879+{
10880+ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
10881+ dwc_otg_hcd_queue_transactions(_dwc_otg_hcd,
10882+ DWC_OTG_TRANSACTION_NON_PERIODIC);
10883+ return 1;
10884+}
10885+
10886+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
10887+ * packets may be written to the FIFO for OUT transfers. More requests may be
10888+ * written to the periodic request queue for IN transfers. This interrupt is
10889+ * enabled only in Slave mode. */
10890+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10891+{
10892+ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
10893+ dwc_otg_hcd_queue_transactions(_dwc_otg_hcd,
10894+ DWC_OTG_TRANSACTION_PERIODIC);
10895+ return 1;
10896+}
10897+
10898+/** There are multiple conditions that can cause a port interrupt. This function
10899+ * determines which interrupt conditions have occurred and handles them
10900+ * appropriately. */
10901+int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
10902+{
10903+ int retval = 0;
10904+ hprt0_data_t hprt0;
10905+ hprt0_data_t hprt0_modify;
10906+
10907+ hprt0.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0);
10908+ hprt0_modify.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0);
10909+
10910+ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
10911+ * GINTSTS */
10912+
10913+ hprt0_modify.b.prtena = 0;
10914+ hprt0_modify.b.prtconndet = 0;
10915+ hprt0_modify.b.prtenchng = 0;
10916+ hprt0_modify.b.prtovrcurrchng = 0;
10917+
10918+ /* Port Connect Detected
10919+ * Set flag and clear if detected */
10920+ if (hprt0.b.prtconndet) {
10921+ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
10922+ "Port Connect Detected--\n", hprt0.d32);
10923+ _dwc_otg_hcd->flags.b.port_connect_status_change = 1;
10924+ _dwc_otg_hcd->flags.b.port_connect_status = 1;
10925+ hprt0_modify.b.prtconndet = 1;
10926+
10927+ /* B-Device has connected, Delete the connection timer. */
10928+ del_timer( &_dwc_otg_hcd->conn_timer );
10929+
10930+ /* The Hub driver asserts a reset when it sees port connect
10931+ * status change flag */
10932+ retval |= 1;
10933+ }
10934+
10935+ /* Port Enable Changed
10936+ * Clear if detected - Set internal flag if disabled */
10937+ if (hprt0.b.prtenchng) {
10938+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
10939+ "Port Enable Changed--\n", hprt0.d32);
10940+ hprt0_modify.b.prtenchng = 1;
10941+ if (hprt0.b.prtena == 1) {
10942+ int do_reset = 0;
10943+ dwc_otg_core_params_t *params = _dwc_otg_hcd->core_if->core_params;
10944+ dwc_otg_core_global_regs_t *global_regs = _dwc_otg_hcd->core_if->core_global_regs;
10945+ dwc_otg_host_if_t *host_if = _dwc_otg_hcd->core_if->host_if;
10946+
10947+ /* Check if we need to adjust the PHY clock speed for
10948+ * low power and adjust it */
10949+ if (params->host_support_fs_ls_low_power)
10950+ {
10951+ gusbcfg_data_t usbcfg;
10952+
10953+ usbcfg.d32 = dwc_read_reg32 (&global_regs->gusbcfg);
10954+
10955+ if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) ||
10956+ (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED))
10957+ {
10958+ /*
10959+ * Low power
10960+ */
10961+ hcfg_data_t hcfg;
10962+ if (usbcfg.b.phylpwrclksel == 0) {
10963+ /* Set PHY low power clock select for FS/LS devices */
10964+ usbcfg.b.phylpwrclksel = 1;
10965+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
10966+ do_reset = 1;
10967+ }
10968+
10969+ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
10970+
10971+ if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) &&
10972+ (params->host_ls_low_power_phy_clk ==
10973+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ))
10974+ {
10975+ /* 6 MHZ */
10976+ DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
10977+ if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
10978+ hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
10979+ dwc_write_reg32(&host_if->host_global_regs->hcfg,
10980+ hcfg.d32);
10981+ do_reset = 1;
10982+ }
10983+ }
10984+ else {
10985+ /* 48 MHZ */
10986+ DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n");
10987+ if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
10988+ hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
10989+ dwc_write_reg32(&host_if->host_global_regs->hcfg,
10990+ hcfg.d32);
10991+ do_reset = 1;
10992+ }
10993+ }
10994+ }
10995+ else {
10996+ /*
10997+ * Not low power
10998+ */
10999+ if (usbcfg.b.phylpwrclksel == 1) {
11000+ usbcfg.b.phylpwrclksel = 0;
11001+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
11002+ do_reset = 1;
11003+ }
11004+ }
11005+
11006+ if (do_reset) {
11007+ tasklet_schedule(_dwc_otg_hcd->reset_tasklet);
11008+ }
11009+ }
11010+
11011+ if (!do_reset) {
11012+ /* Port has been enabled set the reset change flag */
11013+ _dwc_otg_hcd->flags.b.port_reset_change = 1;
11014+ }
11015+
11016+ } else {
11017+ _dwc_otg_hcd->flags.b.port_enable_change = 1;
11018+ }
11019+ retval |= 1;
11020+ }
11021+
11022+ /** Overcurrent Change Interrupt */
11023+ if (hprt0.b.prtovrcurrchng) {
11024+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
11025+ "Port Overcurrent Changed--\n", hprt0.d32);
11026+ _dwc_otg_hcd->flags.b.port_over_current_change = 1;
11027+ hprt0_modify.b.prtovrcurrchng = 1;
11028+ retval |= 1;
11029+ }
11030+
11031+ /* Clear Port Interrupts */
11032+ dwc_write_reg32(_dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
11033+
11034+ return retval;
11035+}
11036+
11037+
11038+/** This interrupt indicates that one or more host channels has a pending
11039+ * interrupt. There are multiple conditions that can cause each host channel
11040+ * interrupt. This function determines which conditions have occurred for each
11041+ * host channel interrupt and handles them appropriately. */
11042+int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
11043+{
11044+ int i;
11045+ int retval = 0;
11046+ haint_data_t haint;
11047+
11048+ /* Clear appropriate bits in HCINTn to clear the interrupt bit in
11049+ * GINTSTS */
11050+
11051+ haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if);
11052+
11053+ for (i=0; i<_dwc_otg_hcd->core_if->core_params->host_channels; i++) {
11054+ if (haint.b2.chint & (1 << i)) {
11055+ retval |= dwc_otg_hcd_handle_hc_n_intr (_dwc_otg_hcd, i);
11056+ }
11057+ }
11058+
11059+ return retval;
11060+}
11061+
11062+/* Macro used to clear one channel interrupt */
11063+#define clear_hc_int(_hc_regs_,_intr_) \
11064+do { \
11065+ hcint_data_t hcint_clear = {.d32 = 0}; \
11066+ hcint_clear.b._intr_ = 1; \
11067+ dwc_write_reg32(&((_hc_regs_)->hcint), hcint_clear.d32); \
11068+} while (0)
11069+
11070+/*
11071+ * Macro used to disable one channel interrupt. Channel interrupts are
11072+ * disabled when the channel is halted or released by the interrupt handler.
11073+ * There is no need to handle further interrupts of that type until the
11074+ * channel is re-assigned. In fact, subsequent handling may cause crashes
11075+ * because the channel structures are cleaned up when the channel is released.
11076+ */
11077+#define disable_hc_int(_hc_regs_,_intr_) \
11078+do { \
11079+ hcintmsk_data_t hcintmsk = {.d32 = 0}; \
11080+ hcintmsk.b._intr_ = 1; \
11081+ dwc_modify_reg32(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \
11082+} while (0)
11083+
11084+/**
11085+ * Gets the actual length of a transfer after the transfer halts. _halt_status
11086+ * holds the reason for the halt.
11087+ *
11088+ * For IN transfers where _halt_status is DWC_OTG_HC_XFER_COMPLETE,
11089+ * *_short_read is set to 1 upon return if less than the requested
11090+ * number of bytes were transferred. Otherwise, *_short_read is set to 0 upon
11091+ * return. _short_read may also be NULL on entry, in which case it remains
11092+ * unchanged.
11093+ */
11094+static uint32_t get_actual_xfer_length(dwc_hc_t *_hc,
11095+ dwc_otg_hc_regs_t *_hc_regs,
11096+ dwc_otg_qtd_t *_qtd,
11097+ dwc_otg_halt_status_e _halt_status,
11098+ int *_short_read)
11099+{
11100+ hctsiz_data_t hctsiz;
11101+ uint32_t length;
11102+
11103+ if (_short_read != NULL) {
11104+ *_short_read = 0;
11105+ }
11106+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11107+
11108+ if (_halt_status == DWC_OTG_HC_XFER_COMPLETE) {
11109+ if (_hc->ep_is_in) {
11110+ length = _hc->xfer_len - hctsiz.b.xfersize;
11111+ if (_short_read != NULL) {
11112+ *_short_read = (hctsiz.b.xfersize != 0);
11113+ }
11114+ } else if (_hc->qh->do_split) {
11115+ length = _qtd->ssplit_out_xfer_count;
11116+ } else {
11117+ length = _hc->xfer_len;
11118+ }
11119+ } else {
11120+ /*
11121+ * Must use the hctsiz.pktcnt field to determine how much data
11122+ * has been transferred. This field reflects the number of
11123+ * packets that have been transferred via the USB. This is
11124+ * always an integral number of packets if the transfer was
11125+ * halted before its normal completion. (Can't use the
11126+ * hctsiz.xfersize field because that reflects the number of
11127+ * bytes transferred via the AHB, not the USB).
11128+ */
11129+ length = (_hc->start_pkt_count - hctsiz.b.pktcnt) * _hc->max_packet;
11130+ }
11131+
11132+ return length;
11133+}
11134+
11135+/**
11136+ * Updates the state of the URB after a Transfer Complete interrupt on the
11137+ * host channel. Updates the actual_length field of the URB based on the
11138+ * number of bytes transferred via the host channel. Sets the URB status
11139+ * if the data transfer is finished.
11140+ *
11141+ * @return 1 if the data transfer specified by the URB is completely finished,
11142+ * 0 otherwise.
11143+ */
11144+static int update_urb_state_xfer_comp(dwc_hc_t *_hc,
11145+ dwc_otg_hc_regs_t * _hc_regs, struct urb *_urb,
11146+ dwc_otg_qtd_t * _qtd, int *status)
11147+{
11148+ int xfer_done = 0;
11149+ int short_read = 0;
11150+
11151+ _urb->actual_length += get_actual_xfer_length(_hc, _hc_regs, _qtd,
11152+ DWC_OTG_HC_XFER_COMPLETE,
11153+ &short_read);
11154+
11155+ if (short_read || (_urb->actual_length == _urb->transfer_buffer_length)) {
11156+ xfer_done = 1;
11157+ if (short_read && (_urb->transfer_flags & URB_SHORT_NOT_OK)) {
11158+ *status = -EREMOTEIO;
11159+ } else {
11160+ *status = 0;
11161+ }
11162+ }
11163+
11164+#ifdef DEBUG
11165+ {
11166+ hctsiz_data_t hctsiz;
11167+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11168+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
11169+ __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num);
11170+ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", _hc->xfer_len);
11171+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize);
11172+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
11173+ _urb->transfer_buffer_length);
11174+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", _urb->actual_length);
11175+ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
11176+ short_read, xfer_done);
11177+ }
11178+#endif
11179+
11180+ return xfer_done;
11181+}
11182+
11183+/*
11184+ * Save the starting data toggle for the next transfer. The data toggle is
11185+ * saved in the QH for non-control transfers and it's saved in the QTD for
11186+ * control transfers.
11187+ */
11188+static void save_data_toggle(dwc_hc_t *_hc,
11189+ dwc_otg_hc_regs_t *_hc_regs,
11190+ dwc_otg_qtd_t *_qtd)
11191+{
11192+ hctsiz_data_t hctsiz;
11193+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11194+
11195+ if (_hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
11196+ dwc_otg_qh_t *qh = _hc->qh;
11197+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
11198+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
11199+ } else {
11200+ qh->data_toggle = DWC_OTG_HC_PID_DATA1;
11201+ }
11202+ } else {
11203+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
11204+ _qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
11205+ } else {
11206+ _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
11207+ }
11208+ }
11209+}
11210+
11211+/**
11212+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
11213+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
11214+ * still linked to the QH, the QH is added to the end of the inactive
11215+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic
11216+ * schedule if no more QTDs are linked to the QH.
11217+ */
11218+static void deactivate_qh(dwc_otg_hcd_t *_hcd,
11219+ dwc_otg_qh_t *_qh,
11220+ int free_qtd)
11221+{
11222+ int continue_split = 0;
11223+ dwc_otg_qtd_t *qtd;
11224+
11225+ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, _hcd, _qh, free_qtd);
11226+
11227+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
11228+
11229+ if (qtd->complete_split) {
11230+ continue_split = 1;
11231+ }
11232+ else if ((qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID) ||
11233+ (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END))
11234+ {
11235+ continue_split = 1;
11236+ }
11237+
11238+ if (free_qtd) {
11239+ /*
11240+ * Note that this was previously a call to
11241+ * dwc_otg_hcd_qtd_remove_and_free(qtd), which frees the qtd.
11242+ * However, that call frees the qtd memory, and we continue in the
11243+ * interrupt logic to access it many more times, including writing
11244+ * to it. With slub debugging on, it is clear that we were writing
11245+ * to memory we had freed.
11246+ * Call this instead, and now I have moved the freeing of the memory to
11247+ * the end of processing this interrupt.
11248+ */
11249+ //dwc_otg_hcd_qtd_remove_and_free(qtd);
11250+ dwc_otg_hcd_qtd_remove(qtd);
11251+
11252+ continue_split = 0;
11253+ }
11254+
11255+ _qh->channel = NULL;
11256+ _qh->qtd_in_process = NULL;
11257+ dwc_otg_hcd_qh_deactivate(_hcd, _qh, continue_split);
11258+}
11259+
11260+/**
11261+ * Updates the state of an Isochronous URB when the transfer is stopped for
11262+ * any reason. The fields of the current entry in the frame descriptor array
11263+ * are set based on the transfer state and the input _halt_status. Completes
11264+ * the Isochronous URB if all the URB frames have been completed.
11265+ *
11266+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
11267+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
11268+ */
11269+static dwc_otg_halt_status_e
11270+update_isoc_urb_state(dwc_otg_hcd_t *_hcd,
11271+ dwc_hc_t *_hc,
11272+ dwc_otg_hc_regs_t *_hc_regs,
11273+ dwc_otg_qtd_t *_qtd,
11274+ dwc_otg_halt_status_e _halt_status)
11275+{
11276+ struct urb *urb = _qtd->urb;
11277+ dwc_otg_halt_status_e ret_val = _halt_status;
11278+ struct usb_iso_packet_descriptor *frame_desc;
11279+
11280+ frame_desc = &urb->iso_frame_desc[_qtd->isoc_frame_index];
11281+ switch (_halt_status) {
11282+ case DWC_OTG_HC_XFER_COMPLETE:
11283+ frame_desc->status = 0;
11284+ frame_desc->actual_length =
11285+ get_actual_xfer_length(_hc, _hc_regs, _qtd,
11286+ _halt_status, NULL);
11287+ break;
11288+ case DWC_OTG_HC_XFER_FRAME_OVERRUN:
11289+ urb->error_count++;
11290+ if (_hc->ep_is_in) {
11291+ frame_desc->status = -ENOSR;
11292+ } else {
11293+ frame_desc->status = -ECOMM;
11294+ }
11295+ frame_desc->actual_length = 0;
11296+ break;
11297+ case DWC_OTG_HC_XFER_BABBLE_ERR:
11298+ urb->error_count++;
11299+ frame_desc->status = -EOVERFLOW;
11300+ /* Don't need to update actual_length in this case. */
11301+ break;
11302+ case DWC_OTG_HC_XFER_XACT_ERR:
11303+ urb->error_count++;
11304+ frame_desc->status = -EPROTO;
11305+ frame_desc->actual_length =
11306+ get_actual_xfer_length(_hc, _hc_regs, _qtd,
11307+ _halt_status, NULL);
11308+ default:
11309+ DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__,
11310+ _halt_status);
11311+ BUG();
11312+ break;
11313+ }
11314+
11315+ if (++_qtd->isoc_frame_index == urb->number_of_packets) {
11316+ /*
11317+ * urb->status is not used for isoc transfers.
11318+ * The individual frame_desc statuses are used instead.
11319+ */
11320+ dwc_otg_hcd_complete_urb(_hcd, urb, 0);
11321+ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
11322+ } else {
11323+ ret_val = DWC_OTG_HC_XFER_COMPLETE;
11324+ }
11325+
11326+ return ret_val;
11327+}
11328+
11329+/**
11330+ * Releases a host channel for use by other transfers. Attempts to select and
11331+ * queue more transactions since at least one host channel is available.
11332+ *
11333+ * @param _hcd The HCD state structure.
11334+ * @param _hc The host channel to release.
11335+ * @param _qtd The QTD associated with the host channel. This QTD may be freed
11336+ * if the transfer is complete or an error has occurred.
11337+ * @param _halt_status Reason the channel is being released. This status
11338+ * determines the actions taken by this function.
11339+ */
11340+static void release_channel(dwc_otg_hcd_t *_hcd,
11341+ dwc_hc_t *_hc,
11342+ dwc_otg_qtd_t *_qtd,
11343+ dwc_otg_halt_status_e _halt_status,
11344+ int *must_free)
11345+{
11346+ dwc_otg_transaction_type_e tr_type;
11347+ int free_qtd;
11348+ dwc_otg_qh_t * _qh;
11349+ int deact = 1;
11350+ int retry_delay = 1;
11351+ unsigned long flags;
11352+
11353+ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", __func__,
11354+ _hc->hc_num, _halt_status);
11355+
11356+ switch (_halt_status) {
11357+ case DWC_OTG_HC_XFER_NYET:
11358+ case DWC_OTG_HC_XFER_NAK:
11359+ if (_halt_status == DWC_OTG_HC_XFER_NYET) {
11360+ retry_delay = nyet_deferral_delay;
11361+ } else {
11362+ retry_delay = nak_deferral_delay;
11363+ }
11364+ free_qtd = 0;
11365+ if (deferral_on && _hc->do_split) {
11366+ _qh = _hc->qh;
11367+ if (_qh) {
11368+ deact = dwc_otg_hcd_qh_deferr(_hcd, _qh , retry_delay);
11369+ }
11370+ }
11371+ break;
11372+ case DWC_OTG_HC_XFER_URB_COMPLETE:
11373+ free_qtd = 1;
11374+ break;
11375+ case DWC_OTG_HC_XFER_AHB_ERR:
11376+ case DWC_OTG_HC_XFER_STALL:
11377+ case DWC_OTG_HC_XFER_BABBLE_ERR:
11378+ free_qtd = 1;
11379+ break;
11380+ case DWC_OTG_HC_XFER_XACT_ERR:
11381+ if (_qtd->error_count >= 3) {
11382+ DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n");
11383+ free_qtd = 1;
11384+ //_qtd->urb->status = -EPROTO;
11385+ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPROTO);
11386+ } else {
11387+ free_qtd = 0;
11388+ }
11389+ break;
11390+ case DWC_OTG_HC_XFER_URB_DEQUEUE:
11391+ /*
11392+ * The QTD has already been removed and the QH has been
11393+ * deactivated. Don't want to do anything except release the
11394+ * host channel and try to queue more transfers.
11395+ */
11396+ goto cleanup;
11397+ case DWC_OTG_HC_XFER_NO_HALT_STATUS:
11398+ DWC_ERROR("%s: No halt_status, channel %d\n", __func__, _hc->hc_num);
11399+ free_qtd = 0;
11400+ break;
11401+ default:
11402+ free_qtd = 0;
11403+ break;
11404+ }
11405+ if (free_qtd) {
11406+ /* Only change must_free to true (do not set to zero here -- it is
11407+ * pre-initialized to zero).
11408+ */
11409+ *must_free = 1;
11410+ }
11411+ if (deact) {
11412+ deactivate_qh(_hcd, _hc->qh, free_qtd);
11413+ }
11414+ cleanup:
11415+ /*
11416+ * Release the host channel for use by other transfers. The cleanup
11417+ * function clears the channel interrupt enables and conditions, so
11418+ * there's no need to clear the Channel Halted interrupt separately.
11419+ */
11420+ dwc_otg_hc_cleanup(_hcd->core_if, _hc);
11421+ list_add_tail(&_hc->hc_list_entry, &_hcd->free_hc_list);
11422+
11423+ local_irq_save(flags);
11424+ _hcd->available_host_channels++;
11425+ local_irq_restore(flags);
11426+ /* Try to queue more transfers now that there's a free channel, */
11427+ /* unless erratum_usb09_patched is set */
11428+ if (!erratum_usb09_patched) {
11429+ tr_type = dwc_otg_hcd_select_transactions(_hcd);
11430+ if (tr_type != DWC_OTG_TRANSACTION_NONE) {
11431+ dwc_otg_hcd_queue_transactions(_hcd, tr_type);
11432+ }
11433+ }
11434+}
11435+
11436+/**
11437+ * Halts a host channel. If the channel cannot be halted immediately because
11438+ * the request queue is full, this function ensures that the FIFO empty
11439+ * interrupt for the appropriate queue is enabled so that the halt request can
11440+ * be queued when there is space in the request queue.
11441+ *
11442+ * This function may also be called in DMA mode. In that case, the channel is
11443+ * simply released since the core always halts the channel automatically in
11444+ * DMA mode.
11445+ */
11446+static void halt_channel(dwc_otg_hcd_t *_hcd,
11447+ dwc_hc_t *_hc,
11448+ dwc_otg_qtd_t *_qtd,
11449+ dwc_otg_halt_status_e _halt_status, int *must_free)
11450+{
11451+ if (_hcd->core_if->dma_enable) {
11452+ release_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11453+ return;
11454+ }
11455+
11456+ /* Slave mode processing... */
11457+ dwc_otg_hc_halt(_hcd->core_if, _hc, _halt_status);
11458+
11459+ if (_hc->halt_on_queue) {
11460+ gintmsk_data_t gintmsk = {.d32 = 0};
11461+ dwc_otg_core_global_regs_t *global_regs;
11462+ global_regs = _hcd->core_if->core_global_regs;
11463+
11464+ if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
11465+ _hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
11466+ /*
11467+ * Make sure the Non-periodic Tx FIFO empty interrupt
11468+ * is enabled so that the non-periodic schedule will
11469+ * be processed.
11470+ */
11471+ gintmsk.b.nptxfempty = 1;
11472+ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
11473+ } else {
11474+ /*
11475+ * Move the QH from the periodic queued schedule to
11476+ * the periodic assigned schedule. This allows the
11477+ * halt to be queued when the periodic schedule is
11478+ * processed.
11479+ */
11480+ list_move(&_hc->qh->qh_list_entry,
11481+ &_hcd->periodic_sched_assigned);
11482+
11483+ /*
11484+ * Make sure the Periodic Tx FIFO Empty interrupt is
11485+ * enabled so that the periodic schedule will be
11486+ * processed.
11487+ */
11488+ gintmsk.b.ptxfempty = 1;
11489+ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
11490+ }
11491+ }
11492+}
11493+
11494+/**
11495+ * Performs common cleanup for non-periodic transfers after a Transfer
11496+ * Complete interrupt. This function should be called after any endpoint type
11497+ * specific handling is finished to release the host channel.
11498+ */
11499+static void complete_non_periodic_xfer(dwc_otg_hcd_t *_hcd,
11500+ dwc_hc_t *_hc,
11501+ dwc_otg_hc_regs_t *_hc_regs,
11502+ dwc_otg_qtd_t *_qtd,
11503+ dwc_otg_halt_status_e _halt_status, int *must_free)
11504+{
11505+ hcint_data_t hcint;
11506+
11507+ _qtd->error_count = 0;
11508+
11509+ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
11510+ if (hcint.b.nyet) {
11511+ /*
11512+ * Got a NYET on the last transaction of the transfer. This
11513+ * means that the endpoint should be in the PING state at the
11514+ * beginning of the next transfer.
11515+ */
11516+ _hc->qh->ping_state = 1;
11517+ clear_hc_int(_hc_regs,nyet);
11518+ }
11519+
11520+ /*
11521+ * Always halt and release the host channel to make it available for
11522+ * more transfers. There may still be more phases for a control
11523+ * transfer or more data packets for a bulk transfer at this point,
11524+ * but the host channel is still halted. A channel will be reassigned
11525+ * to the transfer when the non-periodic schedule is processed after
11526+ * the channel is released. This allows transactions to be queued
11527+ * properly via dwc_otg_hcd_queue_transactions, which also enables the
11528+ * Tx FIFO Empty interrupt if necessary.
11529+ */
11530+ if (_hc->ep_is_in) {
11531+ /*
11532+ * IN transfers in Slave mode require an explicit disable to
11533+ * halt the channel. (In DMA mode, this call simply releases
11534+ * the channel.)
11535+ */
11536+ halt_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11537+ } else {
11538+ /*
11539+ * The channel is automatically disabled by the core for OUT
11540+ * transfers in Slave mode.
11541+ */
11542+ release_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11543+ }
11544+}
11545+
11546+/**
11547+ * Performs common cleanup for periodic transfers after a Transfer Complete
11548+ * interrupt. This function should be called after any endpoint type specific
11549+ * handling is finished to release the host channel.
11550+ */
11551+static void complete_periodic_xfer(dwc_otg_hcd_t *_hcd,
11552+ dwc_hc_t *_hc,
11553+ dwc_otg_hc_regs_t *_hc_regs,
11554+ dwc_otg_qtd_t *_qtd,
11555+ dwc_otg_halt_status_e _halt_status, int *must_free)
11556+{
11557+ hctsiz_data_t hctsiz;
11558+ _qtd->error_count = 0;
11559+
11560+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11561+ if (!_hc->ep_is_in || hctsiz.b.pktcnt == 0) {
11562+ /* Core halts channel in these cases. */
11563+ release_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11564+ } else {
11565+ /* Flush any outstanding requests from the Tx queue. */
11566+ halt_channel(_hcd, _hc, _qtd, _halt_status, must_free);
11567+ }
11568+}
11569+
11570+/**
11571+ * Handles a host channel Transfer Complete interrupt. This handler may be
11572+ * called in either DMA mode or Slave mode.
11573+ */
11574+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *_hcd,
11575+ dwc_hc_t *_hc,
11576+ dwc_otg_hc_regs_t *_hc_regs,
11577+ dwc_otg_qtd_t *_qtd, int *must_free)
11578+{
11579+ int urb_xfer_done;
11580+ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
11581+ struct urb *urb = _qtd->urb;
11582+ int pipe_type = usb_pipetype(urb->pipe);
11583+ int status = -EINPROGRESS;
11584+
11585+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11586+ "Transfer Complete--\n", _hc->hc_num);
11587+
11588+ /*
11589+ * Handle xfer complete on CSPLIT.
11590+ */
11591+ if (_hc->qh->do_split) {
11592+ _qtd->complete_split = 0;
11593+ }
11594+
11595+ /* Update the QTD and URB states. */
11596+ switch (pipe_type) {
11597+ case PIPE_CONTROL:
11598+ switch (_qtd->control_phase) {
11599+ case DWC_OTG_CONTROL_SETUP:
11600+ if (urb->transfer_buffer_length > 0) {
11601+ _qtd->control_phase = DWC_OTG_CONTROL_DATA;
11602+ } else {
11603+ _qtd->control_phase = DWC_OTG_CONTROL_STATUS;
11604+ }
11605+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
11606+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
11607+ break;
11608+ case DWC_OTG_CONTROL_DATA: {
11609+ urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs,urb, _qtd, &status);
11610+ if (urb_xfer_done) {
11611+ _qtd->control_phase = DWC_OTG_CONTROL_STATUS;
11612+ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
11613+ } else {
11614+ save_data_toggle(_hc, _hc_regs, _qtd);
11615+ }
11616+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
11617+ break;
11618+ }
11619+ case DWC_OTG_CONTROL_STATUS:
11620+ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
11621+ if (status == -EINPROGRESS) {
11622+ status = 0;
11623+ }
11624+ dwc_otg_hcd_complete_urb(_hcd, urb, status);
11625+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
11626+ break;
11627+ }
11628+
11629+ complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,
11630+ halt_status, must_free);
11631+ break;
11632+ case PIPE_BULK:
11633+ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
11634+ urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status);
11635+ if (urb_xfer_done) {
11636+ dwc_otg_hcd_complete_urb(_hcd, urb, status);
11637+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
11638+ } else {
11639+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
11640+ }
11641+
11642+ save_data_toggle(_hc, _hc_regs, _qtd);
11643+ complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,halt_status, must_free);
11644+ break;
11645+ case PIPE_INTERRUPT:
11646+ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
11647+ update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status);
11648+
11649+ /*
11650+ * Interrupt URB is done on the first transfer complete
11651+ * interrupt.
11652+ */
11653+ dwc_otg_hcd_complete_urb(_hcd, urb, status);
11654+ save_data_toggle(_hc, _hc_regs, _qtd);
11655+ complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,
11656+ DWC_OTG_HC_XFER_URB_COMPLETE, must_free);
11657+ break;
11658+ case PIPE_ISOCHRONOUS:
11659+ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
11660+ if (_qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL)
11661+ {
11662+ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
11663+ DWC_OTG_HC_XFER_COMPLETE);
11664+ }
11665+ complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, halt_status, must_free);
11666+ break;
11667+ }
11668+
11669+ disable_hc_int(_hc_regs,xfercompl);
11670+
11671+ return 1;
11672+}
11673+
11674+/**
11675+ * Handles a host channel STALL interrupt. This handler may be called in
11676+ * either DMA mode or Slave mode.
11677+ */
11678+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *_hcd,
11679+ dwc_hc_t *_hc,
11680+ dwc_otg_hc_regs_t *_hc_regs,
11681+ dwc_otg_qtd_t *_qtd, int *must_free)
11682+{
11683+ struct urb *urb = _qtd->urb;
11684+ int pipe_type = usb_pipetype(urb->pipe);
11685+
11686+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11687+ "STALL Received--\n", _hc->hc_num);
11688+
11689+ if (pipe_type == PIPE_CONTROL) {
11690+ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE);
11691+ }
11692+
11693+ if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
11694+ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE);
11695+ /*
11696+ * USB protocol requires resetting the data toggle for bulk
11697+ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
11698+ * setup command is issued to the endpoint. Anticipate the
11699+ * CLEAR_FEATURE command since a STALL has occurred and reset
11700+ * the data toggle now.
11701+ */
11702+ _hc->qh->data_toggle = 0;
11703+ }
11704+
11705+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_STALL, must_free);
11706+ disable_hc_int(_hc_regs,stall);
11707+
11708+ return 1;
11709+}
11710+
11711+/*
11712+ * Updates the state of the URB when a transfer has been stopped due to an
11713+ * abnormal condition before the transfer completes. Modifies the
11714+ * actual_length field of the URB to reflect the number of bytes that have
11715+ * actually been transferred via the host channel.
11716+ */
11717+static void update_urb_state_xfer_intr(dwc_hc_t *_hc,
11718+ dwc_otg_hc_regs_t *_hc_regs,
11719+ struct urb *_urb,
11720+ dwc_otg_qtd_t *_qtd,
11721+ dwc_otg_halt_status_e _halt_status)
11722+{
11723+ uint32_t bytes_transferred = get_actual_xfer_length(_hc, _hc_regs, _qtd,
11724+ _halt_status, NULL);
11725+ _urb->actual_length += bytes_transferred;
11726+
11727+#ifdef DEBUG
11728+ {
11729+ hctsiz_data_t hctsiz;
11730+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
11731+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
11732+ __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num);
11733+ DWC_DEBUGPL(DBG_HCDV, " _hc->start_pkt_count %d\n", _hc->start_pkt_count);
11734+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
11735+ DWC_DEBUGPL(DBG_HCDV, " _hc->max_packet %d\n", _hc->max_packet);
11736+ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred);
11737+ DWC_DEBUGPL(DBG_HCDV, " _urb->actual_length %d\n", _urb->actual_length);
11738+ DWC_DEBUGPL(DBG_HCDV, " _urb->transfer_buffer_length %d\n",
11739+ _urb->transfer_buffer_length);
11740+ }
11741+#endif
11742+}
11743+
11744+/**
11745+ * Handles a host channel NAK interrupt. This handler may be called in either
11746+ * DMA mode or Slave mode.
11747+ */
11748+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *_hcd,
11749+ dwc_hc_t *_hc,
11750+ dwc_otg_hc_regs_t *_hc_regs,
11751+ dwc_otg_qtd_t *_qtd, int *must_free)
11752+{
11753+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11754+ "NAK Received--\n", _hc->hc_num);
11755+
11756+ /*
11757+ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
11758+ * interrupt. Re-start the SSPLIT transfer.
11759+ */
11760+ if (_hc->do_split) {
11761+ if (_hc->complete_split) {
11762+ _qtd->error_count = 0;
11763+ }
11764+ _qtd->complete_split = 0;
11765+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free);
11766+ goto handle_nak_done;
11767+ }
11768+
11769+ switch (usb_pipetype(_qtd->urb->pipe)) {
11770+ case PIPE_CONTROL:
11771+ case PIPE_BULK:
11772+ if (_hcd->core_if->dma_enable && _hc->ep_is_in) {
11773+ /*
11774+ * NAK interrupts are enabled on bulk/control IN
11775+ * transfers in DMA mode for the sole purpose of
11776+ * resetting the error count after a transaction error
11777+ * occurs. The core will continue transferring data.
11778+ */
11779+ _qtd->error_count = 0;
11780+ goto handle_nak_done;
11781+ }
11782+
11783+ /*
11784+ * NAK interrupts normally occur during OUT transfers in DMA
11785+ * or Slave mode. For IN transfers, more requests will be
11786+ * queued as request queue space is available.
11787+ */
11788+ _qtd->error_count = 0;
11789+
11790+ if (!_hc->qh->ping_state) {
11791+ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb,
11792+ _qtd, DWC_OTG_HC_XFER_NAK);
11793+ save_data_toggle(_hc, _hc_regs, _qtd);
11794+ if (_qtd->urb->dev->speed == USB_SPEED_HIGH) {
11795+ _hc->qh->ping_state = 1;
11796+ }
11797+ }
11798+
11799+ /*
11800+ * Halt the channel so the transfer can be re-started from
11801+ * the appropriate point or the PING protocol will
11802+ * start/continue.
11803+ */
11804+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free);
11805+ break;
11806+ case PIPE_INTERRUPT:
11807+ _qtd->error_count = 0;
11808+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free);
11809+ break;
11810+ case PIPE_ISOCHRONOUS:
11811+ /* Should never get called for isochronous transfers. */
11812+ BUG();
11813+ break;
11814+ }
11815+
11816+ handle_nak_done:
11817+ disable_hc_int(_hc_regs,nak);
11818+
11819+ return 1;
11820+}
11821+
11822+/**
11823+ * Handles a host channel ACK interrupt. This interrupt is enabled when
11824+ * performing the PING protocol in Slave mode, when errors occur during
11825+ * either Slave mode or DMA mode, and during Start Split transactions.
11826+ */
11827+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *_hcd,
11828+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
11829+{
11830+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11831+ "ACK Received--\n", _hc->hc_num);
11832+
11833+ if (_hc->do_split) {
11834+ /*
11835+ * Handle ACK on SSPLIT.
11836+ * ACK should not occur in CSPLIT.
11837+ */
11838+ if ((!_hc->ep_is_in) && (_hc->data_pid_start != DWC_OTG_HC_PID_SETUP)) {
11839+ _qtd->ssplit_out_xfer_count = _hc->xfer_len;
11840+ }
11841+ if (!(_hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !_hc->ep_is_in)) {
11842+ /* Don't need complete for isochronous out transfers. */
11843+ _qtd->complete_split = 1;
11844+ }
11845+
11846+ /* ISOC OUT */
11847+ if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && !_hc->ep_is_in) {
11848+ switch (_hc->xact_pos) {
11849+ case DWC_HCSPLIT_XACTPOS_ALL:
11850+ break;
11851+ case DWC_HCSPLIT_XACTPOS_END:
11852+ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
11853+ _qtd->isoc_split_offset = 0;
11854+ break;
11855+ case DWC_HCSPLIT_XACTPOS_BEGIN:
11856+ case DWC_HCSPLIT_XACTPOS_MID:
11857+ /*
11858+ * For BEGIN or MID, calculate the length for
11859+ * the next microframe to determine the correct
11860+ * SSPLIT token, either MID or END.
11861+ */
11862+ do {
11863+ struct usb_iso_packet_descriptor *frame_desc;
11864+
11865+ frame_desc = &_qtd->urb->iso_frame_desc[_qtd->isoc_frame_index];
11866+ _qtd->isoc_split_offset += 188;
11867+
11868+ if ((frame_desc->length - _qtd->isoc_split_offset) <= 188) {
11869+ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
11870+ }
11871+ else {
11872+ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
11873+ }
11874+
11875+ } while(0);
11876+ break;
11877+ }
11878+ } else {
11879+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free);
11880+ }
11881+ } else {
11882+ _qtd->error_count = 0;
11883+
11884+ if (_hc->qh->ping_state) {
11885+ _hc->qh->ping_state = 0;
11886+ /*
11887+ * Halt the channel so the transfer can be re-started
11888+ * from the appropriate point. This only happens in
11889+ * Slave mode. In DMA mode, the ping_state is cleared
11890+ * when the transfer is started because the core
11891+ * automatically executes the PING, then the transfer.
11892+ */
11893+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free);
11894+ } else {
11895+ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
11896+ }
11897+ }
11898+
11899+ /*
11900+ * If the ACK occurred when _not_ in the PING state, let the channel
11901+ * continue transferring data after clearing the error count.
11902+ */
11903+
11904+ disable_hc_int(_hc_regs,ack);
11905+
11906+ return 1;
11907+}
11908+
11909+/**
11910+ * Handles a host channel NYET interrupt. This interrupt should only occur on
11911+ * Bulk and Control OUT endpoints and for complete split transactions. If a
11912+ * NYET occurs at the same time as a Transfer Complete interrupt, it is
11913+ * handled in the xfercomp interrupt handler, not here. This handler may be
11914+ * called in either DMA mode or Slave mode.
11915+ */
11916+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *_hcd,
11917+ dwc_hc_t *_hc,
11918+ dwc_otg_hc_regs_t *_hc_regs,
11919+ dwc_otg_qtd_t *_qtd, int *must_free)
11920+{
11921+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11922+ "NYET Received--\n", _hc->hc_num);
11923+
11924+ /*
11925+ * NYET on CSPLIT
11926+ * re-do the CSPLIT immediately on non-periodic
11927+ */
11928+ if ((_hc->do_split) && (_hc->complete_split)) {
11929+ if ((_hc->ep_type == DWC_OTG_EP_TYPE_INTR) ||
11930+ (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
11931+ int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
11932+
11933+ if (dwc_full_frame_num(frnum) !=
11934+ dwc_full_frame_num(_hc->qh->sched_frame)) {
11935+ /*
11936+ * No longer in the same full speed frame.
11937+ * Treat this as a transaction error.
11938+ */
11939+#if 0
11940+ /** @todo Fix system performance so this can
11941+ * be treated as an error. Right now complete
11942+ * splits cannot be scheduled precisely enough
11943+ * due to other system activity, so this error
11944+ * occurs regularly in Slave mode.
11945+ */
11946+ _qtd->error_count++;
11947+#endif
11948+ _qtd->complete_split = 0;
11949+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free);
11950+ /** @todo add support for isoc release */
11951+ goto handle_nyet_done;
11952+ }
11953+ }
11954+
11955+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free);
11956+ goto handle_nyet_done;
11957+ }
11958+
11959+ _hc->qh->ping_state = 1;
11960+ _qtd->error_count = 0;
11961+
11962+ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, _qtd,
11963+ DWC_OTG_HC_XFER_NYET);
11964+ save_data_toggle(_hc, _hc_regs, _qtd);
11965+
11966+ /*
11967+ * Halt the channel and re-start the transfer so the PING
11968+ * protocol will start.
11969+ */
11970+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free);
11971+
11972+handle_nyet_done:
11973+ disable_hc_int(_hc_regs,nyet);
11974+ clear_hc_int(_hc_regs, nyet);
11975+ return 1;
11976+}
11977+
11978+/**
11979+ * Handles a host channel babble interrupt. This handler may be called in
11980+ * either DMA mode or Slave mode.
11981+ */
11982+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *_hcd,
11983+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
11984+{
11985+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
11986+ "Babble Error--\n", _hc->hc_num);
11987+ if (_hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
11988+ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EOVERFLOW);
11989+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_BABBLE_ERR, must_free);
11990+ } else {
11991+ dwc_otg_halt_status_e halt_status;
11992+ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
11993+ DWC_OTG_HC_XFER_BABBLE_ERR);
11994+ halt_channel(_hcd, _hc, _qtd, halt_status, must_free);
11995+ }
11996+ disable_hc_int(_hc_regs,bblerr);
11997+ return 1;
11998+}
11999+
12000+/**
12001+ * Handles a host channel AHB error interrupt. This handler is only called in
12002+ * DMA mode.
12003+ */
12004+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *_hcd,
12005+ dwc_hc_t *_hc,
12006+ dwc_otg_hc_regs_t *_hc_regs,
12007+ dwc_otg_qtd_t *_qtd)
12008+{
12009+ hcchar_data_t hcchar;
12010+ hcsplt_data_t hcsplt;
12011+ hctsiz_data_t hctsiz;
12012+ uint32_t hcdma;
12013+ struct urb *urb = _qtd->urb;
12014+
12015+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12016+ "AHB Error--\n", _hc->hc_num);
12017+
12018+ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
12019+ hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt);
12020+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
12021+ hcdma = dwc_read_reg32(&_hc_regs->hcdma);
12022+
12023+ DWC_ERROR("AHB ERROR, Channel %d\n", _hc->hc_num);
12024+ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
12025+ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
12026+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
12027+ DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe));
12028+ DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
12029+ (usb_pipein(urb->pipe) ? "IN" : "OUT"));
12030+ DWC_ERROR(" Endpoint type: %s\n",
12031+ ({char *pipetype;
12032+ switch (usb_pipetype(urb->pipe)) {
12033+ case PIPE_CONTROL: pipetype = "CONTROL"; break;
12034+ case PIPE_BULK: pipetype = "BULK"; break;
12035+ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
12036+ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
12037+ default: pipetype = "UNKNOWN"; break;
12038+ }; pipetype;}));
12039+ DWC_ERROR(" Speed: %s\n",
12040+ ({char *speed;
12041+ switch (urb->dev->speed) {
12042+ case USB_SPEED_HIGH: speed = "HIGH"; break;
12043+ case USB_SPEED_FULL: speed = "FULL"; break;
12044+ case USB_SPEED_LOW: speed = "LOW"; break;
12045+ default: speed = "UNKNOWN"; break;
12046+ }; speed;}));
12047+ DWC_ERROR(" Max packet size: %d\n",
12048+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
12049+ DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length);
12050+ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
12051+ urb->transfer_buffer, (void *)(u32)urb->transfer_dma);
12052+ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
12053+ urb->setup_packet, (void *)(u32)urb->setup_dma);
12054+ DWC_ERROR(" Interval: %d\n", urb->interval);
12055+
12056+ dwc_otg_hcd_complete_urb(_hcd, urb, -EIO);
12057+
12058+ /*
12059+ * Force a channel halt. Don't call halt_channel because that won't
12060+ * write to the HCCHARn register in DMA mode to force the halt.
12061+ */
12062+ dwc_otg_hc_halt(_hcd->core_if, _hc, DWC_OTG_HC_XFER_AHB_ERR);
12063+
12064+ disable_hc_int(_hc_regs,ahberr);
12065+ return 1;
12066+}
12067+
12068+/**
12069+ * Handles a host channel transaction error interrupt. This handler may be
12070+ * called in either DMA mode or Slave mode.
12071+ */
12072+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *_hcd,
12073+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12074+{
12075+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12076+ "Transaction Error--\n", _hc->hc_num);
12077+
12078+ switch (usb_pipetype(_qtd->urb->pipe)) {
12079+ case PIPE_CONTROL:
12080+ case PIPE_BULK:
12081+ _qtd->error_count++;
12082+ if (!_hc->qh->ping_state) {
12083+ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb,
12084+ _qtd, DWC_OTG_HC_XFER_XACT_ERR);
12085+ save_data_toggle(_hc, _hc_regs, _qtd);
12086+ if (!_hc->ep_is_in && _qtd->urb->dev->speed == USB_SPEED_HIGH) {
12087+ _hc->qh->ping_state = 1;
12088+ }
12089+ }
12090+
12091+ /*
12092+ * Halt the channel so the transfer can be re-started from
12093+ * the appropriate point or the PING protocol will start.
12094+ */
12095+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free);
12096+ break;
12097+ case PIPE_INTERRUPT:
12098+ _qtd->error_count++;
12099+ if ((_hc->do_split) && (_hc->complete_split)) {
12100+ _qtd->complete_split = 0;
12101+ }
12102+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free);
12103+ break;
12104+ case PIPE_ISOCHRONOUS:
12105+ {
12106+ dwc_otg_halt_status_e halt_status;
12107+ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
12108+ DWC_OTG_HC_XFER_XACT_ERR);
12109+
12110+ halt_channel(_hcd, _hc, _qtd, halt_status, must_free);
12111+ }
12112+ break;
12113+ }
12114+
12115+
12116+ disable_hc_int(_hc_regs,xacterr);
12117+
12118+ return 1;
12119+}
12120+
12121+/**
12122+ * Handles a host channel frame overrun interrupt. This handler may be called
12123+ * in either DMA mode or Slave mode.
12124+ */
12125+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *_hcd,
12126+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12127+{
12128+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12129+ "Frame Overrun--\n", _hc->hc_num);
12130+
12131+ switch (usb_pipetype(_qtd->urb->pipe)) {
12132+ case PIPE_CONTROL:
12133+ case PIPE_BULK:
12134+ break;
12135+ case PIPE_INTERRUPT:
12136+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN, must_free);
12137+ break;
12138+ case PIPE_ISOCHRONOUS:
12139+ {
12140+ dwc_otg_halt_status_e halt_status;
12141+ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
12142+ DWC_OTG_HC_XFER_FRAME_OVERRUN);
12143+
12144+ halt_channel(_hcd, _hc, _qtd, halt_status, must_free);
12145+ }
12146+ break;
12147+ }
12148+
12149+ disable_hc_int(_hc_regs,frmovrun);
12150+
12151+ return 1;
12152+}
12153+
12154+/**
12155+ * Handles a host channel data toggle error interrupt. This handler may be
12156+ * called in either DMA mode or Slave mode.
12157+ */
12158+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *_hcd,
12159+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12160+{
12161+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12162+ "Data Toggle Error--\n", _hc->hc_num);
12163+
12164+ if (_hc->ep_is_in) {
12165+ _qtd->error_count = 0;
12166+ } else {
12167+ DWC_ERROR("Data Toggle Error on OUT transfer,"
12168+ "channel %d\n", _hc->hc_num);
12169+ }
12170+
12171+ disable_hc_int(_hc_regs,datatglerr);
12172+
12173+ return 1;
12174+}
12175+
12176+#ifdef DEBUG
12177+/**
12178+ * This function is for debug only. It checks that a valid halt status is set
12179+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
12180+ * taken and a warning is issued.
12181+ * @return 1 if halt status is ok, 0 otherwise.
12182+ */
12183+static inline int halt_status_ok(dwc_otg_hcd_t *_hcd,
12184+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12185+{
12186+ hcchar_data_t hcchar;
12187+ hctsiz_data_t hctsiz;
12188+ hcint_data_t hcint;
12189+ hcintmsk_data_t hcintmsk;
12190+ hcsplt_data_t hcsplt;
12191+
12192+ if (_hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
12193+ /*
12194+ * This code is here only as a check. This condition should
12195+ * never happen. Ignore the halt if it does occur.
12196+ */
12197+ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
12198+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
12199+ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
12200+ hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk);
12201+ hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt);
12202+ DWC_WARN("%s: _hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
12203+ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
12204+ "hcint 0x%08x, hcintmsk 0x%08x, "
12205+ "hcsplt 0x%08x, qtd->complete_split %d\n",
12206+ __func__, _hc->hc_num, hcchar.d32, hctsiz.d32,
12207+ hcint.d32, hcintmsk.d32,
12208+ hcsplt.d32, _qtd->complete_split);
12209+
12210+ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
12211+ __func__, _hc->hc_num);
12212+ DWC_WARN("\n");
12213+ clear_hc_int(_hc_regs,chhltd);
12214+ return 0;
12215+ }
12216+
12217+ /*
12218+ * This code is here only as a check. hcchar.chdis should
12219+ * never be set when the halt interrupt occurs. Halt the
12220+ * channel again if it does occur.
12221+ */
12222+ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
12223+ if (hcchar.b.chdis) {
12224+ DWC_WARN("%s: hcchar.chdis set unexpectedly, "
12225+ "hcchar 0x%08x, trying to halt again\n",
12226+ __func__, hcchar.d32);
12227+ clear_hc_int(_hc_regs,chhltd);
12228+ _hc->halt_pending = 0;
12229+ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12230+ return 0;
12231+ }
12232+
12233+ return 1;
12234+}
12235+#endif
12236+
12237+/**
12238+ * Handles a host Channel Halted interrupt in DMA mode. This handler
12239+ * determines the reason the channel halted and proceeds accordingly.
12240+ */
12241+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *_hcd,
12242+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12243+{
12244+ hcint_data_t hcint;
12245+ hcintmsk_data_t hcintmsk;
12246+
12247+ if (_hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
12248+ _hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
12249+ /*
12250+ * Just release the channel. A dequeue can happen on a
12251+ * transfer timeout. In the case of an AHB Error, the channel
12252+ * was forced to halt because there's no way to gracefully
12253+ * recover.
12254+ */
12255+ release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12256+ return;
12257+ }
12258+
12259+ /* Read the HCINTn register to determine the cause for the halt. */
12260+ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
12261+ hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk);
12262+
12263+ if (hcint.b.xfercomp) {
12264+ /** @todo This is here because of a possible hardware bug. Spec
12265+ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
12266+ * interrupt w/ACK bit set should occur, but I only see the
12267+ * XFERCOMP bit, even with it masked out. This is a workaround
12268+ * for that behavior. Should fix this when hardware is fixed.
12269+ */
12270+ if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!_hc->ep_is_in)) {
12271+ handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12272+ }
12273+ handle_hc_xfercomp_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12274+ } else if (hcint.b.stall) {
12275+ handle_hc_stall_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12276+ } else if (hcint.b.xacterr) {
12277+ /*
12278+ * Must handle xacterr before nak or ack. Could get a xacterr
12279+ * at the same time as either of these on a BULK/CONTROL OUT
12280+ * that started with a PING. The xacterr takes precedence.
12281+ */
12282+ handle_hc_xacterr_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12283+ } else if (hcint.b.nyet) {
12284+ /*
12285+ * Must handle nyet before nak or ack. Could get a nyet at the
12286+ * same time as either of those on a BULK/CONTROL OUT that
12287+ * started with a PING. The nyet takes precedence.
12288+ */
12289+ handle_hc_nyet_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12290+ } else if (hcint.b.bblerr) {
12291+ handle_hc_babble_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12292+ } else if (hcint.b.frmovrun) {
12293+ handle_hc_frmovrun_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12294+ } else if (hcint.b.datatglerr) {
12295+ handle_hc_datatglerr_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12296+ _hc->qh->data_toggle = 0;
12297+ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12298+ } else if (hcint.b.nak && !hcintmsk.b.nak) {
12299+ /*
12300+ * If nak is not masked, it's because a non-split IN transfer
12301+ * is in an error state. In that case, the nak is handled by
12302+ * the nak interrupt handler, not here. Handle nak here for
12303+ * BULK/CONTROL OUT transfers, which halt on a NAK to allow
12304+ * rewinding the buffer pointer.
12305+ */
12306+ handle_hc_nak_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12307+ } else if (hcint.b.ack && !hcintmsk.b.ack) {
12308+ /*
12309+ * If ack is not masked, it's because a non-split IN transfer
12310+ * is in an error state. In that case, the ack is handled by
12311+ * the ack interrupt handler, not here. Handle ack here for
12312+ * split transfers. Start splits halt on ACK.
12313+ */
12314+ handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free);
12315+ } else {
12316+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
12317+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
12318+ /*
12319+ * A periodic transfer halted with no other channel
12320+ * interrupts set. Assume it was halted by the core
12321+ * because it could not be completed in its scheduled
12322+ * (micro)frame.
12323+ */
12324+#ifdef DEBUG
12325+ DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
12326+ __func__, _hc->hc_num);
12327+#endif /* */
12328+ halt_channel(_hcd, _hc, _qtd,
12329+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, must_free);
12330+ } else {
12331+#ifdef DEBUG
12332+ DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
12333+ "for halting is unknown, nyet %d, hcint 0x%08x, intsts 0x%08x\n",
12334+ __func__, _hc->hc_num, hcint.b.nyet, hcint.d32,
12335+ dwc_read_reg32(&_hcd->core_if->core_global_regs->gintsts));
12336+#endif
12337+ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12338+ }
12339+ }
12340+}
12341+
12342+/**
12343+ * Handles a host channel Channel Halted interrupt.
12344+ *
12345+ * In slave mode, this handler is called only when the driver specifically
12346+ * requests a halt. This occurs during handling other host channel interrupts
12347+ * (e.g. nak, xacterr, stall, nyet, etc.).
12348+ *
12349+ * In DMA mode, this is the interrupt that occurs when the core has finished
12350+ * processing a transfer on a channel. Other host channel interrupts (except
12351+ * ahberr) are disabled in DMA mode.
12352+ */
12353+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *_hcd,
12354+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free)
12355+{
12356+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
12357+ "Channel Halted--\n", _hc->hc_num);
12358+
12359+ if (_hcd->core_if->dma_enable) {
12360+ handle_hc_chhltd_intr_dma(_hcd, _hc, _hc_regs, _qtd, must_free);
12361+ } else {
12362+#ifdef DEBUG
12363+ if (!halt_status_ok(_hcd, _hc, _hc_regs, _qtd, must_free)) {
12364+ return 1;
12365+ }
12366+#endif /* */
12367+ release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free);
12368+ }
12369+
12370+ return 1;
12371+}
12372+
12373+/** Handles interrupt for a specific Host Channel */
12374+int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num)
12375+{
12376+ int must_free = 0;
12377+ int retval = 0;
12378+ hcint_data_t hcint;
12379+ hcintmsk_data_t hcintmsk;
12380+ dwc_hc_t *hc;
12381+ dwc_otg_hc_regs_t *hc_regs;
12382+ dwc_otg_qtd_t *qtd;
12383+
12384+ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num);
12385+
12386+ hc = _dwc_otg_hcd->hc_ptr_array[_num];
12387+ hc_regs = _dwc_otg_hcd->core_if->host_if->hc_regs[_num];
12388+ qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
12389+
12390+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
12391+ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
12392+ DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
12393+ hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
12394+ hcint.d32 = hcint.d32 & hcintmsk.d32;
12395+
12396+ if (!_dwc_otg_hcd->core_if->dma_enable) {
12397+ if ((hcint.b.chhltd) && (hcint.d32 != 0x2)) {
12398+ hcint.b.chhltd = 0;
12399+ }
12400+ }
12401+
12402+ if (hcint.b.xfercomp) {
12403+ retval |= handle_hc_xfercomp_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12404+ /*
12405+ * If NYET occurred at same time as Xfer Complete, the NYET is
12406+ * handled by the Xfer Complete interrupt handler. Don't want
12407+ * to call the NYET interrupt handler in this case.
12408+ */
12409+ hcint.b.nyet = 0;
12410+ }
12411+ if (hcint.b.chhltd) {
12412+ retval |= handle_hc_chhltd_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12413+ }
12414+ if (hcint.b.ahberr) {
12415+ retval |= handle_hc_ahberr_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
12416+ }
12417+ if (hcint.b.stall) {
12418+ retval |= handle_hc_stall_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12419+ }
12420+ if (hcint.b.nak) {
12421+ retval |= handle_hc_nak_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12422+ }
12423+ if (hcint.b.ack) {
12424+ retval |= handle_hc_ack_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12425+ }
12426+ if (hcint.b.nyet) {
12427+ retval |= handle_hc_nyet_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12428+ }
12429+ if (hcint.b.xacterr) {
12430+ retval |= handle_hc_xacterr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12431+ }
12432+ if (hcint.b.bblerr) {
12433+ retval |= handle_hc_babble_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12434+ }
12435+ if (hcint.b.frmovrun) {
12436+ retval |= handle_hc_frmovrun_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12437+ }
12438+ if (hcint.b.datatglerr) {
12439+ retval |= handle_hc_datatglerr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free);
12440+ }
12441+
12442+ /*
12443+ * Logic to free the qtd here, at the end of the hc intr
12444+ * processing, if the handling of this interrupt determined
12445+ * that it needs to be freed.
12446+ */
12447+ if (must_free) {
12448+ /* Free the qtd here now that we are done using it. */
12449+ dwc_otg_hcd_qtd_free(qtd);
12450+ }
12451+ return retval;
12452+}
12453+
12454+#endif /* DWC_DEVICE_ONLY */
12455--- /dev/null
12456+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
12457@@ -0,0 +1,794 @@
12458+/* ==========================================================================
12459+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $
12460+ * $Revision: 1.1.1.1 $
12461+ * $Date: 2009-04-17 06:15:34 $
12462+ * $Change: 537387 $
12463+ *
12464+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
12465+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
12466+ * otherwise expressly agreed to in writing between Synopsys and you.
12467+ *
12468+ * The Software IS NOT an item of Licensed Software or Licensed Product under
12469+ * any End User Software License Agreement or Agreement for Licensed Product
12470+ * with Synopsys or any supplement thereto. You are permitted to use and
12471+ * redistribute this Software in source and binary forms, with or without
12472+ * modification, provided that redistributions of source code must retain this
12473+ * notice. You may not view, use, disclose, copy or distribute this file or
12474+ * any information contained herein except pursuant to this license grant from
12475+ * Synopsys. If you do not agree with this notice, including the disclaimer
12476+ * below, then you are not authorized to use the Software.
12477+ *
12478+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
12479+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
12480+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
12481+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
12482+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
12483+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12484+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
12485+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
12486+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
12487+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
12488+ * DAMAGE.
12489+ * ========================================================================== */
12490+#ifndef DWC_DEVICE_ONLY
12491+
12492+/**
12493+ * @file
12494+ *
12495+ * This file contains the functions to manage Queue Heads and Queue
12496+ * Transfer Descriptors.
12497+ */
12498+#include <linux/kernel.h>
12499+#include <linux/module.h>
12500+#include <linux/moduleparam.h>
12501+#include <linux/init.h>
12502+#include <linux/device.h>
12503+#include <linux/errno.h>
12504+#include <linux/list.h>
12505+#include <linux/interrupt.h>
12506+#include <linux/string.h>
12507+
12508+#include "dwc_otg_driver.h"
12509+#include "dwc_otg_hcd.h"
12510+#include "dwc_otg_regs.h"
12511+
12512+/**
12513+ * This function allocates and initializes a QH.
12514+ *
12515+ * @param _hcd The HCD state structure for the DWC OTG controller.
12516+ * @param[in] _urb Holds the information about the device/endpoint that we need
12517+ * to initialize the QH.
12518+ *
12519+ * @return Returns pointer to the newly allocated QH, or NULL on error. */
12520+dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb)
12521+{
12522+ dwc_otg_qh_t *qh;
12523+
12524+ /* Allocate memory */
12525+ /** @todo add memflags argument */
12526+ qh = dwc_otg_hcd_qh_alloc ();
12527+ if (qh == NULL) {
12528+ return NULL;
12529+ }
12530+
12531+ dwc_otg_hcd_qh_init (_hcd, qh, _urb);
12532+ return qh;
12533+}
12534+
12535+/** Free each QTD in the QH's QTD-list then free the QH. QH should already be
12536+ * removed from a list. QTD list should already be empty if called from URB
12537+ * Dequeue.
12538+ *
12539+ * @param[in] _qh The QH to free.
12540+ */
12541+void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh)
12542+{
12543+ dwc_otg_qtd_t *qtd;
12544+ struct list_head *pos;
12545+ unsigned long flags;
12546+
12547+ /* Free each QTD in the QTD list */
12548+ local_irq_save (flags);
12549+ for (pos = _qh->qtd_list.next;
12550+ pos != &_qh->qtd_list;
12551+ pos = _qh->qtd_list.next)
12552+ {
12553+ list_del (pos);
12554+ qtd = dwc_list_to_qtd (pos);
12555+ dwc_otg_hcd_qtd_free (qtd);
12556+ }
12557+ local_irq_restore (flags);
12558+
12559+ kfree (_qh);
12560+ return;
12561+}
12562+
12563+/** Initializes a QH structure.
12564+ *
12565+ * @param[in] _hcd The HCD state structure for the DWC OTG controller.
12566+ * @param[in] _qh The QH to init.
12567+ * @param[in] _urb Holds the information about the device/endpoint that we need
12568+ * to initialize the QH. */
12569+#define SCHEDULE_SLOP 10
12570+void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb)
12571+{
12572+ memset (_qh, 0, sizeof (dwc_otg_qh_t));
12573+
12574+ /* Initialize QH */
12575+ switch (usb_pipetype(_urb->pipe)) {
12576+ case PIPE_CONTROL:
12577+ _qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
12578+ break;
12579+ case PIPE_BULK:
12580+ _qh->ep_type = USB_ENDPOINT_XFER_BULK;
12581+ break;
12582+ case PIPE_ISOCHRONOUS:
12583+ _qh->ep_type = USB_ENDPOINT_XFER_ISOC;
12584+ break;
12585+ case PIPE_INTERRUPT:
12586+ _qh->ep_type = USB_ENDPOINT_XFER_INT;
12587+ break;
12588+ }
12589+
12590+ _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
12591+
12592+ _qh->data_toggle = DWC_OTG_HC_PID_DATA0;
12593+ _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
12594+ INIT_LIST_HEAD(&_qh->qtd_list);
12595+ INIT_LIST_HEAD(&_qh->qh_list_entry);
12596+ _qh->channel = NULL;
12597+
12598+ /* FS/LS Enpoint on HS Hub
12599+ * NOT virtual root hub */
12600+ _qh->do_split = 0;
12601+ _qh->speed = _urb->dev->speed;
12602+ if (((_urb->dev->speed == USB_SPEED_LOW) ||
12603+ (_urb->dev->speed == USB_SPEED_FULL)) &&
12604+ (_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) {
12605+ DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
12606+ usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum,
12607+ _urb->dev->ttport);
12608+ _qh->do_split = 1;
12609+ }
12610+
12611+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
12612+ _qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
12613+ /* Compute scheduling parameters once and save them. */
12614+ hprt0_data_t hprt;
12615+
12616+ /** @todo Account for split transfers in the bus time. */
12617+ int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
12618+ _qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed,
12619+ usb_pipein(_urb->pipe),
12620+ (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount));
12621+
12622+ /* Start in a slightly future (micro)frame. */
12623+ _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP);
12624+ _qh->interval = _urb->interval;
12625+#if 0
12626+ /* Increase interrupt polling rate for debugging. */
12627+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
12628+ _qh->interval = 8;
12629+ }
12630+#endif
12631+ hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
12632+ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
12633+ ((_urb->dev->speed == USB_SPEED_LOW) ||
12634+ (_urb->dev->speed == USB_SPEED_FULL)))
12635+ {
12636+ _qh->interval *= 8;
12637+ _qh->sched_frame |= 0x7;
12638+ _qh->start_split_frame = _qh->sched_frame;
12639+ }
12640+ }
12641+
12642+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
12643+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
12644+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
12645+ _urb->dev->devnum);
12646+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
12647+ usb_pipeendpoint(_urb->pipe),
12648+ usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
12649+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n",
12650+ ({ char *speed; switch (_urb->dev->speed) {
12651+ case USB_SPEED_LOW: speed = "low"; break;
12652+ case USB_SPEED_FULL: speed = "full"; break;
12653+ case USB_SPEED_HIGH: speed = "high"; break;
12654+ default: speed = "?"; break;
12655+ }; speed;}));
12656+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",
12657+ ({ char *type; switch (_qh->ep_type) {
12658+ case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break;
12659+ case USB_ENDPOINT_XFER_INT: type = "interrupt"; break;
12660+ case USB_ENDPOINT_XFER_CONTROL: type = "control"; break;
12661+ case USB_ENDPOINT_XFER_BULK: type = "bulk"; break;
12662+ default: type = "?"; break;
12663+ }; type;}));
12664+#ifdef DEBUG
12665+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
12666+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
12667+ _qh->usecs);
12668+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
12669+ _qh->interval);
12670+ }
12671+#endif
12672+
12673+ return;
12674+}
12675+
12676+/**
12677+ * Microframe scheduler
12678+ * track the total use in hcd->frame_usecs
12679+ * keep each qh use in qh->frame_usecs
12680+ * when surrendering the qh then donate the time back
12681+ */
12682+const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
12683+
12684+/*
12685+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init
12686+ */
12687+int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
12688+{
12689+ int i;
12690+ for (i=0; i<8; i++) {
12691+ _hcd->frame_usecs[i] = max_uframe_usecs[i];
12692+ }
12693+ return 0;
12694+}
12695+
12696+static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
12697+{
12698+ int i;
12699+ unsigned short utime;
12700+ int t_left;
12701+ int ret;
12702+ int done;
12703+
12704+ ret = -1;
12705+ utime = _qh->usecs;
12706+ t_left = utime;
12707+ i = 0;
12708+ done = 0;
12709+ while (done == 0) {
12710+ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
12711+ if (utime <= _hcd->frame_usecs[i]) {
12712+ _hcd->frame_usecs[i] -= utime;
12713+ _qh->frame_usecs[i] += utime;
12714+ t_left -= utime;
12715+ ret = i;
12716+ done = 1;
12717+ return ret;
12718+ } else {
12719+ i++;
12720+ if (i == 8) {
12721+ done = 1;
12722+ ret = -1;
12723+ }
12724+ }
12725+ }
12726+ return ret;
12727+}
12728+
12729+/*
12730+ * use this for FS apps that can span multiple uframes
12731+ */
12732+static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
12733+{
12734+ int i;
12735+ int j;
12736+ unsigned short utime;
12737+ int t_left;
12738+ int ret;
12739+ int done;
12740+ unsigned short xtime;
12741+
12742+ ret = -1;
12743+ utime = _qh->usecs;
12744+ t_left = utime;
12745+ i = 0;
12746+ done = 0;
12747+loop:
12748+ while (done == 0) {
12749+ if(_hcd->frame_usecs[i] <= 0) {
12750+ i++;
12751+ if (i == 8) {
12752+ done = 1;
12753+ ret = -1;
12754+ }
12755+ goto loop;
12756+ }
12757+
12758+ /*
12759+ * we need n consequtive slots
12760+ * so use j as a start slot j plus j+1 must be enough time (for now)
12761+ */
12762+ xtime= _hcd->frame_usecs[i];
12763+ for (j = i+1 ; j < 8 ; j++ ) {
12764+ /*
12765+ * if we add this frame remaining time to xtime we may
12766+ * be OK, if not we need to test j for a complete frame
12767+ */
12768+ if ((xtime+_hcd->frame_usecs[j]) < utime) {
12769+ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
12770+ j = 8;
12771+ ret = -1;
12772+ continue;
12773+ }
12774+ }
12775+ if (xtime >= utime) {
12776+ ret = i;
12777+ j = 8; /* stop loop with a good value ret */
12778+ continue;
12779+ }
12780+ /* add the frame time to x time */
12781+ xtime += _hcd->frame_usecs[j];
12782+ /* we must have a fully available next frame or break */
12783+ if ((xtime < utime)
12784+ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
12785+ ret = -1;
12786+ j = 8; /* stop loop with a bad value ret */
12787+ continue;
12788+ }
12789+ }
12790+ if (ret >= 0) {
12791+ t_left = utime;
12792+ for (j = i; (t_left>0) && (j < 8); j++ ) {
12793+ t_left -= _hcd->frame_usecs[j];
12794+ if ( t_left <= 0 ) {
12795+ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
12796+ _hcd->frame_usecs[j]= -t_left;
12797+ ret = i;
12798+ done = 1;
12799+ } else {
12800+ _qh->frame_usecs[j] += _hcd->frame_usecs[j];
12801+ _hcd->frame_usecs[j] = 0;
12802+ }
12803+ }
12804+ } else {
12805+ i++;
12806+ if (i == 8) {
12807+ done = 1;
12808+ ret = -1;
12809+ }
12810+ }
12811+ }
12812+ return ret;
12813+}
12814+
12815+static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
12816+{
12817+ int ret;
12818+ ret = -1;
12819+
12820+ if (_qh->speed == USB_SPEED_HIGH) {
12821+ /* if this is a hs transaction we need a full frame */
12822+ ret = find_single_uframe(_hcd, _qh);
12823+ } else {
12824+ /* if this is a fs transaction we may need a sequence of frames */
12825+ ret = find_multi_uframe(_hcd, _qh);
12826+ }
12827+ return ret;
12828+}
12829+
12830+/**
12831+ * Checks that the max transfer size allowed in a host channel is large enough
12832+ * to handle the maximum data transfer in a single (micro)frame for a periodic
12833+ * transfer.
12834+ *
12835+ * @param _hcd The HCD state structure for the DWC OTG controller.
12836+ * @param _qh QH for a periodic endpoint.
12837+ *
12838+ * @return 0 if successful, negative error code otherwise.
12839+ */
12840+static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
12841+{
12842+ int status;
12843+ uint32_t max_xfer_size;
12844+ uint32_t max_channel_xfer_size;
12845+
12846+ status = 0;
12847+
12848+ max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp);
12849+ max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size;
12850+
12851+ if (max_xfer_size > max_channel_xfer_size) {
12852+ DWC_NOTICE("%s: Periodic xfer length %d > "
12853+ "max xfer length for channel %d\n",
12854+ __func__, max_xfer_size, max_channel_xfer_size);
12855+ status = -ENOSPC;
12856+ }
12857+
12858+ return status;
12859+}
12860+
12861+/**
12862+ * Schedules an interrupt or isochronous transfer in the periodic schedule.
12863+ *
12864+ * @param _hcd The HCD state structure for the DWC OTG controller.
12865+ * @param _qh QH for the periodic transfer. The QH should already contain the
12866+ * scheduling information.
12867+ *
12868+ * @return 0 if successful, negative error code otherwise.
12869+ */
12870+static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
12871+{
12872+ int status = 0;
12873+
12874+ int frame;
12875+ status = find_uframe(_hcd, _qh);
12876+ frame = -1;
12877+ if (status == 0) {
12878+ frame = 7;
12879+ } else {
12880+ if (status > 0 )
12881+ frame = status-1;
12882+ }
12883+
12884+ /* Set the new frame up */
12885+ if (frame > -1) {
12886+ _qh->sched_frame &= ~0x7;
12887+ _qh->sched_frame |= (frame & 7);
12888+ }
12889+
12890+ if (status != -1 )
12891+ status = 0;
12892+ if (status) {
12893+ DWC_NOTICE("%s: Insufficient periodic bandwidth for "
12894+ "periodic transfer.\n", __func__);
12895+ return status;
12896+ }
12897+
12898+ status = check_max_xfer_size(_hcd, _qh);
12899+ if (status) {
12900+ DWC_NOTICE("%s: Channel max transfer size too small "
12901+ "for periodic transfer.\n", __func__);
12902+ return status;
12903+ }
12904+
12905+ /* Always start in the inactive schedule. */
12906+ list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive);
12907+
12908+
12909+ /* Update claimed usecs per (micro)frame. */
12910+ _hcd->periodic_usecs += _qh->usecs;
12911+
12912+ /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
12913+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval;
12914+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
12915+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++;
12916+ DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n",
12917+ _qh, _qh->usecs, _qh->interval);
12918+ } else {
12919+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++;
12920+ DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n",
12921+ _qh, _qh->usecs, _qh->interval);
12922+ }
12923+
12924+ return status;
12925+}
12926+
12927+/**
12928+ * This function adds a QH to either the non periodic or periodic schedule if
12929+ * it is not already in the schedule. If the QH is already in the schedule, no
12930+ * action is taken.
12931+ *
12932+ * @return 0 if successful, negative error code otherwise.
12933+ */
12934+int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
12935+{
12936+ unsigned long flags;
12937+ int status = 0;
12938+
12939+ local_irq_save(flags);
12940+
12941+ if (!list_empty(&_qh->qh_list_entry)) {
12942+ /* QH already in a schedule. */
12943+ goto done;
12944+ }
12945+
12946+ /* Add the new QH to the appropriate schedule */
12947+ if (dwc_qh_is_non_per(_qh)) {
12948+ /* Always start in the inactive schedule. */
12949+ list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive);
12950+ } else {
12951+ status = schedule_periodic(_hcd, _qh);
12952+ }
12953+
12954+ done:
12955+ local_irq_restore(flags);
12956+
12957+ return status;
12958+}
12959+
12960+/**
12961+ * This function adds a QH to the non periodic deferred schedule.
12962+ *
12963+ * @return 0 if successful, negative error code otherwise.
12964+ */
12965+int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
12966+{
12967+ unsigned long flags;
12968+ local_irq_save(flags);
12969+ if (!list_empty(&_qh->qh_list_entry)) {
12970+ /* QH already in a schedule. */
12971+ goto done;
12972+ }
12973+
12974+ /* Add the new QH to the non periodic deferred schedule */
12975+ if (dwc_qh_is_non_per(_qh)) {
12976+ list_add_tail(&_qh->qh_list_entry,
12977+ &_hcd->non_periodic_sched_deferred);
12978+ }
12979+done:
12980+ local_irq_restore(flags);
12981+ return 0;
12982+}
12983+
12984+/**
12985+ * Removes an interrupt or isochronous transfer from the periodic schedule.
12986+ *
12987+ * @param _hcd The HCD state structure for the DWC OTG controller.
12988+ * @param _qh QH for the periodic transfer.
12989+ */
12990+static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
12991+{
12992+ int i;
12993+ list_del_init(&_qh->qh_list_entry);
12994+
12995+
12996+ /* Update claimed usecs per (micro)frame. */
12997+ _hcd->periodic_usecs -= _qh->usecs;
12998+
12999+ for (i = 0; i < 8; i++) {
13000+ _hcd->frame_usecs[i] += _qh->frame_usecs[i];
13001+ _qh->frame_usecs[i] = 0;
13002+ }
13003+ /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */
13004+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval;
13005+
13006+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
13007+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--;
13008+ DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n",
13009+ _qh, _qh->usecs, _qh->interval);
13010+ } else {
13011+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--;
13012+ DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n",
13013+ _qh, _qh->usecs, _qh->interval);
13014+ }
13015+}
13016+
13017+/**
13018+ * Removes a QH from either the non-periodic or periodic schedule. Memory is
13019+ * not freed.
13020+ *
13021+ * @param[in] _hcd The HCD state structure.
13022+ * @param[in] _qh QH to remove from schedule. */
13023+void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
13024+{
13025+ unsigned long flags;
13026+
13027+ local_irq_save(flags);
13028+
13029+ if (list_empty(&_qh->qh_list_entry)) {
13030+ /* QH is not in a schedule. */
13031+ goto done;
13032+ }
13033+
13034+ if (dwc_qh_is_non_per(_qh)) {
13035+ if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) {
13036+ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
13037+ }
13038+ list_del_init(&_qh->qh_list_entry);
13039+ } else {
13040+ deschedule_periodic(_hcd, _qh);
13041+ }
13042+
13043+ done:
13044+ local_irq_restore(flags);
13045+}
13046+
13047+/**
13048+ * Defers a QH. For non-periodic QHs, removes the QH from the active
13049+ * non-periodic schedule. The QH is added to the deferred non-periodic
13050+ * schedule if any QTDs are still attached to the QH.
13051+ */
13052+int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay)
13053+{
13054+ int deact = 1;
13055+ unsigned long flags;
13056+ local_irq_save(flags);
13057+ if (dwc_qh_is_non_per(_qh)) {
13058+ _qh->sched_frame =
13059+ dwc_frame_num_inc(_hcd->frame_number,
13060+ delay);
13061+ _qh->channel = NULL;
13062+ _qh->qtd_in_process = NULL;
13063+ deact = 0;
13064+ dwc_otg_hcd_qh_remove(_hcd, _qh);
13065+ if (!list_empty(&_qh->qtd_list)) {
13066+ /* Add back to deferred non-periodic schedule. */
13067+ dwc_otg_hcd_qh_add_deferred(_hcd, _qh);
13068+ }
13069+ }
13070+ local_irq_restore(flags);
13071+ return deact;
13072+}
13073+
13074+/**
13075+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active
13076+ * non-periodic schedule. The QH is added to the inactive non-periodic
13077+ * schedule if any QTDs are still attached to the QH.
13078+ *
13079+ * For periodic QHs, the QH is removed from the periodic queued schedule. If
13080+ * there are any QTDs still attached to the QH, the QH is added to either the
13081+ * periodic inactive schedule or the periodic ready schedule and its next
13082+ * scheduled frame is calculated. The QH is placed in the ready schedule if
13083+ * the scheduled frame has been reached already. Otherwise it's placed in the
13084+ * inactive schedule. If there are no QTDs attached to the QH, the QH is
13085+ * completely removed from the periodic schedule.
13086+ */
13087+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split)
13088+{
13089+ unsigned long flags;
13090+ local_irq_save(flags);
13091+
13092+ if (dwc_qh_is_non_per(_qh)) {
13093+ dwc_otg_hcd_qh_remove(_hcd, _qh);
13094+ if (!list_empty(&_qh->qtd_list)) {
13095+ /* Add back to inactive non-periodic schedule. */
13096+ dwc_otg_hcd_qh_add(_hcd, _qh);
13097+ }
13098+ } else {
13099+ uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
13100+
13101+ if (_qh->do_split) {
13102+ /* Schedule the next continuing periodic split transfer */
13103+ if (sched_next_periodic_split) {
13104+
13105+ _qh->sched_frame = frame_number;
13106+ if (dwc_frame_num_le(frame_number,
13107+ dwc_frame_num_inc(_qh->start_split_frame, 1))) {
13108+ /*
13109+ * Allow one frame to elapse after start
13110+ * split microframe before scheduling
13111+ * complete split, but DONT if we are
13112+ * doing the next start split in the
13113+ * same frame for an ISOC out.
13114+ */
13115+ if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) {
13116+ _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1);
13117+ }
13118+ }
13119+ } else {
13120+ _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame,
13121+ _qh->interval);
13122+ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
13123+ _qh->sched_frame = frame_number;
13124+ }
13125+ _qh->sched_frame |= 0x7;
13126+ _qh->start_split_frame = _qh->sched_frame;
13127+ }
13128+ } else {
13129+ _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval);
13130+ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
13131+ _qh->sched_frame = frame_number;
13132+ }
13133+ }
13134+
13135+ if (list_empty(&_qh->qtd_list)) {
13136+ dwc_otg_hcd_qh_remove(_hcd, _qh);
13137+ } else {
13138+ /*
13139+ * Remove from periodic_sched_queued and move to
13140+ * appropriate queue.
13141+ */
13142+ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) {
13143+ list_move(&_qh->qh_list_entry,
13144+ &_hcd->periodic_sched_ready);
13145+ } else {
13146+ list_move(&_qh->qh_list_entry,
13147+ &_hcd->periodic_sched_inactive);
13148+ }
13149+ }
13150+ }
13151+
13152+ local_irq_restore(flags);
13153+}
13154+
13155+/**
13156+ * This function allocates and initializes a QTD.
13157+ *
13158+ * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up
13159+ * pointing to each other so each pair should have a unique correlation.
13160+ *
13161+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */
13162+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb)
13163+{
13164+ dwc_otg_qtd_t *qtd;
13165+
13166+ qtd = dwc_otg_hcd_qtd_alloc ();
13167+ if (qtd == NULL) {
13168+ return NULL;
13169+ }
13170+
13171+ dwc_otg_hcd_qtd_init (qtd, _urb);
13172+ return qtd;
13173+}
13174+
13175+/**
13176+ * Initializes a QTD structure.
13177+ *
13178+ * @param[in] _qtd The QTD to initialize.
13179+ * @param[in] _urb The URB to use for initialization. */
13180+void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb)
13181+{
13182+ memset (_qtd, 0, sizeof (dwc_otg_qtd_t));
13183+ _qtd->urb = _urb;
13184+ if (usb_pipecontrol(_urb->pipe)) {
13185+ /*
13186+ * The only time the QTD data toggle is used is on the data
13187+ * phase of control transfers. This phase always starts with
13188+ * DATA1.
13189+ */
13190+ _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
13191+ _qtd->control_phase = DWC_OTG_CONTROL_SETUP;
13192+ }
13193+
13194+ /* start split */
13195+ _qtd->complete_split = 0;
13196+ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
13197+ _qtd->isoc_split_offset = 0;
13198+
13199+ /* Store the qtd ptr in the urb to reference what QTD. */
13200+ _urb->hcpriv = _qtd;
13201+ return;
13202+}
13203+
13204+/**
13205+ * This function adds a QTD to the QTD-list of a QH. It will find the correct
13206+ * QH to place the QTD into. If it does not find a QH, then it will create a
13207+ * new QH. If the QH to which the QTD is added is not currently scheduled, it
13208+ * is placed into the proper schedule based on its EP type.
13209+ *
13210+ * @param[in] _qtd The QTD to add
13211+ * @param[in] _dwc_otg_hcd The DWC HCD structure
13212+ *
13213+ * @return 0 if successful, negative error code otherwise.
13214+ */
13215+int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd)
13216+{
13217+ struct usb_host_endpoint *ep;
13218+ dwc_otg_qh_t *qh;
13219+ unsigned long flags;
13220+ int retval = 0;
13221+ struct urb *urb = _qtd->urb;
13222+
13223+ local_irq_save(flags);
13224+
13225+ /*
13226+ * Get the QH which holds the QTD-list to insert to. Create QH if it
13227+ * doesn't exist.
13228+ */
13229+ ep = dwc_urb_to_endpoint(urb);
13230+ qh = (dwc_otg_qh_t *)ep->hcpriv;
13231+ if (qh == NULL) {
13232+ qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb);
13233+ if (qh == NULL) {
13234+ retval = -1;
13235+ goto done;
13236+ }
13237+ ep->hcpriv = qh;
13238+ }
13239+
13240+ _qtd->qtd_qh_ptr = qh;
13241+ retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh);
13242+ if (retval == 0) {
13243+ list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list);
13244+ }
13245+
13246+ done:
13247+ local_irq_restore(flags);
13248+ return retval;
13249+}
13250+
13251+#endif /* DWC_DEVICE_ONLY */
13252--- /dev/null
13253+++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c
13254@@ -0,0 +1,101 @@
13255+/******************************************************************************
13256+**
13257+** FILE NAME : dwc_otg_ifx.c
13258+** PROJECT : Twinpass/Danube
13259+** MODULES : DWC OTG USB
13260+**
13261+** DATE : 12 Auguest 2007
13262+** AUTHOR : Sung Winder
13263+** DESCRIPTION : Platform specific initialization.
13264+** COPYRIGHT : Copyright (c) 2007
13265+** Infineon Technologies AG
13266+** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
13267+** Hsin-chu City, 300 Taiwan.
13268+**
13269+** This program is free software; you can redistribute it and/or modify
13270+** it under the terms of the GNU General Public License as published by
13271+** the Free Software Foundation; either version 2 of the License, or
13272+** (at your option) any later version.
13273+**
13274+** HISTORY
13275+** $Date $Author $Comment
13276+** 12 Auguest 2007 Sung Winder Initiate Version
13277+*******************************************************************************/
13278+#include "dwc_otg_ifx.h"
13279+
13280+#include <linux/platform_device.h>
13281+#include <linux/kernel.h>
13282+#include <linux/ioport.h>
13283+#include <linux/gpio.h>
13284+
13285+#include <asm/io.h>
13286+//#include <asm/mach-ifxmips/ifxmips.h>
13287+#include <lantiq_soc.h>
13288+
13289+#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
13290+
13291+#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
13292+#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
13293+#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
13294+#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
13295+#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
13296+#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
13297+#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
13298+#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
13299+#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
13300+#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
13301+#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
13302+#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
13303+#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
13304+#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
13305+#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
13306+#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
13307+#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
13308+#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
13309+
13310+
13311+extern void ltq_enable_irq(unsigned int irq_nr);
13312+#define writel ltq_w32
13313+#define readl ltq_r32
13314+void dwc_otg_power_on (void)
13315+{
13316+ // clear power
13317+ writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
13318+ // set clock gating
13319+ writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
13320+ // set power
13321+ writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
13322+ writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);
13323+ writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR);
13324+
13325+#if 1//defined (DWC_HOST_ONLY)
13326+ // make the hardware be a host controller (default)
13327+ //clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
13328+ writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_HDSEL_BIT), DANUBE_RCU_UBSCFG);
13329+
13330+ //#elif defined (DWC_DEVICE_ONLY)
13331+ /* set the controller to the device mode */
13332+ // set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
13333+#else
13334+#error "For Danube/Twinpass, it should be HOST or Device Only."
13335+#endif
13336+
13337+ // set the HC's byte-order to big-endian
13338+ //set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
13339+ writel(readl(DANUBE_RCU_UBSCFG) | (1<<DANUBE_USBCFG_HOST_END_BIT), DANUBE_RCU_UBSCFG);
13340+ //clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
13341+ writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_SLV_END_BIT), DANUBE_RCU_UBSCFG);
13342+ //writel(0x400, DANUBE_RCU_UBSCFG);
13343+
13344+ // PHY configurations.
13345+ writel (0x14014, (volatile unsigned long *)0xbe10103c);
13346+}
13347+
13348+int ifx_usb_hc_init(unsigned long base_addr, int irq)
13349+{
13350+ return 0;
13351+}
13352+
13353+void ifx_usb_hc_remove(void)
13354+{
13355+}
13356--- /dev/null
13357+++ b/drivers/usb/dwc_otg/dwc_otg_ifx.h
13358@@ -0,0 +1,79 @@
13359+/******************************************************************************
13360+**
13361+** FILE NAME : dwc_otg_ifx.h
13362+** PROJECT : Twinpass/Danube
13363+** MODULES : DWC OTG USB
13364+**
13365+** DATE : 12 April 2007
13366+** AUTHOR : Sung Winder
13367+** DESCRIPTION : Platform specific initialization.
13368+** COPYRIGHT : Copyright (c) 2007
13369+** Infineon Technologies AG
13370+** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
13371+** Hsin-chu City, 300 Taiwan.
13372+**
13373+** This program is free software; you can redistribute it and/or modify
13374+** it under the terms of the GNU General Public License as published by
13375+** the Free Software Foundation; either version 2 of the License, or
13376+** (at your option) any later version.
13377+**
13378+** HISTORY
13379+** $Date $Author $Comment
13380+** 12 April 2007 Sung Winder Initiate Version
13381+*******************************************************************************/
13382+#if !defined(__DWC_OTG_IFX_H__)
13383+#define __DWC_OTG_IFX_H__
13384+
13385+#include <irq.h>
13386+
13387+// 20070316, winder added.
13388+#ifndef SZ_256K
13389+#define SZ_256K 0x00040000
13390+#endif
13391+
13392+extern void dwc_otg_power_on (void);
13393+
13394+/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */
13395+// #include <asm/danube/danube.h>
13396+// #include <asm/ifx/irq.h>
13397+
13398+/* winder, I used the Danube parameter as default. *
13399+ * We could change this through module param. */
13400+#define IFX_USB_IOMEM_BASE 0x1e101000
13401+#define IFX_USB_IOMEM_SIZE SZ_256K
13402+#define IFX_USB_IRQ LTQ_USB_INT
13403+
13404+/**
13405+ * This function is called to set correct clock gating and power.
13406+ * For Twinpass/Danube board.
13407+ */
13408+#ifndef DANUBE_RCU_BASE_ADDR
13409+#define DANUBE_RCU_BASE_ADDR (0xBF203000)
13410+#endif
13411+
13412+#ifndef DANUBE_CGU
13413+#define DANUBE_CGU (0xBF103000)
13414+#endif
13415+#ifndef DANUBE_CGU_IFCCR
13416+/***CGU Interface Clock Control Register***/
13417+#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
13418+#endif
13419+
13420+#ifndef DANUBE_PMU
13421+#define DANUBE_PMU (KSEG1+0x1F102000)
13422+#endif
13423+#ifndef DANUBE_PMU_PWDCR
13424+/* PMU Power down Control Register */
13425+#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C))
13426+#endif
13427+
13428+
13429+#define DANUBE_RCU_UBSCFG ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18))
13430+#define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device
13431+#define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end
13432+#define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end
13433+
13434+extern void ltq_mask_and_ack_irq (unsigned int irq_nr);
13435+#define mask_and_ack_ifx_irq ltq_mask_and_ack_irq
13436+
13437+#endif //__DWC_OTG_IFX_H__
13438--- /dev/null
13439+++ b/drivers/usb/dwc_otg/dwc_otg_plat.h
13440@@ -0,0 +1,269 @@
13441+/* ==========================================================================
13442+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/platform/dwc_otg_plat.h $
13443+ * $Revision: 1.1.1.1 $
13444+ * $Date: 2009-04-17 06:15:34 $
13445+ * $Change: 510301 $
13446+ *
13447+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13448+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13449+ * otherwise expressly agreed to in writing between Synopsys and you.
13450+ *
13451+ * The Software IS NOT an item of Licensed Software or Licensed Product under
13452+ * any End User Software License Agreement or Agreement for Licensed Product
13453+ * with Synopsys or any supplement thereto. You are permitted to use and
13454+ * redistribute this Software in source and binary forms, with or without
13455+ * modification, provided that redistributions of source code must retain this
13456+ * notice. You may not view, use, disclose, copy or distribute this file or
13457+ * any information contained herein except pursuant to this license grant from
13458+ * Synopsys. If you do not agree with this notice, including the disclaimer
13459+ * below, then you are not authorized to use the Software.
13460+ *
13461+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13462+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13463+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13464+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13465+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13466+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13467+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13468+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13469+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13470+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13471+ * DAMAGE.
13472+ * ========================================================================== */
13473+
13474+#if !defined(__DWC_OTG_PLAT_H__)
13475+#define __DWC_OTG_PLAT_H__
13476+
13477+#include <linux/types.h>
13478+#include <linux/slab.h>
13479+#include <linux/list.h>
13480+#include <linux/delay.h>
13481+#include <asm/io.h>
13482+
13483+/**
13484+ * @file
13485+ *
13486+ * This file contains the Platform Specific constants, interfaces
13487+ * (functions and macros) for Linux.
13488+ *
13489+ */
13490+/*#if !defined(__LINUX__)
13491+#error "The contents of this file is Linux specific!!!"
13492+#endif
13493+*/
13494+#include <lantiq_soc.h>
13495+#define writel ltq_w32
13496+#define readl ltq_r32
13497+
13498+/**
13499+ * Reads the content of a register.
13500+ *
13501+ * @param _reg address of register to read.
13502+ * @return contents of the register.
13503+ *
13504+
13505+ * Usage:<br>
13506+ * <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code>
13507+ */
13508+static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg)
13509+{
13510+ return readl(_reg);
13511+};
13512+
13513+/**
13514+ * Writes a register with a 32 bit value.
13515+ *
13516+ * @param _reg address of register to read.
13517+ * @param _value to write to _reg.
13518+ *
13519+ * Usage:<br>
13520+ * <code>dwc_write_reg32(&dev_regs->dctl, 0); </code>
13521+ */
13522+static __inline__ void dwc_write_reg32( volatile uint32_t *_reg, const uint32_t _value)
13523+{
13524+ writel( _value, _reg );
13525+};
13526+
13527+/**
13528+ * This function modifies bit values in a register. Using the
13529+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
13530+ *
13531+ * @param _reg address of register to read.
13532+ * @param _clear_mask bit mask to be cleared.
13533+ * @param _set_mask bit mask to be set.
13534+ *
13535+ * Usage:<br>
13536+ * <code> // Clear the SOF Interrupt Mask bit and <br>
13537+ * // set the OTG Interrupt mask bit, leaving all others as they were.
13538+ * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code>
13539+ */
13540+static __inline__
13541+ void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
13542+{
13543+ writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg );
13544+};
13545+
13546+
13547+/**
13548+ * Wrapper for the OS micro-second delay function.
13549+ * @param[in] _usecs Microseconds of delay
13550+ */
13551+static __inline__ void UDELAY( const uint32_t _usecs )
13552+{
13553+ udelay( _usecs );
13554+}
13555+
13556+/**
13557+ * Wrapper for the OS milli-second delay function.
13558+ * @param[in] _msecs milliseconds of delay
13559+ */
13560+static __inline__ void MDELAY( const uint32_t _msecs )
13561+{
13562+ mdelay( _msecs );
13563+}
13564+
13565+/**
13566+ * Wrapper for the Linux spin_lock. On the ARM (Integrator)
13567+ * spin_lock() is a nop.
13568+ *
13569+ * @param _lock Pointer to the spinlock.
13570+ */
13571+static __inline__ void SPIN_LOCK( spinlock_t *_lock )
13572+{
13573+ spin_lock(_lock);
13574+}
13575+
13576+/**
13577+ * Wrapper for the Linux spin_unlock. On the ARM (Integrator)
13578+ * spin_lock() is a nop.
13579+ *
13580+ * @param _lock Pointer to the spinlock.
13581+ */
13582+static __inline__ void SPIN_UNLOCK( spinlock_t *_lock )
13583+{
13584+ spin_unlock(_lock);
13585+}
13586+
13587+/**
13588+ * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM
13589+ * (Integrator) spin_lock() is a nop.
13590+ *
13591+ * @param _l Pointer to the spinlock.
13592+ * @param _f unsigned long for irq flags storage.
13593+ */
13594+#define SPIN_LOCK_IRQSAVE( _l, _f ) { \
13595+ spin_lock_irqsave(_l,_f); \
13596+ }
13597+
13598+/**
13599+ * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM
13600+ * (Integrator) spin_lock() is a nop.
13601+ *
13602+ * @param _l Pointer to the spinlock.
13603+ * @param _f unsigned long for irq flags storage.
13604+ */
13605+#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) {\
13606+ spin_unlock_irqrestore(_l,_f); \
13607+ }
13608+
13609+
13610+/*
13611+ * Debugging support vanishes in non-debug builds.
13612+ */
13613+
13614+
13615+/**
13616+ * The Debug Level bit-mask variable.
13617+ */
13618+extern uint32_t g_dbg_lvl;
13619+/**
13620+ * Set the Debug Level variable.
13621+ */
13622+static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new )
13623+{
13624+ uint32_t old = g_dbg_lvl;
13625+ g_dbg_lvl = _new;
13626+ return old;
13627+}
13628+
13629+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
13630+#define DBG_CIL (0x2)
13631+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
13632+ * messages */
13633+#define DBG_CILV (0x20)
13634+/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
13635+ * messages */
13636+#define DBG_PCD (0x4)
13637+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
13638+ * messages */
13639+#define DBG_PCDV (0x40)
13640+/** When debug level has the DBG_HCD bit set, display Host debug messages */
13641+#define DBG_HCD (0x8)
13642+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
13643+ * messages */
13644+#define DBG_HCDV (0x80)
13645+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
13646+ * mode. */
13647+#define DBG_HCD_URB (0x800)
13648+
13649+/** When debug level has any bit set, display debug messages */
13650+#define DBG_ANY (0xFF)
13651+
13652+/** All debug messages off */
13653+#define DBG_OFF 0
13654+
13655+/** Prefix string for DWC_DEBUG print macros. */
13656+#define USB_DWC "DWC_otg: "
13657+
13658+/**
13659+ * Print a debug message when the Global debug level variable contains
13660+ * the bit defined in <code>lvl</code>.
13661+ *
13662+ * @param[in] lvl - Debug level, use one of the DBG_ constants above.
13663+ * @param[in] x - like printf
13664+ *
13665+ * Example:<p>
13666+ * <code>
13667+ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
13668+ * </code>
13669+ * <br>
13670+ * results in:<br>
13671+ * <code>
13672+ * usb-DWC_otg: dwc_otg_cil_init(ca867000)
13673+ * </code>
13674+ */
13675+#ifdef DEBUG
13676+
13677+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0)
13678+# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
13679+
13680+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
13681+
13682+#else
13683+
13684+# define DWC_DEBUGPL(lvl, x...) do{}while(0)
13685+# define DWC_DEBUGP(x...)
13686+
13687+# define CHK_DEBUG_LEVEL(level) (0)
13688+
13689+#endif /*DEBUG*/
13690+
13691+/**
13692+ * Print an Error message.
13693+ */
13694+#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x )
13695+/**
13696+ * Print a Warning message.
13697+ */
13698+#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x )
13699+/**
13700+ * Print a notice (normal but significant message).
13701+ */
13702+#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x )
13703+/**
13704+ * Basic message printing.
13705+ */
13706+#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x )
13707+
13708+#endif
13709+
13710--- /dev/null
13711+++ b/drivers/usb/dwc_otg/dwc_otg_regs.h
13712@@ -0,0 +1,1797 @@
13713+/* ==========================================================================
13714+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_regs.h $
13715+ * $Revision: 1.1.1.1 $
13716+ * $Date: 2009-04-17 06:15:34 $
13717+ * $Change: 631780 $
13718+ *
13719+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
13720+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
13721+ * otherwise expressly agreed to in writing between Synopsys and you.
13722+ *
13723+ * The Software IS NOT an item of Licensed Software or Licensed Product under
13724+ * any End User Software License Agreement or Agreement for Licensed Product
13725+ * with Synopsys or any supplement thereto. You are permitted to use and
13726+ * redistribute this Software in source and binary forms, with or without
13727+ * modification, provided that redistributions of source code must retain this
13728+ * notice. You may not view, use, disclose, copy or distribute this file or
13729+ * any information contained herein except pursuant to this license grant from
13730+ * Synopsys. If you do not agree with this notice, including the disclaimer
13731+ * below, then you are not authorized to use the Software.
13732+ *
13733+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
13734+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
13735+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
13736+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
13737+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
13738+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
13739+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
13740+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
13741+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
13742+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
13743+ * DAMAGE.
13744+ * ========================================================================== */
13745+
13746+#ifndef __DWC_OTG_REGS_H__
13747+#define __DWC_OTG_REGS_H__
13748+
13749+/**
13750+ * @file
13751+ *
13752+ * This file contains the data structures for accessing the DWC_otg core registers.
13753+ *
13754+ * The application interfaces with the HS OTG core by reading from and
13755+ * writing to the Control and Status Register (CSR) space through the
13756+ * AHB Slave interface. These registers are 32 bits wide, and the
13757+ * addresses are 32-bit-block aligned.
13758+ * CSRs are classified as follows:
13759+ * - Core Global Registers
13760+ * - Device Mode Registers
13761+ * - Device Global Registers
13762+ * - Device Endpoint Specific Registers
13763+ * - Host Mode Registers
13764+ * - Host Global Registers
13765+ * - Host Port CSRs
13766+ * - Host Channel Specific Registers
13767+ *
13768+ * Only the Core Global registers can be accessed in both Device and
13769+ * Host modes. When the HS OTG core is operating in one mode, either
13770+ * Device or Host, the application must not access registers from the
13771+ * other mode. When the core switches from one mode to another, the
13772+ * registers in the new mode of operation must be reprogrammed as they
13773+ * would be after a power-on reset.
13774+ */
13775+
13776+/****************************************************************************/
13777+/** DWC_otg Core registers .
13778+ * The dwc_otg_core_global_regs structure defines the size
13779+ * and relative field offsets for the Core Global registers.
13780+ */
13781+typedef struct dwc_otg_core_global_regs
13782+{
13783+ /** OTG Control and Status Register. <i>Offset: 000h</i> */
13784+ volatile uint32_t gotgctl;
13785+ /** OTG Interrupt Register. <i>Offset: 004h</i> */
13786+ volatile uint32_t gotgint;
13787+ /**Core AHB Configuration Register. <i>Offset: 008h</i> */
13788+ volatile uint32_t gahbcfg;
13789+#define DWC_GLBINTRMASK 0x0001
13790+#define DWC_DMAENABLE 0x0020
13791+#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
13792+#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
13793+#define DWC_PTXEMPTYLVL_EMPTY 0x0100
13794+#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
13795+
13796+
13797+ /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
13798+ volatile uint32_t gusbcfg;
13799+ /**Core Reset Register. <i>Offset: 010h</i> */
13800+ volatile uint32_t grstctl;
13801+ /**Core Interrupt Register. <i>Offset: 014h</i> */
13802+ volatile uint32_t gintsts;
13803+ /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
13804+ volatile uint32_t gintmsk;
13805+ /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
13806+ volatile uint32_t grxstsr;
13807+ /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
13808+ volatile uint32_t grxstsp;
13809+ /**Receive FIFO Size Register. <i>Offset: 024h</i> */
13810+ volatile uint32_t grxfsiz;
13811+ /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
13812+ volatile uint32_t gnptxfsiz;
13813+ /**Non Periodic Transmit FIFO/Queue Status Register (Read
13814+ * Only). <i>Offset: 02Ch</i> */
13815+ volatile uint32_t gnptxsts;
13816+ /**I2C Access Register. <i>Offset: 030h</i> */
13817+ volatile uint32_t gi2cctl;
13818+ /**PHY Vendor Control Register. <i>Offset: 034h</i> */
13819+ volatile uint32_t gpvndctl;
13820+ /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
13821+ volatile uint32_t ggpio;
13822+ /**User ID Register. <i>Offset: 03Ch</i> */
13823+ volatile uint32_t guid;
13824+ /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
13825+ volatile uint32_t gsnpsid;
13826+ /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
13827+ volatile uint32_t ghwcfg1;
13828+ /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
13829+ volatile uint32_t ghwcfg2;
13830+#define DWC_SLAVE_ONLY_ARCH 0
13831+#define DWC_EXT_DMA_ARCH 1
13832+#define DWC_INT_DMA_ARCH 2
13833+
13834+#define DWC_MODE_HNP_SRP_CAPABLE 0
13835+#define DWC_MODE_SRP_ONLY_CAPABLE 1
13836+#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
13837+#define DWC_MODE_SRP_CAPABLE_DEVICE 3
13838+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
13839+#define DWC_MODE_SRP_CAPABLE_HOST 5
13840+#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
13841+
13842+ /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
13843+ volatile uint32_t ghwcfg3;
13844+ /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
13845+ volatile uint32_t ghwcfg4;
13846+ /** Reserved <i>Offset: 054h-0FFh</i> */
13847+ uint32_t reserved[43];
13848+ /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
13849+ volatile uint32_t hptxfsiz;
13850+ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
13851+ otherwise Device Transmit FIFO#n Register.
13852+ * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
13853+ //volatile uint32_t dptxfsiz[15];
13854+ volatile uint32_t dptxfsiz_dieptxf[15];
13855+} dwc_otg_core_global_regs_t;
13856+
13857+/**
13858+ * This union represents the bit fields of the Core OTG Control
13859+ * and Status Register (GOTGCTL). Set the bits using the bit
13860+ * fields then write the <i>d32</i> value to the register.
13861+ */
13862+typedef union gotgctl_data
13863+{
13864+ /** raw register data */
13865+ uint32_t d32;
13866+ /** register bits */
13867+ struct
13868+ {
13869+ unsigned reserved31_21 : 11;
13870+ unsigned currmod : 1;
13871+ unsigned bsesvld : 1;
13872+ unsigned asesvld : 1;
13873+ unsigned reserved17 : 1;
13874+ unsigned conidsts : 1;
13875+ unsigned reserved15_12 : 4;
13876+ unsigned devhnpen : 1;
13877+ unsigned hstsethnpen : 1;
13878+ unsigned hnpreq : 1;
13879+ unsigned hstnegscs : 1;
13880+ unsigned reserved7_2 : 6;
13881+ unsigned sesreq : 1;
13882+ unsigned sesreqscs : 1;
13883+ } b;
13884+} gotgctl_data_t;
13885+
13886+/**
13887+ * This union represents the bit fields of the Core OTG Interrupt Register
13888+ * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
13889+ * value to the register.
13890+ */
13891+typedef union gotgint_data
13892+{
13893+ /** raw register data */
13894+ uint32_t d32;
13895+ /** register bits */
13896+ struct
13897+ {
13898+ /** Current Mode */
13899+ unsigned reserved31_20 : 12;
13900+ /** Debounce Done */
13901+ unsigned debdone : 1;
13902+ /** A-Device Timeout Change */
13903+ unsigned adevtoutchng : 1;
13904+ /** Host Negotiation Detected */
13905+ unsigned hstnegdet : 1;
13906+ unsigned reserver16_10 : 7;
13907+ /** Host Negotiation Success Status Change */
13908+ unsigned hstnegsucstschng : 1;
13909+ /** Session Request Success Status Change */
13910+ unsigned sesreqsucstschng : 1;
13911+ unsigned reserved3_7 : 5;
13912+ /** Session End Detected */
13913+ unsigned sesenddet : 1;
13914+ /** Current Mode */
13915+ unsigned reserved1_0 : 2;
13916+ } b;
13917+} gotgint_data_t;
13918+
13919+
13920+/**
13921+ * This union represents the bit fields of the Core AHB Configuration
13922+ * Register (GAHBCFG). Set/clear the bits using the bit fields then
13923+ * write the <i>d32</i> value to the register.
13924+ */
13925+typedef union gahbcfg_data
13926+{
13927+ /** raw register data */
13928+ uint32_t d32;
13929+ /** register bits */
13930+ struct
13931+ {
13932+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
13933+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
13934+ unsigned reserved9_31 : 23;
13935+ unsigned ptxfemplvl : 1;
13936+ unsigned nptxfemplvl_txfemplvl : 1;
13937+#define DWC_GAHBCFG_DMAENABLE 1
13938+ unsigned reserved : 1;
13939+ unsigned dmaenable : 1;
13940+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
13941+#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
13942+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
13943+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
13944+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
13945+ unsigned hburstlen : 4;
13946+ unsigned glblintrmsk : 1;
13947+#define DWC_GAHBCFG_GLBINT_ENABLE 1
13948+
13949+ } b;
13950+} gahbcfg_data_t;
13951+
13952+/**
13953+ * This union represents the bit fields of the Core USB Configuration
13954+ * Register (GUSBCFG). Set the bits using the bit fields then write
13955+ * the <i>d32</i> value to the register.
13956+ */
13957+typedef union gusbcfg_data
13958+{
13959+ /** raw register data */
13960+ uint32_t d32;
13961+ /** register bits */
13962+ struct
13963+ {
13964+ unsigned corrupt_tx_packet: 1; /*fscz*/
13965+ unsigned force_device_mode: 1;
13966+ unsigned force_host_mode: 1;
13967+ unsigned reserved23_28 : 6;
13968+ unsigned term_sel_dl_pulse : 1;
13969+ unsigned ulpi_int_vbus_indicator : 1;
13970+ unsigned ulpi_ext_vbus_drv : 1;
13971+ unsigned ulpi_clk_sus_m : 1;
13972+ unsigned ulpi_auto_res : 1;
13973+ unsigned ulpi_fsls : 1;
13974+ unsigned otgutmifssel : 1;
13975+ unsigned phylpwrclksel : 1;
13976+ unsigned nptxfrwnden : 1;
13977+ unsigned usbtrdtim : 4;
13978+ unsigned hnpcap : 1;
13979+ unsigned srpcap : 1;
13980+ unsigned ddrsel : 1;
13981+ unsigned physel : 1;
13982+ unsigned fsintf : 1;
13983+ unsigned ulpi_utmi_sel : 1;
13984+ unsigned phyif : 1;
13985+ unsigned toutcal : 3;
13986+ } b;
13987+} gusbcfg_data_t;
13988+
13989+/**
13990+ * This union represents the bit fields of the Core Reset Register
13991+ * (GRSTCTL). Set/clear the bits using the bit fields then write the
13992+ * <i>d32</i> value to the register.
13993+ */
13994+typedef union grstctl_data
13995+{
13996+ /** raw register data */
13997+ uint32_t d32;
13998+ /** register bits */
13999+ struct
14000+ {
14001+ /** AHB Master Idle. Indicates the AHB Master State
14002+ * Machine is in IDLE condition. */
14003+ unsigned ahbidle : 1;
14004+ /** DMA Request Signal. Indicated DMA request is in
14005+ * probress. Used for debug purpose. */
14006+ unsigned dmareq : 1;
14007+ /** Reserved */
14008+ unsigned reserved29_11 : 19;
14009+ /** TxFIFO Number (TxFNum) (Device and Host).
14010+ *
14011+ * This is the FIFO number which needs to be flushed,
14012+ * using the TxFIFO Flush bit. This field should not
14013+ * be changed until the TxFIFO Flush bit is cleared by
14014+ * the core.
14015+ * - 0x0 : Non Periodic TxFIFO Flush
14016+ * - 0x1 : Periodic TxFIFO #1 Flush in device mode
14017+ * or Periodic TxFIFO in host mode
14018+ * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
14019+ * - ...
14020+ * - 0xF : Periodic TxFIFO #15 Flush in device mode
14021+ * - 0x10: Flush all the Transmit NonPeriodic and
14022+ * Transmit Periodic FIFOs in the core
14023+ */
14024+ unsigned txfnum : 5;
14025+ /** TxFIFO Flush (TxFFlsh) (Device and Host).
14026+ *
14027+ * This bit is used to selectively flush a single or
14028+ * all transmit FIFOs. The application must first
14029+ * ensure that the core is not in the middle of a
14030+ * transaction. <p>The application should write into
14031+ * this bit, only after making sure that neither the
14032+ * DMA engine is writing into the TxFIFO nor the MAC
14033+ * is reading the data out of the FIFO. <p>The
14034+ * application should wait until the core clears this
14035+ * bit, before performing any operations. This bit
14036+ * will takes 8 clocks (slowest of PHY or AHB clock)
14037+ * to clear.
14038+ */
14039+ unsigned txfflsh : 1;
14040+ /** RxFIFO Flush (RxFFlsh) (Device and Host)
14041+ *
14042+ * The application can flush the entire Receive FIFO
14043+ * using this bit. <p>The application must first
14044+ * ensure that the core is not in the middle of a
14045+ * transaction. <p>The application should write into
14046+ * this bit, only after making sure that neither the
14047+ * DMA engine is reading from the RxFIFO nor the MAC
14048+ * is writing the data in to the FIFO. <p>The
14049+ * application should wait until the bit is cleared
14050+ * before performing any other operations. This bit
14051+ * will takes 8 clocks (slowest of PHY or AHB clock)
14052+ * to clear.
14053+ */
14054+ unsigned rxfflsh : 1;
14055+ /** In Token Sequence Learning Queue Flush
14056+ * (INTknQFlsh) (Device Only)
14057+ */
14058+ unsigned intknqflsh : 1;
14059+ /** Host Frame Counter Reset (Host Only)<br>
14060+ *
14061+ * The application can reset the (micro)frame number
14062+ * counter inside the core, using this bit. When the
14063+ * (micro)frame counter is reset, the subsequent SOF
14064+ * sent out by the core, will have a (micro)frame
14065+ * number of 0.
14066+ */
14067+ unsigned hstfrm : 1;
14068+ /** Hclk Soft Reset
14069+ *
14070+ * The application uses this bit to reset the control logic in
14071+ * the AHB clock domain. Only AHB clock domain pipelines are
14072+ * reset.
14073+ */
14074+ unsigned hsftrst : 1;
14075+ /** Core Soft Reset (CSftRst) (Device and Host)
14076+ *
14077+ * The application can flush the control logic in the
14078+ * entire core using this bit. This bit resets the
14079+ * pipelines in the AHB Clock domain as well as the
14080+ * PHY Clock domain.
14081+ *
14082+ * The state machines are reset to an IDLE state, the
14083+ * control bits in the CSRs are cleared, all the
14084+ * transmit FIFOs and the receive FIFO are flushed.
14085+ *
14086+ * The status mask bits that control the generation of
14087+ * the interrupt, are cleared, to clear the
14088+ * interrupt. The interrupt status bits are not
14089+ * cleared, so the application can get the status of
14090+ * any events that occurred in the core after it has
14091+ * set this bit.
14092+ *
14093+ * Any transactions on the AHB are terminated as soon
14094+ * as possible following the protocol. Any
14095+ * transactions on the USB are terminated immediately.
14096+ *
14097+ * The configuration settings in the CSRs are
14098+ * unchanged, so the software doesn't have to
14099+ * reprogram these registers (Device
14100+ * Configuration/Host Configuration/Core System
14101+ * Configuration/Core PHY Configuration).
14102+ *
14103+ * The application can write to this bit, any time it
14104+ * wants to reset the core. This is a self clearing
14105+ * bit and the core clears this bit after all the
14106+ * necessary logic is reset in the core, which may
14107+ * take several clocks, depending on the current state
14108+ * of the core.
14109+ */
14110+ unsigned csftrst : 1;
14111+ } b;
14112+} grstctl_t;
14113+
14114+
14115+/**
14116+ * This union represents the bit fields of the Core Interrupt Mask
14117+ * Register (GINTMSK). Set/clear the bits using the bit fields then
14118+ * write the <i>d32</i> value to the register.
14119+ */
14120+typedef union gintmsk_data
14121+{
14122+ /** raw register data */
14123+ uint32_t d32;
14124+ /** register bits */
14125+ struct
14126+ {
14127+ unsigned wkupintr : 1;
14128+ unsigned sessreqintr : 1;
14129+ unsigned disconnect : 1;
14130+ unsigned conidstschng : 1;
14131+ unsigned reserved27 : 1;
14132+ unsigned ptxfempty : 1;
14133+ unsigned hcintr : 1;
14134+ unsigned portintr : 1;
14135+ unsigned reserved22_23 : 2;
14136+ unsigned incomplisoout : 1;
14137+ unsigned incomplisoin : 1;
14138+ unsigned outepintr : 1;
14139+ unsigned inepintr : 1;
14140+ unsigned epmismatch : 1;
14141+ unsigned reserved16 : 1;
14142+ unsigned eopframe : 1;
14143+ unsigned isooutdrop : 1;
14144+ unsigned enumdone : 1;
14145+ unsigned usbreset : 1;
14146+ unsigned usbsuspend : 1;
14147+ unsigned erlysuspend : 1;
14148+ unsigned i2cintr : 1;
14149+ unsigned reserved8 : 1;
14150+ unsigned goutnakeff : 1;
14151+ unsigned ginnakeff : 1;
14152+ unsigned nptxfempty : 1;
14153+ unsigned rxstsqlvl : 1;
14154+ unsigned sofintr : 1;
14155+ unsigned otgintr : 1;
14156+ unsigned modemismatch : 1;
14157+ unsigned reserved0 : 1;
14158+ } b;
14159+} gintmsk_data_t;
14160+/**
14161+ * This union represents the bit fields of the Core Interrupt Register
14162+ * (GINTSTS). Set/clear the bits using the bit fields then write the
14163+ * <i>d32</i> value to the register.
14164+ */
14165+typedef union gintsts_data
14166+{
14167+ /** raw register data */
14168+ uint32_t d32;
14169+#define DWC_SOF_INTR_MASK 0x0008
14170+ /** register bits */
14171+ struct
14172+ {
14173+#define DWC_HOST_MODE 1
14174+ unsigned wkupintr : 1;
14175+ unsigned sessreqintr : 1;
14176+ unsigned disconnect : 1;
14177+ unsigned conidstschng : 1;
14178+ unsigned reserved27 : 1;
14179+ unsigned ptxfempty : 1;
14180+ unsigned hcintr : 1;
14181+ unsigned portintr : 1;
14182+ unsigned reserved22_23 : 2;
14183+ unsigned incomplisoout : 1;
14184+ unsigned incomplisoin : 1;
14185+ unsigned outepintr : 1;
14186+ unsigned inepint: 1;
14187+ unsigned epmismatch : 1;
14188+ unsigned intokenrx : 1;
14189+ unsigned eopframe : 1;
14190+ unsigned isooutdrop : 1;
14191+ unsigned enumdone : 1;
14192+ unsigned usbreset : 1;
14193+ unsigned usbsuspend : 1;
14194+ unsigned erlysuspend : 1;
14195+ unsigned i2cintr : 1;
14196+ unsigned reserved8 : 1;
14197+ unsigned goutnakeff : 1;
14198+ unsigned ginnakeff : 1;
14199+ unsigned nptxfempty : 1;
14200+ unsigned rxstsqlvl : 1;
14201+ unsigned sofintr : 1;
14202+ unsigned otgintr : 1;
14203+ unsigned modemismatch : 1;
14204+ unsigned curmode : 1;
14205+ } b;
14206+} gintsts_data_t;
14207+
14208+
14209+/**
14210+ * This union represents the bit fields in the Device Receive Status Read and
14211+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
14212+ * element then read out the bits using the <i>b</i>it elements.
14213+ */
14214+typedef union device_grxsts_data {
14215+ /** raw register data */
14216+ uint32_t d32;
14217+ /** register bits */
14218+ struct {
14219+ unsigned reserved : 7;
14220+ unsigned fn : 4;
14221+#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
14222+#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
14223+
14224+#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
14225+#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
14226+#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
14227+ unsigned pktsts : 4;
14228+ unsigned dpid : 2;
14229+ unsigned bcnt : 11;
14230+ unsigned epnum : 4;
14231+ } b;
14232+} device_grxsts_data_t;
14233+
14234+/**
14235+ * This union represents the bit fields in the Host Receive Status Read and
14236+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
14237+ * element then read out the bits using the <i>b</i>it elements.
14238+ */
14239+typedef union host_grxsts_data {
14240+ /** raw register data */
14241+ uint32_t d32;
14242+ /** register bits */
14243+ struct {
14244+ unsigned reserved31_21 : 11;
14245+#define DWC_GRXSTS_PKTSTS_IN 0x2
14246+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
14247+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
14248+#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
14249+ unsigned pktsts : 4;
14250+ unsigned dpid : 2;
14251+ unsigned bcnt : 11;
14252+ unsigned chnum : 4;
14253+ } b;
14254+} host_grxsts_data_t;
14255+
14256+/**
14257+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
14258+ * GNPTXFSIZ, DPTXFSIZn). Read the register into the <i>d32</i> element then
14259+ * read out the bits using the <i>b</i>it elements.
14260+ */
14261+typedef union fifosize_data {
14262+ /** raw register data */
14263+ uint32_t d32;
14264+ /** register bits */
14265+ struct {
14266+ unsigned depth : 16;
14267+ unsigned startaddr : 16;
14268+ } b;
14269+} fifosize_data_t;
14270+
14271+/**
14272+ * This union represents the bit fields in the Non-Periodic Transmit
14273+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
14274+ * <i>d32</i> element then read out the bits using the <i>b</i>it
14275+ * elements.
14276+ */
14277+typedef union gnptxsts_data {
14278+ /** raw register data */
14279+ uint32_t d32;
14280+ /** register bits */
14281+ struct {
14282+ unsigned reserved : 1;
14283+ /** Top of the Non-Periodic Transmit Request Queue
14284+ * - bits 30:27 - Channel/EP Number
14285+ * - bits 26:25 - Token Type
14286+ * - bit 24 - Terminate (Last entry for the selected
14287+ * channel/EP)
14288+ * - 2'b00 - IN/OUT
14289+ * - 2'b01 - Zero Length OUT
14290+ * - 2'b10 - PING/Complete Split
14291+ * - 2'b11 - Channel Halt
14292+
14293+ */
14294+ unsigned nptxqtop_chnep : 4;
14295+ unsigned nptxqtop_token : 2;
14296+ unsigned nptxqtop_terminate : 1;
14297+ unsigned nptxqspcavail : 8;
14298+ unsigned nptxfspcavail : 16;
14299+ } b;
14300+} gnptxsts_data_t;
14301+
14302+/**
14303+ * This union represents the bit fields in the Transmit
14304+ * FIFO Status Register (DTXFSTS). Read the register into the
14305+ * <i>d32</i> element then read out the bits using the <i>b</i>it
14306+ * elements.
14307+ */
14308+typedef union dtxfsts_data /* fscz */ //*
14309+{
14310+ /** raw register data */
14311+ uint32_t d32;
14312+ /** register bits */
14313+ struct {
14314+ unsigned reserved : 16;
14315+ unsigned txfspcavail : 16;
14316+ } b;
14317+} dtxfsts_data_t;
14318+
14319+/**
14320+ * This union represents the bit fields in the I2C Control Register
14321+ * (I2CCTL). Read the register into the <i>d32</i> element then read out the
14322+ * bits using the <i>b</i>it elements.
14323+ */
14324+typedef union gi2cctl_data {
14325+ /** raw register data */
14326+ uint32_t d32;
14327+ /** register bits */
14328+ struct {
14329+ unsigned bsydne : 1;
14330+ unsigned rw : 1;
14331+ unsigned reserved : 2;
14332+ unsigned i2cdevaddr : 2;
14333+ unsigned i2csuspctl : 1;
14334+ unsigned ack : 1;
14335+ unsigned i2cen : 1;
14336+ unsigned addr : 7;
14337+ unsigned regaddr : 8;
14338+ unsigned rwdata : 8;
14339+ } b;
14340+} gi2cctl_data_t;
14341+
14342+/**
14343+ * This union represents the bit fields in the User HW Config1
14344+ * Register. Read the register into the <i>d32</i> element then read
14345+ * out the bits using the <i>b</i>it elements.
14346+ */
14347+typedef union hwcfg1_data {
14348+ /** raw register data */
14349+ uint32_t d32;
14350+ /** register bits */
14351+ struct {
14352+ unsigned ep_dir15 : 2;
14353+ unsigned ep_dir14 : 2;
14354+ unsigned ep_dir13 : 2;
14355+ unsigned ep_dir12 : 2;
14356+ unsigned ep_dir11 : 2;
14357+ unsigned ep_dir10 : 2;
14358+ unsigned ep_dir9 : 2;
14359+ unsigned ep_dir8 : 2;
14360+ unsigned ep_dir7 : 2;
14361+ unsigned ep_dir6 : 2;
14362+ unsigned ep_dir5 : 2;
14363+ unsigned ep_dir4 : 2;
14364+ unsigned ep_dir3 : 2;
14365+ unsigned ep_dir2 : 2;
14366+ unsigned ep_dir1 : 2;
14367+ unsigned ep_dir0 : 2;
14368+ } b;
14369+} hwcfg1_data_t;
14370+
14371+/**
14372+ * This union represents the bit fields in the User HW Config2
14373+ * Register. Read the register into the <i>d32</i> element then read
14374+ * out the bits using the <i>b</i>it elements.
14375+ */
14376+typedef union hwcfg2_data
14377+{
14378+ /** raw register data */
14379+ uint32_t d32;
14380+ /** register bits */
14381+ struct {
14382+ /* GHWCFG2 */
14383+ unsigned reserved31 : 1;
14384+ unsigned dev_token_q_depth : 5;
14385+ unsigned host_perio_tx_q_depth : 2;
14386+ unsigned nonperio_tx_q_depth : 2;
14387+ unsigned rx_status_q_depth : 2;
14388+ unsigned dynamic_fifo : 1;
14389+ unsigned perio_ep_supported : 1;
14390+ unsigned num_host_chan : 4;
14391+ unsigned num_dev_ep : 4;
14392+ unsigned fs_phy_type : 2;
14393+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
14394+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
14395+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
14396+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
14397+ unsigned hs_phy_type : 2;
14398+ unsigned point2point : 1;
14399+ unsigned architecture : 2;
14400+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
14401+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
14402+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
14403+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
14404+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
14405+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
14406+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
14407+ unsigned op_mode : 3;
14408+ } b;
14409+} hwcfg2_data_t;
14410+
14411+/**
14412+ * This union represents the bit fields in the User HW Config3
14413+ * Register. Read the register into the <i>d32</i> element then read
14414+ * out the bits using the <i>b</i>it elements.
14415+ */
14416+typedef union hwcfg3_data
14417+{
14418+ /** raw register data */
14419+ uint32_t d32;
14420+ /** register bits */
14421+ struct {
14422+ /* GHWCFG3 */
14423+ unsigned dfifo_depth : 16;
14424+ unsigned reserved15_13 : 3;
14425+ unsigned ahb_phy_clock_synch : 1;
14426+ unsigned synch_reset_type : 1;
14427+ unsigned optional_features : 1;
14428+ unsigned vendor_ctrl_if : 1;
14429+ unsigned i2c : 1;
14430+ unsigned otg_func : 1;
14431+ unsigned packet_size_cntr_width : 3;
14432+ unsigned xfer_size_cntr_width : 4;
14433+ } b;
14434+} hwcfg3_data_t;
14435+
14436+/**
14437+ * This union represents the bit fields in the User HW Config4
14438+ * Register. Read the register into the <i>d32</i> element then read
14439+ * out the bits using the <i>b</i>it elements.
14440+ */
14441+typedef union hwcfg4_data
14442+{
14443+ /** raw register data */
14444+ uint32_t d32;
14445+ /** register bits */
14446+ struct {
14447+unsigned reserved31_30 : 2; /* fscz */
14448+ unsigned num_in_eps : 4;
14449+ unsigned ded_fifo_en : 1;
14450+
14451+ unsigned session_end_filt_en : 1;
14452+ unsigned b_valid_filt_en : 1;
14453+ unsigned a_valid_filt_en : 1;
14454+ unsigned vbus_valid_filt_en : 1;
14455+ unsigned iddig_filt_en : 1;
14456+ unsigned num_dev_mode_ctrl_ep : 4;
14457+ unsigned utmi_phy_data_width : 2;
14458+ unsigned min_ahb_freq : 9;
14459+ unsigned power_optimiz : 1;
14460+ unsigned num_dev_perio_in_ep : 4;
14461+ } b;
14462+} hwcfg4_data_t;
14463+
14464+////////////////////////////////////////////
14465+// Device Registers
14466+/**
14467+ * Device Global Registers. <i>Offsets 800h-BFFh</i>
14468+ *
14469+ * The following structures define the size and relative field offsets
14470+ * for the Device Mode Registers.
14471+ *
14472+ * <i>These registers are visible only in Device mode and must not be
14473+ * accessed in Host mode, as the results are unknown.</i>
14474+ */
14475+typedef struct dwc_otg_dev_global_regs
14476+{
14477+ /** Device Configuration Register. <i>Offset 800h</i> */
14478+ volatile uint32_t dcfg;
14479+ /** Device Control Register. <i>Offset: 804h</i> */
14480+ volatile uint32_t dctl;
14481+ /** Device Status Register (Read Only). <i>Offset: 808h</i> */
14482+ volatile uint32_t dsts;
14483+ /** Reserved. <i>Offset: 80Ch</i> */
14484+ uint32_t unused;
14485+ /** Device IN Endpoint Common Interrupt Mask
14486+ * Register. <i>Offset: 810h</i> */
14487+ volatile uint32_t diepmsk;
14488+ /** Device OUT Endpoint Common Interrupt Mask
14489+ * Register. <i>Offset: 814h</i> */
14490+ volatile uint32_t doepmsk;
14491+ /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
14492+ volatile uint32_t daint;
14493+ /** Device All Endpoints Interrupt Mask Register. <i>Offset:
14494+ * 81Ch</i> */
14495+ volatile uint32_t daintmsk;
14496+ /** Device IN Token Queue Read Register-1 (Read Only).
14497+ * <i>Offset: 820h</i> */
14498+ volatile uint32_t dtknqr1;
14499+ /** Device IN Token Queue Read Register-2 (Read Only).
14500+ * <i>Offset: 824h</i> */
14501+ volatile uint32_t dtknqr2;
14502+ /** Device VBUS discharge Register. <i>Offset: 828h</i> */
14503+ volatile uint32_t dvbusdis;
14504+ /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
14505+ volatile uint32_t dvbuspulse;
14506+ /** Device IN Token Queue Read Register-3 (Read Only).
14507+ * Device Thresholding control register (Read/Write)
14508+ * <i>Offset: 830h</i> */
14509+ volatile uint32_t dtknqr3_dthrctl;
14510+ /** Device IN Token Queue Read Register-4 (Read Only). /
14511+ * Device IN EPs empty Inr. Mask Register (Read/Write)
14512+ * <i>Offset: 834h</i> */
14513+ volatile uint32_t dtknqr4_fifoemptymsk;
14514+} dwc_otg_device_global_regs_t;
14515+
14516+/**
14517+ * This union represents the bit fields in the Device Configuration
14518+ * Register. Read the register into the <i>d32</i> member then
14519+ * set/clear the bits using the <i>b</i>it elements. Write the
14520+ * <i>d32</i> member to the dcfg register.
14521+ */
14522+typedef union dcfg_data
14523+{
14524+ /** raw register data */
14525+ uint32_t d32;
14526+ /** register bits */
14527+ struct {
14528+ unsigned reserved31_23 : 9;
14529+ /** In Endpoint Mis-match count */
14530+ unsigned epmscnt : 5;
14531+ unsigned reserved13_17 : 5;
14532+ /** Periodic Frame Interval */
14533+#define DWC_DCFG_FRAME_INTERVAL_80 0
14534+#define DWC_DCFG_FRAME_INTERVAL_85 1
14535+#define DWC_DCFG_FRAME_INTERVAL_90 2
14536+#define DWC_DCFG_FRAME_INTERVAL_95 3
14537+ unsigned perfrint : 2;
14538+ /** Device Addresses */
14539+ unsigned devaddr : 7;
14540+ unsigned reserved3 : 1;
14541+ /** Non Zero Length Status OUT Handshake */
14542+#define DWC_DCFG_SEND_STALL 1
14543+ unsigned nzstsouthshk : 1;
14544+ /** Device Speed */
14545+ unsigned devspd : 2;
14546+ } b;
14547+} dcfg_data_t;
14548+
14549+/**
14550+ * This union represents the bit fields in the Device Control
14551+ * Register. Read the register into the <i>d32</i> member then
14552+ * set/clear the bits using the <i>b</i>it elements.
14553+ */
14554+typedef union dctl_data
14555+{
14556+ /** raw register data */
14557+ uint32_t d32;
14558+ /** register bits */
14559+ struct {
14560+ unsigned reserved : 20;
14561+ /** Power-On Programming Done */
14562+ unsigned pwronprgdone : 1;
14563+ /** Clear Global OUT NAK */
14564+ unsigned cgoutnak : 1;
14565+ /** Set Global OUT NAK */
14566+ unsigned sgoutnak : 1;
14567+ /** Clear Global Non-Periodic IN NAK */
14568+ unsigned cgnpinnak : 1;
14569+ /** Set Global Non-Periodic IN NAK */
14570+ unsigned sgnpinnak : 1;
14571+ /** Test Control */
14572+ unsigned tstctl : 3;
14573+ /** Global OUT NAK Status */
14574+ unsigned goutnaksts : 1;
14575+ /** Global Non-Periodic IN NAK Status */
14576+ unsigned gnpinnaksts : 1;
14577+ /** Soft Disconnect */
14578+ unsigned sftdiscon : 1;
14579+ /** Remote Wakeup */
14580+ unsigned rmtwkupsig : 1;
14581+ } b;
14582+} dctl_data_t;
14583+
14584+/**
14585+ * This union represents the bit fields in the Device Status
14586+ * Register. Read the register into the <i>d32</i> member then
14587+ * set/clear the bits using the <i>b</i>it elements.
14588+ */
14589+typedef union dsts_data
14590+{
14591+ /** raw register data */
14592+ uint32_t d32;
14593+ /** register bits */
14594+ struct {
14595+ unsigned reserved22_31 : 10;
14596+ /** Frame or Microframe Number of the received SOF */
14597+ unsigned soffn : 14;
14598+ unsigned reserved4_7: 4;
14599+ /** Erratic Error */
14600+ unsigned errticerr : 1;
14601+ /** Enumerated Speed */
14602+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
14603+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
14604+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
14605+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
14606+ unsigned enumspd : 2;
14607+ /** Suspend Status */
14608+ unsigned suspsts : 1;
14609+ } b;
14610+} dsts_data_t;
14611+
14612+
14613+/**
14614+ * This union represents the bit fields in the Device IN EP Interrupt
14615+ * Register and the Device IN EP Common Mask Register.
14616+ *
14617+ * - Read the register into the <i>d32</i> member then set/clear the
14618+ * bits using the <i>b</i>it elements.
14619+ */
14620+typedef union diepint_data
14621+{
14622+ /** raw register data */
14623+ uint32_t d32;
14624+ /** register bits */
14625+ struct {
14626+ unsigned reserved07_31 : 23;
14627+ unsigned txfifoundrn : 1;
14628+ /** IN Endpoint HAK Effective mask */
14629+ unsigned emptyintr : 1;
14630+ /** IN Endpoint NAK Effective mask */
14631+ unsigned inepnakeff : 1;
14632+ /** IN Token Received with EP mismatch mask */
14633+ unsigned intknepmis : 1;
14634+ /** IN Token received with TxF Empty mask */
14635+ unsigned intktxfemp : 1;
14636+ /** TimeOUT Handshake mask (non-ISOC EPs) */
14637+ unsigned timeout : 1;
14638+ /** AHB Error mask */
14639+ unsigned ahberr : 1;
14640+ /** Endpoint disable mask */
14641+ unsigned epdisabled : 1;
14642+ /** Transfer complete mask */
14643+ unsigned xfercompl : 1;
14644+ } b;
14645+} diepint_data_t;
14646+/**
14647+ * This union represents the bit fields in the Device IN EP Common
14648+ * Interrupt Mask Register.
14649+ */
14650+typedef union diepint_data diepmsk_data_t;
14651+
14652+/**
14653+ * This union represents the bit fields in the Device OUT EP Interrupt
14654+ * Registerand Device OUT EP Common Interrupt Mask Register.
14655+ *
14656+ * - Read the register into the <i>d32</i> member then set/clear the
14657+ * bits using the <i>b</i>it elements.
14658+ */
14659+typedef union doepint_data
14660+{
14661+ /** raw register data */
14662+ uint32_t d32;
14663+ /** register bits */
14664+ struct {
14665+ unsigned reserved04_31 : 27;
14666+ /** OUT Token Received when Endpoint Disabled */
14667+ unsigned outtknepdis : 1;
14668+ /** Setup Phase Done (contorl EPs) */
14669+ unsigned setup : 1;
14670+ /** AHB Error */
14671+ unsigned ahberr : 1;
14672+ /** Endpoint disable */
14673+ unsigned epdisabled : 1;
14674+ /** Transfer complete */
14675+ unsigned xfercompl : 1;
14676+ } b;
14677+} doepint_data_t;
14678+/**
14679+ * This union represents the bit fields in the Device OUT EP Common
14680+ * Interrupt Mask Register.
14681+ */
14682+typedef union doepint_data doepmsk_data_t;
14683+
14684+
14685+/**
14686+ * This union represents the bit fields in the Device All EP Interrupt
14687+ * and Mask Registers.
14688+ * - Read the register into the <i>d32</i> member then set/clear the
14689+ * bits using the <i>b</i>it elements.
14690+ */
14691+typedef union daint_data
14692+{
14693+ /** raw register data */
14694+ uint32_t d32;
14695+ /** register bits */
14696+ struct {
14697+ /** OUT Endpoint bits */
14698+ unsigned out : 16;
14699+ /** IN Endpoint bits */
14700+ unsigned in : 16;
14701+ } ep;
14702+ struct {
14703+ /** OUT Endpoint bits */
14704+ unsigned outep15 : 1;
14705+ unsigned outep14 : 1;
14706+ unsigned outep13 : 1;
14707+ unsigned outep12 : 1;
14708+ unsigned outep11 : 1;
14709+ unsigned outep10 : 1;
14710+ unsigned outep9 : 1;
14711+ unsigned outep8 : 1;
14712+ unsigned outep7 : 1;
14713+ unsigned outep6 : 1;
14714+ unsigned outep5 : 1;
14715+ unsigned outep4 : 1;
14716+ unsigned outep3 : 1;
14717+ unsigned outep2 : 1;
14718+ unsigned outep1 : 1;
14719+ unsigned outep0 : 1;
14720+ /** IN Endpoint bits */
14721+ unsigned inep15 : 1;
14722+ unsigned inep14 : 1;
14723+ unsigned inep13 : 1;
14724+ unsigned inep12 : 1;
14725+ unsigned inep11 : 1;
14726+ unsigned inep10 : 1;
14727+ unsigned inep9 : 1;
14728+ unsigned inep8 : 1;
14729+ unsigned inep7 : 1;
14730+ unsigned inep6 : 1;
14731+ unsigned inep5 : 1;
14732+ unsigned inep4 : 1;
14733+ unsigned inep3 : 1;
14734+ unsigned inep2 : 1;
14735+ unsigned inep1 : 1;
14736+ unsigned inep0 : 1;
14737+ } b;
14738+} daint_data_t;
14739+
14740+/**
14741+ * This union represents the bit fields in the Device IN Token Queue
14742+ * Read Registers.
14743+ * - Read the register into the <i>d32</i> member.
14744+ * - READ-ONLY Register
14745+ */
14746+typedef union dtknq1_data
14747+{
14748+ /** raw register data */
14749+ uint32_t d32;
14750+ /** register bits */
14751+ struct {
14752+ /** EP Numbers of IN Tokens 0 ... 4 */
14753+ unsigned epnums0_5 : 24;
14754+ /** write pointer has wrapped. */
14755+ unsigned wrap_bit : 1;
14756+ /** Reserved */
14757+ unsigned reserved05_06 : 2;
14758+ /** In Token Queue Write Pointer */
14759+ unsigned intknwptr : 5;
14760+ }b;
14761+} dtknq1_data_t;
14762+
14763+/**
14764+ * This union represents Threshold control Register
14765+ * - Read and write the register into the <i>d32</i> member.
14766+ * - READ-WRITABLE Register
14767+ */
14768+typedef union dthrctl_data //* /*fscz */
14769+{
14770+ /** raw register data */
14771+ uint32_t d32;
14772+ /** register bits */
14773+ struct {
14774+ /** Reserved */
14775+ unsigned reserved26_31 : 6;
14776+ /** Rx Thr. Length */
14777+ unsigned rx_thr_len : 9;
14778+ /** Rx Thr. Enable */
14779+ unsigned rx_thr_en : 1;
14780+ /** Reserved */
14781+ unsigned reserved11_15 : 5;
14782+ /** Tx Thr. Length */
14783+ unsigned tx_thr_len : 9;
14784+ /** ISO Tx Thr. Enable */
14785+ unsigned iso_thr_en : 1;
14786+ /** non ISO Tx Thr. Enable */
14787+ unsigned non_iso_thr_en : 1;
14788+
14789+ }b;
14790+} dthrctl_data_t;
14791+
14792+/**
14793+ * Device Logical IN Endpoint-Specific Registers. <i>Offsets
14794+ * 900h-AFCh</i>
14795+ *
14796+ * There will be one set of endpoint registers per logical endpoint
14797+ * implemented.
14798+ *
14799+ * <i>These registers are visible only in Device mode and must not be
14800+ * accessed in Host mode, as the results are unknown.</i>
14801+ */
14802+typedef struct dwc_otg_dev_in_ep_regs
14803+{
14804+ /** Device IN Endpoint Control Register. <i>Offset:900h +
14805+ * (ep_num * 20h) + 00h</i> */
14806+ volatile uint32_t diepctl;
14807+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
14808+ uint32_t reserved04;
14809+ /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
14810+ * (ep_num * 20h) + 08h</i> */
14811+ volatile uint32_t diepint;
14812+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
14813+ uint32_t reserved0C;
14814+ /** Device IN Endpoint Transfer Size
14815+ * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
14816+ volatile uint32_t dieptsiz;
14817+ /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
14818+ * (ep_num * 20h) + 14h</i> */
14819+ volatile uint32_t diepdma;
14820+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 18h - 900h +
14821+ * (ep_num * 20h) + 1Ch</i>*/
14822+ volatile uint32_t dtxfsts;
14823+ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 1Ch - 900h +
14824+ * (ep_num * 20h) + 1Ch</i>*/
14825+ uint32_t reserved18;
14826+} dwc_otg_dev_in_ep_regs_t;
14827+
14828+/**
14829+ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
14830+ * B00h-CFCh</i>
14831+ *
14832+ * There will be one set of endpoint registers per logical endpoint
14833+ * implemented.
14834+ *
14835+ * <i>These registers are visible only in Device mode and must not be
14836+ * accessed in Host mode, as the results are unknown.</i>
14837+ */
14838+typedef struct dwc_otg_dev_out_ep_regs
14839+{
14840+ /** Device OUT Endpoint Control Register. <i>Offset:B00h +
14841+ * (ep_num * 20h) + 00h</i> */
14842+ volatile uint32_t doepctl;
14843+ /** Device OUT Endpoint Frame number Register. <i>Offset:
14844+ * B00h + (ep_num * 20h) + 04h</i> */
14845+ volatile uint32_t doepfn;
14846+ /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
14847+ * (ep_num * 20h) + 08h</i> */
14848+ volatile uint32_t doepint;
14849+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
14850+ uint32_t reserved0C;
14851+ /** Device OUT Endpoint Transfer Size Register. <i>Offset:
14852+ * B00h + (ep_num * 20h) + 10h</i> */
14853+ volatile uint32_t doeptsiz;
14854+ /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
14855+ * + (ep_num * 20h) + 14h</i> */
14856+ volatile uint32_t doepdma;
14857+ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 18h - B00h +
14858+ * (ep_num * 20h) + 1Ch</i> */
14859+ uint32_t unused[2];
14860+} dwc_otg_dev_out_ep_regs_t;
14861+
14862+/**
14863+ * This union represents the bit fields in the Device EP Control
14864+ * Register. Read the register into the <i>d32</i> member then
14865+ * set/clear the bits using the <i>b</i>it elements.
14866+ */
14867+typedef union depctl_data
14868+{
14869+ /** raw register data */
14870+ uint32_t d32;
14871+ /** register bits */
14872+ struct {
14873+ /** Endpoint Enable */
14874+ unsigned epena : 1;
14875+ /** Endpoint Disable */
14876+ unsigned epdis : 1;
14877+ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
14878+ * Writing to this field sets the Endpoint DPID (DPID)
14879+ * field in this register to DATA1 Set Odd
14880+ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
14881+ * Writing to this field sets the Even/Odd
14882+ * (micro)frame (EO_FrNum) field to odd (micro) frame.
14883+ */
14884+ unsigned setd1pid : 1;
14885+ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
14886+ * Writing to this field sets the Endpoint DPID (DPID)
14887+ * field in this register to DATA0. Set Even
14888+ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
14889+ * Writing to this field sets the Even/Odd
14890+ * (micro)frame (EO_FrNum) field to even (micro)
14891+ * frame.
14892+ */
14893+ unsigned setd0pid : 1;
14894+ /** Set NAK */
14895+ unsigned snak : 1;
14896+ /** Clear NAK */
14897+ unsigned cnak : 1;
14898+ /** Tx Fifo Number
14899+ * IN EPn/IN EP0
14900+ * OUT EPn/OUT EP0 - reserved */
14901+ unsigned txfnum : 4;
14902+ /** Stall Handshake */
14903+ unsigned stall : 1;
14904+ /** Snoop Mode
14905+ * OUT EPn/OUT EP0
14906+ * IN EPn/IN EP0 - reserved */
14907+ unsigned snp : 1;
14908+ /** Endpoint Type
14909+ * 2'b00: Control
14910+ * 2'b01: Isochronous
14911+ * 2'b10: Bulk
14912+ * 2'b11: Interrupt */
14913+ unsigned eptype : 2;
14914+ /** NAK Status */
14915+ unsigned naksts : 1;
14916+ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
14917+ * This field contains the PID of the packet going to
14918+ * be received or transmitted on this endpoint. The
14919+ * application should program the PID of the first
14920+ * packet going to be received or transmitted on this
14921+ * endpoint , after the endpoint is
14922+ * activated. Application use the SetD1PID and
14923+ * SetD0PID fields of this register to program either
14924+ * D0 or D1 PID.
14925+ *
14926+ * The encoding for this field is
14927+ * - 0: D0
14928+ * - 1: D1
14929+ */
14930+ unsigned dpid : 1;
14931+ /** USB Active Endpoint */
14932+ unsigned usbactep : 1;
14933+ /** Next Endpoint
14934+ * IN EPn/IN EP0
14935+ * OUT EPn/OUT EP0 - reserved */
14936+ unsigned nextep : 4;
14937+ /** Maximum Packet Size
14938+ * IN/OUT EPn
14939+ * IN/OUT EP0 - 2 bits
14940+ * 2'b00: 64 Bytes
14941+ * 2'b01: 32
14942+ * 2'b10: 16
14943+ * 2'b11: 8 */
14944+#define DWC_DEP0CTL_MPS_64 0
14945+#define DWC_DEP0CTL_MPS_32 1
14946+#define DWC_DEP0CTL_MPS_16 2
14947+#define DWC_DEP0CTL_MPS_8 3
14948+ unsigned mps : 11;
14949+ } b;
14950+} depctl_data_t;
14951+
14952+/**
14953+ * This union represents the bit fields in the Device EP Transfer
14954+ * Size Register. Read the register into the <i>d32</i> member then
14955+ * set/clear the bits using the <i>b</i>it elements.
14956+ */
14957+typedef union deptsiz_data
14958+{
14959+ /** raw register data */
14960+ uint32_t d32;
14961+ /** register bits */
14962+ struct {
14963+ unsigned reserved : 1;
14964+ /** Multi Count - Periodic IN endpoints */
14965+ unsigned mc : 2;
14966+ /** Packet Count */
14967+ unsigned pktcnt : 10;
14968+ /** Transfer size */
14969+ unsigned xfersize : 19;
14970+ } b;
14971+} deptsiz_data_t;
14972+
14973+/**
14974+ * This union represents the bit fields in the Device EP 0 Transfer
14975+ * Size Register. Read the register into the <i>d32</i> member then
14976+ * set/clear the bits using the <i>b</i>it elements.
14977+ */
14978+typedef union deptsiz0_data
14979+{
14980+ /** raw register data */
14981+ uint32_t d32;
14982+ /** register bits */
14983+ struct {
14984+ unsigned reserved31 : 1;
14985+ /**Setup Packet Count (DOEPTSIZ0 Only) */
14986+ unsigned supcnt : 2;
14987+ /** Reserved */
14988+ unsigned reserved28_20 : 9;
14989+ /** Packet Count */
14990+ unsigned pktcnt : 1;
14991+ /** Reserved */
14992+ unsigned reserved18_7 : 12;
14993+ /** Transfer size */
14994+ unsigned xfersize : 7;
14995+ } b;
14996+} deptsiz0_data_t;
14997+
14998+
14999+/** Maximum number of Periodic FIFOs */
15000+#define MAX_PERIO_FIFOS 15
15001+/** Maximum number of TX FIFOs */
15002+#define MAX_TX_FIFOS 15
15003+/** Maximum number of Endpoints/HostChannels */
15004+#define MAX_EPS_CHANNELS 16
15005+//#define MAX_EPS_CHANNELS 4
15006+
15007+/**
15008+ * The dwc_otg_dev_if structure contains information needed to manage
15009+ * the DWC_otg controller acting in device mode. It represents the
15010+ * programming view of the device-specific aspects of the controller.
15011+ */
15012+typedef struct dwc_otg_dev_if {
15013+ /** Pointer to device Global registers.
15014+ * Device Global Registers starting at offset 800h
15015+ */
15016+ dwc_otg_device_global_regs_t *dev_global_regs;
15017+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
15018+
15019+ /**
15020+ * Device Logical IN Endpoint-Specific Registers 900h-AFCh
15021+ */
15022+ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
15023+#define DWC_DEV_IN_EP_REG_OFFSET 0x900
15024+#define DWC_EP_REG_OFFSET 0x20
15025+
15026+ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
15027+ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
15028+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
15029+
15030+ /* Device configuration information*/
15031+ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
15032+ //uint8_t num_eps; /**< Number of EPs range: 0-16 (includes EP0) */
15033+ //uint8_t num_perio_eps; /**< # of Periodic EP range: 0-15 */
15034+ /*fscz */
15035+ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
15036+ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
15037+
15038+ /** Size of periodic FIFOs (Bytes) */
15039+ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
15040+
15041+ /** Size of Tx FIFOs (Bytes) */
15042+ uint16_t tx_fifo_size[MAX_TX_FIFOS];
15043+
15044+ /** Thresholding enable flags and length varaiables **/
15045+ uint16_t rx_thr_en;
15046+ uint16_t iso_tx_thr_en;
15047+ uint16_t non_iso_tx_thr_en;
15048+
15049+ uint16_t rx_thr_length;
15050+ uint16_t tx_thr_length;
15051+} dwc_otg_dev_if_t;
15052+
15053+/**
15054+ * This union represents the bit fields in the Power and Clock Gating Control
15055+ * Register. Read the register into the <i>d32</i> member then set/clear the
15056+ * bits using the <i>b</i>it elements.
15057+ */
15058+typedef union pcgcctl_data
15059+{
15060+ /** raw register data */
15061+ uint32_t d32;
15062+
15063+ /** register bits */
15064+ struct {
15065+ unsigned reserved31_05 : 27;
15066+ /** PHY Suspended */
15067+ unsigned physuspended : 1;
15068+ /** Reset Power Down Modules */
15069+ unsigned rstpdwnmodule : 1;
15070+ /** Power Clamp */
15071+ unsigned pwrclmp : 1;
15072+ /** Gate Hclk */
15073+ unsigned gatehclk : 1;
15074+ /** Stop Pclk */
15075+ unsigned stoppclk : 1;
15076+ } b;
15077+} pcgcctl_data_t;
15078+
15079+/////////////////////////////////////////////////
15080+// Host Mode Register Structures
15081+//
15082+/**
15083+ * The Host Global Registers structure defines the size and relative
15084+ * field offsets for the Host Mode Global Registers. Host Global
15085+ * Registers offsets 400h-7FFh.
15086+*/
15087+typedef struct dwc_otg_host_global_regs
15088+{
15089+ /** Host Configuration Register. <i>Offset: 400h</i> */
15090+ volatile uint32_t hcfg;
15091+ /** Host Frame Interval Register. <i>Offset: 404h</i> */
15092+ volatile uint32_t hfir;
15093+ /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
15094+ volatile uint32_t hfnum;
15095+ /** Reserved. <i>Offset: 40Ch</i> */
15096+ uint32_t reserved40C;
15097+ /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
15098+ volatile uint32_t hptxsts;
15099+ /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
15100+ volatile uint32_t haint;
15101+ /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
15102+ volatile uint32_t haintmsk;
15103+} dwc_otg_host_global_regs_t;
15104+
15105+/**
15106+ * This union represents the bit fields in the Host Configuration Register.
15107+ * Read the register into the <i>d32</i> member then set/clear the bits using
15108+ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
15109+ */
15110+typedef union hcfg_data
15111+{
15112+ /** raw register data */
15113+ uint32_t d32;
15114+
15115+ /** register bits */
15116+ struct {
15117+ /** Reserved */
15118+ //unsigned reserved31_03 : 29;
15119+ /** FS/LS Only Support */
15120+ unsigned fslssupp : 1;
15121+ /** FS/LS Phy Clock Select */
15122+#define DWC_HCFG_30_60_MHZ 0
15123+#define DWC_HCFG_48_MHZ 1
15124+#define DWC_HCFG_6_MHZ 2
15125+ unsigned fslspclksel : 2;
15126+ } b;
15127+} hcfg_data_t;
15128+
15129+/**
15130+ * This union represents the bit fields in the Host Frame Remaing/Number
15131+ * Register.
15132+ */
15133+typedef union hfir_data
15134+{
15135+ /** raw register data */
15136+ uint32_t d32;
15137+
15138+ /** register bits */
15139+ struct {
15140+ unsigned reserved : 16;
15141+ unsigned frint : 16;
15142+ } b;
15143+} hfir_data_t;
15144+
15145+/**
15146+ * This union represents the bit fields in the Host Frame Remaing/Number
15147+ * Register.
15148+ */
15149+typedef union hfnum_data
15150+{
15151+ /** raw register data */
15152+ uint32_t d32;
15153+
15154+ /** register bits */
15155+ struct {
15156+ unsigned frrem : 16;
15157+#define DWC_HFNUM_MAX_FRNUM 0x3FFF
15158+ unsigned frnum : 16;
15159+ } b;
15160+} hfnum_data_t;
15161+
15162+typedef union hptxsts_data
15163+{
15164+ /** raw register data */
15165+ uint32_t d32;
15166+
15167+ /** register bits */
15168+ struct {
15169+ /** Top of the Periodic Transmit Request Queue
15170+ * - bit 24 - Terminate (last entry for the selected channel)
15171+ * - bits 26:25 - Token Type
15172+ * - 2'b00 - Zero length
15173+ * - 2'b01 - Ping
15174+ * - 2'b10 - Disable
15175+ * - bits 30:27 - Channel Number
15176+ * - bit 31 - Odd/even microframe
15177+ */
15178+ unsigned ptxqtop_odd : 1;
15179+ unsigned ptxqtop_chnum : 4;
15180+ unsigned ptxqtop_token : 2;
15181+ unsigned ptxqtop_terminate : 1;
15182+ unsigned ptxqspcavail : 8;
15183+ unsigned ptxfspcavail : 16;
15184+ } b;
15185+} hptxsts_data_t;
15186+
15187+/**
15188+ * This union represents the bit fields in the Host Port Control and Status
15189+ * Register. Read the register into the <i>d32</i> member then set/clear the
15190+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
15191+ * hprt0 register.
15192+ */
15193+typedef union hprt0_data
15194+{
15195+ /** raw register data */
15196+ uint32_t d32;
15197+ /** register bits */
15198+ struct {
15199+ unsigned reserved19_31 : 13;
15200+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
15201+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
15202+#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
15203+ unsigned prtspd : 2;
15204+ unsigned prttstctl : 4;
15205+ unsigned prtpwr : 1;
15206+ unsigned prtlnsts : 2;
15207+ unsigned reserved9 : 1;
15208+ unsigned prtrst : 1;
15209+ unsigned prtsusp : 1;
15210+ unsigned prtres : 1;
15211+ unsigned prtovrcurrchng : 1;
15212+ unsigned prtovrcurract : 1;
15213+ unsigned prtenchng : 1;
15214+ unsigned prtena : 1;
15215+ unsigned prtconndet : 1;
15216+ unsigned prtconnsts : 1;
15217+ } b;
15218+} hprt0_data_t;
15219+
15220+/**
15221+ * This union represents the bit fields in the Host All Interrupt
15222+ * Register.
15223+ */
15224+typedef union haint_data
15225+{
15226+ /** raw register data */
15227+ uint32_t d32;
15228+ /** register bits */
15229+ struct {
15230+ unsigned reserved : 16;
15231+ unsigned ch15 : 1;
15232+ unsigned ch14 : 1;
15233+ unsigned ch13 : 1;
15234+ unsigned ch12 : 1;
15235+ unsigned ch11 : 1;
15236+ unsigned ch10 : 1;
15237+ unsigned ch9 : 1;
15238+ unsigned ch8 : 1;
15239+ unsigned ch7 : 1;
15240+ unsigned ch6 : 1;
15241+ unsigned ch5 : 1;
15242+ unsigned ch4 : 1;
15243+ unsigned ch3 : 1;
15244+ unsigned ch2 : 1;
15245+ unsigned ch1 : 1;
15246+ unsigned ch0 : 1;
15247+ } b;
15248+ struct {
15249+ unsigned reserved : 16;
15250+ unsigned chint : 16;
15251+ } b2;
15252+} haint_data_t;
15253+
15254+/**
15255+ * This union represents the bit fields in the Host All Interrupt
15256+ * Register.
15257+ */
15258+typedef union haintmsk_data
15259+{
15260+ /** raw register data */
15261+ uint32_t d32;
15262+ /** register bits */
15263+ struct {
15264+ unsigned reserved : 16;
15265+ unsigned ch15 : 1;
15266+ unsigned ch14 : 1;
15267+ unsigned ch13 : 1;
15268+ unsigned ch12 : 1;
15269+ unsigned ch11 : 1;
15270+ unsigned ch10 : 1;
15271+ unsigned ch9 : 1;
15272+ unsigned ch8 : 1;
15273+ unsigned ch7 : 1;
15274+ unsigned ch6 : 1;
15275+ unsigned ch5 : 1;
15276+ unsigned ch4 : 1;
15277+ unsigned ch3 : 1;
15278+ unsigned ch2 : 1;
15279+ unsigned ch1 : 1;
15280+ unsigned ch0 : 1;
15281+ } b;
15282+ struct {
15283+ unsigned reserved : 16;
15284+ unsigned chint : 16;
15285+ } b2;
15286+} haintmsk_data_t;
15287+
15288+/**
15289+ * Host Channel Specific Registers. <i>500h-5FCh</i>
15290+ */
15291+typedef struct dwc_otg_hc_regs
15292+{
15293+ /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
15294+ volatile uint32_t hcchar;
15295+ /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
15296+ volatile uint32_t hcsplt;
15297+ /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
15298+ volatile uint32_t hcint;
15299+ /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
15300+ volatile uint32_t hcintmsk;
15301+ /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
15302+ volatile uint32_t hctsiz;
15303+ /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
15304+ volatile uint32_t hcdma;
15305+ /** Reserved. <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
15306+ uint32_t reserved[2];
15307+} dwc_otg_hc_regs_t;
15308+
15309+/**
15310+ * This union represents the bit fields in the Host Channel Characteristics
15311+ * Register. Read the register into the <i>d32</i> member then set/clear the
15312+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
15313+ * hcchar register.
15314+ */
15315+typedef union hcchar_data
15316+{
15317+ /** raw register data */
15318+ uint32_t d32;
15319+
15320+ /** register bits */
15321+ struct {
15322+ /** Channel enable */
15323+ unsigned chen : 1;
15324+ /** Channel disable */
15325+ unsigned chdis : 1;
15326+ /**
15327+ * Frame to transmit periodic transaction.
15328+ * 0: even, 1: odd
15329+ */
15330+ unsigned oddfrm : 1;
15331+ /** Device address */
15332+ unsigned devaddr : 7;
15333+ /** Packets per frame for periodic transfers. 0 is reserved. */
15334+ unsigned multicnt : 2;
15335+ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
15336+ unsigned eptype : 2;
15337+ /** 0: Full/high speed device, 1: Low speed device */
15338+ unsigned lspddev : 1;
15339+ unsigned reserved : 1;
15340+ /** 0: OUT, 1: IN */
15341+ unsigned epdir : 1;
15342+ /** Endpoint number */
15343+ unsigned epnum : 4;
15344+ /** Maximum packet size in bytes */
15345+ unsigned mps : 11;
15346+ } b;
15347+} hcchar_data_t;
15348+
15349+typedef union hcsplt_data
15350+{
15351+ /** raw register data */
15352+ uint32_t d32;
15353+
15354+ /** register bits */
15355+ struct {
15356+ /** Split Enble */
15357+ unsigned spltena : 1;
15358+ /** Reserved */
15359+ unsigned reserved : 14;
15360+ /** Do Complete Split */
15361+ unsigned compsplt : 1;
15362+ /** Transaction Position */
15363+#define DWC_HCSPLIT_XACTPOS_MID 0
15364+#define DWC_HCSPLIT_XACTPOS_END 1
15365+#define DWC_HCSPLIT_XACTPOS_BEGIN 2
15366+#define DWC_HCSPLIT_XACTPOS_ALL 3
15367+ unsigned xactpos : 2;
15368+ /** Hub Address */
15369+ unsigned hubaddr : 7;
15370+ /** Port Address */
15371+ unsigned prtaddr : 7;
15372+ } b;
15373+} hcsplt_data_t;
15374+
15375+
15376+/**
15377+ * This union represents the bit fields in the Host All Interrupt
15378+ * Register.
15379+ */
15380+typedef union hcint_data
15381+{
15382+ /** raw register data */
15383+ uint32_t d32;
15384+ /** register bits */
15385+ struct {
15386+ /** Reserved */
15387+ unsigned reserved : 21;
15388+ /** Data Toggle Error */
15389+ unsigned datatglerr : 1;
15390+ /** Frame Overrun */
15391+ unsigned frmovrun : 1;
15392+ /** Babble Error */
15393+ unsigned bblerr : 1;
15394+ /** Transaction Err */
15395+ unsigned xacterr : 1;
15396+ /** NYET Response Received */
15397+ unsigned nyet : 1;
15398+ /** ACK Response Received */
15399+ unsigned ack : 1;
15400+ /** NAK Response Received */
15401+ unsigned nak : 1;
15402+ /** STALL Response Received */
15403+ unsigned stall : 1;
15404+ /** AHB Error */
15405+ unsigned ahberr : 1;
15406+ /** Channel Halted */
15407+ unsigned chhltd : 1;
15408+ /** Transfer Complete */
15409+ unsigned xfercomp : 1;
15410+ } b;
15411+} hcint_data_t;
15412+
15413+/**
15414+ * This union represents the bit fields in the Host Channel Transfer Size
15415+ * Register. Read the register into the <i>d32</i> member then set/clear the
15416+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
15417+ * hcchar register.
15418+ */
15419+typedef union hctsiz_data
15420+{
15421+ /** raw register data */
15422+ uint32_t d32;
15423+
15424+ /** register bits */
15425+ struct {
15426+ /** Do PING protocol when 1 */
15427+ unsigned dopng : 1;
15428+ /**
15429+ * Packet ID for next data packet
15430+ * 0: DATA0
15431+ * 1: DATA2
15432+ * 2: DATA1
15433+ * 3: MDATA (non-Control), SETUP (Control)
15434+ */
15435+#define DWC_HCTSIZ_DATA0 0
15436+#define DWC_HCTSIZ_DATA1 2
15437+#define DWC_HCTSIZ_DATA2 1
15438+#define DWC_HCTSIZ_MDATA 3
15439+#define DWC_HCTSIZ_SETUP 3
15440+ unsigned pid : 2;
15441+ /** Data packets to transfer */
15442+ unsigned pktcnt : 10;
15443+ /** Total transfer size in bytes */
15444+ unsigned xfersize : 19;
15445+ } b;
15446+} hctsiz_data_t;
15447+
15448+/**
15449+ * This union represents the bit fields in the Host Channel Interrupt Mask
15450+ * Register. Read the register into the <i>d32</i> member then set/clear the
15451+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
15452+ * hcintmsk register.
15453+ */
15454+typedef union hcintmsk_data
15455+{
15456+ /** raw register data */
15457+ uint32_t d32;
15458+
15459+ /** register bits */
15460+ struct {
15461+ unsigned reserved : 21;
15462+ unsigned datatglerr : 1;
15463+ unsigned frmovrun : 1;
15464+ unsigned bblerr : 1;
15465+ unsigned xacterr : 1;
15466+ unsigned nyet : 1;
15467+ unsigned ack : 1;
15468+ unsigned nak : 1;
15469+ unsigned stall : 1;
15470+ unsigned ahberr : 1;
15471+ unsigned chhltd : 1;
15472+ unsigned xfercompl : 1;
15473+ } b;
15474+} hcintmsk_data_t;
15475+
15476+/** OTG Host Interface Structure.
15477+ *
15478+ * The OTG Host Interface Structure structure contains information
15479+ * needed to manage the DWC_otg controller acting in host mode. It
15480+ * represents the programming view of the host-specific aspects of the
15481+ * controller.
15482+ */
15483+typedef struct dwc_otg_host_if {
15484+ /** Host Global Registers starting at offset 400h.*/
15485+ dwc_otg_host_global_regs_t *host_global_regs;
15486+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
15487+
15488+ /** Host Port 0 Control and Status Register */
15489+ volatile uint32_t *hprt0;
15490+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
15491+
15492+
15493+ /** Host Channel Specific Registers at offsets 500h-5FCh. */
15494+ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
15495+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
15496+#define DWC_OTG_CHAN_REGS_OFFSET 0x20
15497+
15498+
15499+ /* Host configuration information */
15500+ /** Number of Host Channels (range: 1-16) */
15501+ uint8_t num_host_channels;
15502+ /** Periodic EPs supported (0: no, 1: yes) */
15503+ uint8_t perio_eps_supported;
15504+ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
15505+ uint16_t perio_tx_fifo_size;
15506+
15507+} dwc_otg_host_if_t;
15508+
15509+#endif
15510--- a/arch/mips/lantiq/xway/Makefile
15511+++ b/arch/mips/lantiq/xway/Makefile
15512@@ -6,3 +6,4 @@
15513 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
15514 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
15515 obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o
15516+obj-y += dev-dwc_otg.o
15517--- /dev/null
15518+++ b/arch/mips/lantiq/xway/dev-dwc_otg.c
15519@@ -0,0 +1,68 @@
15520+/*
15521+ * This program is free software; you can redistribute it and/or modify
15522+ * it under the terms of the GNU General Public License as published by
15523+ * the Free Software Foundation; either version 2 of the License, or
15524+ * (at your option) any later version.
15525+ *
15526+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
15527+ */
15528+
15529+#include <linux/init.h>
15530+#include <linux/module.h>
15531+#include <linux/types.h>
15532+#include <linux/string.h>
15533+#include <linux/mtd/physmap.h>
15534+#include <linux/kernel.h>
15535+#include <linux/reboot.h>
15536+#include <linux/platform_device.h>
15537+#include <linux/leds.h>
15538+#include <linux/etherdevice.h>
15539+#include <linux/reboot.h>
15540+#include <linux/time.h>
15541+#include <linux/io.h>
15542+#include <linux/gpio.h>
15543+#include <linux/leds.h>
15544+
15545+#include <asm/bootinfo.h>
15546+#include <asm/irq.h>
15547+
15548+#include <lantiq_soc.h>
15549+#include <lantiq_irq.h>
15550+#include <lantiq_platform.h>
15551+
15552+#define LTQ_USB_IOMEM_BASE 0x1e101000
15553+#define LTQ_USB_IOMEM_SIZE 0x00001000
15554+
15555+static struct resource resources[] =
15556+{
15557+ [0] = {
15558+ .name = "dwc_otg_membase",
15559+ .start = LTQ_USB_IOMEM_BASE,
15560+ .end = LTQ_USB_IOMEM_BASE + LTQ_USB_IOMEM_SIZE - 1,
15561+ .flags = IORESOURCE_MEM,
15562+ },
15563+ [1] = {
15564+ .name = "dwc_otg_irq",
15565+ .start = LTQ_USB_INT,
15566+ .flags = IORESOURCE_IRQ,
15567+ },
15568+};
15569+
15570+static u64 dwc_dmamask = (u32)0x1fffffff;
15571+
15572+static struct platform_device platform_dev = {
15573+ .name = "dwc_otg",
15574+ .dev = {
15575+ .dma_mask = &dwc_dmamask,
15576+ },
15577+ .resource = resources,
15578+ .num_resources = ARRAY_SIZE(resources),
15579+};
15580+
15581+int __init
15582+xway_register_dwc(int pin)
15583+{
15584+ ltq_enable_irq(resources[1].start);
15585+ platform_dev.dev.platform_data = (void*) pin;
15586+ return platform_device_register(&platform_dev);
15587+}
15588--- /dev/null
15589+++ b/arch/mips/lantiq/xway/dev-dwc_otg.h
15590@@ -0,0 +1,17 @@
15591+/*
15592+ * This program is free software; you can redistribute it and/or modify
15593+ * it under the terms of the GNU General Public License as published by
15594+ * the Free Software Foundation; either version 2 of the License, or
15595+ * (at your option) any later version.
15596+ *
15597+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
15598+ */
15599+
15600+#ifndef _LTQ_DEV_DWC_H__
15601+#define _LTQ_DEV_DWC_H__
15602+
15603+#include <lantiq_platform.h>
15604+
15605+extern void __init xway_register_dwc(int pin);
15606+
15607+#endif
15608--- a/drivers/usb/core/hub.c
15609+++ b/drivers/usb/core/hub.c
15610@@ -2704,11 +2704,11 @@
15611         udev->ttport = hdev->ttport;
15612     } else if (udev->speed != USB_SPEED_HIGH
15613             && hdev->speed == USB_SPEED_HIGH) {
15614- if (!hub->tt.hub) {
15615+/* if (!hub->tt.hub) {
15616             dev_err(&udev->dev, "parent hub has no TT\n");
15617             retval = -EINVAL;
15618             goto fail;
15619- }
15620+ }*/
15621         udev->tt = &hub->tt;
15622         udev->ttport = port1;
15623     }
15624

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