Root/target/linux/lantiq/patches-2.6.39/0010-MIPS-Lantiq-Add-DMA-support.patch

1From bd620ec1ca053bab8ce2562968700e6f80e4ff83 Mon Sep 17 00:00:00 2001
2From: John Crispin <blogic@openwrt.org>
3Date: Fri, 6 May 2011 00:10:00 +0200
4Subject: [PATCH 10/13] MIPS: Lantiq: Add DMA support
5
6This patch adds support for the DMA engine found inside the XWAY family of
7SoCs. The engine has 5 ports and 20 channels.
8
9Signed-off-by: John Crispin <blogic@openwrt.org>
10Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
11Cc: linux-mips@linux-mips.org
12Patchwork: https://patchwork.linux-mips.org/patch/2355/
13Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
14---
15 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +-
16 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 60 +++++
17 arch/mips/lantiq/xway/Makefile | 2 +-
18 arch/mips/lantiq/xway/devices.h | 1 +
19 arch/mips/lantiq/xway/dma.c | 253 ++++++++++++++++++++
20 5 files changed, 317 insertions(+), 2 deletions(-)
21 create mode 100644 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
22 create mode 100644 arch/mips/lantiq/xway/dma.c
23
24--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
25+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
26@@ -86,7 +86,8 @@
27 #define LTQ_PPE32_SIZE 0x40000
28 
29 /* DMA */
30-#define LTQ_DMA_BASE_ADDR 0xBE104100
31+#define LTQ_DMA_BASE_ADDR 0x1E104100
32+#define LTQ_DMA_SIZE 0x800
33 
34 /* PCI */
35 #define PCI_CR_BASE_ADDR 0x1E105400
36--- /dev/null
37+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
38@@ -0,0 +1,60 @@
39+/*
40+ * This program is free software; you can redistribute it and/or modify it
41+ * under the terms of the GNU General Public License version 2 as published
42+ * by the Free Software Foundation.
43+ *
44+ * This program is distributed in the hope that it will be useful,
45+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
46+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
47+ * GNU General Public License for more details.
48+ *
49+ * You should have received a copy of the GNU General Public License
50+ * along with this program; if not, write to the Free Software
51+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
52+ *
53+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
54+ */
55+
56+#ifndef LTQ_DMA_H__
57+#define LTQ_DMA_H__
58+
59+#define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */
60+#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */
61+
62+#define LTQ_DMA_OWN BIT(31) /* owner bit */
63+#define LTQ_DMA_C BIT(30) /* complete bit */
64+#define LTQ_DMA_SOP BIT(29) /* start of packet */
65+#define LTQ_DMA_EOP BIT(28) /* end of packet */
66+#define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */
67+#define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */
68+#define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */
69+
70+struct ltq_dma_desc {
71+ u32 ctl;
72+ u32 addr;
73+};
74+
75+struct ltq_dma_channel {
76+ int nr; /* the channel number */
77+ int irq; /* the mapped irq */
78+ int desc; /* the current descriptor */
79+ struct ltq_dma_desc *desc_base; /* the descriptor base */
80+ int phys; /* physical addr */
81+};
82+
83+enum {
84+ DMA_PORT_ETOP = 0,
85+ DMA_PORT_DEU,
86+};
87+
88+extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
89+extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
90+extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
91+extern void ltq_dma_open(struct ltq_dma_channel *ch);
92+extern void ltq_dma_close(struct ltq_dma_channel *ch);
93+extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
94+extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
95+extern void ltq_dma_free(struct ltq_dma_channel *ch);
96+extern void ltq_dma_init_port(int p);
97+
98+#endif
99--- a/arch/mips/lantiq/xway/Makefile
100+++ b/arch/mips/lantiq/xway/Makefile
101@@ -1,4 +1,4 @@
102-obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o
103+obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
104 
105 obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
106 obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
107--- a/arch/mips/lantiq/xway/devices.h
108+++ b/arch/mips/lantiq/xway/devices.h
109@@ -10,6 +10,7 @@
110 #define _LTQ_DEVICES_XWAY_H__
111 
112 #include "../devices.h"
113+#include <linux/phy.h>
114 
115 extern void ltq_register_gpio(void);
116 extern void ltq_register_gpio_stp(void);
117--- /dev/null
118+++ b/arch/mips/lantiq/xway/dma.c
119@@ -0,0 +1,253 @@
120+/*
121+ * This program is free software; you can redistribute it and/or modify it
122+ * under the terms of the GNU General Public License version 2 as published
123+ * by the Free Software Foundation.
124+ *
125+ * This program is distributed in the hope that it will be useful,
126+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
127+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
128+ * GNU General Public License for more details.
129+ *
130+ * You should have received a copy of the GNU General Public License
131+ * along with this program; if not, write to the Free Software
132+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
133+ *
134+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
135+ */
136+
137+#include <linux/init.h>
138+#include <linux/platform_device.h>
139+#include <linux/io.h>
140+#include <linux/dma-mapping.h>
141+
142+#include <lantiq_soc.h>
143+#include <xway_dma.h>
144+
145+#define LTQ_DMA_CTRL 0x10
146+#define LTQ_DMA_CPOLL 0x14
147+#define LTQ_DMA_CS 0x18
148+#define LTQ_DMA_CCTRL 0x1C
149+#define LTQ_DMA_CDBA 0x20
150+#define LTQ_DMA_CDLEN 0x24
151+#define LTQ_DMA_CIS 0x28
152+#define LTQ_DMA_CIE 0x2C
153+#define LTQ_DMA_PS 0x40
154+#define LTQ_DMA_PCTRL 0x44
155+#define LTQ_DMA_IRNEN 0xf4
156+
157+#define DMA_DESCPT BIT(3) /* descriptor complete irq */
158+#define DMA_TX BIT(8) /* TX channel direction */
159+#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
160+#define DMA_PDEN BIT(6) /* enable packet drop */
161+#define DMA_CHAN_RST BIT(1) /* channel on / off bit */
162+#define DMA_RESET BIT(0) /* channel on / off bit */
163+#define DMA_IRQ_ACK 0x7e /* IRQ status register */
164+#define DMA_POLL BIT(31) /* turn on channel polling */
165+#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
166+#define DMA_2W_BURST BIT(1) /* 2 word burst length */
167+#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
168+#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */
169+#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
170+
171+#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
172+#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
173+#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
174+ ltq_dma_membase + (z))
175+
176+static struct resource ltq_dma_resource = {
177+ .name = "dma",
178+ .start = LTQ_DMA_BASE_ADDR,
179+ .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
180+ .flags = IORESOURCE_MEM,
181+};
182+
183+static void __iomem *ltq_dma_membase;
184+
185+void
186+ltq_dma_enable_irq(struct ltq_dma_channel *ch)
187+{
188+ unsigned long flags;
189+
190+ local_irq_save(flags);
191+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
192+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
193+ local_irq_restore(flags);
194+}
195+EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
196+
197+void
198+ltq_dma_disable_irq(struct ltq_dma_channel *ch)
199+{
200+ unsigned long flags;
201+
202+ local_irq_save(flags);
203+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
204+ ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
205+ local_irq_restore(flags);
206+}
207+EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
208+
209+void
210+ltq_dma_ack_irq(struct ltq_dma_channel *ch)
211+{
212+ unsigned long flags;
213+
214+ local_irq_save(flags);
215+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
216+ ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
217+ local_irq_restore(flags);
218+}
219+EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
220+
221+void
222+ltq_dma_open(struct ltq_dma_channel *ch)
223+{
224+ unsigned long flag;
225+
226+ local_irq_save(flag);
227+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
228+ ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
229+ ltq_dma_enable_irq(ch);
230+ local_irq_restore(flag);
231+}
232+EXPORT_SYMBOL_GPL(ltq_dma_open);
233+
234+void
235+ltq_dma_close(struct ltq_dma_channel *ch)
236+{
237+ unsigned long flag;
238+
239+ local_irq_save(flag);
240+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
241+ ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
242+ ltq_dma_disable_irq(ch);
243+ local_irq_restore(flag);
244+}
245+EXPORT_SYMBOL_GPL(ltq_dma_close);
246+
247+static void
248+ltq_dma_alloc(struct ltq_dma_channel *ch)
249+{
250+ unsigned long flags;
251+
252+ ch->desc = 0;
253+ ch->desc_base = dma_alloc_coherent(NULL,
254+ LTQ_DESC_NUM * LTQ_DESC_SIZE,
255+ &ch->phys, GFP_ATOMIC);
256+ memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE);
257+
258+ local_irq_save(flags);
259+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
260+ ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
261+ ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
262+ ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
263+ wmb();
264+ ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
265+ while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
266+ ;
267+ local_irq_restore(flags);
268+}
269+
270+void
271+ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
272+{
273+ unsigned long flags;
274+
275+ ltq_dma_alloc(ch);
276+
277+ local_irq_save(flags);
278+ ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
279+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
280+ ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
281+ local_irq_restore(flags);
282+}
283+EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
284+
285+void
286+ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
287+{
288+ unsigned long flags;
289+
290+ ltq_dma_alloc(ch);
291+
292+ local_irq_save(flags);
293+ ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
294+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
295+ ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
296+ local_irq_restore(flags);
297+}
298+EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
299+
300+void
301+ltq_dma_free(struct ltq_dma_channel *ch)
302+{
303+ if (!ch->desc_base)
304+ return;
305+ ltq_dma_close(ch);
306+ dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE,
307+ ch->desc_base, ch->phys);
308+}
309+EXPORT_SYMBOL_GPL(ltq_dma_free);
310+
311+void
312+ltq_dma_init_port(int p)
313+{
314+ ltq_dma_w32(p, LTQ_DMA_PS);
315+ switch (p) {
316+ case DMA_PORT_ETOP:
317+ /*
318+ * Tell the DMA engine to swap the endianess of data frames and
319+ * drop packets if the channel arbitration fails.
320+ */
321+ ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN,
322+ LTQ_DMA_PCTRL);
323+ break;
324+
325+ case DMA_PORT_DEU:
326+ ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
327+ LTQ_DMA_PCTRL);
328+ break;
329+
330+ default:
331+ break;
332+ }
333+}
334+EXPORT_SYMBOL_GPL(ltq_dma_init_port);
335+
336+int __init
337+ltq_dma_init(void)
338+{
339+ int i;
340+
341+ /* insert and request the memory region */
342+ if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
343+ panic("Failed to insert dma memory\n");
344+
345+ if (request_mem_region(ltq_dma_resource.start,
346+ resource_size(&ltq_dma_resource), "dma") < 0)
347+ panic("Failed to request dma memory\n");
348+
349+ /* remap dma register range */
350+ ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
351+ resource_size(&ltq_dma_resource));
352+ if (!ltq_dma_membase)
353+ panic("Failed to remap dma memory\n");
354+
355+ /* power up and reset the dma engine */
356+ ltq_pmu_enable(PMU_DMA);
357+ ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
358+
359+ /* disable all interrupts */
360+ ltq_dma_w32(0, LTQ_DMA_IRNEN);
361+
362+ /* reset/configure each channel */
363+ for (i = 0; i < DMA_MAX_CHANNEL; i++) {
364+ ltq_dma_w32(i, LTQ_DMA_CS);
365+ ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
366+ ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
367+ ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
368+ }
369+ return 0;
370+}
371+
372+postcore_initcall(ltq_dma_init);
373

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