Root/target/linux/lantiq/patches-2.6.39/120-falcon-i2c.patch

1--- a/drivers/i2c/busses/Makefile
2+++ b/drivers/i2c/busses/Makefile
3@@ -82,5 +82,6 @@ obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
4 obj-$(CONFIG_I2C_STUB) += i2c-stub.o
5 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
6 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
7+obj-$(CONFIG_I2C_FALCON) += i2c-falcon.o
8 
9 ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
10--- a/drivers/i2c/busses/Kconfig
11+++ b/drivers/i2c/busses/Kconfig
12@@ -282,6 +282,10 @@ config I2C_POWERMAC
13 
14 comment "I2C system bus drivers (mostly embedded / system-on-chip)"
15 
16+config I2C_FALCON
17+ tristate "Falcon I2C interface"
18+# depends on SOC_FALCON
19+
20 config I2C_AT91
21     tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
22     depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
23--- /dev/null
24+++ b/drivers/i2c/busses/i2c-falcon.c
25@@ -0,0 +1,803 @@
26+/*
27+ * This program is free software; you can redistribute it and/or modify
28+ * it under the terms of the GNU General Public License as published by
29+ * the Free Software Foundation; either version 2 of the License, or
30+ * (at your option) any later version.
31+ *
32+ * This program is distributed in the hope that it will be useful,
33+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
34+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35+ * GNU General Public License for more details.
36+ *
37+ * You should have received a copy of the GNU General Public License
38+ * along with this program; if not, write to the Free Software
39+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
40+ */
41+
42+/* #define DEBUG */
43+
44+#include <linux/module.h>
45+#include <linux/ioport.h>
46+#include <linux/init.h>
47+#include <linux/platform_device.h>
48+#include <linux/i2c.h>
49+#include <linux/interrupt.h>
50+#include <linux/spinlock.h>
51+#include <linux/io.h>
52+#include <linux/clk.h>
53+#include <linux/err.h>
54+#include <linux/slab.h>
55+
56+/* CURRENT ISSUES:
57+ * - no high speed support
58+ * - rx issue with "address mode" & "tx end" interrupts
59+ * - ten bit mode is not tested
60+ */
61+
62+/* mapping for access macros */
63+#define reg_r32(reg) __raw_readl(reg)
64+#define reg_w32(val, reg) __raw_writel(val, reg)
65+#define reg_w32_mask(clear, set, reg) \
66+ reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
67+#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)&reg)[idx])
68+#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)&reg)[idx])
69+#define i2c (priv->membase)
70+#include <falcon/i2c_reg.h>
71+
72+/* enable hacks to overcome current issue */
73+#define FALCON_FIX_ME
74+
75+#define FALCON_I2C_ADDR 0x00
76+#define FALCON_I2C_READY_TIMEOUT 1000
77+#define FALCON_I2C_WAIT_TIMEOUT 10
78+
79+#define DRV_NAME "i2c-falcon"
80+
81+#if defined(DEBUG)
82+#define static /* no static functions for better debugging */
83+#endif
84+
85+#define FALCON_I2C_ARB_LOST (1 << 0)
86+#define FALCON_I2C_NACK (1 << 1)
87+#define FALCON_I2C_RX_UFL (1 << 2)
88+#define FALCON_I2C_RX_OFL (1 << 3)
89+#define FALCON_I2C_TX_UFL (1 << 4)
90+#define FALCON_I2C_TX_OFL (1 << 5)
91+#define FALCON_I2C_BURST_REQ (1 << 6)
92+#define FALCON_I2C_RX (1 << 7)
93+#define FALCON_I2C_TX_END (1 << 8)
94+#define FALCON_I2C_ADDR_MATCH (1 << 9) /* doesn't trigger */
95+
96+struct falcon_i2c {
97+ spinlock_t lock;
98+
99+ enum {
100+ FALCON_I2C_MODE_100 = 1,
101+ FALCON_I2C_MODE_400 = 2,
102+ FALCON_I2C_MODE_3400 = 3
103+ } mode; /* current speed mode */
104+
105+ int ten_bit; /* current address mode */
106+ unsigned long status; /* bus events holder */
107+ struct clk *clk; /* clock input for i2c hardware block */
108+ struct gpon_reg_i2c __iomem *membase; /* base of mapped registers */
109+ int irq_lb, irq_b, irq_err, irq_p; /* last burst, burst, error,
110+ protocol IRQs */
111+ struct completion done;
112+ struct i2c_adapter adap;
113+ struct device *dev;
114+};
115+
116+#define FALCON_I2C_ERROR_MASK (FALCON_I2C_NACK \
117+ | FALCON_I2C_ARB_LOST \
118+ | FALCON_I2C_RX_OFL \
119+ | FALCON_I2C_RX_UFL \
120+ | FALCON_I2C_TX_OFL \
121+ | FALCON_I2C_TX_UFL)
122+
123+#define FALCON_I2C_ERROR(priv) (priv->status & FALCON_I2C_ERROR_MASK)
124+#define FALCON_I2C_ERROR_CLEAR(priv) do { \
125+ priv->status &= \
126+ ~FALCON_I2C_ERROR_MASK; \
127+ } while (0)
128+
129+static void falcon_addr_configure(struct falcon_i2c *priv, int ten_bit)
130+{
131+ u32 ten_bit_mask = ten_bit ? I2C_ADDR_CFG_TBAM_10bit : 0;
132+
133+ /* configure address */
134+ i2c_w32(I2C_ADDR_CFG_SOPE_EN /* generate stop when no more data in the
135+ fifo */
136+ | I2C_ADDR_CFG_SONA_EN /* generate stop when NA received */
137+ | I2C_ADDR_CFG_MnS_EN /* we are master device */
138+ | ten_bit_mask
139+ | FALCON_I2C_ADDR, /* our address */
140+ addr_cfg);
141+}
142+
143+static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
144+{
145+ u32 i_raw, i_pro, i_err;
146+ struct falcon_i2c *priv = dev_id;
147+ unsigned long flags;
148+ unsigned int old_status;
149+
150+ spin_lock_irqsave(&priv->lock, flags);
151+
152+ old_status = (unsigned int)priv->status;
153+
154+ i_raw = i2c_r32(mis);
155+
156+ /* protocol interrupt */
157+ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) {
158+ i_pro = i2c_r32(p_irqss);
159+
160+ /* tx -> rx switch */
161+ if (i_pro & I2C_P_IRQSS_RX)
162+ priv->status |= FALCON_I2C_RX;
163+
164+ /* tx end */
165+ if (i_pro & I2C_P_IRQSS_TX_END)
166+ priv->status |= FALCON_I2C_TX_END;
167+
168+ /* not acknowledge */
169+ if (i_pro & I2C_P_IRQSS_NACK)
170+ priv->status |= FALCON_I2C_NACK;
171+
172+ /* arbitration lost */
173+ if (i_pro & I2C_P_IRQSS_AL)
174+ priv->status |= FALCON_I2C_ARB_LOST;
175+
176+ /* address match */
177+ if (i_pro & I2C_P_IRQSS_AM)
178+ priv->status |= FALCON_I2C_ADDR_MATCH;
179+
180+ i2c_w32(i_pro, p_irqsc);
181+ }
182+
183+ /* error interrupt */
184+ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
185+ i_err = i2c_r32(err_irqss);
186+
187+ /* tx fifo overflow */
188+ if (i_err & I2C_ERR_IRQSS_TXF_OFL)
189+ priv->status |= FALCON_I2C_TX_OFL;
190+
191+ /* tx fifo underflow */
192+ if (i_err & I2C_ERR_IRQSS_TXF_UFL)
193+ priv->status |= FALCON_I2C_TX_UFL;
194+
195+ /* rx fifo overflow */
196+ if (i_err & I2C_ERR_IRQSS_RXF_OFL)
197+ priv->status |= FALCON_I2C_RX_OFL;
198+
199+ /* rx fifo underflow */
200+ if (i_err & I2C_ERR_IRQSS_RXF_UFL)
201+ priv->status |= FALCON_I2C_RX_UFL;
202+
203+ i2c_w32(i_err, err_irqsc);
204+ }
205+
206+ /* burst request */
207+ if (i_raw & I2C_RIS_BREQ_INT_INTOCC) {
208+ i2c_w32_mask(I2C_IMSC_BREQ_INT_EN, 0, imsc);
209+ i2c_w32_mask(0, I2C_ICR_BREQ_INT_CLR, icr);
210+
211+ priv->status |= FALCON_I2C_BURST_REQ;
212+ }
213+
214+ /* last burst request */
215+ if (i_raw & I2C_RIS_LBREQ_INT_INTOCC) {
216+ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN, 0, imsc);
217+ i2c_w32_mask(0, I2C_ICR_LBREQ_INT_CLR, icr);
218+
219+ priv->status |= FALCON_I2C_BURST_REQ;
220+ }
221+
222+ if (old_status != (unsigned int)priv->status)
223+ complete(&priv->done);
224+
225+ spin_unlock_irqrestore(&priv->lock, flags);
226+
227+ return IRQ_HANDLED;
228+}
229+
230+static int falcon_i2c_ready(struct falcon_i2c *priv)
231+{
232+ int timeout;
233+ u32 bus_stat;
234+ unsigned long flags;
235+ int ret;
236+
237+ for (timeout = 0; timeout < FALCON_I2C_READY_TIMEOUT; timeout++) {
238+ bus_stat = i2c_r32(bus_stat);
239+
240+ if (bus_stat & I2C_BUS_STAT_BS_SC) {
241+ cpu_relax();
242+ } else {
243+ spin_lock_irqsave(&priv->lock, flags);
244+
245+ if (FALCON_I2C_ERROR(priv)) {
246+ ret = priv->status;
247+
248+ dev_dbg(priv->dev, "bus ready wait error 0x%08lx\n", priv->status);
249+
250+ FALCON_I2C_ERROR_CLEAR(priv);
251+ } else {
252+ ret = 0;
253+ }
254+
255+ spin_unlock_irqrestore(&priv->lock, flags);
256+
257+ return ret;
258+ }
259+ }
260+
261+ dev_dbg(priv->dev, "bus ready wait timeout\n");
262+
263+ return -ETIME;
264+}
265+
266+static int falcon_i2c_wait(struct falcon_i2c *priv, unsigned long status)
267+{
268+ int ret = 0;
269+ unsigned long flags;
270+ unsigned int timeout;
271+
272+ spin_lock_irqsave(&priv->lock, flags);
273+
274+ priv->status &= FALCON_I2C_BURST_REQ;
275+
276+ /* check if the event already occurred */
277+ if ((priv->status & status) == status) {
278+ priv->status &= ~status;
279+ spin_unlock_irqrestore(&priv->lock, flags);
280+
281+ return 0;
282+ }
283+
284+ spin_unlock_irqrestore(&priv->lock, flags);
285+
286+ /* unmask burst interrupts */
287+ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
288+
289+ for (timeout = 0; timeout < FALCON_I2C_WAIT_TIMEOUT; timeout++) {
290+ /* wait for the data request */
291+ wait_for_completion_timeout(&priv->done, HZ / 10);
292+
293+ /* handle errors */
294+ spin_lock_irqsave(&priv->lock, flags);
295+
296+ if (FALCON_I2C_ERROR(priv)) {
297+ dev_dbg(priv->dev, "wait error 0x%08lx (waiting for 0x%08lx)\n",
298+ priv->status,
299+ status);
300+
301+ if (priv->status & FALCON_I2C_NACK)
302+ ret = -ENXIO;
303+ else
304+ ret = -EREMOTEIO;
305+
306+ FALCON_I2C_ERROR_CLEAR(priv);
307+ } else {
308+ if ((priv->status & status) == status) {
309+ priv->status &= ~status;
310+ spin_unlock_irqrestore(&priv->lock, flags);
311+
312+ return 0;
313+ }
314+ }
315+
316+ spin_unlock_irqrestore(&priv->lock, flags);
317+
318+ if (ret)
319+ return ret;
320+ }
321+
322+ dev_dbg(priv->dev, "wait timeout error 0x%08lx (waiting for 0x%08lx)\n",
323+ priv->status,
324+ status);
325+
326+ return -ETIME;
327+}
328+
329+static int falcon_i2c_tx(struct falcon_i2c *priv, int ten_bit, u16 addr,
330+ u8 *buf, int len)
331+{
332+ int i;
333+ int ret;
334+
335+ dev_dbg(priv->dev, "%s\n", __func__);
336+
337+ /* tell fifo the number of bytes we are going to send */
338+ i2c_w32(len + (ten_bit ? 2 : 1), tps_ctrl);
339+
340+ /* wait for the data request */
341+ ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
342+ if (ret)
343+ return ret;
344+
345+ /* send slave address */
346+ if (ten_bit) {
347+ i2c_w32(0x78 | ((addr >> 7) & 0x7), txd);
348+ i2c_w32(0x78 | ((addr & 0x7f) << 1) | 0, txd);
349+ } else {
350+ i2c_w32((addr << 1) | 0, txd);
351+ }
352+
353+ /* fill fifo */
354+ for (i = 0; i < len; i++) {
355+ ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
356+ if (ret)
357+ return ret;
358+
359+ i2c_w32(buf[i], txd);
360+ }
361+
362+ return falcon_i2c_wait(priv, FALCON_I2C_TX_END);
363+}
364+
365+static int falcon_i2c_rx(struct falcon_i2c *priv, int ten_bit, u16 addr,
366+ u8 *buf, int len)
367+{
368+ int i;
369+ int ret;
370+
371+ dev_dbg(priv->dev, "%s\n", __func__);
372+
373+ /* we need to transmit address only */
374+ i2c_w32(ten_bit ? 2 : 1, tps_ctrl);
375+
376+ /* set maximum received packet size */
377+ i2c_w32(len, mrps_ctrl);
378+
379+ /* wait for the data request */
380+ ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
381+ if (ret)
382+ return ret;
383+
384+ /* write down the address */
385+ if (ten_bit) {
386+ i2c_w32(0x78 | ((addr >> 7) & 0x7), txd);
387+ i2c_w32(0x78 | ((addr & 0x7f) << 1) | 1, txd);
388+ } else {
389+ i2c_w32((addr << 1) | 1, txd);
390+ }
391+
392+ /* wait for the read request */
393+ ret = falcon_i2c_wait(priv, FALCON_I2C_TX_END
394+#ifndef FALCON_FIX_ME
395+ | FALCON_I2C_ADDR_MATCH
396+#endif
397+ | FALCON_I2C_RX);
398+
399+ if (ret)
400+ return ret;
401+
402+ /* read bytes */
403+ for (i = 0; i < len; i++) {
404+#ifdef FALCON_FIX_ME
405+ while (i2c_r32(rps_stat) == 0)
406+ cpu_relax();
407+#else
408+ ret = falcon_i2c_wait(priv, FALCON_I2C_BURST_REQ);
409+
410+ if (ret)
411+ return ret;
412+#endif
413+
414+ buf[i] = i2c_r32(rxd);
415+ }
416+
417+#ifndef FALCON_FIX_ME
418+ /* wait for transmission end */
419+ return falcon_i2c_wait(priv, FALCON_I2C_TX_END);
420+#else
421+ return 0;
422+#endif
423+}
424+
425+static int falcon_i2c_xfer_msg(struct falcon_i2c *priv, struct i2c_msg *msg)
426+{
427+ int ret;
428+ int ten_bit;
429+ unsigned long flags;
430+
431+ dev_dbg(priv->dev, "%s %u byte(s) %s 0x%02x\n",
432+ (msg->flags & I2C_M_RD) ? "read" : "write", msg->len,
433+ (msg->flags & I2C_M_RD) ? "from" : "to", msg->addr);
434+
435+ if (msg->flags & I2C_M_TEN)
436+ ten_bit = 1;
437+ else
438+ ten_bit = 0;
439+
440+ /* reconfigure bus if need to send message in different address mode */
441+ spin_lock_irqsave(&priv->lock, flags);
442+ if (ten_bit != priv->ten_bit) {
443+
444+ /* disable bus */
445+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
446+
447+ /* reconfigure address */
448+ falcon_addr_configure(priv, ten_bit);
449+
450+ /* enable bus */
451+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
452+
453+ priv->ten_bit = ten_bit;
454+ }
455+ spin_unlock_irqrestore(&priv->lock, flags);
456+
457+ /* read/write actual message */
458+ if (msg->flags & I2C_M_RD)
459+ ret = falcon_i2c_rx(priv, ten_bit, msg->addr, msg->buf,
460+ msg->len);
461+ else
462+ ret = falcon_i2c_tx(priv, ten_bit, msg->addr, msg->buf,
463+ msg->len);
464+
465+ if (ret)
466+ return ret;
467+
468+ return 0;
469+}
470+
471+static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
472+ int num)
473+{
474+ int i;
475+ int ret;
476+ unsigned long flags;
477+ struct falcon_i2c *priv = i2c_get_adapdata(adap);
478+
479+ dev_dbg(priv->dev, "xfer %u messages\n", num);
480+
481+ /* transfer each message */
482+ for (i = 0; i < num; i++) {
483+#ifdef FALCON_FIX_ME
484+ /* disable bus */
485+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
486+ /* enable bus */
487+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
488+#endif
489+
490+ /* clear bus status */
491+ spin_lock_irqsave(&priv->lock, flags);
492+ priv->status = 0;
493+ spin_unlock_irqrestore(&priv->lock, flags);
494+
495+ /* wait for the bus to become ready */
496+ ret = falcon_i2c_ready(priv);
497+ if (ret)
498+ return ret;
499+
500+ /* transfer message */
501+ ret = falcon_i2c_xfer_msg(priv, &msg[i]);
502+
503+ if (ret)
504+ return ret;
505+
506+ /* check for unhandled errors */
507+ spin_lock_irqsave(&priv->lock, flags);
508+ if (FALCON_I2C_ERROR(priv))
509+ ret = priv->status;
510+ spin_unlock_irqrestore(&priv->lock, flags);
511+
512+ if (ret) {
513+ dev_warn(priv->dev, "message %u unhandled error 0x%x\n",
514+ i, ret);
515+
516+ return ret;
517+ }
518+ }
519+
520+ return 0;
521+}
522+
523+static u32 falcon_i2c_func(struct i2c_adapter *adap)
524+{
525+ return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
526+}
527+
528+static struct i2c_algorithm falcon_i2c_algorithm = {
529+ .master_xfer = falcon_i2c_xfer,
530+ .functionality = falcon_i2c_func,
531+};
532+
533+static int falcon_i2c_hw_init(struct i2c_adapter *adap)
534+{
535+ struct falcon_i2c *priv = i2c_get_adapdata(adap);
536+
537+ /* disable bus */
538+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
539+
540+ /* set normal operation clock divider */
541+ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
542+
543+ /* set frequency */
544+ if (priv->mode == FALCON_I2C_MODE_100) {
545+ dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
546+
547+ i2c_w32(0, fdiv_high_cfg);
548+
549+ i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET)
550+ | (499 << I2C_FDIV_CFG_DEC_OFFSET),
551+ fdiv_cfg);
552+ } else if (priv->mode == FALCON_I2C_MODE_400) {
553+ dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
554+
555+ i2c_w32(0, fdiv_high_cfg);
556+
557+ i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET)
558+ | (124 << I2C_FDIV_CFG_DEC_OFFSET),
559+ fdiv_cfg);
560+ } else if (priv->mode == FALCON_I2C_MODE_3400) {
561+ dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
562+
563+ i2c_w32(0, fdiv_cfg);
564+
565+ /* TODO recalculate value for 100MHz input */
566+ i2c_w32((41 << I2C_FDIV_CFG_INC_OFFSET)
567+ | (152 << I2C_FDIV_CFG_DEC_OFFSET),
568+ fdiv_high_cfg);
569+ } else {
570+ dev_warn(priv->dev, "unknown mode\n");
571+
572+ return -ENODEV;
573+ }
574+
575+ /* configure fifo */
576+ i2c_w32(I2C_FIFO_CFG_TXFC /* tx fifo as flow controller */
577+ | I2C_FIFO_CFG_RXFC /* rx fifo as flow controller */
578+ | I2C_FIFO_CFG_TXFA_TXFA2 /* tx fifo 4-byte aligned */
579+ | I2C_FIFO_CFG_RXFA_RXFA2 /* rx fifo 4-byte aligned */
580+ | I2C_FIFO_CFG_TXBS_TXBS0 /* tx fifo burst size is 1 word */
581+ | I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
582+ fifo_cfg);
583+
584+ /* configure address */
585+ falcon_addr_configure(priv, priv->ten_bit);
586+
587+ /* enable bus */
588+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
589+
590+ /* mask burst interrupts */
591+ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
592+
593+ /* enable interrupts */
594+ i2c_w32(I2C_IMSC_LBREQ_INT_EN
595+ | I2C_IMSC_BREQ_INT_EN
596+ | I2C_IMSC_I2C_P_INT_EN
597+ | I2C_IMSC_I2C_ERR_INT_EN,
598+ imsc);
599+
600+ return 0;
601+}
602+
603+static int __devinit falcon_i2c_probe(struct platform_device *pdev)
604+{
605+ int ret = 0;
606+ struct falcon_i2c *priv;
607+ struct i2c_adapter *adap;
608+ struct resource *mmres, *ioarea,
609+ *irqres_lb, *irqres_b, *irqres_err, *irqres_p;
610+ struct clk *clk;
611+
612+ dev_dbg(&pdev->dev, "probing\n");
613+
614+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
615+ irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
616+ "i2c_lb");
617+ irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
618+ irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
619+ "i2c_err");
620+ irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
621+
622+ if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
623+ dev_err(&pdev->dev, "no resources\n");
624+ return -ENODEV;
625+ }
626+
627+ clk = clk_get(&pdev->dev, "fpi");
628+ if (IS_ERR(clk)) {
629+ dev_err(&pdev->dev, "failed to get fpi clk\n");
630+ return -ENOENT;
631+ }
632+
633+ if (clk_get_rate(clk) != 100000000) {
634+ dev_err(&pdev->dev, "input clock is not 100MHz\n");
635+ return -ENOENT;
636+ }
637+
638+ /* allocate private data */
639+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
640+ if (!priv) {
641+ dev_err(&pdev->dev, "can't allocate private data\n");
642+ return -ENOMEM;
643+ }
644+
645+ adap = &priv->adap;
646+ i2c_set_adapdata(adap, priv);
647+ adap->owner = THIS_MODULE;
648+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
649+ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
650+ adap->algo = &falcon_i2c_algorithm;
651+
652+ priv->ten_bit = 0;
653+ priv->mode = FALCON_I2C_MODE_100;
654+ priv->clk = clk;
655+ priv->dev = &pdev->dev;
656+
657+ spin_lock_init(&priv->lock);
658+
659+ ioarea = request_mem_region(mmres->start, resource_size(mmres),
660+ pdev->name);
661+
662+ if (ioarea == NULL) {
663+ dev_err(&pdev->dev, "I2C region already claimed\n");
664+ ret = -ENXIO;
665+ goto err_free_priv;
666+ }
667+
668+ /* map memory */
669+ priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
670+ resource_size(mmres));
671+ if (priv->membase == NULL) {
672+ ret = -ENOMEM;
673+ goto err_release_region;
674+ }
675+
676+ priv->irq_lb = irqres_lb->start;
677+ ret = request_irq(priv->irq_lb, falcon_i2c_isr, IRQF_DISABLED,
678+ irqres_lb->name, priv);
679+ if (ret) {
680+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", irqres_lb->start);
681+ ret = -ENODEV;
682+ goto err_unmap_mem;
683+ }
684+
685+ priv->irq_b = irqres_b->start;
686+ ret = request_irq(priv->irq_b, falcon_i2c_isr, IRQF_DISABLED,
687+ irqres_b->name, priv);
688+ if (ret) {
689+ dev_err(&pdev->dev, "can't get burst IRQ %d\n", irqres_b->start);
690+ ret = -ENODEV;
691+ goto err_free_lb_irq;
692+ }
693+
694+ priv->irq_err = irqres_err->start;
695+ ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
696+ irqres_err->name, priv);
697+ if (ret) {
698+ dev_err(&pdev->dev, "can't get error IRQ %d\n", irqres_err->start);
699+ ret = -ENODEV;
700+ goto err_free_b_irq;
701+ }
702+
703+ priv->irq_p = irqres_p->start;
704+ ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
705+ irqres_p->name, priv);
706+ if (ret) {
707+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", irqres_p->start);
708+ ret = -ENODEV;
709+ goto err_free_err_irq;
710+ }
711+
712+ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
713+ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
714+ irqres_b->start, irqres_err->start, irqres_p->start);
715+
716+ /* add our adapter to the i2c stack */
717+ ret = i2c_add_numbered_adapter(adap);
718+ if (ret) {
719+ dev_err(&pdev->dev, "can't register I2C adapter\n");
720+ goto err_free_p_irq;
721+ }
722+
723+ platform_set_drvdata(pdev, priv);
724+ i2c_set_adapdata(adap, priv);
725+
726+ /* print module version information */
727+ dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
728+ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
729+ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
730+
731+ init_completion(&priv->done);
732+
733+ /* initialize HW */
734+ ret = falcon_i2c_hw_init(adap);
735+ if (ret) {
736+ dev_err(&pdev->dev, "can't configure adapter\n");
737+ goto err_remove_adapter;
738+ }
739+
740+ return 0;
741+
742+err_remove_adapter:
743+ i2c_del_adapter(adap);
744+ platform_set_drvdata(pdev, NULL);
745+
746+err_free_p_irq:
747+ free_irq(priv->irq_p, priv);
748+
749+err_free_err_irq:
750+ free_irq(priv->irq_err, priv);
751+
752+err_free_b_irq:
753+ free_irq(priv->irq_b, priv);
754+
755+err_free_lb_irq:
756+ free_irq(priv->irq_lb, priv);
757+
758+err_unmap_mem:
759+ iounmap(priv->membase);
760+
761+err_release_region:
762+ release_mem_region(mmres->start, resource_size(mmres));
763+
764+err_free_priv:
765+ kfree(priv);
766+
767+ return ret;
768+}
769+
770+static int __devexit falcon_i2c_remove(struct platform_device *pdev)
771+{
772+ struct falcon_i2c *priv = platform_get_drvdata(pdev);
773+ struct resource *mmres;
774+
775+ /* disable bus */
776+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
777+
778+ /* remove driver */
779+ platform_set_drvdata(pdev, NULL);
780+ i2c_del_adapter(&priv->adap);
781+
782+ free_irq(priv->irq_lb, priv);
783+ free_irq(priv->irq_b, priv);
784+ free_irq(priv->irq_err, priv);
785+ free_irq(priv->irq_p, priv);
786+
787+ kfree(priv);
788+
789+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
790+ release_mem_region(mmres->start, resource_size(mmres));
791+
792+ dev_dbg(&pdev->dev, "removed\n");
793+
794+ return 0;
795+}
796+
797+static struct platform_driver falcon_i2c_driver = {
798+ .probe = falcon_i2c_probe,
799+ .remove = __devexit_p(falcon_i2c_remove),
800+ .driver = {
801+ .name = DRV_NAME,
802+ .owner = THIS_MODULE,
803+ },
804+};
805+
806+static int __init falcon_i2c_init(void)
807+{
808+ int ret;
809+
810+ ret = platform_driver_register(&falcon_i2c_driver);
811+
812+ if (ret)
813+ printk(KERN_DEBUG DRV_NAME ": can't register platform driver");
814+
815+ return ret;
816+}
817+
818+static void __exit falcon_i2c_exit(void)
819+{
820+ platform_driver_unregister(&falcon_i2c_driver);
821+}
822+
823+module_init(falcon_i2c_init);
824+module_exit(falcon_i2c_exit);
825+
826+MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
827+MODULE_ALIAS("platform:i2c_falcon");
828+MODULE_LICENSE("GPL");
829

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