Root/target/linux/mpc83xx/patches-2.6.36/013-drivers_ata_pata_rbppc_cf.patch

1--- /dev/null
2+++ b/drivers/ata/pata_rbppc_cf.c
3@@ -0,0 +1,701 @@
4+/*
5+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
6+ * Copyright (C) Mikrotik 2007
7+ *
8+ * This program is free software; you can redistribute it and/or modify it
9+ * under the terms of the GNU General Public License as published by the
10+ * Free Software Foundation; either version 2 of the License, or (at your
11+ * option) any later version.
12+ */
13+
14+#include <linux/kernel.h>
15+#include <linux/module.h>
16+#include <linux/init.h>
17+#include <scsi/scsi_host.h>
18+#include <linux/libata.h>
19+#include <linux/of_platform.h>
20+#include <linux/ata_platform.h>
21+
22+#define DEBUG_UPM 0
23+
24+#define DRV_NAME "pata_rbppc_cf"
25+#define DRV_VERSION "0.0.2"
26+
27+#define DEV2SEL_OFFSET 0x00100000
28+
29+#define IMMR_LBCFG_OFFSET 0x00005000
30+#define IMMR_LBCFG_SIZE 0x00001000
31+
32+#define LOCAL_BUS_MCMR 0x00000078
33+#define MxMR_OP_MASK 0x30000000
34+#define MxMR_OP_NORMAL 0x00000000
35+#define MxMR_OP_WRITE 0x10000000
36+#define MxMR_OP_READ 0x20000000
37+#define MxMR_OP_RUN 0x30000000
38+#define MxMR_LUPWAIT_LOW 0x08000000
39+#define MxMR_LUPWAIT_HIGH 0x00000000
40+#define MxMR_LUPWAIT_ENABLE 0x00040000
41+#define MxMR_RLF_MASK 0x0003c000
42+#define MxMR_RLF_SHIFT 14
43+#define MxMR_WLF_MASK 0x00003c00
44+#define MxMR_WLF_SHIFT 10
45+#define MxMR_MAD_MASK 0x0000003f
46+#define LOCAL_BUS_MDR 0x00000088
47+#define LOCAL_BUS_LCRR 0x000000D4
48+#define LCRR_CLKDIV_MASK 0x0000000f
49+
50+#define LOOP_SIZE 4
51+
52+#define UPM_READ_SINGLE_OFFSET 0x00
53+#define UPM_WRITE_SINGLE_OFFSET 0x18
54+#define UPM_DATA_SIZE 0x40
55+
56+#define LBT_CPUIN_MIN 0
57+#define LBT_CPUOUT_MIN 1
58+#define LBT_CPUOUT_MAX 2
59+#define LBT_EXTDEL_MIN 3
60+#define LBT_EXTDEL_MAX 4
61+#define LBT_SIZE 5
62+
63+/* UPM machine configuration bits */
64+#define N_BASE 0x00f00000
65+#define N_CS 0xf0000000
66+#define N_CS_H1 0xc0000000
67+#define N_CS_H2 0x30000000
68+#define N_WE 0x0f000000
69+#define N_WE_H1 0x0c000000
70+#define N_WE_H2 0x03000000
71+#define N_OE 0x00030000
72+#define N_OE_H1 0x00020000
73+#define N_OE_H2 0x00010000
74+#define WAEN 0x00001000
75+#define REDO_2 0x00000100
76+#define REDO_3 0x00000200
77+#define REDO_4 0x00000300
78+#define LOOP 0x00000080
79+#define NA 0x00000008
80+#define UTA 0x00000004
81+#define LAST 0x00000001
82+
83+#define REDO_VAL(mult) (REDO_2 * ((mult) - 1))
84+#define REDO_MAX_MULT 4
85+
86+#define READ_BASE (N_BASE | N_WE)
87+#define WRITE_BASE (N_BASE | N_OE)
88+#define EMPTY (N_BASE | N_CS | N_OE | N_WE | LAST)
89+
90+#define EOF_UPM_SETTINGS 0
91+#define ANOTHER_TIMING 1
92+
93+#define OA_CPUIN_MIN 0x01
94+#define OA_CPUOUT_MAX 0x02
95+#define OD_CPUOUT_MIN 0x04
96+#define OA_CPUOUT_DELTA 0x06
97+#define OA_EXTDEL_MAX 0x08
98+#define OD_EXTDEL_MIN 0x10
99+#define OA_EXTDEL_DELTA 0x18
100+#define O_MIN_CYCLE_TIME 0x20
101+#define O_MINUS_PREV 0x40
102+#define O_HALF_CYCLE 0x80
103+
104+extern void __iomem *localbus_map(unsigned long addr, unsigned int len);
105+extern void localbus_unmap(void __iomem *addr);
106+
107+struct rbppc_cf_info {
108+ unsigned lbcfg_addr;
109+ unsigned clk_time_ps;
110+ int cur_mode;
111+ u32 lb_timings[LBT_SIZE];
112+};
113+static struct rbppc_cf_info *rbinfo = NULL;
114+
115+struct upm_setting {
116+ unsigned value;
117+ unsigned ns[7];
118+ unsigned clk_minus;
119+ unsigned group_size;
120+ unsigned options;
121+};
122+
123+static const struct upm_setting cfUpmReadSingle[] = {
124+ { READ_BASE | N_OE,
125+ /* t1 - ADDR setup time */
126+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
127+ OA_EXTDEL_MAX) },
128+ { READ_BASE | N_OE_H1,
129+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
130+ { READ_BASE,
131+ /* t2 - OE0 time */
132+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 2, (OA_CPUOUT_MAX |
133+ OA_CPUIN_MIN) },
134+ { READ_BASE | WAEN,
135+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
136+ { READ_BASE | UTA,
137+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
138+ { READ_BASE | N_OE,
139+ /* t9 - ADDR hold time */
140+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
141+ OD_EXTDEL_MIN) },
142+ { READ_BASE | N_OE | N_CS_H2,
143+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
144+ { READ_BASE | N_OE | N_CS,
145+ /* t6Z -IORD data tristate */
146+ { 30, 30, 30, 30, 30, 20, 20 }, 1, 1, O_MINUS_PREV },
147+ { ANOTHER_TIMING,
148+ /* t2i -IORD recovery time */
149+ { 0, 0, 0, 70, 25, 25, 20 }, 2, 0, 0 },
150+ { ANOTHER_TIMING,
151+ /* CS 0 -> 1 MAX */
152+ { 0, 0, 0, 0, 0, 0, 0 }, 1, 0, (OA_CPUOUT_DELTA |
153+ OA_EXTDEL_MAX) },
154+ { READ_BASE | N_OE | N_CS | LAST,
155+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
156+ { EOF_UPM_SETTINGS,
157+ /* min total cycle time - includes turnaround and ALE cycle */
158+ { 600, 383, 240, 180, 120, 100, 80 }, 2, 0, O_MIN_CYCLE_TIME },
159+};
160+
161+static const struct upm_setting cfUpmWriteSingle[] = {
162+ { WRITE_BASE | N_WE,
163+ /* t1 - ADDR setup time */
164+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
165+ OA_EXTDEL_MAX) },
166+ { WRITE_BASE | N_WE_H1,
167+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
168+ { WRITE_BASE,
169+ /* t2 - WE0 time */
170+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 1, OA_CPUOUT_DELTA },
171+ { WRITE_BASE | WAEN,
172+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
173+ { WRITE_BASE | N_WE,
174+ /* t9 - ADDR hold time */
175+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
176+ OD_EXTDEL_MIN) },
177+ { WRITE_BASE | N_WE | N_CS_H2,
178+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
179+ { WRITE_BASE | N_WE | N_CS,
180+ /* t4 - DATA hold time */
181+ { 30, 20, 15, 10, 10, 10, 10 }, 0, 1, O_MINUS_PREV },
182+ { ANOTHER_TIMING,
183+ /* t2i -IOWR recovery time */
184+ { 0, 0, 0, 70, 25, 25, 20 }, 1, 0, 0 },
185+ { ANOTHER_TIMING,
186+ /* CS 0 -> 1 MAX */
187+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, (OA_CPUOUT_DELTA |
188+ OA_EXTDEL_MAX) },
189+ { WRITE_BASE | N_WE | N_CS | UTA | LAST,
190+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
191+ /* min total cycle time - includes ALE cycle */
192+ { EOF_UPM_SETTINGS,
193+ { 600, 383, 240, 180, 120, 100, 80 }, 1, 0, O_MIN_CYCLE_TIME },
194+};
195+
196+static u8 rbppc_cf_check_status(struct ata_port *ap) {
197+ u8 val = ioread8(ap->ioaddr.status_addr);
198+ if (val == 0xF9)
199+ val = 0x7F;
200+ return val;
201+}
202+
203+static u8 rbppc_cf_check_altstatus(struct ata_port *ap) {
204+ u8 val = ioread8(ap->ioaddr.altstatus_addr);
205+ if (val == 0xF9)
206+ val = 0x7F;
207+ return val;
208+}
209+
210+static void rbppc_cf_dummy_noret(struct ata_port *ap) { }
211+static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; }
212+
213+static int ps2clk(int ps, unsigned clk_time_ps) {
214+ int psMaxOver;
215+ if (ps <= 0) return 0;
216+
217+ /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */
218+ psMaxOver = ps * 2 / 100;
219+ if (4 * psMaxOver > clk_time_ps) {
220+ psMaxOver = clk_time_ps / 4;
221+ }
222+ return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps;
223+}
224+
225+static int upm_gen_ps_table(const struct upm_setting *upm,
226+ int mode, struct rbppc_cf_info *info,
227+ int *psFinal) {
228+ int uidx;
229+ int lastUpmValIdx = 0;
230+ int group_start_idx = -1;
231+ int group_left_num = -1;
232+ int clk_time_ps = info->clk_time_ps;
233+
234+ for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) {
235+ const struct upm_setting *us = upm + uidx;
236+ unsigned opt = us->options;
237+ int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps;
238+
239+ if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN];
240+ if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN];
241+ if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX];
242+ if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN];
243+ if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX];
244+
245+ if (us->value == ANOTHER_TIMING) {
246+ /* use longest timing from alternatives */
247+ if (psFinal[lastUpmValIdx] < ps) {
248+ psFinal[lastUpmValIdx] = ps;
249+ }
250+ ps = 0;
251+ }
252+ else {
253+ if (us->group_size) {
254+ group_start_idx = uidx;
255+ group_left_num = us->group_size;
256+ }
257+ else if (group_left_num > 0) {
258+ /* group time is divided on all group members */
259+ int clk = ps2clk(ps, clk_time_ps);
260+ psFinal[group_start_idx] -= clk * clk_time_ps;
261+ --group_left_num;
262+ }
263+ if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) {
264+ int clk = ps2clk(psFinal[lastUpmValIdx],
265+ clk_time_ps);
266+ ps -= clk * clk_time_ps;
267+ }
268+ lastUpmValIdx = uidx;
269+ }
270+ psFinal[uidx] = ps;
271+ }
272+ return uidx;
273+}
274+
275+static int free_half(int ps, int clk, int clk_time_ps) {
276+ if (clk < 2) return 0;
277+ return (clk * clk_time_ps - ps) * 2 >= clk_time_ps;
278+}
279+
280+static void upm_gen_clk_table(const struct upm_setting *upm,
281+ int mode, int clk_time_ps,
282+ int max_uidx, const int *psFinal, int *clkFinal) {
283+ int clk_cycle_time;
284+ int clk_total;
285+ int uidx;
286+
287+ /* convert picoseconds to clocks */
288+ clk_total = 0;
289+ for (uidx = 0; uidx < max_uidx; ++uidx) {
290+ int clk = ps2clk(psFinal[uidx], clk_time_ps);
291+ clkFinal[uidx] = clk;
292+ clk_total += clk;
293+ }
294+
295+ /* check possibility of half cycle usage */
296+ for (uidx = 1; uidx < max_uidx - 1; ++uidx) {
297+ if ((upm[uidx].options & O_HALF_CYCLE) &&
298+ free_half(psFinal[uidx - 1], clkFinal[uidx - 1],
299+ clk_time_ps) &&
300+ free_half(psFinal[uidx + 1], clkFinal[uidx + 1],
301+ clk_time_ps)) {
302+ ++clkFinal[uidx];
303+ --clkFinal[uidx - 1];
304+ --clkFinal[uidx + 1];
305+ }
306+ }
307+
308+ if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return;
309+
310+ /* check cycle time, adjust timings if needed */
311+ clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) -
312+ upm[max_uidx].clk_minus);
313+ uidx = 0;
314+ while (clk_total < clk_cycle_time) {
315+ /* extend all timings in round-robin to match cycle time */
316+ if (clkFinal[uidx]) {
317+#if DEBUG_UPM
318+ printk(KERN_INFO "extending %u by 1 clk\n", uidx);
319+#endif
320+ ++clkFinal[uidx];
321+ ++clk_total;
322+ }
323+ ++uidx;
324+ if (uidx == max_uidx) uidx = 0;
325+ }
326+}
327+
328+static void add_data_val(unsigned val, int *clkLeft, int maxClk,
329+ unsigned *data, int *dataIdx) {
330+ if (*clkLeft == 0) return;
331+
332+ if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) {
333+ int times;
334+ int times1;
335+ int times2;
336+
337+ times = *clkLeft / LOOP_SIZE;
338+ if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2;
339+ times1 = times / 2;
340+ times2 = times - times1;
341+
342+ val |= LOOP;
343+ data[*dataIdx] = val | REDO_VAL(times1);
344+ ++(*dataIdx);
345+ data[*dataIdx] = val | REDO_VAL(times2);
346+ ++(*dataIdx);
347+
348+ *clkLeft -= times * LOOP_SIZE;
349+ return;
350+ }
351+
352+ if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT;
353+ if (*clkLeft < maxClk) maxClk = *clkLeft;
354+
355+ *clkLeft -= maxClk;
356+ val |= REDO_VAL(maxClk);
357+
358+ data[*dataIdx] = val;
359+ ++(*dataIdx);
360+}
361+
362+static int upm_gen_final_data(const struct upm_setting *upm,
363+ int max_uidx, int *clkFinal, unsigned *data) {
364+ int dataIdx;
365+ int uidx;
366+
367+ dataIdx = 0;
368+ for (uidx = 0; uidx < max_uidx; ++uidx) {
369+ int clk = clkFinal[uidx];
370+ while (clk > 0) {
371+ add_data_val(upm[uidx].value, &clk, 0,
372+ data, &dataIdx);
373+ }
374+ }
375+ return dataIdx;
376+}
377+
378+static int conv_upm_table(const struct upm_setting *upm,
379+ int mode, struct rbppc_cf_info *info,
380+ unsigned *data) {
381+#if DEBUG_UPM
382+ int uidx;
383+#endif
384+ int psFinal[32];
385+ int clkFinal[32];
386+ int max_uidx;
387+ int data_len;
388+
389+ max_uidx = upm_gen_ps_table(upm, mode, info, psFinal);
390+
391+ upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx,
392+ psFinal, clkFinal);
393+
394+#if DEBUG_UPM
395+ /* dump out debug info */
396+ for (uidx = 0; uidx < max_uidx; ++uidx) {
397+ if (clkFinal[uidx]) {
398+ printk(KERN_INFO "idx %d val %08x clk %d ps %d\n",
399+ uidx, upm[uidx].value,
400+ clkFinal[uidx], psFinal[uidx]);
401+ }
402+ }
403+#endif
404+
405+ data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data);
406+
407+#if DEBUG_UPM
408+ for (uidx = 0; uidx < data_len; ++uidx) {
409+ printk(KERN_INFO "cf UPM x result: idx %d val %08x\n",
410+ uidx, data[uidx]);
411+ }
412+#endif
413+ return 0;
414+}
415+
416+static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) {
417+ int i;
418+
419+ for (i = 0; i < UPM_DATA_SIZE; ++i) {
420+ data[i] = EMPTY;
421+ }
422+
423+ if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) {
424+ return -1;
425+ }
426+ if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) {
427+ return -1;
428+ }
429+ return 0;
430+}
431+
432+static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) {
433+ unsigned i;
434+ unsigned mxmr;
435+
436+ mxmr = in_be32(lbcfg_mxmr);
437+ mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK);
438+ mxmr |= (MxMR_OP_WRITE | offset);
439+ out_be32(lbcfg_mxmr, mxmr);
440+ in_be32(lbcfg_mxmr); /* flush MxMR write */
441+
442+ for (i = 0; i < len; ++i) {
443+ int to;
444+ unsigned data = upmData[i + offset];
445+ out_be32(lbcfg_mdr, data);
446+ in_be32(lbcfg_mdr); /* flush MDR write */
447+
448+ iowrite8(1, upmMemAddr); /* dummy write to any CF addr */
449+
450+ /* wait for dummy write to complete */
451+ for (to = 10000; to >= 0; --to) {
452+ mxmr = in_be32(lbcfg_mxmr);
453+ if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) {
454+ break;
455+ }
456+ if (to == 0) {
457+ printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i);
458+ }
459+ }
460+ }
461+ mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK);
462+ mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT));
463+ out_be32(lbcfg_mxmr, mxmr);
464+}
465+
466+static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) {
467+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
468+ void *lbcfgBase;
469+ unsigned upmData[UPM_DATA_SIZE];
470+
471+ if (gen_upm_data(mode, info, upmData)) {
472+ return -1;
473+ }
474+
475+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
476+
477+ rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE);
478+ iounmap(lbcfgBase);
479+ return 0;
480+}
481+
482+static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
483+{
484+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
485+ int mode = adev->pio_mode - XFER_PIO_0;
486+
487+ DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode);
488+ if (mode < 0) mode = 0;
489+ if (mode > 6) mode = 6;
490+
491+ if (info->cur_mode < 0 || info->cur_mode > mode) {
492+ if (rbppc_cf_update_piomode(ap, mode) == 0) {
493+ printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode);
494+ info->cur_mode = mode;
495+ }
496+ }
497+}
498+
499+static struct scsi_host_template rbppc_cf_sht = {
500+ ATA_BASE_SHT(DRV_NAME),
501+};
502+
503+static struct ata_port_operations rbppc_cf_port_ops = {
504+ .inherits = &ata_bmdma_port_ops,
505+
506+ .sff_check_status = rbppc_cf_check_status,
507+ .sff_check_altstatus = rbppc_cf_check_altstatus,
508+
509+ .set_piomode = rbppc_cf_set_piomode,
510+
511+ .port_start = rbppc_cf_dummy_ret0,
512+
513+ .sff_irq_clear = rbppc_cf_dummy_noret,
514+};
515+
516+static int rbppc_cf_init_info(struct of_device *pdev, struct rbppc_cf_info *info) {
517+ struct device_node *np;
518+ struct resource res;
519+ const u32 *u32ptr;
520+ void *lbcfgBase;
521+ void *lbcfg_lcrr;
522+ unsigned lbc_clk_khz;
523+ unsigned lbc_extra_divider = 1;
524+ unsigned ccb_freq_hz;
525+ unsigned lb_div;
526+
527+ u32ptr = of_get_property(pdev->node, "lbc_extra_divider", NULL);
528+ if (u32ptr && *u32ptr) {
529+ lbc_extra_divider = *u32ptr;
530+#if DEBUG_UPM
531+ printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n",
532+ lbc_extra_divider);
533+#endif
534+ }
535+
536+ np = of_find_node_by_type(NULL, "serial");
537+ if (!np) {
538+ printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n");
539+ return -1;
540+ }
541+ u32ptr = of_get_property(np, "clock-frequency", NULL);
542+ if (u32ptr == 0 || *u32ptr == 0) {
543+ printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n");
544+ of_node_put(np);
545+ return -1;
546+ }
547+ ccb_freq_hz = *u32ptr;
548+ of_node_put(np);
549+
550+ np = of_find_node_by_type(NULL, "soc");
551+ if (!np) {
552+ printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n");
553+ return -1;
554+ }
555+ if (of_address_to_resource(np, 0, &res)) {
556+ printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n");
557+ of_node_put(np);
558+ return -1;
559+ }
560+ info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET;
561+ of_node_put(np);
562+
563+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
564+ lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR;
565+ lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider;
566+ iounmap(lbcfgBase);
567+
568+ lbc_clk_khz = ccb_freq_hz / (1000 * lb_div);
569+ info->clk_time_ps = 1000000000 / lbc_clk_khz;
570+ printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
571+ lbc_clk_khz, info->clk_time_ps);
572+
573+ u32ptr = of_get_property(pdev->node, "lb-timings", NULL);
574+ if (u32ptr) {
575+ memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
576+#if DEBUG_UPM
577+ printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n",
578+ u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]);
579+#endif
580+ }
581+ info->cur_mode = -1;
582+ return 0;
583+}
584+
585+static int rbppc_cf_probe(struct of_device *pdev,
586+ const struct of_device_id *match)
587+{
588+ struct ata_host *host;
589+ struct ata_port *ap;
590+ struct rbppc_cf_info *info = NULL;
591+ struct resource res;
592+ void *baddr;
593+ const u32 *u32ptr;
594+ int irq_level = 0;
595+ int err = -ENOMEM;
596+
597+ printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n");
598+
599+ if (rbinfo == NULL) {
600+ info = kmalloc(sizeof(*info), GFP_KERNEL);
601+ if (info == NULL) {
602+ printk(KERN_ERR "rbppc_cf_probe: Out of memory\n");
603+ goto err_info;
604+ }
605+ memset(info, 0, sizeof(*info));
606+
607+ if (rbppc_cf_init_info(pdev, info)) {
608+ goto err_info;
609+ }
610+ rbinfo = info;
611+ }
612+
613+ u32ptr = of_get_property(pdev->node, "interrupt-at-level", NULL);
614+ if (u32ptr) {
615+ irq_level = *u32ptr;
616+ printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
617+ }
618+
619+ if (of_address_to_resource(pdev->node, 0, &res)) {
620+ printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
621+ goto err_info;
622+ }
623+
624+ host = ata_host_alloc(&pdev->dev, 1);
625+ if (!host)
626+ goto err_info;
627+
628+ baddr = localbus_map(res.start, res.end - res.start + 1);
629+ host->iomap = baddr;
630+ host->private_data = rbinfo;
631+
632+ ap = host->ports[0];
633+ ap->ops = &rbppc_cf_port_ops;
634+ ap->pio_mask = 0x7F; /* PIO modes 0-6 */
635+ ap->flags = ATA_FLAG_NO_LEGACY;
636+ ap->mwdma_mask = 0;
637+
638+ ap->ioaddr.cmd_addr = baddr;
639+ ata_sff_std_ports(&ap->ioaddr);
640+ ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14;
641+ ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
642+ ap->ioaddr.bmdma_addr = 0;
643+
644+ err = ata_host_activate(
645+ host,
646+ irq_of_parse_and_map(pdev->node, 0), ata_sff_interrupt,
647+ irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
648+ &rbppc_cf_sht);
649+ if (!err) return 0;
650+
651+ localbus_unmap(baddr);
652+err_info:
653+ if (info) {
654+ kfree(info);
655+ rbinfo = NULL;
656+ }
657+ return err;
658+}
659+
660+static int rbppc_cf_remove(struct of_device *pdev)
661+{
662+ struct device *dev = &pdev->dev;
663+ struct ata_host *host = dev_get_drvdata(dev);
664+
665+ if (host == NULL) return -1;
666+
667+ ata_host_detach(host);
668+ return 0;
669+}
670+
671+static struct of_device_id rbppc_cf_ids[] = {
672+ { .name = "cf", },
673+ { },
674+};
675+
676+static struct of_platform_driver rbppc_cf_driver = {
677+ .name = "cf",
678+ .probe = rbppc_cf_probe,
679+ .remove = rbppc_cf_remove,
680+ .match_table = rbppc_cf_ids,
681+ .driver = {
682+ .name = "rbppc-cf",
683+ .owner = THIS_MODULE,
684+ },
685+};
686+
687+static int __init rbppc_init(void)
688+{
689+ return of_register_platform_driver(&rbppc_cf_driver);
690+}
691+
692+static void __exit rbppc_exit(void)
693+{
694+ of_unregister_platform_driver(&rbppc_cf_driver);
695+}
696+
697+MODULE_AUTHOR("Mikrotikls SIA");
698+MODULE_AUTHOR("Noah Fontes");
699+MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver");
700+MODULE_LICENSE("GPL");
701+MODULE_VERSION(DRV_VERSION);
702+
703+module_init(rbppc_init);
704+module_exit(rbppc_exit);
705

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