| 1 | --- /dev/null |
| 2 | +++ b/arch/powerpc/boot/dts/rb333.dts |
| 3 | @@ -0,0 +1,432 @@ |
| 4 | + |
| 5 | +/* |
| 6 | + * RouterBOARD 333 series Device Tree Source |
| 7 | + * |
| 8 | + * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com> |
| 9 | + * Copyright 2009 Michael Guntsche <mike@it-loops.com> |
| 10 | + * |
| 11 | + * This program is free software; you can redistribute it and/or modify it |
| 12 | + * under the terms of the GNU General Public License as published by the |
| 13 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | + * option) any later version. |
| 15 | + * |
| 16 | + * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) |
| 17 | + * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1) |
| 18 | + * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0 |
| 19 | + * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0 |
| 20 | + * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property |
| 21 | + * |
| 22 | + */ |
| 23 | + |
| 24 | + |
| 25 | +/dts-v1/; |
| 26 | + |
| 27 | +/ { |
| 28 | + model = "RB333"; |
| 29 | + compatible = "MPC83xx"; |
| 30 | + #size-cells = <1>; |
| 31 | + #address-cells = <1>; |
| 32 | + |
| 33 | + |
| 34 | + aliases { |
| 35 | + ethernet0 = &enet0; |
| 36 | + ethernet1 = &enet1; |
| 37 | + ethernet2 = &enet2; |
| 38 | + pci0 = &pci0; |
| 39 | + }; |
| 40 | + |
| 41 | + |
| 42 | + chosen { |
| 43 | + bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1"; |
| 44 | + // linux,platform = <0x8062>; |
| 45 | + // linux,initrd = <0x488000 0x0>; |
| 46 | + linux,stdout-path = "/soc8323@e0000000/serial@4500"; |
| 47 | + // interrupt-controller = <&ipic>; |
| 48 | + }; |
| 49 | + |
| 50 | + cpus { |
| 51 | + #cpus = <1>; |
| 52 | + #size-cells = <0>; |
| 53 | + #address-cells = <1>; |
| 54 | + |
| 55 | + PowerPC,8323E@0 { |
| 56 | + device_type = "cpu"; |
| 57 | + reg = <0x0>; |
| 58 | + i-cache-size = <0x4000>; |
| 59 | + d-cache-size = <0x4000>; |
| 60 | + i-cache-line-size = <0x20>; |
| 61 | + d-cache-line-size = <0x20>; |
| 62 | + // clock-frequency = <0x13de3650>; |
| 63 | + // timebase-frequency = <0x1fc9f08>; |
| 64 | + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob |
| 65 | + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob |
| 66 | + 32-bit; |
| 67 | + }; |
| 68 | + }; |
| 69 | + |
| 70 | + memory { |
| 71 | + device_type = "memory"; |
| 72 | + reg = <0x0 0x4000000>; |
| 73 | + // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob |
| 74 | + }; |
| 75 | + |
| 76 | + flash { |
| 77 | + reg = <0xfe000000 0x20000>; |
| 78 | + }; |
| 79 | + |
| 80 | + nand { |
| 81 | + ale = <&gpio2 0x3>; |
| 82 | + cle = <&gpio2 0x2>; |
| 83 | + nce = <&gpio2 0x1>; |
| 84 | + rdy = <&gpio2 0x0>; |
| 85 | + reg = <0xf8000000 0x1000>; |
| 86 | + device_type = "rb,nand"; |
| 87 | + }; |
| 88 | + |
| 89 | + nnand { |
| 90 | + reg = <0xf0000000 0x1000>; |
| 91 | + }; |
| 92 | + |
| 93 | + voltage { |
| 94 | + voltage_gpio = <&gpio3 0x11>; |
| 95 | + }; |
| 96 | + |
| 97 | + fancon { |
| 98 | + interrupt-parent = <&ipic>; |
| 99 | + interrupts = <0x14 0x8>; |
| 100 | + fan_on = <&gpio0 0x10>; |
| 101 | + }; |
| 102 | + |
| 103 | + pci0: pci@e0008500 { |
| 104 | + device_type = "pci"; |
| 105 | + // compatible = "83xx"; |
| 106 | + compatible = "fsl,mpc8349-pci"; |
| 107 | + reg = <0xe0008500 0x100 0xe0008300 0x8>; |
| 108 | + #address-cells = <3>; |
| 109 | + #size-cells = <2>; |
| 110 | + #interrupt-cells = <1>; |
| 111 | + // clock-frequency = <0>; |
| 112 | + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>; |
| 113 | + bus-range = <0x0 0x0>; |
| 114 | + interrupt-map = < |
| 115 | + /* IDSEL 0x10 AD16 miniPCI slot 0 */ |
| 116 | + 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8 |
| 117 | + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8 |
| 118 | + |
| 119 | + /* IDSEL 0x11 AD17 miniPCI slot 1 */ |
| 120 | + 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8 |
| 121 | + 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8 |
| 122 | + |
| 123 | + /* IDSEL 0x12 AD18 miniPCI slot 2 */ |
| 124 | + 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8 |
| 125 | + 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>; |
| 126 | + |
| 127 | + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 128 | + interrupt-parent = <&ipic>; |
| 129 | + // interrupts = <66 0x8>; |
| 130 | + }; |
| 131 | + |
| 132 | + |
| 133 | + qe@e0100000 { |
| 134 | + reg = <0xe0100000 0x480>; |
| 135 | + ranges = <0x0 0xe0100000 0x100000>; |
| 136 | + model = "QE"; |
| 137 | + device_type = "qe"; |
| 138 | + compatible = "fsl,qe"; |
| 139 | + #size-cells = <1>; |
| 140 | + #address-cells = <1>; |
| 141 | + brg-frequency = <0>; |
| 142 | + bus-frequency = <0>; |
| 143 | + // bus-frequency = <198000000>; |
| 144 | + fsl,qe-num-riscs = <1>; |
| 145 | + fsl,qe-num-snums = <28>; |
| 146 | + |
| 147 | + qeic: qeic@80 { |
| 148 | + interrupt-controller; |
| 149 | + compatible = "fsl,qe-ic"; |
| 150 | + big-endian; |
| 151 | + built-in; |
| 152 | + reg = <0x80 0x80>; |
| 153 | + #interrupt-cells = <1>; |
| 154 | + #address-cells = <0>; |
| 155 | + device_type = "qeic"; |
| 156 | + interrupts = <0x20 0x8 0x21 0x8>; |
| 157 | + interrupt-parent = <&ipic>; |
| 158 | + }; |
| 159 | + |
| 160 | + mdio@2120 { |
| 161 | + compatible = "ucc_geth_phy"; |
| 162 | + device_type = "mdio"; |
| 163 | + reg = <0x3120 0x18>; |
| 164 | + #size-cells = <0>; |
| 165 | + #address-cells = <1>; |
| 166 | + |
| 167 | + phy3: ethernet-phy@03 { |
| 168 | + // interface = <0x3>; |
| 169 | + device_type = "ethernet-phy"; |
| 170 | + reg = <0x3>; |
| 171 | + }; |
| 172 | + |
| 173 | + phy2: ethernet-phy@02 { |
| 174 | + // interface = <0x3>; |
| 175 | + device_type = "ethernet-phy"; |
| 176 | + reg = <0x2>; |
| 177 | + }; |
| 178 | + |
| 179 | + phy1: ethernet-phy@01 { |
| 180 | + // interface = <0x3>; |
| 181 | + device_type = "ethernet-phy"; |
| 182 | + reg = <0x1>; |
| 183 | + }; |
| 184 | + }; |
| 185 | + |
| 186 | + enet0: ucc@2200 { |
| 187 | + tx-clock = <0x1a>; |
| 188 | + rx-clock = <0x1f>; |
| 189 | + mac-address = [00 0c 42 1c 29 d2]; |
| 190 | + interrupt-parent = <&qeic>; |
| 191 | + interrupts = <0x22>; |
| 192 | + reg = <0x2200 0x200>; |
| 193 | + device-id = <0x3>; |
| 194 | + model = "UCC"; |
| 195 | + compatible = "ucc_geth"; |
| 196 | + device_type = "network"; |
| 197 | + phy-handle = <&phy2>; |
| 198 | + pio-handle = <&pio3>; |
| 199 | + }; |
| 200 | + |
| 201 | + enet1: ucc@3200 { |
| 202 | + tx-clock = <0x22>; |
| 203 | + rx-clock = <0x20>; |
| 204 | + mac-address = [00 0c 42 1c 29 d1]; |
| 205 | + interrupt-parent = <&qeic>; |
| 206 | + interrupts = <0x23>; |
| 207 | + reg = <0x3200 0x200>; |
| 208 | + device-id = <0x4>; |
| 209 | + model = "UCC"; |
| 210 | + compatible = "ucc_geth"; |
| 211 | + device_type = "network"; |
| 212 | + phy-handle = <&phy3>; |
| 213 | + pio-handle = <&pio4>; |
| 214 | + }; |
| 215 | + |
| 216 | + enet2: ucc@3000 { |
| 217 | + tx-clock = <0x18>; |
| 218 | + rx-clock = <0x17>; |
| 219 | + mac-address = [00 0c 42 1c 29 d0]; |
| 220 | + interrupt-parent = <&qeic>; |
| 221 | + interrupts = <0x21>; |
| 222 | + reg = <0x3000 0x200>; |
| 223 | + device-id = <0x2>; |
| 224 | + model = "UCC"; |
| 225 | + compatible = "ucc_geth"; |
| 226 | + device_type = "network"; |
| 227 | + phy-handle = <&phy1>; |
| 228 | + pio-handle = <&pio2>; |
| 229 | + }; |
| 230 | + |
| 231 | + spi@500 { |
| 232 | + mode = "cpu"; |
| 233 | + interrupt-parent = <&qeic>; |
| 234 | + interrupts = <0x1>; |
| 235 | + reg = <0x500 0x40>; |
| 236 | + compatible = "fsl,spi"; |
| 237 | + device_type = "spi"; |
| 238 | + }; |
| 239 | + |
| 240 | + spi@4c0 { |
| 241 | + mode = "cpu"; |
| 242 | + interrupt-parent = <&qeic>; |
| 243 | + interrupts = <0x2>; |
| 244 | + reg = <0x4c0 0x40>; |
| 245 | + compatible = "fsl,spi"; |
| 246 | + device_type = "spi"; |
| 247 | + }; |
| 248 | + |
| 249 | + muram@10000 { |
| 250 | + #address-cells = <1>; |
| 251 | + #size-cells = <1>; |
| 252 | + compatible = "fsl,qe-muram", "fsl,cpm-muram"; |
| 253 | + ranges = <0x0 0x10000 0x4000>; |
| 254 | + device_type = "muram"; |
| 255 | + |
| 256 | + data-only@0 { |
| 257 | + compatible = "fsl,qe-muram-data", |
| 258 | + "fsl,cpm-muram-data"; |
| 259 | + reg = <0x0 0x4000>; |
| 260 | + }; |
| 261 | + }; |
| 262 | + }; |
| 263 | + |
| 264 | + |
| 265 | + soc8323@e0000000 { |
| 266 | + bus-frequency = <0x1>; |
| 267 | + reg = <0xe0000000 0x200>; |
| 268 | + ranges = <0x0 0xe0000000 0x100000>; |
| 269 | + device_type = "soc"; |
| 270 | + compatible = "simple-bus"; |
| 271 | + #interrupt-cells = <0x2>; |
| 272 | + #size-cells = <1>; |
| 273 | + #address-cells = <1>; |
| 274 | + |
| 275 | + beeper { |
| 276 | + gpio = <&gpio3 0x12>; |
| 277 | + reg = <0x500 0x100>; |
| 278 | + interrupt-parent = <&ipic>; |
| 279 | + interrupts = <0x48 0x8>; |
| 280 | + }; |
| 281 | + |
| 282 | + gpio3: gpio@3 { |
| 283 | + reg = <0x144c 0x4>; |
| 284 | + device-id = <0x3>; |
| 285 | + compatible = "qe_gpio"; |
| 286 | + device_type = "gpio"; |
| 287 | + }; |
| 288 | + |
| 289 | + gpio2: gpio@2 { |
| 290 | + reg = <0x1434 0x4>; |
| 291 | + device-id = <0x2>; |
| 292 | + compatible = "qe_gpio"; |
| 293 | + device_type = "gpio"; |
| 294 | + }; |
| 295 | + |
| 296 | + gpio0: gpio@0 { |
| 297 | + reg = <0x1404 0x4>; |
| 298 | + device-id = <0x0>; |
| 299 | + compatible = "qe_gpio"; |
| 300 | + device_type = "gpio"; |
| 301 | + }; |
| 302 | + |
| 303 | + par_io@1400 { |
| 304 | + num-ports = <4>; |
| 305 | + device_type = "par_io"; |
| 306 | + reg = <0x1400 0x100>; |
| 307 | + |
| 308 | + pio4: ucc_pin@04 { |
| 309 | + pio-map = < |
| 310 | + /* port pin dir open_drain assignment has_irq */ |
| 311 | + 1 18 1 0 1 0 |
| 312 | + 1 19 1 0 1 0 |
| 313 | + 1 20 1 0 1 0 |
| 314 | + 1 21 1 0 1 0 |
| 315 | + 1 30 1 0 1 0 |
| 316 | + 3 20 2 0 1 0 |
| 317 | + 1 30 2 0 1 0 |
| 318 | + 1 31 2 0 1 0 |
| 319 | + 1 22 2 0 1 0 |
| 320 | + 1 23 2 0 1 0 |
| 321 | + 1 24 2 0 1 0 |
| 322 | + 1 25 2 0 1 0 |
| 323 | + 1 28 2 0 1 0 |
| 324 | + 1 26 2 0 1 0 |
| 325 | + 3 21 2 0 1 0>; |
| 326 | + }; |
| 327 | + |
| 328 | + pio3: ucc_pin@03 { |
| 329 | + pio-map = < |
| 330 | + /* port pin dir open_drain assignment has_irq */ |
| 331 | + 1 0 1 0 1 0 |
| 332 | + 1 1 1 0 1 0 |
| 333 | + 1 2 1 0 1 0 |
| 334 | + 1 3 1 0 1 0 |
| 335 | + 1 12 1 0 1 0 |
| 336 | + 3 24 2 0 1 0 |
| 337 | + 1 11 2 0 1 0 |
| 338 | + 1 13 2 0 1 0 |
| 339 | + 1 4 2 0 1 0 |
| 340 | + 1 5 2 0 1 0 |
| 341 | + 1 6 2 0 1 0 |
| 342 | + 1 7 2 0 1 0 |
| 343 | + 1 10 2 0 1 0 |
| 344 | + 1 8 2 0 1 0 |
| 345 | + 3 29 2 0 1 0>; |
| 346 | + }; |
| 347 | + |
| 348 | + pio2: ucc_pin@02 { |
| 349 | + pio-map = < |
| 350 | + /* port pin dir open_drain assignment has_irq */ |
| 351 | + 3 4 3 0 2 0 |
| 352 | + 3 5 1 0 2 0 |
| 353 | + 0 18 1 0 1 0 |
| 354 | + 0 19 1 0 1 0 |
| 355 | + 0 20 1 0 1 0 |
| 356 | + 0 21 1 0 1 0 |
| 357 | + 0 30 1 0 1 0 |
| 358 | + 3 6 2 0 1 0 |
| 359 | + 0 29 2 0 1 0 |
| 360 | + 0 31 2 0 1 0 |
| 361 | + 0 22 2 0 1 0 |
| 362 | + 0 23 2 0 1 0 |
| 363 | + 0 24 2 0 1 0 |
| 364 | + 0 25 2 0 1 0 |
| 365 | + 0 28 2 0 1 0 |
| 366 | + 0 26 2 0 1 0 |
| 367 | + 3 31 2 0 1 0>; |
| 368 | + }; |
| 369 | + }; |
| 370 | + |
| 371 | + ipic: pic@700 { |
| 372 | + device_type = "ipic"; |
| 373 | + built-in; |
| 374 | + reg = <0x700 0x100>; |
| 375 | + #interrupt-cells = <0x2>; |
| 376 | + #address-cells = <0x0>; |
| 377 | + interrupt-controller; |
| 378 | + }; |
| 379 | + |
| 380 | + |
| 381 | + serial@4500 { |
| 382 | + interrupt-parent = <&ipic>; |
| 383 | + interrupts = <0x9 0x8>; |
| 384 | + clock-frequency = <0x7f27c20>; |
| 385 | + reg = <0x4500 0x100>; |
| 386 | + compatible = "ns16550"; |
| 387 | + device_type = "serial"; |
| 388 | + }; |
| 389 | + |
| 390 | + dma@82a8 { |
| 391 | + #address-cells = <1>; |
| 392 | + #size-cells = <1>; |
| 393 | + compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; |
| 394 | + reg = <0x82a8 4>; |
| 395 | + ranges = <0 0x8100 0x1a8>; |
| 396 | + interrupt-parent = <&ipic>; |
| 397 | + interrupts = <71 8>; |
| 398 | + cell-index = <0>; |
| 399 | + dma-channel@0 { |
| 400 | + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; |
| 401 | + reg = <0 0x80>; |
| 402 | + cell-index = <0>; |
| 403 | + interrupt-parent = <&ipic>; |
| 404 | + interrupts = <71 8>; |
| 405 | + }; |
| 406 | + dma-channel@80 { |
| 407 | + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; |
| 408 | + reg = <0x80 0x80>; |
| 409 | + cell-index = <1>; |
| 410 | + interrupt-parent = <&ipic>; |
| 411 | + interrupts = <71 8>; |
| 412 | + }; |
| 413 | + dma-channel@100 { |
| 414 | + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; |
| 415 | + reg = <0x100 0x80>; |
| 416 | + cell-index = <2>; |
| 417 | + interrupt-parent = <&ipic>; |
| 418 | + interrupts = <71 8>; |
| 419 | + }; |
| 420 | + dma-channel@180 { |
| 421 | + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; |
| 422 | + reg = <0x180 0x28>; |
| 423 | + cell-index = <3>; |
| 424 | + interrupt-parent = <&ipic>; |
| 425 | + interrupts = <71 8>; |
| 426 | + }; |
| 427 | + }; |
| 428 | + |
| 429 | + wdt@200 { |
| 430 | + reg = <0x200 0x100>; |
| 431 | + compatible = "mpc83xx_wdt"; |
| 432 | + device_type = "watchdog"; |
| 433 | + }; |
| 434 | + }; |
| 435 | +}; |
| 436 | |
