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Root/target/linux/omap35xx/patches-2.6.32/002-OMAP.patch

1	--- a/arch/arm/Kconfig
2	+++ b/arch/arm/Kconfig
3	@@ -1511,6 +1511,10 @@ source "net/Kconfig"
4
5	source "drivers/Kconfig"
6
7	+if ARCH_OMAP
8	+source "drivers/cbus/Kconfig"
9	+endif
10	+
11	source "fs/Kconfig"
12
13	source "arch/arm/Kconfig.debug"
14	--- a/arch/arm/mach-omap1/board-fsample.c
15	+++ b/arch/arm/mach-omap1/board-fsample.c
16	@@ -107,7 +107,7 @@ static struct resource smc91x_resources[
17	.flags = IORESOURCE_MEM,
18	},
19	[1] = {
20	- .start = INT_730_MPU_EXT_NIRQ,
21	+ .start = INT_7XX_MPU_EXT_NIRQ,
22	.end = 0,
23	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
24	},
25	@@ -196,8 +196,8 @@ static struct platform_device smc91x_dev
26
27	static struct resource kp_resources[] = {
28	[0] = {
29	- .start = INT_730_MPUIO_KEYPAD,
30	- .end = INT_730_MPUIO_KEYPAD,
31	+ .start = INT_7XX_MPUIO_KEYPAD,
32	+ .end = INT_7XX_MPUIO_KEYPAD,
33	.flags = IORESOURCE_IRQ,
34	},
35	};
36	@@ -309,7 +309,7 @@ static void __init omap_fsample_map_io(v
37	/*
38	* Hold GSM Reset until needed
39	*/
40	- omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
41	+ omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
42
43	/*
44	* UARTs -> done automagically by 8250 driver
45	@@ -320,21 +320,21 @@ static void __init omap_fsample_map_io(v
46	*/
47
48	/* Flash: CS0 timings setup */
49	- omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
50	- omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
51	+ omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
52	+ omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
53
54	/*
55	* Ethernet support through the debug board
56	* CS1 timings setup
57	*/
58	- omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
59	- omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
60	+ omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
61	+ omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
62
63	/*
64	* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
65	* It is used as the Ethernet controller interrupt
66	*/
67	- omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
68	+ omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
69	}
70
71	MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
72	--- a/arch/arm/mach-omap1/board-perseus2.c
73	+++ b/arch/arm/mach-omap1/board-perseus2.c
74	@@ -74,7 +74,7 @@ static struct resource smc91x_resources[
75	.flags = IORESOURCE_MEM,
76	},
77	[1] = {
78	- .start = INT_730_MPU_EXT_NIRQ,
79	+ .start = INT_7XX_MPU_EXT_NIRQ,
80	.end = 0,
81	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
82	},
83	@@ -163,8 +163,8 @@ static struct platform_device smc91x_dev
84
85	static struct resource kp_resources[] = {
86	[0] = {
87	- .start = INT_730_MPUIO_KEYPAD,
88	- .end = INT_730_MPUIO_KEYPAD,
89	+ .start = INT_7XX_MPUIO_KEYPAD,
90	+ .end = INT_7XX_MPUIO_KEYPAD,
91	.flags = IORESOURCE_IRQ,
92	},
93	};
94	@@ -270,7 +270,7 @@ static void __init omap_perseus2_map_io(
95	/*
96	* Hold GSM Reset until needed
97	*/
98	- omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
99	+ omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
100
101	/*
102	* UARTs -> done automagically by 8250 driver
103	@@ -281,21 +281,21 @@ static void __init omap_perseus2_map_io(
104	*/
105
106	/* Flash: CS0 timings setup */
107	- omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
108	- omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
109	+ omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
110	+ omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
111
112	/*
113	* Ethernet support through the debug board
114	* CS1 timings setup
115	*/
116	- omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
117	- omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
118	+ omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
119	+ omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
120
121	/*
122	* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
123	* It is used as the Ethernet controller interrupt
124	*/
125	- omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
126	+ omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
127	}
128
129	MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
130	--- a/arch/arm/mach-omap1/clock.c
131	+++ b/arch/arm/mach-omap1/clock.c
132	@@ -69,13 +69,13 @@ struct omap_clk {
133	}
134
135	#define CK_310 (1 << 0)
136	-#define CK_730 (1 << 1)
137	+#define CK_7XX (1 << 1)
138	#define CK_1510 (1 << 2)
139	#define CK_16XX (1 << 3)
140
141	static struct omap_clk omap_clks[] = {
142	/* non-ULPD clocks */
143	- CLK(NULL, "ck_ref", &ck_ref, CK_16XX \| CK_1510 \| CK_310),
144	+ CLK(NULL, "ck_ref", &ck_ref, CK_16XX \| CK_1510 \| CK_310 \| CK_7XX),
145	CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX \| CK_1510 \| CK_310),
146	/* CK_GEN1 clocks */
147	CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
148	@@ -83,7 +83,7 @@ static struct omap_clk omap_clks[] = {
149	CLK(NULL, "arm_ck", &arm_ck, CK_16XX \| CK_1510 \| CK_310),
150	CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX \| CK_1510 \| CK_310),
151	CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 \| CK_310),
152	- CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX \| CK_1510 \| CK_310),
153	+ CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX \| CK_1510 \| CK_310 \| CK_7XX),
154	CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX \| CK_1510 \| CK_310),
155	CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX \| CK_1510 \| CK_310),
156	CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
157	@@ -97,7 +97,7 @@ static struct omap_clk omap_clks[] = {
158	CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX \| CK_1510 \| CK_310),
159	CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX \| CK_1510 \| CK_310),
160	/* CK_GEN3 clocks */
161	- CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX \| CK_1510 \| CK_310 \| CK_730),
162	+ CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX \| CK_1510 \| CK_310 \| CK_7XX),
163	CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 \| CK_310),
164	CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX),
165	CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
166	@@ -108,7 +108,7 @@ static struct omap_clk omap_clks[] = {
167	CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 \| CK_310),
168	CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
169	CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
170	- CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX \| CK_730),
171	+ CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX \| CK_7XX),
172	CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 \| CK_310),
173	/* ULPD clocks */
174	CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 \| CK_310),
175	@@ -398,7 +398,7 @@ static int omap1_select_table_rate(struc
176	* Reprogramming the DPLL is tricky, it must be done from SRAM.
177	* (on 730, bit 13 must always be 1)
178	*/
179	- if (cpu_is_omap730())
180	+ if (cpu_is_omap7xx())
181	omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val \| 0x2000);
182	else
183	omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
184	@@ -783,8 +783,8 @@ int __init omap1_clk_init(void)
185	cpu_mask \|= CK_16XX;
186	if (cpu_is_omap1510())
187	cpu_mask \|= CK_1510;
188	- if (cpu_is_omap730())
189	- cpu_mask \|= CK_730;
190	+ if (cpu_is_omap7xx())
191	+ cpu_mask \|= CK_7XX;
192	if (cpu_is_omap310())
193	cpu_mask \|= CK_310;
194
195	@@ -800,7 +800,7 @@ int __init omap1_clk_init(void)
196	crystal_type = info->system_clock_type;
197	}
198
199	-#if defined(CONFIG_ARCH_OMAP730)
200	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
201	ck_ref.rate = 13000000;
202	#elif defined(CONFIG_ARCH_OMAP16XX)
203	if (crystal_type == 2)
204	@@ -847,7 +847,7 @@ int __init omap1_clk_init(void)
205	printk(KERN_ERR "System frequencies not set. Check your config.\n");
206	/* Guess sane values (60MHz) */
207	omap_writew(0x2290, DPLL_CTL);
208	- omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
209	+ omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
210	ck_dpll1.rate = 60000000;
211	}
212	#endif
213	@@ -862,7 +862,7 @@ int __init omap1_clk_init(void)
214
215	#if defined(CONFIG_MACH_OMAP_PERSEUS2) \|\| defined(CONFIG_MACH_OMAP_FSAMPLE)
216	/* Select slicer output as OMAP input clock */
217	- omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
218	+ omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
219	#endif
220
221	/* Amstrad Delta wants BCLK high when inactive */
222	@@ -873,7 +873,7 @@ int __init omap1_clk_init(void)
223
224	/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
225	/* (on 730, bit 13 must not be cleared) */
226	- if (cpu_is_omap730())
227	+ if (cpu_is_omap7xx())
228	omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
229	else
230	omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
231	--- a/arch/arm/mach-omap1/io.c
232	+++ b/arch/arm/mach-omap1/io.c
233	@@ -36,33 +36,17 @@ static struct map_desc omap_io_desc[] __
234	}
235	};
236
237	-#ifdef CONFIG_ARCH_OMAP730
238	-static struct map_desc omap730_io_desc[] __initdata = {
239	+#if defined (CONFIG_ARCH_OMAP730) \|\| defined (CONFIG_ARCH_OMAP850)
240	+static struct map_desc omap7xx_io_desc[] __initdata = {
241	{
242	- .virtual = OMAP730_DSP_BASE,
243	- .pfn = __phys_to_pfn(OMAP730_DSP_START),
244	- .length = OMAP730_DSP_SIZE,
245	+ .virtual = OMAP7XX_DSP_BASE,
246	+ .pfn = __phys_to_pfn(OMAP7XX_DSP_START),
247	+ .length = OMAP7XX_DSP_SIZE,
248	.type = MT_DEVICE
249	}, {
250	- .virtual = OMAP730_DSPREG_BASE,
251	- .pfn = __phys_to_pfn(OMAP730_DSPREG_START),
252	- .length = OMAP730_DSPREG_SIZE,
253	- .type = MT_DEVICE
254	- }
255	-};
256	-#endif
257	-
258	-#ifdef CONFIG_ARCH_OMAP850
259	-static struct map_desc omap850_io_desc[] __initdata = {
260	- {
261	- .virtual = OMAP850_DSP_BASE,
262	- .pfn = __phys_to_pfn(OMAP850_DSP_START),
263	- .length = OMAP850_DSP_SIZE,
264	- .type = MT_DEVICE
265	- }, {
266	- .virtual = OMAP850_DSPREG_BASE,
267	- .pfn = __phys_to_pfn(OMAP850_DSPREG_START),
268	- .length = OMAP850_DSPREG_SIZE,
269	+ .virtual = OMAP7XX_DSPREG_BASE,
270	+ .pfn = __phys_to_pfn(OMAP7XX_DSPREG_START),
271	+ .length = OMAP7XX_DSPREG_SIZE,
272	.type = MT_DEVICE
273	}
274	};
275	@@ -120,18 +104,11 @@ void __init omap1_map_common_io(void)
276	*/
277	omap_check_revision();
278
279	-#ifdef CONFIG_ARCH_OMAP730
280	- if (cpu_is_omap730()) {
281	- iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
282	- }
283	-#endif
284	-
285	-#ifdef CONFIG_ARCH_OMAP850
286	- if (cpu_is_omap850()) {
287	- iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc));
288	+#if defined (CONFIG_ARCH_OMAP730) \|\| defined (CONFIG_ARCH_OMAP850)
289	+ if (cpu_is_omap7xx()) {
290	+ iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
291	}
292	#endif
293	-
294	#ifdef CONFIG_ARCH_OMAP15XX
295	if (cpu_is_omap15xx()) {
296	iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
297	--- a/arch/arm/mach-omap1/irq.c
298	+++ b/arch/arm/mach-omap1/irq.c
299	@@ -137,16 +137,8 @@ static void omap_irq_set_cfg(int irq, in
300	irq_bank_writel(val, bank, offset);
301	}
302
303	-#ifdef CONFIG_ARCH_OMAP730
304	-static struct omap_irq_bank omap730_irq_banks[] = {
305	- { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
306	- { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
307	- { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
308	-};
309	-#endif
310	-
311	-#ifdef CONFIG_ARCH_OMAP850
312	-static struct omap_irq_bank omap850_irq_banks[] = {
313	+#if defined (CONFIG_ARCH_OMAP730) \|\| defined (CONFIG_ARCH_OMAP850)
314	+static struct omap_irq_bank omap7xx_irq_banks[] = {
315	{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
316	{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
317	{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
318	@@ -186,16 +178,10 @@ void __init omap_init_irq(void)
319	{
320	int i, j;
321
322	-#ifdef CONFIG_ARCH_OMAP730
323	- if (cpu_is_omap730()) {
324	- irq_banks = omap730_irq_banks;
325	- irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
326	- }
327	-#endif
328	-#ifdef CONFIG_ARCH_OMAP850
329	- if (cpu_is_omap850()) {
330	- irq_banks = omap850_irq_banks;
331	- irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
332	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
333	+ if (cpu_is_omap7xx()) {
334	+ irq_banks = omap7xx_irq_banks;
335	+ irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
336	}
337	#endif
338	#ifdef CONFIG_ARCH_OMAP15XX
339	@@ -247,10 +233,8 @@ void __init omap_init_irq(void)
340
341	/* Unmask level 2 handler */
342
343	- if (cpu_is_omap730())
344	- omap_unmask_irq(INT_730_IH2_IRQ);
345	- else if (cpu_is_omap850())
346	- omap_unmask_irq(INT_850_IH2_IRQ);
347	+ if (cpu_is_omap7xx())
348	+ omap_unmask_irq(INT_7XX_IH2_IRQ);
349	else if (cpu_is_omap15xx())
350	omap_unmask_irq(INT_1510_IH2_IRQ);
351	else if (cpu_is_omap16xx())
352	--- a/arch/arm/mach-omap1/mcbsp.c
353	+++ b/arch/arm/mach-omap1/mcbsp.c
354	@@ -79,29 +79,29 @@ static struct omap_mcbsp_ops omap1_mcbsp
355	.free = omap1_mcbsp_free,
356	};
357
358	-#ifdef CONFIG_ARCH_OMAP730
359	-static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
360	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
361	+static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
362	{
363	- .phys_base = OMAP730_MCBSP1_BASE,
364	+ .phys_base = OMAP7XX_MCBSP1_BASE,
365	.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
366	.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
367	- .rx_irq = INT_730_McBSP1RX,
368	- .tx_irq = INT_730_McBSP1TX,
369	+ .rx_irq = INT_7XX_McBSP1RX,
370	+ .tx_irq = INT_7XX_McBSP1TX,
371	.ops = &omap1_mcbsp_ops,
372	},
373	{
374	- .phys_base = OMAP730_MCBSP2_BASE,
375	+ .phys_base = OMAP7XX_MCBSP2_BASE,
376	.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
377	.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
378	- .rx_irq = INT_730_McBSP2RX,
379	- .tx_irq = INT_730_McBSP2TX,
380	+ .rx_irq = INT_7XX_McBSP2RX,
381	+ .tx_irq = INT_7XX_McBSP2TX,
382	.ops = &omap1_mcbsp_ops,
383	},
384	};
385	-#define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata)
386	+#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata)
387	#else
388	-#define omap730_mcbsp_pdata NULL
389	-#define OMAP730_MCBSP_PDATA_SZ 0
390	+#define omap7xx_mcbsp_pdata NULL
391	+#define OMAP7XX_MCBSP_PDATA_SZ 0
392	#endif
393
394	#ifdef CONFIG_ARCH_OMAP15XX
395	@@ -172,8 +172,8 @@ static struct omap_mcbsp_platform_data o
396
397	int __init omap1_mcbsp_init(void)
398	{
399	- if (cpu_is_omap730())
400	- omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
401	+ if (cpu_is_omap7xx())
402	+ omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
403	if (cpu_is_omap15xx())
404	omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
405	if (cpu_is_omap16xx())
406	@@ -184,9 +184,9 @@ int __init omap1_mcbsp_init(void)
407	if (!mcbsp_ptr)
408	return -ENOMEM;
409
410	- if (cpu_is_omap730())
411	- omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
412	- OMAP730_MCBSP_PDATA_SZ);
413	+ if (cpu_is_omap7xx())
414	+ omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
415	+ OMAP7XX_MCBSP_PDATA_SZ);
416
417	if (cpu_is_omap15xx())
418	omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
419	--- a/arch/arm/mach-omap1/mux.c
420	+++ b/arch/arm/mach-omap1/mux.c
421	@@ -35,47 +35,28 @@
422
423	static struct omap_mux_cfg arch_mux_cfg;
424
425	-#ifdef CONFIG_ARCH_OMAP730
426	-static struct pin_config __initdata_or_module omap730_pins[] = {
427	-MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0)
428	-MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0)
429	-MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0)
430	-MUX_CFG_730("F3_730_KBR3", 13, 1, 0, 0, 1, 0)
431	-MUX_CFG_730("D2_730_KBR4", 13, 5, 0, 4, 1, 0)
432	-MUX_CFG_730("C2_730_KBC0", 13, 9, 0, 8, 1, 0)
433	-MUX_CFG_730("D3_730_KBC1", 13, 13, 0, 12, 1, 0)
434	-MUX_CFG_730("E4_730_KBC2", 13, 17, 0, 16, 1, 0)
435	-MUX_CFG_730("F4_730_KBC3", 13, 21, 0, 20, 1, 0)
436	-MUX_CFG_730("E3_730_KBC4", 13, 25, 0, 24, 1, 0)
437	-
438	-MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0)
439	-MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0)
440	-MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0)
441	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
442	+static struct pin_config __initdata_or_module omap7xx_pins[] = {
443	+MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
444	+MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
445	+MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
446	+MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0)
447	+MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0)
448	+MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0)
449	+MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0)
450	+MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0)
451	+MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0)
452	+MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
453	+
454	+MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
455	+MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
456	+MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0)
457	};
458	-#define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins)
459	+#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
460	#else
461	-#define omap730_pins NULL
462	-#define OMAP730_PINS_SZ 0
463	-#endif /* CONFIG_ARCH_OMAP730 */
464	-
465	-#ifdef CONFIG_ARCH_OMAP850
466	-struct pin_config __initdata_or_module omap850_pins[] = {
467	-MUX_CFG_850("E2_850_KBR0", 12, 21, 0, 20, 1, 0)
468	-MUX_CFG_850("J7_850_KBR1", 12, 25, 0, 24, 1, 0)
469	-MUX_CFG_850("E1_850_KBR2", 12, 29, 0, 28, 1, 0)
470	-MUX_CFG_850("F3_850_KBR3", 13, 1, 0, 0, 1, 0)
471	-MUX_CFG_850("D2_850_KBR4", 13, 5, 0, 4, 1, 0)
472	-MUX_CFG_850("C2_850_KBC0", 13, 9, 0, 8, 1, 0)
473	-MUX_CFG_850("D3_850_KBC1", 13, 13, 0, 12, 1, 0)
474	-MUX_CFG_850("E4_850_KBC2", 13, 17, 0, 16, 1, 0)
475	-MUX_CFG_850("F4_850_KBC3", 13, 21, 0, 20, 1, 0)
476	-MUX_CFG_850("E3_850_KBC4", 13, 25, 0, 24, 1, 0)
477	-
478	-MUX_CFG_850("AA17_850_USB_DM", 2, 21, 0, 20, 0, 0)
479	-MUX_CFG_850("W16_850_USB_PU_EN", 2, 25, 0, 24, 0, 0)
480	-MUX_CFG_850("W17_850_USB_VBUSI", 2, 29, 0, 28, 0, 0)
481	-};
482	-#endif
483	+#define omap7xx_pins NULL
484	+#define OMAP7XX_PINS_SZ 0
485	+#endif /* CONFIG_ARCH_OMAP730 \|\| CONFIG_ARCH_OMAP850 */
486
487	#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX)
488	static struct pin_config __initdata_or_module omap1xxx_pins[] = {
489	@@ -438,11 +419,6 @@ int __init_or_module omap1_cfg_reg(const
490	printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
491	cfg->pull_name, cfg->pull_reg, pull_orig, pull);
492	}
493	-
494	-#ifdef CONFIG_ARCH_OMAP850
495	- omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins));
496	-#endif
497	-
498	#endif
499
500	#ifdef CONFIG_OMAP_MUX_ERRORS
501	@@ -454,9 +430,9 @@ int __init_or_module omap1_cfg_reg(const
502
503	int __init omap1_mux_init(void)
504	{
505	- if (cpu_is_omap730()) {
506	- arch_mux_cfg.pins = omap730_pins;
507	- arch_mux_cfg.size = OMAP730_PINS_SZ;
508	+ if (cpu_is_omap7xx()) {
509	+ arch_mux_cfg.pins = omap7xx_pins;
510	+ arch_mux_cfg.size = OMAP7XX_PINS_SZ;
511	arch_mux_cfg.cfg_reg = omap1_cfg_reg;
512	}
513
514	--- a/arch/arm/mach-omap1/pm.c
515	+++ b/arch/arm/mach-omap1/pm.c
516	@@ -62,7 +62,7 @@
517	static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
518	static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
519	static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
520	-static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
521	+static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
522	static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
523	static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
524
525	@@ -183,9 +183,9 @@ static void omap_pm_wakeup_setup(void)
526	* drivers must still separately call omap_set_gpio_wakeup() to
527	* wake up to a GPIO interrupt.
528	*/
529	- if (cpu_is_omap730())
530	- level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) \|
531	- OMAP_IRQ_BIT(INT_730_IH2_IRQ);
532	+ if (cpu_is_omap7xx())
533	+ level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) \|
534	+ OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
535	else if (cpu_is_omap15xx())
536	level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) \|
537	OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
538	@@ -195,10 +195,10 @@ static void omap_pm_wakeup_setup(void)
539
540	omap_writel(~level1_wake, OMAP_IH1_MIR);
541
542	- if (cpu_is_omap730()) {
543	+ if (cpu_is_omap7xx()) {
544	omap_writel(~level2_wake, OMAP_IH2_0_MIR);
545	- omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) \|
546	- OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
547	+ omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) \|
548	+ OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
549	OMAP_IH2_1_MIR);
550	} else if (cpu_is_omap15xx()) {
551	level2_wake \|= OMAP_IRQ_BIT(INT_KEYBOARD);
552	@@ -253,15 +253,15 @@ void omap1_pm_suspend(void)
553	* Save interrupt, MPUI, ARM and UPLD control registers.
554	*/
555
556	- if (cpu_is_omap730()) {
557	- MPUI730_SAVE(OMAP_IH1_MIR);
558	- MPUI730_SAVE(OMAP_IH2_0_MIR);
559	- MPUI730_SAVE(OMAP_IH2_1_MIR);
560	- MPUI730_SAVE(MPUI_CTRL);
561	- MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
562	- MPUI730_SAVE(MPUI_DSP_API_CONFIG);
563	- MPUI730_SAVE(EMIFS_CONFIG);
564	- MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
565	+ if (cpu_is_omap7xx()) {
566	+ MPUI7XX_SAVE(OMAP_IH1_MIR);
567	+ MPUI7XX_SAVE(OMAP_IH2_0_MIR);
568	+ MPUI7XX_SAVE(OMAP_IH2_1_MIR);
569	+ MPUI7XX_SAVE(MPUI_CTRL);
570	+ MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
571	+ MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
572	+ MPUI7XX_SAVE(EMIFS_CONFIG);
573	+ MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
574
575	} else if (cpu_is_omap15xx()) {
576	MPUI1510_SAVE(OMAP_IH1_MIR);
577	@@ -306,7 +306,7 @@ void omap1_pm_suspend(void)
578	omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
579
580	/* shut down dsp_ck */
581	- if (!cpu_is_omap730())
582	+ if (!cpu_is_omap7xx())
583	omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
584
585	/* temporarily enabling api_ck to access DSP registers */
586	@@ -383,12 +383,12 @@ void omap1_pm_suspend(void)
587	ULPD_RESTORE(ULPD_CLOCK_CTRL);
588	ULPD_RESTORE(ULPD_STATUS_REQ);
589
590	- if (cpu_is_omap730()) {
591	- MPUI730_RESTORE(EMIFS_CONFIG);
592	- MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
593	- MPUI730_RESTORE(OMAP_IH1_MIR);
594	- MPUI730_RESTORE(OMAP_IH2_0_MIR);
595	- MPUI730_RESTORE(OMAP_IH2_1_MIR);
596	+ if (cpu_is_omap7xx()) {
597	+ MPUI7XX_RESTORE(EMIFS_CONFIG);
598	+ MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
599	+ MPUI7XX_RESTORE(OMAP_IH1_MIR);
600	+ MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
601	+ MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
602	} else if (cpu_is_omap15xx()) {
603	MPUI1510_RESTORE(MPUI_CTRL);
604	MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
605	@@ -461,13 +461,13 @@ static int omap_pm_read_proc(
606	ULPD_SAVE(ULPD_DPLL_CTRL);
607	ULPD_SAVE(ULPD_POWER_CTRL);
608
609	- if (cpu_is_omap730()) {
610	- MPUI730_SAVE(MPUI_CTRL);
611	- MPUI730_SAVE(MPUI_DSP_STATUS);
612	- MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
613	- MPUI730_SAVE(MPUI_DSP_API_CONFIG);
614	- MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
615	- MPUI730_SAVE(EMIFS_CONFIG);
616	+ if (cpu_is_omap7xx()) {
617	+ MPUI7XX_SAVE(MPUI_CTRL);
618	+ MPUI7XX_SAVE(MPUI_DSP_STATUS);
619	+ MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
620	+ MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
621	+ MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
622	+ MPUI7XX_SAVE(EMIFS_CONFIG);
623	} else if (cpu_is_omap15xx()) {
624	MPUI1510_SAVE(MPUI_CTRL);
625	MPUI1510_SAVE(MPUI_DSP_STATUS);
626	@@ -517,20 +517,20 @@ static int omap_pm_read_proc(
627	ULPD_SHOW(ULPD_STATUS_REQ),
628	ULPD_SHOW(ULPD_POWER_CTRL));
629
630	- if (cpu_is_omap730()) {
631	+ if (cpu_is_omap7xx()) {
632	my_buffer_offset += sprintf(my_base + my_buffer_offset,
633	- "MPUI730_CTRL_REG 0x%-8x \n"
634	- "MPUI730_DSP_STATUS_REG: 0x%-8x \n"
635	- "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
636	- "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
637	- "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
638	- "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
639	- MPUI730_SHOW(MPUI_CTRL),
640	- MPUI730_SHOW(MPUI_DSP_STATUS),
641	- MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
642	- MPUI730_SHOW(MPUI_DSP_API_CONFIG),
643	- MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
644	- MPUI730_SHOW(EMIFS_CONFIG));
645	+ "MPUI7XX_CTRL_REG 0x%-8x \n"
646	+ "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
647	+ "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
648	+ "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
649	+ "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
650	+ "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
651	+ MPUI7XX_SHOW(MPUI_CTRL),
652	+ MPUI7XX_SHOW(MPUI_DSP_STATUS),
653	+ MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
654	+ MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
655	+ MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
656	+ MPUI7XX_SHOW(EMIFS_CONFIG));
657	} else if (cpu_is_omap15xx()) {
658	my_buffer_offset += sprintf(my_base + my_buffer_offset,
659	"MPUI1510_CTRL_REG 0x%-8x \n"
660	@@ -668,9 +668,9 @@ static int __init omap_pm_init(void)
661	* These routines need to be in SRAM as that's the only
662	* memory the MPU can see when it wakes up.
663	*/
664	- if (cpu_is_omap730()) {
665	- omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
666	- omap730_cpu_suspend_sz);
667	+ if (cpu_is_omap7xx()) {
668	+ omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
669	+ omap7xx_cpu_suspend_sz);
670	} else if (cpu_is_omap15xx()) {
671	omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
672	omap1510_cpu_suspend_sz);
673	@@ -686,8 +686,8 @@ static int __init omap_pm_init(void)
674
675	pm_idle = omap1_pm_idle;
676
677	- if (cpu_is_omap730())
678	- setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
679	+ if (cpu_is_omap7xx())
680	+ setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
681	else if (cpu_is_omap16xx())
682	setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
683
684	@@ -700,8 +700,8 @@ static int __init omap_pm_init(void)
685	omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
686
687	/* Configure IDLECT3 */
688	- if (cpu_is_omap730())
689	- omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
690	+ if (cpu_is_omap7xx())
691	+ omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
692	else if (cpu_is_omap16xx())
693	omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
694
695	--- a/arch/arm/mach-omap1/pm.h
696	+++ b/arch/arm/mach-omap1/pm.h
697	@@ -98,13 +98,14 @@
698	#define OMAP1610_IDLECT3 0xfffece24
699	#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
700
701	-#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7
702	-#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7
703	-#define OMAP730_IDLECT3_VAL 0x3f
704	-#define OMAP730_IDLECT3 0xfffece24
705	-#define OMAP730_IDLE_LOOP_REQUEST 0x0C00
706	+#define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7
707	+#define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7
708	+#define OMAP7XX_IDLECT3_VAL 0x3f
709	+#define OMAP7XX_IDLECT3 0xfffece24
710	+#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00
711
712	#if !defined(CONFIG_ARCH_OMAP730) && \
713	+ !defined(CONFIG_ARCH_OMAP850) && \
714	!defined(CONFIG_ARCH_OMAP15XX) && \
715	!defined(CONFIG_ARCH_OMAP16XX)
716	#warning "Power management for this processor not implemented yet"
717	@@ -122,17 +123,17 @@ extern void allow_idle_sleep(void);
718	extern void omap1_pm_idle(void);
719	extern void omap1_pm_suspend(void);
720
721	-extern void omap730_cpu_suspend(unsigned short, unsigned short);
722	+extern void omap7xx_cpu_suspend(unsigned short, unsigned short);
723	extern void omap1510_cpu_suspend(unsigned short, unsigned short);
724	extern void omap1610_cpu_suspend(unsigned short, unsigned short);
725	-extern void omap730_idle_loop_suspend(void);
726	+extern void omap7xx_idle_loop_suspend(void);
727	extern void omap1510_idle_loop_suspend(void);
728	extern void omap1610_idle_loop_suspend(void);
729
730	-extern unsigned int omap730_cpu_suspend_sz;
731	+extern unsigned int omap7xx_cpu_suspend_sz;
732	extern unsigned int omap1510_cpu_suspend_sz;
733	extern unsigned int omap1610_cpu_suspend_sz;
734	-extern unsigned int omap730_idle_loop_suspend_sz;
735	+extern unsigned int omap7xx_idle_loop_suspend_sz;
736	extern unsigned int omap1510_idle_loop_suspend_sz;
737	extern unsigned int omap1610_idle_loop_suspend_sz;
738
739	@@ -155,9 +156,9 @@ extern void omap_serial_wake_trigger(int
740	#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
741	#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
742
743	-#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
744	-#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
745	-#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
746	+#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
747	+#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
748	+#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
749
750	#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
751	#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
752	@@ -232,24 +233,24 @@ enum mpui1510_save_state {
753	#endif
754	};
755
756	-enum mpui730_save_state {
757	- MPUI730_SLEEP_SAVE_START = 0,
758	+enum mpui7xx_save_state {
759	+ MPUI7XX_SLEEP_SAVE_START = 0,
760	/*
761	* MPUI registers 32 bits
762	*/
763	- MPUI730_SLEEP_SAVE_MPUI_CTRL,
764	- MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
765	- MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
766	- MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
767	- MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
768	- MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
769	- MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
770	- MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
771	- MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
772	-#if defined(CONFIG_ARCH_OMAP730)
773	- MPUI730_SLEEP_SAVE_SIZE
774	+ MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
775	+ MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
776	+ MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
777	+ MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
778	+ MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
779	+ MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
780	+ MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
781	+ MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
782	+ MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
783	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
784	+ MPUI7XX_SLEEP_SAVE_SIZE
785	#else
786	- MPUI730_SLEEP_SAVE_SIZE = 0
787	+ MPUI7XX_SLEEP_SAVE_SIZE = 0
788	#endif
789	};
790
791	--- a/arch/arm/mach-omap1/serial.c
792	+++ b/arch/arm/mach-omap1/serial.c
793	@@ -64,7 +64,6 @@ static void __init omap_serial_reset(str
794
795	static struct plat_serial8250_port serial_platform_data[] = {
796	{
797	- .membase = OMAP1_IO_ADDRESS(OMAP_UART1_BASE),
798	.mapbase = OMAP_UART1_BASE,
799	.irq = INT_UART1,
800	.flags = UPF_BOOT_AUTOCONF,
801	@@ -73,7 +72,6 @@ static struct plat_serial8250_port seria
802	.uartclk = OMAP16XX_BASE_BAUD * 16,
803	},
804	{
805	- .membase = OMAP1_IO_ADDRESS(OMAP_UART2_BASE),
806	.mapbase = OMAP_UART2_BASE,
807	.irq = INT_UART2,
808	.flags = UPF_BOOT_AUTOCONF,
809	@@ -82,7 +80,6 @@ static struct plat_serial8250_port seria
810	.uartclk = OMAP16XX_BASE_BAUD * 16,
811	},
812	{
813	- .membase = OMAP1_IO_ADDRESS(OMAP_UART3_BASE),
814	.mapbase = OMAP_UART3_BASE,
815	.irq = INT_UART3,
816	.flags = UPF_BOOT_AUTOCONF,
817	@@ -90,7 +87,6 @@ static struct plat_serial8250_port seria
818	.regshift = 2,
819	.uartclk = OMAP16XX_BASE_BAUD * 16,
820	},
821	- { },
822	};
823
824	static struct platform_device serial_device = {
825	@@ -110,18 +106,11 @@ void __init omap_serial_init(void)
826	{
827	int i;
828
829	- if (cpu_is_omap730()) {
830	+ if (cpu_is_omap7xx()) {
831	serial_platform_data[0].regshift = 0;
832	serial_platform_data[1].regshift = 0;
833	- serial_platform_data[0].irq = INT_730_UART_MODEM_1;
834	- serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
835	- }
836	-
837	- if (cpu_is_omap850()) {
838	- serial_platform_data[0].regshift = 0;
839	- serial_platform_data[1].regshift = 0;
840	- serial_platform_data[0].irq = INT_850_UART_MODEM_1;
841	- serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2;
842	+ serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
843	+ serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
844	}
845
846	if (cpu_is_omap15xx()) {
847	--- a/arch/arm/mach-omap1/sleep.S
848	+++ b/arch/arm/mach-omap1/sleep.S
849	@@ -1,7 +1,7 @@
850	/*
851	* linux/arch/arm/mach-omap1/sleep.S
852	*
853	- * Low-level OMAP730/1510/1610 sleep/wakeUp support
854	+ * Low-level OMAP7XX/1510/1610 sleep/wakeUp support
855	*
856	* Initial SA1110 code:
857	* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
858	@@ -57,8 +57,8 @@
859	*
860	*/
861
862	-#if defined(CONFIG_ARCH_OMAP730)
863	-ENTRY(omap730_cpu_suspend)
864	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
865	+ENTRY(omap7xx_cpu_suspend)
866
867	@ save registers on stack
868	stmfd sp!, {r0 - r12, lr}
869	@@ -91,13 +91,13 @@ ENTRY(omap730_cpu_suspend)
870
871	@ turn off clock domains
872	@ do not disable PERCK (0x04)
873	- mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
874	- orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
875	+ mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
876	+ orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
877	strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
878
879	@ request ARM idle
880	- mov r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff
881	- orr r3, r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff00
882	+ mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
883	+ orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
884	strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
885
886	@ disable instruction cache
887	@@ -113,7 +113,7 @@ ENTRY(omap730_cpu_suspend)
888	mov r2, #0
889	mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
890	/*
891	- * omap730_cpu_suspend()'s resume point.
892	+ * omap7xx_cpu_suspend()'s resume point.
893	*
894	* It will just start executing here, so we'll restore stuff from the
895	* stack.
896	@@ -132,9 +132,9 @@ ENTRY(omap730_cpu_suspend)
897	@ restore regs and return
898	ldmfd sp!, {r0 - r12, pc}
899
900	-ENTRY(omap730_cpu_suspend_sz)
901	- .word . - omap730_cpu_suspend
902	-#endif /* CONFIG_ARCH_OMAP730 */
903	+ENTRY(omap7xx_cpu_suspend_sz)
904	+ .word . - omap7xx_cpu_suspend
905	+#endif /* CONFIG_ARCH_OMAP730 \|\| CONFIG_ARCH_OMAP850 */
906
907	#ifdef CONFIG_ARCH_OMAP15XX
908	ENTRY(omap1510_cpu_suspend)
909	--- a/arch/arm/mach-omap2/Makefile
910	+++ b/arch/arm/mach-omap2/Makefile
911	@@ -80,6 +80,7 @@ obj-$(CONFIG_MACH_OMAP_4430SDP) += boar
912	# Platform specific device init code
913	obj-y += usb-musb.o
914	obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
915	+obj-y += usb-ehci.o
916
917	onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
918	obj-y += $(onenand-m) $(onenand-y)
919	--- a/arch/arm/mach-omap2/board-2430sdp.c
920	+++ b/arch/arm/mach-omap2/board-2430sdp.c
921	@@ -221,7 +221,7 @@ static void __init omap_2430sdp_map_io(v
922	MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
923	/* Maintainer: Syed Khasim - Texas Instruments Inc */
924	.phys_io = 0x48000000,
925	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
926	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
927	.boot_params = 0x80000100,
928	.map_io = omap_2430sdp_map_io,
929	.init_irq = omap_2430sdp_init_irq,
930	--- a/arch/arm/mach-omap2/board-3430sdp.c
931	+++ b/arch/arm/mach-omap2/board-3430sdp.c
932	@@ -618,6 +618,18 @@ static void enable_board_wakeup_source(v
933	omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
934	}
935
936	+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
937	+
938	+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
939	+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
940	+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
941	+
942	+ .phy_reset = true,
943	+ .reset_gpio_port[0] = 57,
944	+ .reset_gpio_port[1] = 61,
945	+ .reset_gpio_port[2] = -EINVAL
946	+};
947	+
948	static void __init omap_3430sdp_init(void)
949	{
950	omap3430_i2c_init();
951	@@ -635,6 +647,7 @@ static void __init omap_3430sdp_init(voi
952	board_smc91x_init();
953	sdp3430_display_init();
954	enable_board_wakeup_source();
955	+ usb_ehci_init(&ehci_pdata);
956	}
957
958	static void __init omap_3430sdp_map_io(void)
959	@@ -646,7 +659,7 @@ static void __init omap_3430sdp_map_io(v
960	MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
961	/* Maintainer: Syed Khasim - Texas Instruments Inc */
962	.phys_io = 0x48000000,
963	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
964	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
965	.boot_params = 0x80000100,
966	.map_io = omap_3430sdp_map_io,
967	.init_irq = omap_3430sdp_init_irq,
968	--- a/arch/arm/mach-omap2/board-4430sdp.c
969	+++ b/arch/arm/mach-omap2/board-4430sdp.c
970	@@ -52,8 +52,17 @@ static struct omap_board_config_kernel s
971
972	static void __init gic_init_irq(void)
973	{
974	- gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
975	- gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
976	+ void __iomem *base;
977	+
978	+ /* Static mapping, never released */
979	+ base = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
980	+ BUG_ON(!base);
981	+ gic_dist_init(0, base, 29);
982	+
983	+ /* Static mapping, never released */
984	+ base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256);
985	+ BUG_ON(!base);
986	+ gic_cpu_init(0, OMAP44XX_GIC_CPU_BASE);
987	}
988
989	static void __init omap_4430sdp_init_irq(void)
990	@@ -84,7 +93,7 @@ static void __init omap_4430sdp_map_io(v
991	MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
992	/* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
993	.phys_io = 0x48000000,
994	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
995	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
996	.boot_params = 0x80000100,
997	.map_io = omap_4430sdp_map_io,
998	.init_irq = omap_4430sdp_init_irq,
999	--- a/arch/arm/mach-omap2/board-apollon.c
1000	+++ b/arch/arm/mach-omap2/board-apollon.c
1001	@@ -333,7 +333,7 @@ static void __init omap_apollon_map_io(v
1002	MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
1003	/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
1004	.phys_io = 0x48000000,
1005	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1006	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1007	.boot_params = 0x80000100,
1008	.map_io = omap_apollon_map_io,
1009	.init_irq = omap_apollon_init_irq,
1010	--- a/arch/arm/mach-omap2/board-generic.c
1011	+++ b/arch/arm/mach-omap2/board-generic.c
1012	@@ -56,7 +56,7 @@ static void __init omap_generic_map_io(v
1013	MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
1014	/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
1015	.phys_io = 0x48000000,
1016	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1017	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1018	.boot_params = 0x80000100,
1019	.map_io = omap_generic_map_io,
1020	.init_irq = omap_generic_init_irq,
1021	--- a/arch/arm/mach-omap2/board-h4.c
1022	+++ b/arch/arm/mach-omap2/board-h4.c
1023	@@ -376,7 +376,7 @@ static void __init omap_h4_map_io(void)
1024	MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
1025	/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
1026	.phys_io = 0x48000000,
1027	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1028	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1029	.boot_params = 0x80000100,
1030	.map_io = omap_h4_map_io,
1031	.init_irq = omap_h4_init_irq,
1032	--- a/arch/arm/mach-omap2/board-ldp.c
1033	+++ b/arch/arm/mach-omap2/board-ldp.c
1034	@@ -399,7 +399,7 @@ static void __init omap_ldp_map_io(void)
1035
1036	MACHINE_START(OMAP_LDP, "OMAP LDP board")
1037	.phys_io = 0x48000000,
1038	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1039	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1040	.boot_params = 0x80000100,
1041	.map_io = omap_ldp_map_io,
1042	.init_irq = omap_ldp_init_irq,
1043	--- a/arch/arm/mach-omap2/board-n8x0.c
1044	+++ b/arch/arm/mach-omap2/board-n8x0.c
1045	@@ -121,7 +121,7 @@ static void __init n8x0_init_machine(voi
1046
1047	MACHINE_START(NOKIA_N800, "Nokia N800")
1048	.phys_io = 0x48000000,
1049	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1050	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1051	.boot_params = 0x80000100,
1052	.map_io = n8x0_map_io,
1053	.init_irq = n8x0_init_irq,
1054	@@ -131,7 +131,7 @@ MACHINE_END
1055
1056	MACHINE_START(NOKIA_N810, "Nokia N810")
1057	.phys_io = 0x48000000,
1058	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1059	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1060	.boot_params = 0x80000100,
1061	.map_io = n8x0_map_io,
1062	.init_irq = n8x0_init_irq,
1063	@@ -141,7 +141,7 @@ MACHINE_END
1064
1065	MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
1066	.phys_io = 0x48000000,
1067	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1068	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1069	.boot_params = 0x80000100,
1070	.map_io = n8x0_map_io,
1071	.init_irq = n8x0_init_irq,
1072	--- a/arch/arm/mach-omap2/board-omap3beagle.c
1073	+++ b/arch/arm/mach-omap2/board-omap3beagle.c
1074	@@ -400,6 +400,18 @@ static void __init omap3beagle_flash_ini
1075	}
1076	}
1077
1078	+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
1079	+
1080	+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
1081	+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
1082	+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1083	+
1084	+ .phy_reset = true,
1085	+ .reset_gpio_port[0] = -EINVAL,
1086	+ .reset_gpio_port[1] = 147,
1087	+ .reset_gpio_port[2] = -EINVAL
1088	+};
1089	+
1090	static void __init omap3_beagle_init(void)
1091	{
1092	omap3_beagle_i2c_init();
1093	@@ -413,6 +425,7 @@ static void __init omap3_beagle_init(voi
1094	gpio_direction_output(170, true);
1095
1096	usb_musb_init();
1097	+ usb_ehci_init(&ehci_pdata);
1098	omap3beagle_flash_init();
1099
1100	/* Ensure SDRC pins are mux'd for self-refresh */
1101	@@ -429,7 +442,7 @@ static void __init omap3_beagle_map_io(v
1102	MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
1103	/* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
1104	.phys_io = 0x48000000,
1105	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1106	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1107	.boot_params = 0x80000100,
1108	.map_io = omap3_beagle_map_io,
1109	.init_irq = omap3_beagle_init_irq,
1110	--- a/arch/arm/mach-omap2/board-omap3evm.c
1111	+++ b/arch/arm/mach-omap2/board-omap3evm.c
1112	@@ -297,6 +297,18 @@ static struct platform_device *omap3_evm
1113	&omap3evm_smc911x_device,
1114	};
1115
1116	+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
1117	+
1118	+ .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1119	+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
1120	+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1121	+
1122	+ .phy_reset = true,
1123	+ .reset_gpio_port[0] = -EINVAL,
1124	+ .reset_gpio_port[1] = 135,
1125	+ .reset_gpio_port[2] = -EINVAL
1126	+};
1127	+
1128	static void __init omap3_evm_init(void)
1129	{
1130	omap3_evm_i2c_init();
1131	@@ -312,6 +324,9 @@ static void __init omap3_evm_init(void)
1132	usb_nop_xceiv_register();
1133	#endif
1134	usb_musb_init();
1135	+ /* Setup EHCI phy reset padconfig */
1136	+ omap_cfg_reg(AF4_34XX_GPIO135_OUT);
1137	+ usb_ehci_init(&ehci_pdata);
1138	ads7846_dev_init();
1139	}
1140
1141	@@ -324,7 +339,7 @@ static void __init omap3_evm_map_io(void
1142	MACHINE_START(OMAP3EVM, "OMAP3 EVM")
1143	/* Maintainer: Syed Mohammed Khasim - Texas Instruments */
1144	.phys_io = 0x48000000,
1145	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1146	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1147	.boot_params = 0x80000100,
1148	.map_io = omap3_evm_map_io,
1149	.init_irq = omap3_evm_init_irq,
1150	--- a/arch/arm/mach-omap2/board-omap3pandora.c
1151	+++ b/arch/arm/mach-omap2/board-omap3pandora.c
1152	@@ -387,6 +387,18 @@ static struct platform_device *omap3pand
1153	&pandora_keys_gpio,
1154	};
1155
1156	+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
1157	+
1158	+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
1159	+ .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1160	+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1161	+
1162	+ .phy_reset = true,
1163	+ .reset_gpio_port[0] = 16,
1164	+ .reset_gpio_port[1] = -EINVAL,
1165	+ .reset_gpio_port[2] = -EINVAL
1166	+};
1167	+
1168	static void __init omap3pandora_init(void)
1169	{
1170	omap3pandora_i2c_init();
1171	@@ -396,6 +408,7 @@ static void __init omap3pandora_init(voi
1172	spi_register_board_info(omap3pandora_spi_board_info,
1173	ARRAY_SIZE(omap3pandora_spi_board_info));
1174	omap3pandora_ads7846_init();
1175	+ usb_ehci_init(&ehci_pdata);
1176	pandora_keys_gpio_init();
1177	usb_musb_init();
1178
1179	@@ -412,7 +425,7 @@ static void __init omap3pandora_map_io(v
1180
1181	MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
1182	.phys_io = 0x48000000,
1183	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1184	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1185	.boot_params = 0x80000100,
1186	.map_io = omap3pandora_map_io,
1187	.init_irq = omap3pandora_init_irq,
1188	--- a/arch/arm/mach-omap2/board-overo.c
1189	+++ b/arch/arm/mach-omap2/board-overo.c
1190	@@ -384,6 +384,18 @@ static struct platform_device *overo_dev
1191	&overo_lcd_device,
1192	};
1193
1194	+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
1195	+ .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1196	+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
1197	+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1198	+
1199	+ .phy_reset = true,
1200	+ .reset_gpio_port[0] = -EINVAL,
1201	+ .reset_gpio_port[1] = OVERO_GPIO_USBH_NRESET,
1202	+ .reset_gpio_port[2] = -EINVAL
1203	+};
1204	+
1205	+
1206	static void __init overo_init(void)
1207	{
1208	overo_i2c_init();
1209	@@ -391,6 +403,7 @@ static void __init overo_init(void)
1210	omap_serial_init();
1211	overo_flash_init();
1212	usb_musb_init();
1213	+ usb_ehci_init(&ehci_pdata);
1214	overo_ads7846_init();
1215	overo_init_smsc911x();
1216
1217	@@ -433,14 +446,6 @@ static void __init overo_init(void)
1218	else
1219	printk(KERN_ERR "could not obtain gpio for "
1220	"OVERO_GPIO_USBH_CPEN\n");
1221	-
1222	- if ((gpio_request(OVERO_GPIO_USBH_NRESET,
1223	- "OVERO_GPIO_USBH_NRESET") == 0) &&
1224	- (gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0))
1225	- gpio_export(OVERO_GPIO_USBH_NRESET, 0);
1226	- else
1227	- printk(KERN_ERR "could not obtain gpio for "
1228	- "OVERO_GPIO_USBH_NRESET\n");
1229	}
1230
1231	static void __init overo_map_io(void)
1232	@@ -451,7 +456,7 @@ static void __init overo_map_io(void)
1233
1234	MACHINE_START(OVERO, "Gumstix Overo")
1235	.phys_io = 0x48000000,
1236	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1237	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1238	.boot_params = 0x80000100,
1239	.map_io = overo_map_io,
1240	.init_irq = overo_init_irq,
1241	--- a/arch/arm/mach-omap2/board-rx51.c
1242	+++ b/arch/arm/mach-omap2/board-rx51.c
1243	@@ -84,7 +84,7 @@ static void __init rx51_map_io(void)
1244	MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
1245	/* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
1246	.phys_io = 0x48000000,
1247	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1248	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1249	.boot_params = 0x80000100,
1250	.map_io = rx51_map_io,
1251	.init_irq = rx51_init_irq,
1252	--- a/arch/arm/mach-omap2/board-zoom2.c
1253	+++ b/arch/arm/mach-omap2/board-zoom2.c
1254	@@ -282,7 +282,7 @@ static void __init omap_zoom2_map_io(voi
1255
1256	MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
1257	.phys_io = 0x48000000,
1258	- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
1259	+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
1260	.boot_params = 0x80000100,
1261	.map_io = omap_zoom2_map_io,
1262	.init_irq = omap_zoom2_init_irq,
1263	--- a/arch/arm/mach-omap2/cm.h
1264	+++ b/arch/arm/mach-omap2/cm.h
1265	@@ -17,11 +17,11 @@
1266	#include "prcm-common.h"
1267
1268	#define OMAP2420_CM_REGADDR(module, reg) \
1269	- OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
1270	+ OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
1271	#define OMAP2430_CM_REGADDR(module, reg) \
1272	- OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
1273	+ OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
1274	#define OMAP34XX_CM_REGADDR(module, reg) \
1275	- OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
1276	+ OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
1277
1278	/*
1279	* Architecture-specific global CM registers
1280	--- a/arch/arm/mach-omap2/id.c
1281	+++ b/arch/arm/mach-omap2/id.c
1282	@@ -28,6 +28,7 @@
1283	static struct omap_chip_id omap_chip;
1284	static unsigned int omap_revision;
1285
1286	+u32 omap3_features;
1287
1288	unsigned int omap_rev(void)
1289	{
1290	@@ -155,12 +156,37 @@ void __init omap24xx_check_revision(void
1291	pr_info("\n");
1292	}
1293
1294	-void __init omap34xx_check_revision(void)
1295	+#define OMAP3_CHECK_FEATURE(status,feat) \
1296	+ if (((status & OMAP3_ ##feat## _MASK) \
1297	+ >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
1298	+ omap3_features \|= OMAP3_HAS_ ##feat; \
1299	+ }
1300	+
1301	+void __init omap3_check_features(void)
1302	+{
1303	+ u32 status;
1304	+
1305	+ omap3_features = 0;
1306	+
1307	+ status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
1308	+
1309	+ OMAP3_CHECK_FEATURE(status, L2CACHE);
1310	+ OMAP3_CHECK_FEATURE(status, IVA);
1311	+ OMAP3_CHECK_FEATURE(status, SGX);
1312	+ OMAP3_CHECK_FEATURE(status, NEON);
1313	+ OMAP3_CHECK_FEATURE(status, ISP);
1314	+
1315	+ /*
1316	+ * TODO: Get additional info (where applicable)
1317	+ * e.g. Size of L2 cache.
1318	+ */
1319	+}
1320	+
1321	+void __init omap3_check_revision(void)
1322	{
1323	u32 cpuid, idcode;
1324	u16 hawkeye;
1325	u8 rev;
1326	- char *rev_name = "ES1.0";
1327
1328	/*
1329	* We cannot access revision registers on ES1.0.
1330	@@ -170,7 +196,7 @@ void __init omap34xx_check_revision(void
1331	cpuid = read_cpuid(CPUID_ID);
1332	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
1333	omap_revision = OMAP3430_REV_ES1_0;
1334	- goto out;
1335	+ return;
1336	}
1337
1338	/*
1339	@@ -183,33 +209,111 @@ void __init omap34xx_check_revision(void
1340	hawkeye = (idcode >> 12) & 0xffff;
1341	rev = (idcode >> 28) & 0xff;
1342
1343	- if (hawkeye == 0xb7ae) {
1344	+ switch (hawkeye) {
1345	+ case 0xb7ae:
1346	+ /* Handle 34xx/35xx devices */
1347	switch (rev) {
1348	- case 0:
1349	+ case 0: /* Take care of early samples */
1350	+ case 1:
1351	omap_revision = OMAP3430_REV_ES2_0;
1352	- rev_name = "ES2.0";
1353	break;
1354	case 2:
1355	omap_revision = OMAP3430_REV_ES2_1;
1356	- rev_name = "ES2.1";
1357	break;
1358	case 3:
1359	omap_revision = OMAP3430_REV_ES3_0;
1360	- rev_name = "ES3.0";
1361	break;
1362	case 4:
1363	omap_revision = OMAP3430_REV_ES3_1;
1364	- rev_name = "ES3.1";
1365	break;
1366	default:
1367	/* Use the latest known revision as default */
1368	omap_revision = OMAP3430_REV_ES3_1;
1369	- rev_name = "Unknown revision\n";
1370	}
1371	+ break;
1372	+ case 0xb891:
1373	+ /* Handle 36xx devices */
1374	+ switch (rev) {
1375	+ case 0:
1376	+ omap_revision = OMAP3630_REV_ES1_0;
1377	+ break;
1378	+ default:
1379	+ /* Use the latest known revision as default */
1380	+ omap_revision = OMAP3630_REV_ES1_0;
1381	+ }
1382	+ break;
1383	+ default:
1384	+ /* Unknown default to latest silicon rev as default*/
1385	+ omap_revision = OMAP3630_REV_ES1_0;
1386	}
1387	+}
1388
1389	-out:
1390	- pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
1391	+#define OMAP3_SHOW_FEATURE(feat) \
1392	+ if (omap3_has_ ##feat()) { \
1393	+ pr_info (" - "#feat" : Y"); \
1394	+ } else { \
1395	+ pr_info (" - "#feat" : N"); \
1396	+ }
1397	+
1398	+void __init omap3_cpuinfo(void)
1399	+{
1400	+ u8 rev = GET_OMAP_REVISION();
1401	+ char cpu_name[16], cpu_rev[16];
1402	+
1403	+ /* OMAP3430 and OMAP3530 are assumed to be same.
1404	+ *
1405	+ * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
1406	+ * on available features. Upon detection, update the CPU id
1407	+ * and CPU class bits.
1408	+ */
1409	+ if (cpu_is_omap3630())
1410	+ strcpy(cpu_name, "3630");
1411	+ else if (omap3_has_iva() && omap3_has_sgx())
1412	+ strcpy(cpu_name, "3430/3530");
1413	+ else if (omap3_has_sgx()) {
1414	+ omap_revision = OMAP3525_REV(rev);
1415	+ strcpy(cpu_name, "3525");
1416	+ }
1417	+ else if (omap3_has_iva()) {
1418	+ omap_revision = OMAP3515_REV(rev);
1419	+ strcpy(cpu_name, "3515");
1420	+ }
1421	+ else {
1422	+ omap_revision = OMAP3503_REV(rev);
1423	+ strcpy(cpu_name, "3503");
1424	+ }
1425	+
1426	+ switch (rev) {
1427	+ case OMAP_REVBITS_00:
1428	+ strcpy(cpu_rev, "1.0");
1429	+ break;
1430	+ case OMAP_REVBITS_10:
1431	+ strcpy(cpu_rev, "2.0");
1432	+ break;
1433	+ case OMAP_REVBITS_20:
1434	+ strcpy(cpu_rev, "2.1");
1435	+ break;
1436	+ case OMAP_REVBITS_30:
1437	+ strcpy(cpu_rev, "3.0");
1438	+ break;
1439	+ case OMAP_REVBITS_40:
1440	+ strcpy(cpu_rev, "3.1");
1441	+ break;
1442	+ default:
1443	+ /* Use the latest known revision as default */
1444	+ strcpy(cpu_rev, "3.1");
1445	+ }
1446	+
1447	+ /*
1448	+ * Print verbose information
1449	+ */
1450	+ pr_info("OMAP%s ES%s\n", cpu_name, cpu_rev);
1451	+
1452	+ OMAP3_SHOW_FEATURE(l2cache);
1453	+ OMAP3_SHOW_FEATURE(iva);
1454	+ OMAP3_SHOW_FEATURE(sgx);
1455	+ OMAP3_SHOW_FEATURE(neon);
1456	+ OMAP3_SHOW_FEATURE(isp);
1457	}
1458
1459	/*
1460	@@ -223,8 +327,11 @@ void __init omap2_check_revision(void)
1461	*/
1462	if (cpu_is_omap24xx())
1463	omap24xx_check_revision();
1464	- else if (cpu_is_omap34xx())
1465	- omap34xx_check_revision();
1466	+ else if (cpu_is_omap34xx()) {
1467	+ omap3_check_features();
1468	+ omap3_check_revision();
1469	+ omap3_cpuinfo();
1470	+ }
1471	else if (cpu_is_omap44xx()) {
1472	printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
1473	return;
1474	--- a/arch/arm/mach-omap2/io.c
1475	+++ b/arch/arm/mach-omap2/io.c
1476	@@ -204,6 +204,24 @@ static struct map_desc omap44xx_io_desc[
1477	.type = MT_DEVICE,
1478	},
1479	{
1480	+ .virtual = OMAP44XX_EMIF1_VIRT,
1481	+ .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
1482	+ .length = OMAP44XX_EMIF1_SIZE,
1483	+ .type = MT_DEVICE,
1484	+ },
1485	+ {
1486	+ .virtual = OMAP44XX_EMIF2_VIRT,
1487	+ .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
1488	+ .length = OMAP44XX_EMIF2_SIZE,
1489	+ .type = MT_DEVICE,
1490	+ },
1491	+ {
1492	+ .virtual = OMAP44XX_DMM_VIRT,
1493	+ .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
1494	+ .length = OMAP44XX_DMM_SIZE,
1495	+ .type = MT_DEVICE,
1496	+ },
1497	+ {
1498	.virtual = L4_PER_44XX_VIRT,
1499	.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
1500	.length = L4_PER_44XX_SIZE,
1501	--- a/arch/arm/mach-omap2/irq.c
1502	+++ b/arch/arm/mach-omap2/irq.c
1503	@@ -178,12 +178,20 @@ void __init omap_init_irq(void)
1504	int i;
1505
1506	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
1507	+ unsigned long base;
1508	struct omap_irq_bank *bank = irq_banks + i;
1509
1510	if (cpu_is_omap24xx())
1511	- bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
1512	+ base = OMAP24XX_IC_BASE;
1513	else if (cpu_is_omap34xx())
1514	- bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
1515	+ base = OMAP34XX_IC_BASE;
1516	+
1517	+ /* Static mapping, never released */
1518	+ bank->base_reg = ioremap(base, SZ_4K);
1519	+ if (!bank->base_reg) {
1520	+ printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
1521	+ continue;
1522	+ }
1523
1524	omap_irq_bank_init_one(bank);
1525
1526	--- a/arch/arm/mach-omap2/omap-smp.c
1527	+++ b/arch/arm/mach-omap2/omap-smp.c
1528	@@ -26,11 +26,11 @@
1529	#include <mach/hardware.h>
1530
1531	/* Registers used for communicating startup information */
1532	-#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800)
1533	-#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804)
1534	+static void __iomem *omap4_auxcoreboot_reg0;
1535	+static void __iomem *omap4_auxcoreboot_reg1;
1536
1537	/* SCU base address */
1538	-static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE;
1539	+static void __iomem *scu_base;
1540
1541	/*
1542	* Use SCU config register to count number of cores
1543	@@ -46,6 +46,8 @@ static DEFINE_SPINLOCK(boot_lock);
1544
1545	void __cpuinit platform_secondary_init(unsigned int cpu)
1546	{
1547	+ void __iomem *gic_cpu_base;
1548	+
1549	trace_hardirqs_off();
1550
1551	/*
1552	@@ -54,7 +56,10 @@ void __cpuinit platform_secondary_init(u
1553	* for us: do so
1554	*/
1555
1556	- gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
1557	+ /* Static mapping, never released */
1558	+ gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256);
1559	+ BUG_ON(!gic_cpu_base);
1560	+ gic_cpu_init(0, gic_cpu_base);
1561
1562	/*
1563	* Synchronise with the boot thread.
1564	@@ -79,7 +84,7 @@ int __cpuinit boot_secondary(unsigned in
1565	* the AuxCoreBoot1 register is updated with cpu state
1566	* A barrier is added to ensure that write buffer is drained
1567	*/
1568	- __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1);
1569	+ __raw_writel(cpu, omap4_auxcoreboot_reg1);
1570	smp_wmb();
1571
1572	timeout = jiffies + (1 * HZ);
1573	@@ -104,7 +109,7 @@ static void __init wakeup_secondary(void
1574	* A barrier is added to ensure that write buffer is drained
1575	*/
1576	__raw_writel(virt_to_phys(omap_secondary_startup), \
1577	- OMAP4_AUXCOREBOOT_REG0);
1578	+ omap4_auxcoreboot_reg0);
1579	smp_wmb();
1580
1581	/*
1582	@@ -130,6 +135,7 @@ void __init smp_prepare_cpus(unsigned in
1583	{
1584	unsigned int ncores = get_core_count();
1585	unsigned int cpu = smp_processor_id();
1586	+ void __iomem *omap4_wkupgen_base;
1587	int i;
1588
1589	/* sanity check */
1590	@@ -161,6 +167,16 @@ void __init smp_prepare_cpus(unsigned in
1591	for (i = 0; i < max_cpus; i++)
1592	set_cpu_present(i, true);
1593
1594	+ /* Never released */
1595	+ omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
1596	+ BUG_ON(!omap4_wkupgen_base);
1597	+ omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
1598	+ omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x804;
1599	+
1600	+ /* Never released */
1601	+ scu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256);
1602	+ BUG_ON(!scu_base);
1603	+
1604	if (max_cpus > 1) {
1605	/*
1606	* Enable the local timer or broadcast device for the
1607	--- a/arch/arm/mach-omap2/omap_hwmod.c
1608	+++ b/arch/arm/mach-omap2/omap_hwmod.c
1609	@@ -496,6 +496,7 @@ static void __iomem *_find_mpu_rt_base(s
1610	struct omap_hwmod_addr_space *mem;
1611	int i;
1612	int found = 0;
1613	+ void __iomem *va_start;
1614
1615	if (!oh \|\| oh->slaves_cnt == 0)
1616	return NULL;
1617	@@ -509,16 +510,20 @@ static void __iomem *_find_mpu_rt_base(s
1618	}
1619	}
1620
1621	- /* XXX use ioremap() instead? */
1622	-
1623	- if (found)
1624	+ if (found) {
1625	+ va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
1626	+ if (!va_start) {
1627	+ pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
1628	+ return NULL;
1629	+ }
1630	pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
1631	- oh->name, OMAP2_IO_ADDRESS(mem->pa_start));
1632	- else
1633	+ oh->name, va_start);
1634	+ } else {
1635	pr_debug("omap_hwmod: %s: no MPU register target found\n",
1636	oh->name);
1637	+ }
1638
1639	- return (found) ? OMAP2_IO_ADDRESS(mem->pa_start) : NULL;
1640	+ return (found) ? va_start : NULL;
1641	}
1642
1643	/**
1644	@@ -1148,6 +1153,7 @@ int omap_hwmod_unregister(struct omap_hw
1645	pr_debug("omap_hwmod: %s: unregistering\n", oh->name);
1646
1647	mutex_lock(&omap_hwmod_mutex);
1648	+ iounmap(oh->_rt_va);
1649	list_del(&oh->node);
1650	mutex_unlock(&omap_hwmod_mutex);
1651
1652	--- a/arch/arm/mach-omap2/pm-debug.c
1653	+++ b/arch/arm/mach-omap2/pm-debug.c
1654	@@ -51,7 +51,8 @@ int omap2_pm_debug;
1655	regs[reg_count++].val = __raw_readl(reg)
1656	#define DUMP_INTC_REG(reg, off) \
1657	regs[reg_count].name = #reg; \
1658	- regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off)))
1659	+ regs[reg_count++].val = \
1660	+ __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
1661
1662	static int __init pm_dbg_init(void);
1663
1664	--- a/arch/arm/mach-omap2/prm.h
1665	+++ b/arch/arm/mach-omap2/prm.h
1666	@@ -17,11 +17,11 @@
1667	#include "prcm-common.h"
1668
1669	#define OMAP2420_PRM_REGADDR(module, reg) \
1670	- OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
1671	+ OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
1672	#define OMAP2430_PRM_REGADDR(module, reg) \
1673	- OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
1674	+ OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
1675	#define OMAP34XX_PRM_REGADDR(module, reg) \
1676	- OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
1677	+ OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
1678
1679	/*
1680	* Architecture-specific global PRM registers
1681	--- a/arch/arm/mach-omap2/sdrc.h
1682	+++ b/arch/arm/mach-omap2/sdrc.h
1683	@@ -48,9 +48,12 @@ static inline u32 sms_read_reg(u16 reg)
1684	return __raw_readl(OMAP_SMS_REGADDR(reg));
1685	}
1686	#else
1687	-#define OMAP242X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
1688	-#define OMAP243X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
1689	-#define OMAP34XX_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
1690	+#define OMAP242X_SDRC_REGADDR(reg) \
1691	+ OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
1692	+#define OMAP243X_SDRC_REGADDR(reg) \
1693	+ OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
1694	+#define OMAP34XX_SDRC_REGADDR(reg) \
1695	+ OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
1696	#endif /* __ASSEMBLER__ */
1697
1698	#endif
1699	--- a/arch/arm/mach-omap2/serial.c
1700	+++ b/arch/arm/mach-omap2/serial.c
1701	@@ -73,7 +73,6 @@ static LIST_HEAD(uart_list);
1702
1703	static struct plat_serial8250_port serial_platform_data0[] = {
1704	{
1705	- .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
1706	.mapbase = OMAP_UART1_BASE,
1707	.irq = 72,
1708	.flags = UPF_BOOT_AUTOCONF,
1709	@@ -87,7 +86,6 @@ static struct plat_serial8250_port seria
1710
1711	static struct plat_serial8250_port serial_platform_data1[] = {
1712	{
1713	- .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
1714	.mapbase = OMAP_UART2_BASE,
1715	.irq = 73,
1716	.flags = UPF_BOOT_AUTOCONF,
1717	@@ -101,7 +99,6 @@ static struct plat_serial8250_port seria
1718
1719	static struct plat_serial8250_port serial_platform_data2[] = {
1720	{
1721	- .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
1722	.mapbase = OMAP_UART3_BASE,
1723	.irq = 74,
1724	.flags = UPF_BOOT_AUTOCONF,
1725	@@ -116,7 +113,6 @@ static struct plat_serial8250_port seria
1726	#ifdef CONFIG_ARCH_OMAP4
1727	static struct plat_serial8250_port serial_platform_data3[] = {
1728	{
1729	- .membase = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
1730	.mapbase = OMAP_UART4_BASE,
1731	.irq = 70,
1732	.flags = UPF_BOOT_AUTOCONF,
1733	@@ -539,7 +535,7 @@ static inline void omap_uart_idle_init(s
1734	#define DEV_CREATE_FILE(dev, attr)
1735	#endif /* CONFIG_PM */
1736
1737	-static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
1738	+static struct omap_uart_state omap_uart[] = {
1739	{
1740	.pdev = {
1741	.name = "serial8250",
1742	@@ -589,12 +585,22 @@ void __init omap_serial_early_init(void)
1743	* if not needed.
1744	*/
1745
1746	- for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
1747	+ for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
1748	struct omap_uart_state *uart = &omap_uart[i];
1749	struct platform_device *pdev = &uart->pdev;
1750	struct device *dev = &pdev->dev;
1751	struct plat_serial8250_port *p = dev->platform_data;
1752
1753	+ /*
1754	+ * Module 4KB + L4 interconnect 4KB
1755	+ * Static mapping, never released
1756	+ */
1757	+ p->membase = ioremap(p->mapbase, SZ_8K);
1758	+ if (!p->membase) {
1759	+ printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
1760	+ continue;
1761	+ }
1762	+
1763	sprintf(name, "uart%d_ick", i+1);
1764	uart->ick = clk_get(NULL, name);
1765	if (IS_ERR(uart->ick)) {
1766	@@ -631,7 +637,7 @@ void __init omap_serial_init(void)
1767	{
1768	int i;
1769
1770	- for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
1771	+ for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
1772	struct omap_uart_state *uart = &omap_uart[i];
1773	struct platform_device *pdev = &uart->pdev;
1774	struct device *dev = &pdev->dev;
1775	--- a/arch/arm/mach-omap2/sram242x.S
1776	+++ b/arch/arm/mach-omap2/sram242x.S
1777	@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl:
1778	prcm_mask_val:
1779	.word 0xFFFF3FFC
1780	omap242x_sdi_timer_32ksynct_cr:
1781	- .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1782	+ .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1783	ENTRY(omap242x_sram_ddr_init_sz)
1784	.word . - omap242x_sram_ddr_init
1785
1786	@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl:
1787	ddr_prcm_mask_val:
1788	.word 0xFFFF3FFC
1789	omap242x_srs_timer_32ksynct:
1790	- .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1791	+ .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1792
1793	ENTRY(omap242x_sram_reprogram_sdrc_sz)
1794	.word . - omap242x_sram_reprogram_sdrc
1795	--- a/arch/arm/mach-omap2/sram243x.S
1796	+++ b/arch/arm/mach-omap2/sram243x.S
1797	@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl:
1798	prcm_mask_val:
1799	.word 0xFFFF3FFC
1800	omap243x_sdi_timer_32ksynct_cr:
1801	- .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
1802	+ .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
1803	ENTRY(omap243x_sram_ddr_init_sz)
1804	.word . - omap243x_sram_ddr_init
1805
1806	@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl:
1807	ddr_prcm_mask_val:
1808	.word 0xFFFF3FFC
1809	omap243x_srs_timer_32ksynct:
1810	- .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
1811	+ .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
1812
1813	ENTRY(omap243x_sram_reprogram_sdrc_sz)
1814	.word . - omap243x_sram_reprogram_sdrc
1815	--- a/arch/arm/mach-omap2/timer-gp.c
1816	+++ b/arch/arm/mach-omap2/timer-gp.c
1817	@@ -231,7 +231,8 @@ static void __init omap2_gp_clocksource_
1818	static void __init omap2_gp_timer_init(void)
1819	{
1820	#ifdef CONFIG_LOCAL_TIMERS
1821	- twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
1822	+ twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
1823	+ BUG_ON(!twd_base);
1824	#endif
1825	omap_dm_timer_init();
1826
1827	--- /dev/null
1828	+++ b/arch/arm/mach-omap2/usb-ehci.c
1829	@@ -0,0 +1,192 @@
1830	+/*
1831	+ * linux/arch/arm/mach-omap2/usb-ehci.c
1832	+ *
1833	+ * This file will contain the board specific details for the
1834	+ * Synopsys EHCI host controller on OMAP3430
1835	+ *
1836	+ * Copyright (C) 2007 Texas Instruments
1837	+ * Author: Vikram Pandita <vikram.pandita@ti.com>
1838	+ *
1839	+ * Generalization by:
1840	+ * Felipe Balbi <felipe.balbi@nokia.com>
1841	+ *
1842	+ * This program is free software; you can redistribute it and/or modify
1843	+ * it under the terms of the GNU General Public License version 2 as
1844	+ * published by the Free Software Foundation.
1845	+ */
1846	+
1847	+#include <linux/types.h>
1848	+#include <linux/errno.h>
1849	+#include <linux/delay.h>
1850	+#include <linux/platform_device.h>
1851	+#include <linux/clk.h>
1852	+#include <asm/io.h>
1853	+#include <mach/mux.h>
1854	+
1855	+#include <mach/hardware.h>
1856	+#include <mach/irqs.h>
1857	+#include <mach/usb.h>
1858	+
1859	+#if defined(CONFIG_USB_EHCI_HCD) \|\| defined(CONFIG_USB_EHCI_HCD_MODULE)
1860	+
1861	+static struct resource ehci_resources[] = {
1862	+ {
1863	+ .start = OMAP34XX_EHCI_BASE,
1864	+ .end = OMAP34XX_EHCI_BASE + SZ_1K - 1,
1865	+ .flags = IORESOURCE_MEM,
1866	+ },
1867	+ {
1868	+ .start = OMAP34XX_UHH_CONFIG_BASE,
1869	+ .end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1,
1870	+ .flags = IORESOURCE_MEM,
1871	+ },
1872	+ {
1873	+ .start = OMAP34XX_USBTLL_BASE,
1874	+ .end = OMAP34XX_USBTLL_BASE + SZ_4K - 1,
1875	+ .flags = IORESOURCE_MEM,
1876	+ },
1877	+ { /* general IRQ */
1878	+ .start = INT_34XX_EHCI_IRQ,
1879	+ .flags = IORESOURCE_IRQ,
1880	+ }
1881	+};
1882	+
1883	+static u64 ehci_dmamask = ~(u32)0;
1884	+static struct platform_device ehci_device = {
1885	+ .name = "ehci-omap",
1886	+ .id = 0,
1887	+ .dev = {
1888	+ .dma_mask = &ehci_dmamask,
1889	+ .coherent_dma_mask = 0xffffffff,
1890	+ .platform_data = NULL,
1891	+ },
1892	+ .num_resources = ARRAY_SIZE(ehci_resources),
1893	+ .resource = ehci_resources,
1894	+};
1895	+
1896	+/* MUX settings for EHCI pins */
1897	+/*
1898	+ * setup_ehci_io_mux - initialize IO pad mux for USBHOST
1899	+ */
1900	+static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
1901	+{
1902	+ switch (port_mode[0]) {
1903	+ case EHCI_HCD_OMAP_MODE_PHY:
1904	+ omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
1905	+ omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
1906	+ omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
1907	+ omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
1908	+ omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
1909	+ omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
1910	+ omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
1911	+ omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
1912	+ omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
1913	+ omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
1914	+ omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
1915	+ omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
1916	+ break;
1917	+ case EHCI_HCD_OMAP_MODE_TLL:
1918	+ omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
1919	+ omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
1920	+ omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
1921	+ omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
1922	+ omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
1923	+ omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
1924	+ omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
1925	+ omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
1926	+ omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
1927	+ omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
1928	+ omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
1929	+ omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
1930	+ break;
1931	+ case EHCI_HCD_OMAP_MODE_UNKNOWN:
1932	+ /* FALLTHROUGH */
1933	+ default:
1934	+ break;
1935	+ }
1936	+
1937	+ switch (port_mode[1]) {
1938	+ case EHCI_HCD_OMAP_MODE_PHY:
1939	+ omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
1940	+ omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
1941	+ omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
1942	+ omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
1943	+ omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
1944	+ omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
1945	+ omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
1946	+ omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
1947	+ omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
1948	+ omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
1949	+ omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
1950	+ omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
1951	+ break;
1952	+ case EHCI_HCD_OMAP_MODE_TLL:
1953	+ omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
1954	+ omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
1955	+ omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
1956	+ omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
1957	+ omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
1958	+ omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
1959	+ omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
1960	+ omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
1961	+ omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
1962	+ omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
1963	+ omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
1964	+ omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
1965	+ break;
1966	+ case EHCI_HCD_OMAP_MODE_UNKNOWN:
1967	+ /* FALLTHROUGH */
1968	+ default:
1969	+ break;
1970	+ }
1971	+
1972	+ switch (port_mode[2]) {
1973	+ case EHCI_HCD_OMAP_MODE_PHY:
1974	+ printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
1975	+ break;
1976	+ case EHCI_HCD_OMAP_MODE_TLL:
1977	+ omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
1978	+ omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
1979	+ omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
1980	+ omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
1981	+ omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
1982	+ omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
1983	+ omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
1984	+ omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
1985	+ omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
1986	+ omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
1987	+ omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
1988	+ omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
1989	+ break;
1990	+ case EHCI_HCD_OMAP_MODE_UNKNOWN:
1991	+ /* FALLTHROUGH */
1992	+ default:
1993	+ break;
1994	+ }
1995	+
1996	+ return;
1997	+}
1998	+
1999	+void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
2000	+{
2001	+ platform_device_add_data(&ehci_device, pdata, sizeof(*pdata));
2002	+
2003	+ /* Setup Pin IO MUX for EHCI */
2004	+ if (cpu_is_omap34xx())
2005	+ setup_ehci_io_mux(pdata->port_mode);
2006	+
2007	+ if (platform_device_register(&ehci_device) < 0) {
2008	+ printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
2009	+ return;
2010	+ }
2011	+}
2012	+
2013	+#else
2014	+
2015	+void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
2016	+
2017	+{
2018	+}
2019	+
2020	+#endif /* CONFIG_USB_EHCI_HCD */
2021	+
2022	--- a/arch/arm/plat-omap/common.c
2023	+++ b/arch/arm/plat-omap/common.c
2024	@@ -224,12 +224,12 @@ static void __init __omap2_set_globals(s
2025
2026	static struct omap_globals omap242x_globals = {
2027	.class = OMAP242X_CLASS,
2028	- .tap = OMAP2_IO_ADDRESS(0x48014000),
2029	- .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
2030	- .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
2031	- .ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
2032	- .prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
2033	- .cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
2034	+ .tap = OMAP2_L4_IO_ADDRESS(0x48014000),
2035	+ .sdrc = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
2036	+ .sms = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
2037	+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE),
2038	+ .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
2039	+ .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
2040	};
2041
2042	void __init omap2_set_globals_242x(void)
2043	@@ -242,12 +242,12 @@ void __init omap2_set_globals_242x(void)
2044
2045	static struct omap_globals omap243x_globals = {
2046	.class = OMAP243X_CLASS,
2047	- .tap = OMAP2_IO_ADDRESS(0x4900a000),
2048	- .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
2049	- .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
2050	- .ctrl = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
2051	- .prm = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
2052	- .cm = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
2053	+ .tap = OMAP2_L4_IO_ADDRESS(0x4900a000),
2054	+ .sdrc = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
2055	+ .sms = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
2056	+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
2057	+ .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
2058	+ .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
2059	};
2060
2061	void __init omap2_set_globals_243x(void)
2062	@@ -260,12 +260,12 @@ void __init omap2_set_globals_243x(void)
2063
2064	static struct omap_globals omap343x_globals = {
2065	.class = OMAP343X_CLASS,
2066	- .tap = OMAP2_IO_ADDRESS(0x4830A000),
2067	- .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
2068	- .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
2069	- .ctrl = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
2070	- .prm = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
2071	- .cm = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
2072	+ .tap = OMAP2_L4_IO_ADDRESS(0x4830A000),
2073	+ .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
2074	+ .sms = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
2075	+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
2076	+ .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
2077	+ .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
2078	};
2079
2080	void __init omap2_set_globals_343x(void)
2081	@@ -277,10 +277,10 @@ void __init omap2_set_globals_343x(void)
2082	#if defined(CONFIG_ARCH_OMAP4)
2083	static struct omap_globals omap4_globals = {
2084	.class = OMAP443X_CLASS,
2085	- .tap = OMAP2_IO_ADDRESS(0x4830a000),
2086	- .ctrl = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE),
2087	- .prm = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE),
2088	- .cm = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE),
2089	+ .tap = OMAP2_L4_IO_ADDRESS(0x4830a000),
2090	+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
2091	+ .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
2092	+ .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
2093	};
2094
2095	void __init omap2_set_globals_443x(void)
2096	--- a/arch/arm/plat-omap/devices.c
2097	+++ b/arch/arm/plat-omap/devices.c
2098	@@ -113,17 +113,17 @@ static void omap_init_kp(void)
2099	omap_cfg_reg(E19_1610_KBR4);
2100	omap_cfg_reg(N19_1610_KBR5);
2101	} else if (machine_is_omap_perseus2() \|\| machine_is_omap_fsample()) {
2102	- omap_cfg_reg(E2_730_KBR0);
2103	- omap_cfg_reg(J7_730_KBR1);
2104	- omap_cfg_reg(E1_730_KBR2);
2105	- omap_cfg_reg(F3_730_KBR3);
2106	- omap_cfg_reg(D2_730_KBR4);
2107	-
2108	- omap_cfg_reg(C2_730_KBC0);
2109	- omap_cfg_reg(D3_730_KBC1);
2110	- omap_cfg_reg(E4_730_KBC2);
2111	- omap_cfg_reg(F4_730_KBC3);
2112	- omap_cfg_reg(E3_730_KBC4);
2113	+ omap_cfg_reg(E2_7XX_KBR0);
2114	+ omap_cfg_reg(J7_7XX_KBR1);
2115	+ omap_cfg_reg(E1_7XX_KBR2);
2116	+ omap_cfg_reg(F3_7XX_KBR3);
2117	+ omap_cfg_reg(D2_7XX_KBR4);
2118	+
2119	+ omap_cfg_reg(C2_7XX_KBC0);
2120	+ omap_cfg_reg(D3_7XX_KBC1);
2121	+ omap_cfg_reg(E4_7XX_KBC2);
2122	+ omap_cfg_reg(F4_7XX_KBC3);
2123	+ omap_cfg_reg(E3_7XX_KBC4);
2124	} else if (machine_is_omap_h4()) {
2125	omap_cfg_reg(T19_24XX_KBR0);
2126	omap_cfg_reg(R19_24XX_KBR1);
2127	--- a/arch/arm/plat-omap/dma.c
2128	+++ b/arch/arm/plat-omap/dma.c
2129	@@ -2359,40 +2359,46 @@ EXPORT_SYMBOL(omap_stop_lcd_dma);
2130
2131	static int __init omap_init_dma(void)
2132	{
2133	+ unsigned long base;
2134	int ch, r;
2135
2136	if (cpu_class_is_omap1()) {
2137	- omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
2138	+ base = OMAP1_DMA_BASE;
2139	dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2140	} else if (cpu_is_omap24xx()) {
2141	- omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
2142	+ base = OMAP24XX_DMA4_BASE;
2143	dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2144	} else if (cpu_is_omap34xx()) {
2145	- omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
2146	+ base = OMAP34XX_DMA4_BASE;
2147	dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2148	} else if (cpu_is_omap44xx()) {
2149	- omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
2150	+ base = OMAP44XX_DMA4_BASE;
2151	dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2152	} else {
2153	pr_err("DMA init failed for unsupported omap\n");
2154	return -ENODEV;
2155	}
2156
2157	+ omap_dma_base = ioremap(base, SZ_4K);
2158	+ BUG_ON(!omap_dma_base);
2159	+
2160	if (cpu_class_is_omap2() && omap_dma_reserve_channels
2161	&& (omap_dma_reserve_channels <= dma_lch_count))
2162	dma_lch_count = omap_dma_reserve_channels;
2163
2164	dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2165	GFP_KERNEL);
2166	- if (!dma_chan)
2167	- return -ENOMEM;
2168	+ if (!dma_chan) {
2169	+ r = -ENOMEM;
2170	+ goto out_unmap;
2171	+ }
2172
2173	if (cpu_class_is_omap2()) {
2174	dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2175	dma_lch_count, GFP_KERNEL);
2176	if (!dma_linked_lch) {
2177	- kfree(dma_chan);
2178	- return -ENOMEM;
2179	+ r = -ENOMEM;
2180	+ goto out_free;
2181	}
2182	}
2183
2184	@@ -2466,7 +2472,7 @@ static int __init omap_init_dma(void)
2185	for (i = 0; i < ch; i++)
2186	free_irq(omap1_dma_irq[i],
2187	(void *) (i + 1));
2188	- return r;
2189	+ goto out_free;
2190	}
2191	}
2192	}
2193	@@ -2508,11 +2514,19 @@ static int __init omap_init_dma(void)
2194	"(error %d)\n", r);
2195	for (i = 0; i < dma_chan_count; i++)
2196	free_irq(omap1_dma_irq[i], (void *) (i + 1));
2197	- return r;
2198	+ goto out_free;
2199	}
2200	}
2201
2202	return 0;
2203	+
2204	+out_free:
2205	+ kfree(dma_chan);
2206	+
2207	+out_unmap:
2208	+ iounmap(omap_dma_base);
2209	+
2210	+ return r;
2211	}
2212
2213	arch_initcall(omap_init_dma);
2214	--- a/arch/arm/plat-omap/dmtimer.c
2215	+++ b/arch/arm/plat-omap/dmtimer.c
2216	@@ -742,16 +742,17 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active)
2217	int __init omap_dm_timer_init(void)
2218	{
2219	struct omap_dm_timer *timer;
2220	- int i;
2221	+ int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
2222
2223	if (!(cpu_is_omap16xx() \|\| cpu_class_is_omap2()))
2224	return -ENODEV;
2225
2226	spin_lock_init(&dm_timer_lock);
2227
2228	- if (cpu_class_is_omap1())
2229	+ if (cpu_class_is_omap1()) {
2230	dm_timers = omap1_dm_timers;
2231	- else if (cpu_is_omap24xx()) {
2232	+ map_size = SZ_2K;
2233	+ } else if (cpu_is_omap24xx()) {
2234	dm_timers = omap2_dm_timers;
2235	dm_source_names = omap2_dm_source_names;
2236	dm_source_clocks = omap2_dm_source_clocks;
2237	@@ -774,10 +775,11 @@ int __init omap_dm_timer_init(void)
2238
2239	for (i = 0; i < dm_timer_count; i++) {
2240	timer = &dm_timers[i];
2241	- if (cpu_class_is_omap1())
2242	- timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base);
2243	- else
2244	- timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base);
2245	+
2246	+ /* Static mapping, never released */
2247	+ timer->io_base = ioremap(timer->phys_base, map_size);
2248	+ BUG_ON(!timer->io_base);
2249	+
2250	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3) \|\| \
2251	defined(CONFIG_ARCH_OMAP4)
2252	if (cpu_class_is_omap2()) {
2253	--- a/arch/arm/plat-omap/gpio.c
2254	+++ b/arch/arm/plat-omap/gpio.c
2255	@@ -31,7 +31,7 @@
2256	/*
2257	* OMAP1510 GPIO registers
2258	*/
2259	-#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000)
2260	+#define OMAP1510_GPIO_BASE 0xfffce000
2261	#define OMAP1510_GPIO_DATA_INPUT 0x00
2262	#define OMAP1510_GPIO_DATA_OUTPUT 0x04
2263	#define OMAP1510_GPIO_DIR_CONTROL 0x08
2264	@@ -45,10 +45,10 @@
2265	/*
2266	* OMAP1610 specific GPIO registers
2267	*/
2268	-#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400)
2269	-#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00)
2270	-#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400)
2271	-#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00)
2272	+#define OMAP1610_GPIO1_BASE 0xfffbe400
2273	+#define OMAP1610_GPIO2_BASE 0xfffbec00
2274	+#define OMAP1610_GPIO3_BASE 0xfffbb400
2275	+#define OMAP1610_GPIO4_BASE 0xfffbbc00
2276	#define OMAP1610_GPIO_REVISION 0x0000
2277	#define OMAP1610_GPIO_SYSCONFIG 0x0010
2278	#define OMAP1610_GPIO_SYSSTATUS 0x0014
2279	@@ -68,52 +68,36 @@
2280	#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
2281
2282	/*
2283	- * OMAP730 specific GPIO registers
2284	+ * OMAP7XX specific GPIO registers
2285	*/
2286	-#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
2287	-#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
2288	-#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
2289	-#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
2290	-#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
2291	-#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
2292	-#define OMAP730_GPIO_DATA_INPUT 0x00
2293	-#define OMAP730_GPIO_DATA_OUTPUT 0x04
2294	-#define OMAP730_GPIO_DIR_CONTROL 0x08
2295	-#define OMAP730_GPIO_INT_CONTROL 0x0c
2296	-#define OMAP730_GPIO_INT_MASK 0x10
2297	-#define OMAP730_GPIO_INT_STATUS 0x14
2298	+#define OMAP7XX_GPIO1_BASE 0xfffbc000
2299	+#define OMAP7XX_GPIO2_BASE 0xfffbc800
2300	+#define OMAP7XX_GPIO3_BASE 0xfffbd000
2301	+#define OMAP7XX_GPIO4_BASE 0xfffbd800
2302	+#define OMAP7XX_GPIO5_BASE 0xfffbe000
2303	+#define OMAP7XX_GPIO6_BASE 0xfffbe800
2304	+#define OMAP7XX_GPIO_DATA_INPUT 0x00
2305	+#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
2306	+#define OMAP7XX_GPIO_DIR_CONTROL 0x08
2307	+#define OMAP7XX_GPIO_INT_CONTROL 0x0c
2308	+#define OMAP7XX_GPIO_INT_MASK 0x10
2309	+#define OMAP7XX_GPIO_INT_STATUS 0x14
2310
2311	-/*
2312	- * OMAP850 specific GPIO registers
2313	- */
2314	-#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
2315	-#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
2316	-#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
2317	-#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
2318	-#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
2319	-#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
2320	-#define OMAP850_GPIO_DATA_INPUT 0x00
2321	-#define OMAP850_GPIO_DATA_OUTPUT 0x04
2322	-#define OMAP850_GPIO_DIR_CONTROL 0x08
2323	-#define OMAP850_GPIO_INT_CONTROL 0x0c
2324	-#define OMAP850_GPIO_INT_MASK 0x10
2325	-#define OMAP850_GPIO_INT_STATUS 0x14
2326	-
2327	-#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
2328	+#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
2329
2330	/*
2331	* omap24xx specific GPIO registers
2332	*/
2333	-#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000)
2334	-#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000)
2335	-#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000)
2336	-#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000)
2337	-
2338	-#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000)
2339	-#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000)
2340	-#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000)
2341	-#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000)
2342	-#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000)
2343	+#define OMAP242X_GPIO1_BASE 0x48018000
2344	+#define OMAP242X_GPIO2_BASE 0x4801a000
2345	+#define OMAP242X_GPIO3_BASE 0x4801c000
2346	+#define OMAP242X_GPIO4_BASE 0x4801e000
2347	+
2348	+#define OMAP243X_GPIO1_BASE 0x4900C000
2349	+#define OMAP243X_GPIO2_BASE 0x4900E000
2350	+#define OMAP243X_GPIO3_BASE 0x49010000
2351	+#define OMAP243X_GPIO4_BASE 0x49012000
2352	+#define OMAP243X_GPIO5_BASE 0x480B6000
2353
2354	#define OMAP24XX_GPIO_REVISION 0x0000
2355	#define OMAP24XX_GPIO_SYSCONFIG 0x0010
2356	@@ -170,24 +154,25 @@
2357	* omap34xx specific GPIO registers
2358	*/
2359
2360	-#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000)
2361	-#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000)
2362	-#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000)
2363	-#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000)
2364	-#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000)
2365	-#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000)
2366	+#define OMAP34XX_GPIO1_BASE 0x48310000
2367	+#define OMAP34XX_GPIO2_BASE 0x49050000
2368	+#define OMAP34XX_GPIO3_BASE 0x49052000
2369	+#define OMAP34XX_GPIO4_BASE 0x49054000
2370	+#define OMAP34XX_GPIO5_BASE 0x49056000
2371	+#define OMAP34XX_GPIO6_BASE 0x49058000
2372
2373	/*
2374	* OMAP44XX specific GPIO registers
2375	*/
2376	-#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000)
2377	-#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000)
2378	-#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000)
2379	-#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000)
2380	-#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000)
2381	-#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000)
2382	+#define OMAP44XX_GPIO1_BASE 0x4a310000
2383	+#define OMAP44XX_GPIO2_BASE 0x48055000
2384	+#define OMAP44XX_GPIO3_BASE 0x48057000
2385	+#define OMAP44XX_GPIO4_BASE 0x48059000
2386	+#define OMAP44XX_GPIO5_BASE 0x4805B000
2387	+#define OMAP44XX_GPIO6_BASE 0x4805D000
2388
2389	struct gpio_bank {
2390	+ unsigned long pbase;
2391	void __iomem *base;
2392	u16 irq;
2393	u16 virtual_irq_start;
2394	@@ -215,96 +200,111 @@ struct gpio_bank {
2395	#define METHOD_MPUIO 0
2396	#define METHOD_GPIO_1510 1
2397	#define METHOD_GPIO_1610 2
2398	-#define METHOD_GPIO_730 3
2399	-#define METHOD_GPIO_850 4
2400	+#define METHOD_GPIO_7XX 3
2401	#define METHOD_GPIO_24XX 5
2402
2403	#ifdef CONFIG_ARCH_OMAP16XX
2404	static struct gpio_bank gpio_bank_1610[5] = {
2405	- { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
2406	- { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
2407	- { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
2408	- { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
2409	- { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
2410	+ { OMAP1_MPUIO_VBASE, 0, INT_MPUIO, IH_MPUIO_BASE,
2411	+ METHOD_MPUIO },
2412	+ { OMAP1610_GPIO1_BASE, 0, INT_GPIO_BANK1, IH_GPIO_BASE,
2413	+ METHOD_GPIO_1610 },
2414	+ { OMAP1610_GPIO2_BASE, 0, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
2415	+ METHOD_GPIO_1610 },
2416	+ { OMAP1610_GPIO3_BASE, 0, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
2417	+ METHOD_GPIO_1610 },
2418	+ { OMAP1610_GPIO4_BASE, 0, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
2419	+ METHOD_GPIO_1610 },
2420	};
2421	#endif
2422
2423	#ifdef CONFIG_ARCH_OMAP15XX
2424	static struct gpio_bank gpio_bank_1510[2] = {
2425	- { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
2426	- { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
2427	-};
2428	-#endif
2429	-
2430	-#ifdef CONFIG_ARCH_OMAP730
2431	-static struct gpio_bank gpio_bank_730[7] = {
2432	- { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
2433	- { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
2434	- { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
2435	- { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
2436	- { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
2437	- { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
2438	- { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
2439	+ { OMAP1_MPUIO_VBASE, 0, INT_MPUIO, IH_MPUIO_BASE,
2440	+ METHOD_MPUIO },
2441	+ { OMAP1510_GPIO_BASE, 0, INT_GPIO_BANK1, IH_GPIO_BASE,
2442	+ METHOD_GPIO_1510 }
2443	};
2444	#endif
2445
2446	-#ifdef CONFIG_ARCH_OMAP850
2447	-static struct gpio_bank gpio_bank_850[7] = {
2448	- { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
2449	- { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
2450	- { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
2451	- { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
2452	- { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
2453	- { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
2454	- { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
2455	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2456	+static struct gpio_bank gpio_bank_7xx[7] = {
2457	+ { OMAP1_MPUIO_VBASE, 0, INT_7XX_MPUIO, IH_MPUIO_BASE,
2458	+ METHOD_MPUIO },
2459	+ { OMAP7XX_GPIO1_BASE, 0, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
2460	+ METHOD_GPIO_7XX },
2461	+ { OMAP7XX_GPIO2_BASE, 0, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2462	+ METHOD_GPIO_7XX },
2463	+ { OMAP7XX_GPIO3_BASE, 0, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2464	+ METHOD_GPIO_7XX },
2465	+ { OMAP7XX_GPIO4_BASE, 0, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2466	+ METHOD_GPIO_7XX },
2467	+ { OMAP7XX_GPIO5_BASE, 0, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
2468	+ METHOD_GPIO_7XX },
2469	+ { OMAP7XX_GPIO6_BASE, 0, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
2470	+ METHOD_GPIO_7XX },
2471	};
2472	#endif
2473
2474	-
2475	#ifdef CONFIG_ARCH_OMAP24XX
2476
2477	static struct gpio_bank gpio_bank_242x[4] = {
2478	- { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
2479	- { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
2480	- { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
2481	- { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
2482	+ { OMAP242X_GPIO1_BASE, 0, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
2483	+ METHOD_GPIO_24XX },
2484	+ { OMAP242X_GPIO2_BASE, 0, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2485	+ METHOD_GPIO_24XX },
2486	+ { OMAP242X_GPIO3_BASE, 0, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2487	+ METHOD_GPIO_24XX },
2488	+ { OMAP242X_GPIO4_BASE, 0, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2489	+ METHOD_GPIO_24XX },
2490	};
2491
2492	static struct gpio_bank gpio_bank_243x[5] = {
2493	- { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
2494	- { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
2495	- { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
2496	- { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
2497	- { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
2498	+ { OMAP243X_GPIO1_BASE, 0, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
2499	+ METHOD_GPIO_24XX },
2500	+ { OMAP243X_GPIO2_BASE, 0, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2501	+ METHOD_GPIO_24XX },
2502	+ { OMAP243X_GPIO3_BASE, 0, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2503	+ METHOD_GPIO_24XX },
2504	+ { OMAP243X_GPIO4_BASE, 0, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2505	+ METHOD_GPIO_24XX },
2506	+ { OMAP243X_GPIO5_BASE, 0, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
2507	+ METHOD_GPIO_24XX },
2508	};
2509
2510	#endif
2511
2512	#ifdef CONFIG_ARCH_OMAP34XX
2513	static struct gpio_bank gpio_bank_34xx[6] = {
2514	- { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
2515	- { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
2516	- { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
2517	- { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
2518	- { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
2519	- { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
2520	+ { OMAP34XX_GPIO1_BASE, 0, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
2521	+ METHOD_GPIO_24XX },
2522	+ { OMAP34XX_GPIO2_BASE, 0, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2523	+ METHOD_GPIO_24XX },
2524	+ { OMAP34XX_GPIO3_BASE, 0, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2525	+ METHOD_GPIO_24XX },
2526	+ { OMAP34XX_GPIO4_BASE, 0, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2527	+ METHOD_GPIO_24XX },
2528	+ { OMAP34XX_GPIO5_BASE, 0, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
2529	+ METHOD_GPIO_24XX },
2530	+ { OMAP34XX_GPIO6_BASE, 0, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
2531	+ METHOD_GPIO_24XX },
2532	};
2533
2534	#endif
2535
2536	#ifdef CONFIG_ARCH_OMAP4
2537	static struct gpio_bank gpio_bank_44xx[6] = {
2538	- { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
2539	+ { OMAP44XX_GPIO1_BASE, 0, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
2540	METHOD_GPIO_24XX },
2541	- { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
2542	+ { OMAP44XX_GPIO2_BASE, 0, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2543	METHOD_GPIO_24XX },
2544	- { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
2545	+ { OMAP44XX_GPIO3_BASE, 0, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2546	METHOD_GPIO_24XX },
2547	- { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
2548	+ { OMAP44XX_GPIO4_BASE, 0, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2549	METHOD_GPIO_24XX },
2550	- { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
2551	+ { OMAP44XX_GPIO5_BASE, 0, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
2552	METHOD_GPIO_24XX },
2553	- { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
2554	+ { OMAP44XX_GPIO6_BASE, 0, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
2555	METHOD_GPIO_24XX },
2556	};
2557
2558	@@ -402,14 +402,9 @@ static void _set_gpio_direction(struct g
2559	reg += OMAP1610_GPIO_DIRECTION;
2560	break;
2561	#endif
2562	-#ifdef CONFIG_ARCH_OMAP730
2563	- case METHOD_GPIO_730:
2564	- reg += OMAP730_GPIO_DIR_CONTROL;
2565	- break;
2566	-#endif
2567	-#ifdef CONFIG_ARCH_OMAP850
2568	- case METHOD_GPIO_850:
2569	- reg += OMAP850_GPIO_DIR_CONTROL;
2570	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2571	+ case METHOD_GPIO_7XX:
2572	+ reg += OMAP7XX_GPIO_DIR_CONTROL;
2573	break;
2574	#endif
2575	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
2576	@@ -469,19 +464,9 @@ static void _set_gpio_dataout(struct gpi
2577	l = 1 << gpio;
2578	break;
2579	#endif
2580	-#ifdef CONFIG_ARCH_OMAP730
2581	- case METHOD_GPIO_730:
2582	- reg += OMAP730_GPIO_DATA_OUTPUT;
2583	- l = __raw_readl(reg);
2584	- if (enable)
2585	- l \|= 1 << gpio;
2586	- else
2587	- l &= ~(1 << gpio);
2588	- break;
2589	-#endif
2590	-#ifdef CONFIG_ARCH_OMAP850
2591	- case METHOD_GPIO_850:
2592	- reg += OMAP850_GPIO_DATA_OUTPUT;
2593	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2594	+ case METHOD_GPIO_7XX:
2595	+ reg += OMAP7XX_GPIO_DATA_OUTPUT;
2596	l = __raw_readl(reg);
2597	if (enable)
2598	l \|= 1 << gpio;
2599	@@ -537,14 +522,9 @@ static int _get_gpio_datain(struct gpio_
2600	reg += OMAP1610_GPIO_DATAIN;
2601	break;
2602	#endif
2603	-#ifdef CONFIG_ARCH_OMAP730
2604	- case METHOD_GPIO_730:
2605	- reg += OMAP730_GPIO_DATA_INPUT;
2606	- break;
2607	-#endif
2608	-#ifdef CONFIG_ARCH_OMAP850
2609	- case METHOD_GPIO_850:
2610	- reg += OMAP850_GPIO_DATA_INPUT;
2611	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2612	+ case METHOD_GPIO_7XX:
2613	+ reg += OMAP7XX_GPIO_DATA_INPUT;
2614	break;
2615	#endif
2616	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
2617	@@ -588,14 +568,9 @@ static int _get_gpio_dataout(struct gpio
2618	reg += OMAP1610_GPIO_DATAOUT;
2619	break;
2620	#endif
2621	-#ifdef CONFIG_ARCH_OMAP730
2622	- case METHOD_GPIO_730:
2623	- reg += OMAP730_GPIO_DATA_OUTPUT;
2624	- break;
2625	-#endif
2626	-#ifdef CONFIG_ARCH_OMAP850
2627	- case METHOD_GPIO_850:
2628	- reg += OMAP850_GPIO_DATA_OUTPUT;
2629	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2630	+ case METHOD_GPIO_7XX:
2631	+ reg += OMAP7XX_GPIO_DATA_OUTPUT;
2632	break;
2633	#endif
2634	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
2635	@@ -797,21 +772,9 @@ static int _set_gpio_triggering(struct g
2636	__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
2637	break;
2638	#endif
2639	-#ifdef CONFIG_ARCH_OMAP730
2640	- case METHOD_GPIO_730:
2641	- reg += OMAP730_GPIO_INT_CONTROL;
2642	- l = __raw_readl(reg);
2643	- if (trigger & IRQ_TYPE_EDGE_RISING)
2644	- l \|= 1 << gpio;
2645	- else if (trigger & IRQ_TYPE_EDGE_FALLING)
2646	- l &= ~(1 << gpio);
2647	- else
2648	- goto bad;
2649	- break;
2650	-#endif
2651	-#ifdef CONFIG_ARCH_OMAP850
2652	- case METHOD_GPIO_850:
2653	- reg += OMAP850_GPIO_INT_CONTROL;
2654	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2655	+ case METHOD_GPIO_7XX:
2656	+ reg += OMAP7XX_GPIO_INT_CONTROL;
2657	l = __raw_readl(reg);
2658	if (trigger & IRQ_TYPE_EDGE_RISING)
2659	l \|= 1 << gpio;
2660	@@ -897,14 +860,9 @@ static void _clear_gpio_irqbank(struct g
2661	reg += OMAP1610_GPIO_IRQSTATUS1;
2662	break;
2663	#endif
2664	-#ifdef CONFIG_ARCH_OMAP730
2665	- case METHOD_GPIO_730:
2666	- reg += OMAP730_GPIO_INT_STATUS;
2667	- break;
2668	-#endif
2669	-#ifdef CONFIG_ARCH_OMAP850
2670	- case METHOD_GPIO_850:
2671	- reg += OMAP850_GPIO_INT_STATUS;
2672	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2673	+ case METHOD_GPIO_7XX:
2674	+ reg += OMAP7XX_GPIO_INT_STATUS;
2675	break;
2676	#endif
2677	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
2678	@@ -971,16 +929,9 @@ static u32 _get_gpio_irqbank_mask(struct
2679	mask = 0xffff;
2680	break;
2681	#endif
2682	-#ifdef CONFIG_ARCH_OMAP730
2683	- case METHOD_GPIO_730:
2684	- reg += OMAP730_GPIO_INT_MASK;
2685	- mask = 0xffffffff;
2686	- inv = 1;
2687	- break;
2688	-#endif
2689	-#ifdef CONFIG_ARCH_OMAP850
2690	- case METHOD_GPIO_850:
2691	- reg += OMAP850_GPIO_INT_MASK;
2692	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2693	+ case METHOD_GPIO_7XX:
2694	+ reg += OMAP7XX_GPIO_INT_MASK;
2695	mask = 0xffffffff;
2696	inv = 1;
2697	break;
2698	@@ -1044,19 +995,9 @@ static void _enable_gpio_irqbank(struct
2699	l = gpio_mask;
2700	break;
2701	#endif
2702	-#ifdef CONFIG_ARCH_OMAP730
2703	- case METHOD_GPIO_730:
2704	- reg += OMAP730_GPIO_INT_MASK;
2705	- l = __raw_readl(reg);
2706	- if (enable)
2707	- l &= ~(gpio_mask);
2708	- else
2709	- l \|= gpio_mask;
2710	- break;
2711	-#endif
2712	-#ifdef CONFIG_ARCH_OMAP850
2713	- case METHOD_GPIO_850:
2714	- reg += OMAP850_GPIO_INT_MASK;
2715	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2716	+ case METHOD_GPIO_7XX:
2717	+ reg += OMAP7XX_GPIO_INT_MASK;
2718	l = __raw_readl(reg);
2719	if (enable)
2720	l &= ~(gpio_mask);
2721	@@ -1249,13 +1190,9 @@ static void gpio_irq_handler(unsigned in
2722	if (bank->method == METHOD_GPIO_1610)
2723	isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
2724	#endif
2725	-#ifdef CONFIG_ARCH_OMAP730
2726	- if (bank->method == METHOD_GPIO_730)
2727	- isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
2728	-#endif
2729	-#ifdef CONFIG_ARCH_OMAP850
2730	- if (bank->method == METHOD_GPIO_850)
2731	- isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
2732	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2733	+ if (bank->method == METHOD_GPIO_7XX)
2734	+ isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
2735	#endif
2736	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
2737	if (bank->method == METHOD_GPIO_24XX)
2738	@@ -1524,11 +1461,8 @@ static int gpio_is_input(struct gpio_ban
2739	case METHOD_GPIO_1610:
2740	reg += OMAP1610_GPIO_DIRECTION;
2741	break;
2742	- case METHOD_GPIO_730:
2743	- reg += OMAP730_GPIO_DIR_CONTROL;
2744	- break;
2745	- case METHOD_GPIO_850:
2746	- reg += OMAP850_GPIO_DIR_CONTROL;
2747	+ case METHOD_GPIO_7XX:
2748	+ reg += OMAP7XX_GPIO_DIR_CONTROL;
2749	break;
2750	case METHOD_GPIO_24XX:
2751	reg += OMAP24XX_GPIO_OE;
2752	@@ -1607,6 +1541,23 @@ static struct clk * gpio5_fck;
2753	static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
2754	#endif
2755
2756	+static void __init omap_gpio_show_rev(void)
2757	+{
2758	+ u32 rev;
2759	+
2760	+ if (cpu_is_omap16xx())
2761	+ rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
2762	+ else if (cpu_is_omap24xx() \|\| cpu_is_omap34xx())
2763	+ rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
2764	+ else if (cpu_is_omap44xx())
2765	+ rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
2766	+ else
2767	+ return;
2768	+
2769	+ printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
2770	+ (rev >> 4) & 0x0f, rev & 0x0f);
2771	+}
2772	+
2773	/* This lock class tells lockdep that GPIO irqs are in a different
2774	* category than their parents, so it won't report false recursion.
2775	*/
2776	@@ -1617,6 +1568,7 @@ static int __init _omap_gpio_init(void)
2777	int i;
2778	int gpio = 0;
2779	struct gpio_bank *bank;
2780	+ int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
2781	char clk_name[11];
2782
2783	initialized = 1;
2784	@@ -1679,77 +1631,45 @@ static int __init _omap_gpio_init(void)
2785
2786	#ifdef CONFIG_ARCH_OMAP15XX
2787	if (cpu_is_omap15xx()) {
2788	- printk(KERN_INFO "OMAP1510 GPIO hardware\n");
2789	gpio_bank_count = 2;
2790	gpio_bank = gpio_bank_1510;
2791	+ bank_size = SZ_2K;
2792	}
2793	#endif
2794	#if defined(CONFIG_ARCH_OMAP16XX)
2795	if (cpu_is_omap16xx()) {
2796	- u32 rev;
2797	-
2798	gpio_bank_count = 5;
2799	gpio_bank = gpio_bank_1610;
2800	- rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
2801	- printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
2802	- (rev >> 4) & 0x0f, rev & 0x0f);
2803	+ bank_size = SZ_2K;
2804	}
2805	#endif
2806	-#ifdef CONFIG_ARCH_OMAP730
2807	- if (cpu_is_omap730()) {
2808	- printk(KERN_INFO "OMAP730 GPIO hardware\n");
2809	- gpio_bank_count = 7;
2810	- gpio_bank = gpio_bank_730;
2811	- }
2812	-#endif
2813	-#ifdef CONFIG_ARCH_OMAP850
2814	- if (cpu_is_omap850()) {
2815	- printk(KERN_INFO "OMAP850 GPIO hardware\n");
2816	+#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
2817	+ if (cpu_is_omap7xx()) {
2818	gpio_bank_count = 7;
2819	- gpio_bank = gpio_bank_850;
2820	+ gpio_bank = gpio_bank_7xx;
2821	+ bank_size = SZ_2K;
2822	}
2823	#endif
2824	-
2825	#ifdef CONFIG_ARCH_OMAP24XX
2826	if (cpu_is_omap242x()) {
2827	- int rev;
2828	-
2829	gpio_bank_count = 4;
2830	gpio_bank = gpio_bank_242x;
2831	- rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
2832	- printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
2833	- (rev >> 4) & 0x0f, rev & 0x0f);
2834	}
2835	if (cpu_is_omap243x()) {
2836	- int rev;
2837	-
2838	gpio_bank_count = 5;
2839	gpio_bank = gpio_bank_243x;
2840	- rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
2841	- printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
2842	- (rev >> 4) & 0x0f, rev & 0x0f);
2843	}
2844	#endif
2845	#ifdef CONFIG_ARCH_OMAP34XX
2846	if (cpu_is_omap34xx()) {
2847	- int rev;
2848	-
2849	gpio_bank_count = OMAP34XX_NR_GPIOS;
2850	gpio_bank = gpio_bank_34xx;
2851	- rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
2852	- printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
2853	- (rev >> 4) & 0x0f, rev & 0x0f);
2854	}
2855	#endif
2856	#ifdef CONFIG_ARCH_OMAP4
2857	if (cpu_is_omap44xx()) {
2858	- int rev;
2859	-
2860	gpio_bank_count = OMAP34XX_NR_GPIOS;
2861	gpio_bank = gpio_bank_44xx;
2862	- rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
2863	- printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
2864	- (rev >> 4) & 0x0f, rev & 0x0f);
2865	}
2866	#endif
2867	for (i = 0; i < gpio_bank_count; i++) {
2868	@@ -1757,6 +1677,14 @@ static int __init _omap_gpio_init(void)
2869
2870	bank = &gpio_bank[i];
2871	spin_lock_init(&bank->lock);
2872	+
2873	+ /* Static mapping, never released */
2874	+ bank->base = ioremap(bank->pbase, bank_size);
2875	+ if (!bank->base) {
2876	+ printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
2877	+ continue;
2878	+ }
2879	+
2880	if (bank_is_mpuio(bank))
2881	__raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
2882	if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
2883	@@ -1768,11 +1696,11 @@ static int __init _omap_gpio_init(void)
2884	__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
2885	__raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
2886	}
2887	- if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
2888	- __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
2889	- __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
2890	+ if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
2891	+ __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
2892	+ __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
2893
2894	- gpio_count = 32; /* 730 has 32-bit GPIOs */
2895	+ gpio_count = 32; /* 7xx has 32-bit GPIOs */
2896	}
2897
2898	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
2899	@@ -1862,6 +1790,8 @@ static int __init _omap_gpio_init(void)
2900	if (cpu_is_omap34xx())
2901	omap_writel(1 << 0, 0x48306814);
2902
2903	+ omap_gpio_show_rev();
2904	+
2905	return 0;
2906	}
2907
2908	@@ -2160,8 +2090,7 @@ static int dbg_gpio_show(struct seq_file
2909
2910	if (bank_is_mpuio(bank))
2911	gpio = OMAP_MPUIO(0);
2912	- else if (cpu_class_is_omap2() \|\| cpu_is_omap730() \|\|
2913	- cpu_is_omap850())
2914	+ else if (cpu_class_is_omap2() \|\| cpu_is_omap7xx())
2915	bankwidth = 32;
2916
2917	for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2918	--- a/arch/arm/plat-omap/include/mach/control.h
2919	+++ b/arch/arm/plat-omap/include/mach/control.h
2920	@@ -20,15 +20,18 @@
2921
2922	#ifndef __ASSEMBLY__
2923	#define OMAP242X_CTRL_REGADDR(reg) \
2924	- OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
2925	+ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
2926	#define OMAP243X_CTRL_REGADDR(reg) \
2927	- OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
2928	+ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
2929	#define OMAP343X_CTRL_REGADDR(reg) \
2930	- OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
2931	+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
2932	#else
2933	-#define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
2934	-#define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
2935	-#define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
2936	+#define OMAP242X_CTRL_REGADDR(reg) \
2937	+ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
2938	+#define OMAP243X_CTRL_REGADDR(reg) \
2939	+ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
2940	+#define OMAP343X_CTRL_REGADDR(reg) \
2941	+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
2942	#endif /* __ASSEMBLY__ */
2943
2944	/*
2945	@@ -202,6 +205,40 @@
2946	#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
2947	#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
2948
2949	+/*
2950	+ * CONTROL OMAP STATUS register to identify OMAP3 features
2951	+ */
2952	+#define OMAP3_CONTROL_OMAP_STATUS 0x044c
2953	+
2954	+#define OMAP3_SGX_SHIFT 13
2955	+#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
2956	+#define FEAT_SGX_FULL 0
2957	+#define FEAT_SGX_HALF 1
2958	+#define FEAT_SGX_NONE 2
2959	+
2960	+#define OMAP3_IVA_SHIFT 12
2961	+#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
2962	+#define FEAT_IVA 0
2963	+#define FEAT_IVA_NONE 1
2964	+
2965	+#define OMAP3_L2CACHE_SHIFT 10
2966	+#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
2967	+#define FEAT_L2CACHE_NONE 0
2968	+#define FEAT_L2CACHE_64KB 1
2969	+#define FEAT_L2CACHE_128KB 2
2970	+#define FEAT_L2CACHE_256KB 3
2971	+
2972	+#define OMAP3_ISP_SHIFT 5
2973	+#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
2974	+#define FEAT_ISP 0
2975	+#define FEAT_ISP_NONE 1
2976	+
2977	+#define OMAP3_NEON_SHIFT 4
2978	+#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
2979	+#define FEAT_NEON 0
2980	+#define FEAT_NEON_NONE 1
2981	+
2982	+
2983	#ifndef __ASSEMBLY__
2984	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3) \|\| \
2985	defined(CONFIG_ARCH_OMAP4)
2986	--- a/arch/arm/plat-omap/include/mach/cpu.h
2987	+++ b/arch/arm/plat-omap/include/mach/cpu.h
2988	@@ -30,6 +30,8 @@
2989	#ifndef __ASM_ARCH_OMAP_CPU_H
2990	#define __ASM_ARCH_OMAP_CPU_H
2991
2992	+#include <linux/bitops.h>
2993	+
2994	/*
2995	* Omap device type i.e. EMU/HS/TST/GP/BAD
2996	*/
2997	@@ -57,6 +59,23 @@ struct omap_chip_id {
2998	unsigned int omap_rev(void);
2999
3000	/*
3001	+ * Define CPU revision bits
3002	+ *
3003	+ * Verbose meaning of the revision bits may be different for a silicon
3004	+ * family. This difference can be handled separately.
3005	+ */
3006	+#define OMAP_REVBITS_00 0x00
3007	+#define OMAP_REVBITS_10 0x10
3008	+#define OMAP_REVBITS_20 0x20
3009	+#define OMAP_REVBITS_30 0x30
3010	+#define OMAP_REVBITS_40 0x40
3011	+
3012	+/*
3013	+ * Get the CPU revision for OMAP devices
3014	+ */
3015	+#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
3016	+
3017	+/*
3018	* Test if multicore OMAP support is needed
3019	*/
3020	#undef MULTI_OMAP1
3021	@@ -161,6 +180,7 @@ IS_OMAP_CLASS(34xx, 0x34)
3022	IS_OMAP_SUBCLASS(242x, 0x242)
3023	IS_OMAP_SUBCLASS(243x, 0x243)
3024	IS_OMAP_SUBCLASS(343x, 0x343)
3025	+IS_OMAP_SUBCLASS(363x, 0x363)
3026
3027	#define cpu_is_omap7xx() 0
3028	#define cpu_is_omap15xx() 0
3029	@@ -301,7 +321,12 @@ IS_OMAP_TYPE(3430, 0x3430)
3030	#define cpu_is_omap2422() 0
3031	#define cpu_is_omap2423() 0
3032	#define cpu_is_omap2430() 0
3033	+#define cpu_is_omap3503() 0
3034	+#define cpu_is_omap3515() 0
3035	+#define cpu_is_omap3525() 0
3036	+#define cpu_is_omap3530() 0
3037	#define cpu_is_omap3430() 0
3038	+#define cpu_is_omap3630() 0
3039
3040	/*
3041	* Whether we have MULTI_OMAP1 or not, we still need to distinguish
3042	@@ -351,7 +376,23 @@ IS_OMAP_TYPE(3430, 0x3430)
3043
3044	#if defined(CONFIG_ARCH_OMAP34XX)
3045	# undef cpu_is_omap3430
3046	+# undef cpu_is_omap3503
3047	+# undef cpu_is_omap3515
3048	+# undef cpu_is_omap3525
3049	+# undef cpu_is_omap3530
3050	# define cpu_is_omap3430() is_omap3430()
3051	+# define cpu_is_omap3503 (cpu_is_omap3430() && \
3052	+ (!omap3_has_iva()) && \
3053	+ (!omap3_has_sgx()))
3054	+# define cpu_is_omap3515 (cpu_is_omap3430() && \
3055	+ (omap3_has_iva()) && \
3056	+ (!omap3_has_sgx()))
3057	+# define cpu_is_omap3525 (cpu_is_omap3430() && \
3058	+ (omap3_has_sgx()) && \
3059	+ (!omap3_has_iva()))
3060	+# define cpu_is_omap3530 (cpu_is_omap3430())
3061	+# undef cpu_is_omap3630
3062	+# define cpu_is_omap3630() is_omap363x()
3063	#endif
3064
3065	# if defined(CONFIG_ARCH_OMAP4)
3066	@@ -382,6 +423,14 @@ IS_OMAP_TYPE(3430, 0x3430)
3067	#define OMAP3430_REV_ES3_0 0x34303034
3068	#define OMAP3430_REV_ES3_1 0x34304034
3069
3070	+#define OMAP3630_REV_ES1_0 0x36300034
3071	+
3072	+#define OMAP35XX_CLASS 0x35000034
3073	+#define OMAP3503_REV(v) (OMAP35XX_CLASS \| (0x3503 << 16) \| (v << 12))
3074	+#define OMAP3515_REV(v) (OMAP35XX_CLASS \| (0x3515 << 16) \| (v << 12))
3075	+#define OMAP3525_REV(v) (OMAP35XX_CLASS \| (0x3525 << 16) \| (v << 12))
3076	+#define OMAP3530_REV(v) (OMAP35XX_CLASS \| (0x3530 << 16) \| (v << 12))
3077	+
3078	#define OMAP443X_CLASS 0x44300034
3079
3080	/*
3081	@@ -423,4 +472,27 @@ IS_OMAP_TYPE(3430, 0x3430)
3082	int omap_chip_is(struct omap_chip_id oci);
3083	void omap2_check_revision(void);
3084
3085	+/*
3086	+ * Runtime detection of OMAP3 features
3087	+ */
3088	+extern u32 omap3_features;
3089	+
3090	+#define OMAP3_HAS_L2CACHE BIT(0)
3091	+#define OMAP3_HAS_IVA BIT(1)
3092	+#define OMAP3_HAS_SGX BIT(2)
3093	+#define OMAP3_HAS_NEON BIT(3)
3094	+#define OMAP3_HAS_ISP BIT(4)
3095	+
3096	+#define OMAP3_HAS_FEATURE(feat,flag) \
3097	+static inline unsigned int omap3_has_ ##feat(void) \
3098	+{ \
3099	+ return (omap3_features & OMAP3_HAS_ ##flag); \
3100	+} \
3101	+
3102	+OMAP3_HAS_FEATURE(l2cache, L2CACHE)
3103	+OMAP3_HAS_FEATURE(sgx, SGX)
3104	+OMAP3_HAS_FEATURE(iva, IVA)
3105	+OMAP3_HAS_FEATURE(neon, NEON)
3106	+OMAP3_HAS_FEATURE(isp, ISP)
3107	+
3108	#endif
3109	--- a/arch/arm/plat-omap/include/mach/debug-macro.S
3110	+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
3111	@@ -27,7 +27,7 @@
3112
3113	#elif CONFIG_ARCH_OMAP2
3114	moveq \rx, #0x48000000 @ physical base address
3115	- movne \rx, #0xd8000000 @ virtual base
3116	+ movne \rx, #0xfa000000 @ virtual base
3117	orr \rx, \rx, #0x0006a000
3118	#ifdef CONFIG_OMAP_LL_DEBUG_UART2
3119	add \rx, \rx, #0x00002000 @ UART 2
3120	@@ -38,7 +38,7 @@
3121
3122	#elif defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP4)
3123	moveq \rx, #0x48000000 @ physical base address
3124	- movne \rx, #0xd8000000 @ virtual base
3125	+ movne \rx, #0xfa000000 @ virtual base
3126	orr \rx, \rx, #0x0006a000
3127	#ifdef CONFIG_OMAP_LL_DEBUG_UART2
3128	add \rx, \rx, #0x00002000 @ UART 2
3129	--- a/arch/arm/plat-omap/include/mach/entry-macro.S
3130	+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
3131	@@ -17,11 +17,11 @@
3132
3133	#if defined(CONFIG_ARCH_OMAP1)
3134
3135	-#if defined(CONFIG_ARCH_OMAP730) && \
3136	+#if (defined(CONFIG_ARCH_OMAP730)\|\|defined(CONFIG_ARCH_OMAP850)) && \
3137	(defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX))
3138	-#error "FIXME: OMAP730 doesn't support multiple-OMAP"
3139	-#elif defined(CONFIG_ARCH_OMAP730)
3140	-#define INT_IH2_IRQ INT_730_IH2_IRQ
3141	+#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
3142	+#elif defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
3143	+#define INT_IH2_IRQ INT_7XX_IH2_IRQ
3144	#elif defined(CONFIG_ARCH_OMAP15XX)
3145	#define INT_IH2_IRQ INT_1510_IH2_IRQ
3146	#elif defined(CONFIG_ARCH_OMAP16XX)
3147	@@ -68,9 +68,9 @@
3148
3149	/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
3150	#if defined(CONFIG_ARCH_OMAP2420) \|\| defined(CONFIG_ARCH_OMAP2430)
3151	-#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
3152	+#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
3153	#elif defined(CONFIG_ARCH_OMAP34XX)
3154	-#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
3155	+#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
3156	#endif
3157	#if defined(CONFIG_ARCH_OMAP4)
3158	#include <mach/omap44xx.h>
3159	@@ -104,6 +104,8 @@
3160
3161	.endm
3162	#else
3163	+#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
3164	+
3165	/*
3166	* The interrupt numbering scheme is defined in the
3167	* interrupt controller spec. To wit:
3168	--- a/arch/arm/plat-omap/include/mach/hardware.h
3169	+++ b/arch/arm/plat-omap/include/mach/hardware.h
3170	@@ -280,7 +280,7 @@
3171	* ---------------------------------------------------------------------------
3172	*/
3173
3174	-#include "omap730.h"
3175	+#include "omap7xx.h"
3176	#include "omap1510.h"
3177	#include "omap16xx.h"
3178	#include "omap24xx.h"
3179	--- a/arch/arm/plat-omap/include/mach/io.h
3180	+++ b/arch/arm/plat-omap/include/mach/io.h
3181	@@ -63,8 +63,24 @@
3182	#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
3183	#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
3184
3185	-#define OMAP2_IO_OFFSET 0x90000000
3186	-#define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
3187	+#define OMAP2_L3_IO_OFFSET 0x90000000
3188	+#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
3189	+
3190	+
3191	+#define OMAP2_L4_IO_OFFSET 0xb2000000
3192	+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
3193	+
3194	+#define OMAP4_L3_IO_OFFSET 0xb4000000
3195	+#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
3196	+
3197	+#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
3198	+#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
3199	+
3200	+#define OMAP4_GPMC_IO_OFFSET 0xa9000000
3201	+#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
3202	+
3203	+#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
3204	+#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
3205
3206	/*
3207	* ----------------------------------------------------------------------------
3208	@@ -83,24 +99,27 @@
3209	*/
3210
3211	/* We map both L3 and L4 on OMAP2 */
3212	-#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */
3213	-#define L3_24XX_VIRT 0xf8000000
3214	+#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
3215	+#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
3216	#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
3217	-#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
3218	-#define L4_24XX_VIRT 0xd8000000
3219	+#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
3220	+#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
3221	#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
3222
3223	-#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
3224	-#define L4_WK_243X_VIRT 0xd9000000
3225	+#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
3226	+#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
3227	#define L4_WK_243X_SIZE SZ_1M
3228	-#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
3229	-#define OMAP243X_GPMC_VIRT 0xFE000000
3230	+#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
3231	+#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
3232	+ /* 0x6e000000 --> 0xfe000000 */
3233	#define OMAP243X_GPMC_SIZE SZ_1M
3234	#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
3235	-#define OMAP243X_SDRC_VIRT 0xFD000000
3236	+ /* 0x6D000000 --> 0xfd000000 */
3237	+#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
3238	#define OMAP243X_SDRC_SIZE SZ_1M
3239	#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
3240	-#define OMAP243X_SMS_VIRT 0xFC000000
3241	+ /* 0x6c000000 --> 0xfc000000 */
3242	+#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
3243	#define OMAP243X_SMS_SIZE SZ_1M
3244
3245	/* DSP */
3246	@@ -121,12 +140,12 @@
3247	*/
3248
3249	/* We map both L3 and L4 on OMAP3 */
3250	-#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
3251	-#define L3_34XX_VIRT 0xf8000000
3252	+#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
3253	+#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
3254	#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
3255
3256	-#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
3257	-#define L4_34XX_VIRT 0xd8000000
3258	+#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
3259	+#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
3260	#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
3261
3262	/*
3263	@@ -134,28 +153,33 @@
3264	* VPOM3430 was not working for Int controller
3265	*/
3266
3267	-#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
3268	-#define L4_WK_34XX_VIRT 0xd8300000
3269	+#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
3270	+#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
3271	#define L4_WK_34XX_SIZE SZ_1M
3272
3273	-#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
3274	-#define L4_PER_34XX_VIRT 0xd9000000
3275	+#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
3276	+ /* 0x49000000 --> 0xfb000000 */
3277	+#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
3278	#define L4_PER_34XX_SIZE SZ_1M
3279
3280	-#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
3281	-#define L4_EMU_34XX_VIRT 0xe4000000
3282	-#define L4_EMU_34XX_SIZE SZ_64M
3283	-
3284	-#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
3285	-#define OMAP34XX_GPMC_VIRT 0xFE000000
3286	+#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
3287	+ /* 0x54000000 --> 0xfe800000 */
3288	+#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
3289	+#define L4_EMU_34XX_SIZE SZ_8M
3290	+
3291	+#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
3292	+ /* 0x6e000000 --> 0xfe000000 */
3293	+#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
3294	#define OMAP34XX_GPMC_SIZE SZ_1M
3295
3296	-#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
3297	-#define OMAP343X_SMS_VIRT 0xFC000000
3298	+#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
3299	+ /* 0x6c000000 --> 0xfc000000 */
3300	+#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
3301	#define OMAP343X_SMS_SIZE SZ_1M
3302
3303	-#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
3304	-#define OMAP343X_SDRC_VIRT 0xFD000000
3305	+#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
3306	+ /* 0x6D000000 --> 0xfd000000 */
3307	+#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
3308	#define OMAP343X_SDRC_SIZE SZ_1M
3309
3310	/* DSP */
3311	@@ -176,32 +200,54 @@
3312	*/
3313
3314	/* We map both L3 and L4 on OMAP4 */
3315	-#define L3_44XX_PHYS L3_44XX_BASE
3316	-#define L3_44XX_VIRT 0xd4000000
3317	+#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
3318	+#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
3319	#define L3_44XX_SIZE SZ_1M
3320
3321	-#define L4_44XX_PHYS L4_44XX_BASE
3322	-#define L4_44XX_VIRT 0xda000000
3323	+#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
3324	+#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
3325	#define L4_44XX_SIZE SZ_4M
3326
3327
3328	-#define L4_WK_44XX_PHYS L4_WK_44XX_BASE
3329	-#define L4_WK_44XX_VIRT 0xda300000
3330	+#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
3331	+#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
3332	#define L4_WK_44XX_SIZE SZ_1M
3333
3334	#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
3335	-#define L4_PER_44XX_VIRT 0xd8000000
3336	+ /* 0x48000000 --> 0xfa000000 */
3337	+#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
3338	#define L4_PER_44XX_SIZE SZ_4M
3339
3340	+#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
3341	+ /* 0x49000000 --> 0xfb000000 */
3342	+#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
3343	+#define L4_ABE_44XX_SIZE SZ_1M
3344	+
3345	#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
3346	-#define L4_EMU_44XX_VIRT 0xe4000000
3347	-#define L4_EMU_44XX_SIZE SZ_64M
3348	+ /* 0x54000000 --> 0xfe800000 */
3349	+#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
3350	+#define L4_EMU_44XX_SIZE SZ_8M
3351
3352	#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
3353	-#define OMAP44XX_GPMC_VIRT 0xe0000000
3354	+ /* 0x50000000 --> 0xf9000000 */
3355	+#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
3356	#define OMAP44XX_GPMC_SIZE SZ_1M
3357
3358
3359	+#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
3360	+ /* 0x4c000000 --> 0xfd100000 */
3361	+#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
3362	+#define OMAP44XX_EMIF1_SIZE SZ_1M
3363	+
3364	+#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
3365	+ /* 0x4d000000 --> 0xfd200000 */
3366	+#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
3367	+#define OMAP44XX_EMIF2_SIZE SZ_1M
3368	+
3369	+#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
3370	+ /* 0x4e000000 --> 0xfd300000 */
3371	+#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
3372	+#define OMAP44XX_DMM_SIZE SZ_1M
3373	/*
3374	* ----------------------------------------------------------------------------
3375	* Omap specific register access
3376	--- a/arch/arm/plat-omap/include/mach/irqs.h
3377	+++ b/arch/arm/plat-omap/include/mach/irqs.h
3378	@@ -86,49 +86,26 @@
3379	#define INT_1610_SSR_FIFO_0 29
3380
3381	/*
3382	- * OMAP-730 specific IRQ numbers for interrupt handler 1
3383	+ * OMAP-7xx specific IRQ numbers for interrupt handler 1
3384	*/
3385	-#define INT_730_IH2_FIQ 0
3386	-#define INT_730_IH2_IRQ 1
3387	-#define INT_730_USB_NON_ISO 2
3388	-#define INT_730_USB_ISO 3
3389	-#define INT_730_ICR 4
3390	-#define INT_730_EAC 5
3391	-#define INT_730_GPIO_BANK1 6
3392	-#define INT_730_GPIO_BANK2 7
3393	-#define INT_730_GPIO_BANK3 8
3394	-#define INT_730_McBSP2TX 10
3395	-#define INT_730_McBSP2RX 11
3396	-#define INT_730_McBSP2RX_OVF 12
3397	-#define INT_730_LCD_LINE 14
3398	-#define INT_730_GSM_PROTECT 15
3399	-#define INT_730_TIMER3 16
3400	-#define INT_730_GPIO_BANK5 17
3401	-#define INT_730_GPIO_BANK6 18
3402	-#define INT_730_SPGIO_WR 29
3403	-
3404	-/*
3405	- * OMAP-850 specific IRQ numbers for interrupt handler 1
3406	- */
3407	-#define INT_850_IH2_FIQ 0
3408	-#define INT_850_IH2_IRQ 1
3409	-#define INT_850_USB_NON_ISO 2
3410	-#define INT_850_USB_ISO 3
3411	-#define INT_850_ICR 4
3412	-#define INT_850_EAC 5
3413	-#define INT_850_GPIO_BANK1 6
3414	-#define INT_850_GPIO_BANK2 7
3415	-#define INT_850_GPIO_BANK3 8
3416	-#define INT_850_McBSP2TX 10
3417	-#define INT_850_McBSP2RX 11
3418	-#define INT_850_McBSP2RX_OVF 12
3419	-#define INT_850_LCD_LINE 14
3420	-#define INT_850_GSM_PROTECT 15
3421	-#define INT_850_TIMER3 16
3422	-#define INT_850_GPIO_BANK5 17
3423	-#define INT_850_GPIO_BANK6 18
3424	-#define INT_850_SPGIO_WR 29
3425	-
3426	+#define INT_7XX_IH2_FIQ 0
3427	+#define INT_7XX_IH2_IRQ 1
3428	+#define INT_7XX_USB_NON_ISO 2
3429	+#define INT_7XX_USB_ISO 3
3430	+#define INT_7XX_ICR 4
3431	+#define INT_7XX_EAC 5
3432	+#define INT_7XX_GPIO_BANK1 6
3433	+#define INT_7XX_GPIO_BANK2 7
3434	+#define INT_7XX_GPIO_BANK3 8
3435	+#define INT_7XX_McBSP2TX 10
3436	+#define INT_7XX_McBSP2RX 11
3437	+#define INT_7XX_McBSP2RX_OVF 12
3438	+#define INT_7XX_LCD_LINE 14
3439	+#define INT_7XX_GSM_PROTECT 15
3440	+#define INT_7XX_TIMER3 16
3441	+#define INT_7XX_GPIO_BANK5 17
3442	+#define INT_7XX_GPIO_BANK6 18
3443	+#define INT_7XX_SPGIO_WR 29
3444
3445	/*
3446	* IRQ numbers for interrupt handler 2
3447	@@ -206,120 +183,62 @@
3448	#define INT_1610_SHA1MD5 (91 + IH2_BASE)
3449
3450	/*
3451	- * OMAP-730 specific IRQ numbers for interrupt handler 2
3452	- */
3453	-#define INT_730_HW_ERRORS (0 + IH2_BASE)
3454	-#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE)
3455	-#define INT_730_CFCD (2 + IH2_BASE)
3456	-#define INT_730_CFIREQ (3 + IH2_BASE)
3457	-#define INT_730_I2C (4 + IH2_BASE)
3458	-#define INT_730_PCC (5 + IH2_BASE)
3459	-#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE)
3460	-#define INT_730_SPI_100K_1 (7 + IH2_BASE)
3461	-#define INT_730_SYREN_SPI (8 + IH2_BASE)
3462	-#define INT_730_VLYNQ (9 + IH2_BASE)
3463	-#define INT_730_GPIO_BANK4 (10 + IH2_BASE)
3464	-#define INT_730_McBSP1TX (11 + IH2_BASE)
3465	-#define INT_730_McBSP1RX (12 + IH2_BASE)
3466	-#define INT_730_McBSP1RX_OF (13 + IH2_BASE)
3467	-#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
3468	-#define INT_730_UART_MODEM_1 (15 + IH2_BASE)
3469	-#define INT_730_MCSI (16 + IH2_BASE)
3470	-#define INT_730_uWireTX (17 + IH2_BASE)
3471	-#define INT_730_uWireRX (18 + IH2_BASE)
3472	-#define INT_730_SMC_CD (19 + IH2_BASE)
3473	-#define INT_730_SMC_IREQ (20 + IH2_BASE)
3474	-#define INT_730_HDQ_1WIRE (21 + IH2_BASE)
3475	-#define INT_730_TIMER32K (22 + IH2_BASE)
3476	-#define INT_730_MMC_SDIO (23 + IH2_BASE)
3477	-#define INT_730_UPLD (24 + IH2_BASE)
3478	-#define INT_730_USB_HHC_1 (27 + IH2_BASE)
3479	-#define INT_730_USB_HHC_2 (28 + IH2_BASE)
3480	-#define INT_730_USB_GENI (29 + IH2_BASE)
3481	-#define INT_730_USB_OTG (30 + IH2_BASE)
3482	-#define INT_730_CAMERA_IF (31 + IH2_BASE)
3483	-#define INT_730_RNG (32 + IH2_BASE)
3484	-#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
3485	-#define INT_730_DBB_RF_EN (34 + IH2_BASE)
3486	-#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE)
3487	-#define INT_730_SHA1_MD5 (36 + IH2_BASE)
3488	-#define INT_730_SPI_100K_2 (37 + IH2_BASE)
3489	-#define INT_730_RNG_IDLE (38 + IH2_BASE)
3490	-#define INT_730_MPUIO (39 + IH2_BASE)
3491	-#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
3492	-#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
3493	-#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
3494	-#define INT_730_LLPC_VSYNC (43 + IH2_BASE)
3495	-#define INT_730_WAKE_UP_REQ (46 + IH2_BASE)
3496	-#define INT_730_DMA_CH6 (53 + IH2_BASE)
3497	-#define INT_730_DMA_CH7 (54 + IH2_BASE)
3498	-#define INT_730_DMA_CH8 (55 + IH2_BASE)
3499	-#define INT_730_DMA_CH9 (56 + IH2_BASE)
3500	-#define INT_730_DMA_CH10 (57 + IH2_BASE)
3501	-#define INT_730_DMA_CH11 (58 + IH2_BASE)
3502	-#define INT_730_DMA_CH12 (59 + IH2_BASE)
3503	-#define INT_730_DMA_CH13 (60 + IH2_BASE)
3504	-#define INT_730_DMA_CH14 (61 + IH2_BASE)
3505	-#define INT_730_DMA_CH15 (62 + IH2_BASE)
3506	-#define INT_730_NAND (63 + IH2_BASE)
3507	-
3508	-/*
3509	- * OMAP-850 specific IRQ numbers for interrupt handler 2
3510	+ * OMAP-7xx specific IRQ numbers for interrupt handler 2
3511	*/
3512	-#define INT_850_HW_ERRORS (0 + IH2_BASE)
3513	-#define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE)
3514	-#define INT_850_CFCD (2 + IH2_BASE)
3515	-#define INT_850_CFIREQ (3 + IH2_BASE)
3516	-#define INT_850_I2C (4 + IH2_BASE)
3517	-#define INT_850_PCC (5 + IH2_BASE)
3518	-#define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE)
3519	-#define INT_850_SPI_100K_1 (7 + IH2_BASE)
3520	-#define INT_850_SYREN_SPI (8 + IH2_BASE)
3521	-#define INT_850_VLYNQ (9 + IH2_BASE)
3522	-#define INT_850_GPIO_BANK4 (10 + IH2_BASE)
3523	-#define INT_850_McBSP1TX (11 + IH2_BASE)
3524	-#define INT_850_McBSP1RX (12 + IH2_BASE)
3525	-#define INT_850_McBSP1RX_OF (13 + IH2_BASE)
3526	-#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
3527	-#define INT_850_UART_MODEM_1 (15 + IH2_BASE)
3528	-#define INT_850_MCSI (16 + IH2_BASE)
3529	-#define INT_850_uWireTX (17 + IH2_BASE)
3530	-#define INT_850_uWireRX (18 + IH2_BASE)
3531	-#define INT_850_SMC_CD (19 + IH2_BASE)
3532	-#define INT_850_SMC_IREQ (20 + IH2_BASE)
3533	-#define INT_850_HDQ_1WIRE (21 + IH2_BASE)
3534	-#define INT_850_TIMER32K (22 + IH2_BASE)
3535	-#define INT_850_MMC_SDIO (23 + IH2_BASE)
3536	-#define INT_850_UPLD (24 + IH2_BASE)
3537	-#define INT_850_USB_HHC_1 (27 + IH2_BASE)
3538	-#define INT_850_USB_HHC_2 (28 + IH2_BASE)
3539	-#define INT_850_USB_GENI (29 + IH2_BASE)
3540	-#define INT_850_USB_OTG (30 + IH2_BASE)
3541	-#define INT_850_CAMERA_IF (31 + IH2_BASE)
3542	-#define INT_850_RNG (32 + IH2_BASE)
3543	-#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
3544	-#define INT_850_DBB_RF_EN (34 + IH2_BASE)
3545	-#define INT_850_MPUIO_KEYPAD (35 + IH2_BASE)
3546	-#define INT_850_SHA1_MD5 (36 + IH2_BASE)
3547	-#define INT_850_SPI_100K_2 (37 + IH2_BASE)
3548	-#define INT_850_RNG_IDLE (38 + IH2_BASE)
3549	-#define INT_850_MPUIO (39 + IH2_BASE)
3550	-#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
3551	-#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
3552	-#define INT_850_LLPC_OE_RISING (42 + IH2_BASE)
3553	-#define INT_850_LLPC_VSYNC (43 + IH2_BASE)
3554	-#define INT_850_WAKE_UP_REQ (46 + IH2_BASE)
3555	-#define INT_850_DMA_CH6 (53 + IH2_BASE)
3556	-#define INT_850_DMA_CH7 (54 + IH2_BASE)
3557	-#define INT_850_DMA_CH8 (55 + IH2_BASE)
3558	-#define INT_850_DMA_CH9 (56 + IH2_BASE)
3559	-#define INT_850_DMA_CH10 (57 + IH2_BASE)
3560	-#define INT_850_DMA_CH11 (58 + IH2_BASE)
3561	-#define INT_850_DMA_CH12 (59 + IH2_BASE)
3562	-#define INT_850_DMA_CH13 (60 + IH2_BASE)
3563	-#define INT_850_DMA_CH14 (61 + IH2_BASE)
3564	-#define INT_850_DMA_CH15 (62 + IH2_BASE)
3565	-#define INT_850_NAND (63 + IH2_BASE)
3566	+#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
3567	+#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
3568	+#define INT_7XX_CFCD (2 + IH2_BASE)
3569	+#define INT_7XX_CFIREQ (3 + IH2_BASE)
3570	+#define INT_7XX_I2C (4 + IH2_BASE)
3571	+#define INT_7XX_PCC (5 + IH2_BASE)
3572	+#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
3573	+#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
3574	+#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
3575	+#define INT_7XX_VLYNQ (9 + IH2_BASE)
3576	+#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
3577	+#define INT_7XX_McBSP1TX (11 + IH2_BASE)
3578	+#define INT_7XX_McBSP1RX (12 + IH2_BASE)
3579	+#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
3580	+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
3581	+#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
3582	+#define INT_7XX_MCSI (16 + IH2_BASE)
3583	+#define INT_7XX_uWireTX (17 + IH2_BASE)
3584	+#define INT_7XX_uWireRX (18 + IH2_BASE)
3585	+#define INT_7XX_SMC_CD (19 + IH2_BASE)
3586	+#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
3587	+#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
3588	+#define INT_7XX_TIMER32K (22 + IH2_BASE)
3589	+#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
3590	+#define INT_7XX_UPLD (24 + IH2_BASE)
3591	+#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
3592	+#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
3593	+#define INT_7XX_USB_GENI (29 + IH2_BASE)
3594	+#define INT_7XX_USB_OTG (30 + IH2_BASE)
3595	+#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
3596	+#define INT_7XX_RNG (32 + IH2_BASE)
3597	+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
3598	+#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
3599	+#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
3600	+#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
3601	+#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
3602	+#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
3603	+#define INT_7XX_MPUIO (39 + IH2_BASE)
3604	+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
3605	+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
3606	+#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
3607	+#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
3608	+#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
3609	+#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
3610	+#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
3611	+#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
3612	+#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
3613	+#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
3614	+#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
3615	+#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
3616	+#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
3617	+#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
3618	+#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
3619	+#define INT_7XX_NAND (63 + IH2_BASE)
3620
3621	#define INT_24XX_SYS_NIRQ 7
3622	#define INT_24XX_SDMA_IRQ0 12
3623	--- a/arch/arm/plat-omap/include/mach/mcbsp.h
3624	+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
3625	@@ -30,8 +30,8 @@
3626	#include <mach/hardware.h>
3627	#include <mach/clock.h>
3628
3629	-#define OMAP730_MCBSP1_BASE 0xfffb1000
3630	-#define OMAP730_MCBSP2_BASE 0xfffb1800
3631	+#define OMAP7XX_MCBSP1_BASE 0xfffb1000
3632	+#define OMAP7XX_MCBSP2_BASE 0xfffb1800
3633
3634	#define OMAP1510_MCBSP1_BASE 0xe1011800
3635	#define OMAP1510_MCBSP2_BASE 0xfffb1000
3636	@@ -58,7 +58,7 @@
3637	#define OMAP44XX_MCBSP3_BASE 0x49026000
3638	#define OMAP44XX_MCBSP4_BASE 0x48074000
3639
3640	-#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX) \|\| defined(CONFIG_ARCH_OMAP730)
3641	+#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX) \|\| defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
3642
3643	#define OMAP_MCBSP_REG_DRR2 0x00
3644	#define OMAP_MCBSP_REG_DRR1 0x02
3645	--- a/arch/arm/plat-omap/include/mach/mux.h
3646	+++ b/arch/arm/plat-omap/include/mach/mux.h
3647	@@ -51,23 +51,13 @@
3648	.pu_pd_reg = PU_PD_SEL_##reg, \
3649	.pu_pd_val = status,
3650
3651	-#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
3652	- .mux_reg = OMAP730_IO_CONF_##reg, \
3653	+#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
3654	+ .mux_reg = OMAP7XX_IO_CONF_##reg, \
3655	.mask_offset = mode_offset, \
3656	.mask = mode,
3657
3658	-#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
3659	- .pull_reg = OMAP730_IO_CONF_##reg, \
3660	- .pull_bit = bit, \
3661	- .pull_val = status,
3662	-
3663	-#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
3664	- .mux_reg = OMAP850_IO_CONF_##reg, \
3665	- .mask_offset = mode_offset, \
3666	- .mask = mode,
3667	-
3668	-#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
3669	- .pull_reg = OMAP850_IO_CONF_##reg, \
3670	+#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
3671	+ .pull_reg = OMAP7XX_IO_CONF_##reg, \
3672	.pull_bit = bit, \
3673	.pull_val = status,
3674
3675	@@ -84,21 +74,12 @@
3676	#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
3677	.pu_pd_val = status,
3678
3679	-#define MUX_REG_730(reg, mode_offset, mode) \
3680	- .mux_reg = OMAP730_IO_CONF_##reg, \
3681	+#define MUX_REG_7XX(reg, mode_offset, mode) \
3682	+ .mux_reg = OMAP7XX_IO_CONF_##reg, \
3683	.mask_offset = mode_offset, \
3684	.mask = mode,
3685
3686	-#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
3687	- .pull_bit = bit, \
3688	- .pull_val = status,
3689	-
3690	-#define MUX_REG_850(reg, mode_offset, mode) \
3691	- .mux_reg = OMAP850_IO_CONF_##reg, \
3692	- .mask_offset = mode_offset, \
3693	- .mask = mode,
3694	-
3695	-#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
3696	+#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
3697	.pull_bit = bit, \
3698	.pull_val = status,
3699
3700	@@ -118,32 +99,21 @@
3701
3702	/*
3703	* OMAP730/850 has a slightly different config for the pin mux.
3704	- * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
3705	+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
3706	* not the FUNC_MUX_CTRL_x regs from hardware.h
3707	* - for pull-up/down, only has one enable bit which is is in the same register
3708	* as mux config
3709	*/
3710	-#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
3711	+#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
3712	pull_bit, pull_status, debug_status)\
3713	{ \
3714	.name = desc, \
3715	.debug = debug_status, \
3716	- MUX_REG_730(mux_reg, mode_offset, mode) \
3717	- PULL_REG_730(mux_reg, pull_bit, pull_status) \
3718	+ MUX_REG_7XX(mux_reg, mode_offset, mode) \
3719	+ PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
3720	PU_PD_REG(NA, 0) \
3721	},
3722
3723	-#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
3724	- pull_bit, pull_status, debug_status)\
3725	-{ \
3726	- .name = desc, \
3727	- .debug = debug_status, \
3728	- MUX_REG_850(mux_reg, mode_offset, mode) \
3729	- PULL_REG_850(mux_reg, pull_bit, pull_status) \
3730	- PU_PD_REG(NA, 0) \
3731	-},
3732	-
3733	-
3734	#define MUX_CFG_24XX(desc, reg_offset, mode, \
3735	pull_en, pull_mode, dbg) \
3736	{ \
3737	@@ -232,45 +202,25 @@ struct pin_config {
3738
3739	};
3740
3741	-enum omap730_index {
3742	+enum omap7xx_index {
3743	/* OMAP 730 keyboard */
3744	- E2_730_KBR0,
3745	- J7_730_KBR1,
3746	- E1_730_KBR2,
3747	- F3_730_KBR3,
3748	- D2_730_KBR4,
3749	- C2_730_KBC0,
3750	- D3_730_KBC1,
3751	- E4_730_KBC2,
3752	- F4_730_KBC3,
3753	- E3_730_KBC4,
3754	-
3755	- /* USB */
3756	- AA17_730_USB_DM,
3757	- W16_730_USB_PU_EN,
3758	- W17_730_USB_VBUSI,
3759	-};
3760	-
3761	-enum omap850_index {
3762	- /* OMAP 850 keyboard */
3763	- E2_850_KBR0,
3764	- J7_850_KBR1,
3765	- E1_850_KBR2,
3766	- F3_850_KBR3,
3767	- D2_850_KBR4,
3768	- C2_850_KBC0,
3769	- D3_850_KBC1,
3770	- E4_850_KBC2,
3771	- F4_850_KBC3,
3772	- E3_850_KBC4,
3773	+ E2_7XX_KBR0,
3774	+ J7_7XX_KBR1,
3775	+ E1_7XX_KBR2,
3776	+ F3_7XX_KBR3,
3777	+ D2_7XX_KBR4,
3778	+ C2_7XX_KBC0,
3779	+ D3_7XX_KBC1,
3780	+ E4_7XX_KBC2,
3781	+ F4_7XX_KBC3,
3782	+ E3_7XX_KBC4,
3783
3784	/* USB */
3785	- AA17_850_USB_DM,
3786	- W16_850_USB_PU_EN,
3787	- W17_850_USB_VBUSI,
3788	+ AA17_7XX_USB_DM,
3789	+ W16_7XX_USB_PU_EN,
3790	+ W17_7XX_USB_VBUSI,
3791	};
3792
3793	-
3794	enum omap1xxx_index {
3795	/* UART1 (BT_UART_GATING)*/
3796	UART1_TX = 0,
3797	--- a/arch/arm/plat-omap/include/mach/omap34xx.h
3798	+++ b/arch/arm/plat-omap/include/mach/omap34xx.h
3799	@@ -74,8 +74,12 @@
3800
3801	#define OMAP34XX_IVA_INTC_BASE 0x40000000
3802	#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
3803	-#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
3804	#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
3805	+#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
3806	+#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
3807	+#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
3808	+#define OMAP34XX_SR1_BASE 0x480C9000
3809	+#define OMAP34XX_SR2_BASE 0x480CB000
3810
3811	#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
3812
3813	--- a/arch/arm/plat-omap/include/mach/omap44xx.h
3814	+++ b/arch/arm/plat-omap/include/mach/omap44xx.h
3815	@@ -22,6 +22,9 @@
3816	#define L4_PER_44XX_BASE 0x48000000
3817	#define L4_EMU_44XX_BASE 0x54000000
3818	#define L3_44XX_BASE 0x44000000
3819	+#define OMAP44XX_EMIF1_BASE 0x4c000000
3820	+#define OMAP44XX_EMIF2_BASE 0x4d000000
3821	+#define OMAP44XX_DMM_BASE 0x4e000000
3822	#define OMAP4430_32KSYNCT_BASE 0x4a304000
3823	#define OMAP4430_CM_BASE 0x4a004000
3824	#define OMAP4430_PRM_BASE 0x48306000
3825	@@ -33,14 +36,9 @@
3826	#define IRQ_SIR_IRQ 0x0040
3827	#define OMAP44XX_GIC_DIST_BASE 0x48241000
3828	#define OMAP44XX_GIC_CPU_BASE 0x48240100
3829	-#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
3830	#define OMAP44XX_SCU_BASE 0x48240000
3831	-#define OMAP44XX_VA_SCU_BASE OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
3832	#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
3833	-#define OMAP44XX_VA_LOCAL_TWD_BASE OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
3834	-#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100
3835	#define OMAP44XX_WKUPGEN_BASE 0x48281000
3836	-#define OMAP44XX_VA_WKUPGEN_BASE OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
3837
3838	#endif /* __ASM_ARCH_OMAP44XX_H */
3839
3840	--- /dev/null
3841	+++ b/arch/arm/plat-omap/include/mach/omap7xx.h
3842	@@ -0,0 +1,104 @@
3843	+/* arch/arm/plat-omap/include/mach/omap7xx.h
3844	+ *
3845	+ * Hardware definitions for TI OMAP7XX processor.
3846	+ *
3847	+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
3848	+ * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
3849	+ * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
3850	+ *
3851	+ * This program is free software; you can redistribute it and/or modify it
3852	+ * under the terms of the GNU General Public License as published by the
3853	+ * Free Software Foundation; either version 2 of the License, or (at your
3854	+ * option) any later version.
3855	+ *
3856	+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3857	+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3858	+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3859	+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3860	+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3861	+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3862	+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3863	+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3864	+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3865	+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3866	+ *
3867	+ * You should have received a copy of the GNU General Public License along
3868	+ * with this program; if not, write to the Free Software Foundation, Inc.,
3869	+ * 675 Mass Ave, Cambridge, MA 02139, USA.
3870	+ */
3871	+
3872	+#ifndef __ASM_ARCH_OMAP7XX_H
3873	+#define __ASM_ARCH_OMAP7XX_H
3874	+
3875	+/*
3876	+ * ----------------------------------------------------------------------------
3877	+ * Base addresses
3878	+ * ----------------------------------------------------------------------------
3879	+ */
3880	+
3881	+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
3882	+
3883	+#define OMAP7XX_DSP_BASE 0xE0000000
3884	+#define OMAP7XX_DSP_SIZE 0x50000
3885	+#define OMAP7XX_DSP_START 0xE0000000
3886	+
3887	+#define OMAP7XX_DSPREG_BASE 0xE1000000
3888	+#define OMAP7XX_DSPREG_SIZE SZ_128K
3889	+#define OMAP7XX_DSPREG_START 0xE1000000
3890	+
3891	+/*
3892	+ * ----------------------------------------------------------------------------
3893	+ * OMAP7XX specific configuration registers
3894	+ * ----------------------------------------------------------------------------
3895	+ */
3896	+#define OMAP7XX_CONFIG_BASE 0xfffe1000
3897	+#define OMAP7XX_IO_CONF_0 0xfffe1070
3898	+#define OMAP7XX_IO_CONF_1 0xfffe1074
3899	+#define OMAP7XX_IO_CONF_2 0xfffe1078
3900	+#define OMAP7XX_IO_CONF_3 0xfffe107c
3901	+#define OMAP7XX_IO_CONF_4 0xfffe1080
3902	+#define OMAP7XX_IO_CONF_5 0xfffe1084
3903	+#define OMAP7XX_IO_CONF_6 0xfffe1088
3904	+#define OMAP7XX_IO_CONF_7 0xfffe108c
3905	+#define OMAP7XX_IO_CONF_8 0xfffe1090
3906	+#define OMAP7XX_IO_CONF_9 0xfffe1094
3907	+#define OMAP7XX_IO_CONF_10 0xfffe1098
3908	+#define OMAP7XX_IO_CONF_11 0xfffe109c
3909	+#define OMAP7XX_IO_CONF_12 0xfffe10a0
3910	+#define OMAP7XX_IO_CONF_13 0xfffe10a4
3911	+
3912	+#define OMAP7XX_MODE_1 0xfffe1010
3913	+#define OMAP7XX_MODE_2 0xfffe1014
3914	+
3915	+/* CSMI specials: in terms of base + offset */
3916	+#define OMAP7XX_MODE2_OFFSET 0x14
3917	+
3918	+/*
3919	+ * ----------------------------------------------------------------------------
3920	+ * OMAP7XX traffic controller configuration registers
3921	+ * ----------------------------------------------------------------------------
3922	+ */
3923	+#define OMAP7XX_FLASH_CFG_0 0xfffecc10
3924	+#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
3925	+#define OMAP7XX_FLASH_CFG_1 0xfffecc14
3926	+#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
3927	+
3928	+/*
3929	+ * ----------------------------------------------------------------------------
3930	+ * OMAP7XX DSP control registers
3931	+ * ----------------------------------------------------------------------------
3932	+ */
3933	+#define OMAP7XX_ICR_BASE 0xfffbb800
3934	+#define OMAP7XX_DSP_M_CTL 0xfffbb804
3935	+#define OMAP7XX_DSP_MMU_BASE 0xfffed200
3936	+
3937	+/*
3938	+ * ----------------------------------------------------------------------------
3939	+ * OMAP7XX PCC_UPLD configuration registers
3940	+ * ----------------------------------------------------------------------------
3941	+ */
3942	+#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
3943	+#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
3944	+
3945	+#endif /* __ASM_ARCH_OMAP7XX_H */
3946	+
3947	--- a/arch/arm/plat-omap/include/mach/sdrc.h
3948	+++ b/arch/arm/plat-omap/include/mach/sdrc.h
3949	@@ -80,11 +80,11 @@
3950	*/
3951
3952	#define OMAP242X_SMS_REGADDR(reg) \
3953	- (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
3954	+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
3955	#define OMAP243X_SMS_REGADDR(reg) \
3956	- (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
3957	+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
3958	#define OMAP343X_SMS_REGADDR(reg) \
3959	- (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
3960	+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
3961
3962	/* SMS register offsets - read/write with sms_{read,write}_reg() */
3963
3964	--- a/arch/arm/plat-omap/include/mach/serial.h
3965	+++ b/arch/arm/plat-omap/include/mach/serial.h
3966	@@ -20,26 +20,22 @@
3967	#define OMAP_UART1_BASE 0xfffb0000
3968	#define OMAP_UART2_BASE 0xfffb0800
3969	#define OMAP_UART3_BASE 0xfffb9800
3970	-#define OMAP_MAX_NR_PORTS 3
3971	#elif defined(CONFIG_ARCH_OMAP2)
3972	/* OMAP2 serial ports */
3973	#define OMAP_UART1_BASE 0x4806a000
3974	#define OMAP_UART2_BASE 0x4806c000
3975	#define OMAP_UART3_BASE 0x4806e000
3976	-#define OMAP_MAX_NR_PORTS 3
3977	#elif defined(CONFIG_ARCH_OMAP3)
3978	/* OMAP3 serial ports */
3979	#define OMAP_UART1_BASE 0x4806a000
3980	#define OMAP_UART2_BASE 0x4806c000
3981	#define OMAP_UART3_BASE 0x49020000
3982	-#define OMAP_MAX_NR_PORTS 3
3983	#elif defined(CONFIG_ARCH_OMAP4)
3984	/* OMAP4 serial ports */
3985	#define OMAP_UART1_BASE 0x4806a000
3986	#define OMAP_UART2_BASE 0x4806c000
3987	#define OMAP_UART3_BASE 0x48020000
3988	#define OMAP_UART4_BASE 0x4806e000
3989	-#define OMAP_MAX_NR_PORTS 4
3990	#endif
3991
3992	#define OMAP1510_BASE_BAUD (12000000/16)
3993	--- a/arch/arm/plat-omap/include/mach/uncompress.h
3994	+++ b/arch/arm/plat-omap/include/mach/uncompress.h
3995	@@ -25,6 +25,7 @@ unsigned int system_rev;
3996
3997	#define UART_OMAP_MDR1 0x08 /* mode definition register */
3998	#define OMAP_ID_730 0x355F
3999	+#define OMAP_ID_850 0x362C
4000	#define ID_MASK 0x7fff
4001	#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
4002	#define omap_get_id() (((volatile unsigned int )(0xfffed404)) >> 12) & ID_MASK
4003	@@ -53,7 +54,7 @@ static void putc(int c)
4004	/* MMU is not on, so cpu_is_omapXXXX() won't work here */
4005	unsigned int omap_id = omap_get_id();
4006
4007	- if (omap_id == OMAP_ID_730)
4008	+ if (omap_id == OMAP_ID_730 \|\| omap_id == OMAP_ID_850)
4009	shift = 0;
4010
4011	if (check_port(uart, shift))
4012	--- a/arch/arm/plat-omap/include/mach/usb.h
4013	+++ b/arch/arm/plat-omap/include/mach/usb.h
4014	@@ -5,6 +5,21 @@
4015
4016	#include <mach/board.h>
4017
4018	+#define OMAP3_HS_USB_PORTS 3
4019	+enum ehci_hcd_omap_mode {
4020	+ EHCI_HCD_OMAP_MODE_UNKNOWN,
4021	+ EHCI_HCD_OMAP_MODE_PHY,
4022	+ EHCI_HCD_OMAP_MODE_TLL,
4023	+};
4024	+
4025	+struct ehci_hcd_omap_platform_data {
4026	+ enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
4027	+ unsigned phy_reset:1;
4028	+
4029	+ /* have to be valid if phy_reset is true and portx is in phy mode */
4030	+ int reset_gpio_port[OMAP3_HS_USB_PORTS];
4031	+};
4032	+
4033	/-------------------------------------------------------------------------/
4034
4035	#define OMAP1_OTG_BASE 0xfffb0400
4036	@@ -29,6 +44,8 @@
4037
4038	extern void usb_musb_init(void);
4039
4040	+extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
4041	+
4042	#endif
4043
4044	void omap_usb_init(struct omap_usb_config *pdata);
4045	--- a/arch/arm/plat-omap/include/mach/vmalloc.h
4046	+++ b/arch/arm/plat-omap/include/mach/vmalloc.h
4047	@@ -17,5 +17,5 @@
4048	* along with this program; if not, write to the Free Software
4049	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4050	*/
4051	-#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
4052	+#define VMALLOC_END (PAGE_OFFSET + 0x38000000)
4053
4054	--- a/arch/arm/plat-omap/io.c
4055	+++ b/arch/arm/plat-omap/io.c
4056	@@ -13,7 +13,7 @@
4057	#include <linux/io.h>
4058	#include <linux/mm.h>
4059
4060	-#include <mach/omap730.h>
4061	+#include <mach/omap7xx.h>
4062	#include <mach/omap1510.h>
4063	#include <mach/omap16xx.h>
4064	#include <mach/omap24xx.h>
4065	@@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long
4066	if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
4067	return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
4068	}
4069	- if (cpu_is_omap730()) {
4070	- if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
4071	- return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
4072	-
4073	- if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
4074	- return XLATE(p, OMAP730_DSPREG_BASE,
4075	- OMAP730_DSPREG_START);
4076	+ if (cpu_is_omap7xx()) {
4077	+ if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
4078	+ return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
4079	+
4080	+ if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
4081	+ return XLATE(p, OMAP7XX_DSPREG_BASE,
4082	+ OMAP7XX_DSPREG_START);
4083	}
4084	if (cpu_is_omap15xx()) {
4085	if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
4086	@@ -114,6 +114,14 @@ void __iomem *omap_ioremap(unsigned long
4087	return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
4088	if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
4089	return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
4090	+ if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE))
4091	+ return XLATE(p, OMAP44XX_EMIF1_PHYS, \
4092	+ OMAP44XX_EMIF1_VIRT);
4093	+ if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE))
4094	+ return XLATE(p, OMAP44XX_EMIF2_PHYS, \
4095	+ OMAP44XX_EMIF2_VIRT);
4096	+ if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE))
4097	+ return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT);
4098	if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
4099	return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
4100	if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
4101	@@ -142,7 +150,7 @@ u8 omap_readb(u32 pa)
4102	if (cpu_class_is_omap1())
4103	return __raw_readb(OMAP1_IO_ADDRESS(pa));
4104	else
4105	- return __raw_readb(OMAP2_IO_ADDRESS(pa));
4106	+ return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
4107	}
4108	EXPORT_SYMBOL(omap_readb);
4109
4110	@@ -151,7 +159,7 @@ u16 omap_readw(u32 pa)
4111	if (cpu_class_is_omap1())
4112	return __raw_readw(OMAP1_IO_ADDRESS(pa));
4113	else
4114	- return __raw_readw(OMAP2_IO_ADDRESS(pa));
4115	+ return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
4116	}
4117	EXPORT_SYMBOL(omap_readw);
4118
4119	@@ -160,7 +168,7 @@ u32 omap_readl(u32 pa)
4120	if (cpu_class_is_omap1())
4121	return __raw_readl(OMAP1_IO_ADDRESS(pa));
4122	else
4123	- return __raw_readl(OMAP2_IO_ADDRESS(pa));
4124	+ return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
4125	}
4126	EXPORT_SYMBOL(omap_readl);
4127
4128	@@ -169,7 +177,7 @@ void omap_writeb(u8 v, u32 pa)
4129	if (cpu_class_is_omap1())
4130	__raw_writeb(v, OMAP1_IO_ADDRESS(pa));
4131	else
4132	- __raw_writeb(v, OMAP2_IO_ADDRESS(pa));
4133	+ __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
4134	}
4135	EXPORT_SYMBOL(omap_writeb);
4136
4137	@@ -178,7 +186,7 @@ void omap_writew(u16 v, u32 pa)
4138	if (cpu_class_is_omap1())
4139	__raw_writew(v, OMAP1_IO_ADDRESS(pa));
4140	else
4141	- __raw_writew(v, OMAP2_IO_ADDRESS(pa));
4142	+ __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
4143	}
4144	EXPORT_SYMBOL(omap_writew);
4145
4146	@@ -187,6 +195,6 @@ void omap_writel(u32 v, u32 pa)
4147	if (cpu_class_is_omap1())
4148	__raw_writel(v, OMAP1_IO_ADDRESS(pa));
4149	else
4150	- __raw_writel(v, OMAP2_IO_ADDRESS(pa));
4151	+ __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
4152	}
4153	EXPORT_SYMBOL(omap_writel);
4154	--- a/arch/arm/plat-omap/omap_device.c
4155	+++ b/arch/arm/plat-omap/omap_device.c
4156	@@ -103,21 +103,6 @@
4157	/* Private functions */
4158
4159	/**
4160	- * _read_32ksynct - read the OMAP 32K sync timer
4161	- *
4162	- * Returns the current value of the 32KiHz synchronization counter.
4163	- * XXX this should be generalized to simply read the system clocksource.
4164	- * XXX this should be moved to a separate synctimer32k.c file
4165	- */
4166	-static u32 _read_32ksynct(void)
4167	-{
4168	- if (!cpu_class_is_omap2())
4169	- BUG();
4170	-
4171	- return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010));
4172	-}
4173	-
4174	-/**
4175	* _omap_device_activate - increase device readiness
4176	* @od: struct omap_device *
4177	* @ignore_lat: increase to latency target (0) or full readiness (1)?
4178	@@ -133,13 +118,13 @@ static u32 _read_32ksynct(void)
4179	*/
4180	static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
4181	{
4182	- u32 a, b;
4183	+ struct timespec a, b, c;
4184
4185	pr_debug("omap_device: %s: activating\n", od->pdev.name);
4186
4187	while (od->pm_lat_level > 0) {
4188	struct omap_device_pm_latency *odpl;
4189	- int act_lat = 0;
4190	+ unsigned long long act_lat = 0;
4191
4192	od->pm_lat_level--;
4193
4194	@@ -149,20 +134,22 @@ static int _omap_device_activate(struct
4195	(od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
4196	break;
4197
4198	- a = _read_32ksynct();
4199	+ getnstimeofday(&a);
4200
4201	/* XXX check return code */
4202	odpl->activate_func(od);
4203
4204	- b = _read_32ksynct();
4205	+ getnstimeofday(&b);
4206
4207	- act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
4208	+ c = timespec_sub(b, a);
4209	+ act_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
4210
4211	pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
4212	- "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat);
4213	+ "%llu usec\n", od->pdev.name, od->pm_lat_level,
4214	+ act_lat);
4215
4216	WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
4217	- "activate step %d took longer than expected (%d > %d)\n",
4218	+ "activate step %d took longer than expected (%llu > %d)\n",
4219	od->pdev.name, od->pdev.id, od->pm_lat_level,
4220	act_lat, odpl->activate_lat);
4221
4222	@@ -188,13 +175,13 @@ static int _omap_device_activate(struct
4223	*/
4224	static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
4225	{
4226	- u32 a, b;
4227	+ struct timespec a, b, c;
4228
4229	pr_debug("omap_device: %s: deactivating\n", od->pdev.name);
4230
4231	while (od->pm_lat_level < od->pm_lats_cnt) {
4232	struct omap_device_pm_latency *odpl;
4233	- int deact_lat = 0;
4234	+ unsigned long long deact_lat = 0;
4235
4236	odpl = od->pm_lats + od->pm_lat_level;
4237
4238	@@ -203,23 +190,24 @@ static int _omap_device_deactivate(struc
4239	od->_dev_wakeup_lat_limit))
4240	break;
4241
4242	- a = _read_32ksynct();
4243	+ getnstimeofday(&a);
4244
4245	/* XXX check return code */
4246	odpl->deactivate_func(od);
4247
4248	- b = _read_32ksynct();
4249	+ getnstimeofday(&b);
4250
4251	- deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
4252	+ c = timespec_sub(b, a);
4253	+ deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
4254
4255	pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
4256	- "%d usec\n", od->pdev.name, od->pm_lat_level,
4257	+ "%llu usec\n", od->pdev.name, od->pm_lat_level,
4258	deact_lat);
4259
4260	WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
4261	- "deactivate step %d took longer than expected (%d > %d)\n",
4262	- od->pdev.name, od->pdev.id, od->pm_lat_level,
4263	- deact_lat, odpl->deactivate_lat);
4264	+ "deactivate step %d took longer than expected "
4265	+ "(%llu > %d)\n", od->pdev.name, od->pdev.id,
4266	+ od->pm_lat_level, deact_lat, odpl->deactivate_lat);
4267
4268	od->dev_wakeup_lat += odpl->activate_lat;
4269
4270	--- a/arch/arm/plat-omap/sram.c
4271	+++ b/arch/arm/plat-omap/sram.c
4272	@@ -42,14 +42,14 @@
4273	#define OMAP1_SRAM_VA VMALLOC_END
4274	#define OMAP2_SRAM_PA 0x40200000
4275	#define OMAP2_SRAM_PUB_PA 0x4020f800
4276	-#define OMAP2_SRAM_VA 0xe3000000
4277	+#define OMAP2_SRAM_VA 0xfe400000
4278	#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
4279	#define OMAP3_SRAM_PA 0x40200000
4280	-#define OMAP3_SRAM_VA 0xe3000000
4281	+#define OMAP3_SRAM_VA 0xfe400000
4282	#define OMAP3_SRAM_PUB_PA 0x40208000
4283	#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
4284	#define OMAP4_SRAM_PA 0x40200000 /0x402f0000/
4285	-#define OMAP4_SRAM_VA 0xd7000000 /0xd70f0000/
4286	+#define OMAP4_SRAM_VA 0xfe400000 /0xfe4f0000/
4287
4288	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
4289	#define SRAM_BOOTLOADER_SZ 0x00
4290	@@ -57,16 +57,16 @@
4291	#define SRAM_BOOTLOADER_SZ 0x80
4292	#endif
4293
4294	-#define OMAP24XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68005048)
4295	-#define OMAP24XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68005050)
4296	-#define OMAP24XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68005058)
4297	-
4298	-#define OMAP34XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68012848)
4299	-#define OMAP34XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68012850)
4300	-#define OMAP34XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68012858)
4301	-#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_IO_ADDRESS(0x68012880)
4302	-#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_IO_ADDRESS(0x6C000048)
4303	-#define OMAP34XX_VA_CONTROL_STAT OMAP2_IO_ADDRESS(0x480022F0)
4304	+#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
4305	+#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
4306	+#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
4307	+
4308	+#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
4309	+#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
4310	+#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
4311	+#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
4312	+#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
4313	+#define OMAP34XX_VA_CONTROL_STAT OMAP2_L4_IO_ADDRESS(0x480022F0)
4314
4315	#define GP_DEVICE 0x300
4316
4317	--- a/arch/arm/plat-omap/usb.c
4318	+++ b/arch/arm/plat-omap/usb.c
4319	@@ -614,8 +614,8 @@ omap_otg_init(struct omap_usb_config *co
4320	if (config->otg \|\| config->register_host) {
4321	syscon &= ~HST_IDLE_EN;
4322	ohci_device.dev.platform_data = config;
4323	- if (cpu_is_omap730())
4324	- ohci_resources[1].start = INT_730_USB_HHC_1;
4325	+ if (cpu_is_omap7xx())
4326	+ ohci_resources[1].start = INT_7XX_USB_HHC_1;
4327	status = platform_device_register(&ohci_device);
4328	if (status)
4329	pr_debug("can't register OHCI device, %d\n", status);
4330	@@ -626,8 +626,8 @@ omap_otg_init(struct omap_usb_config *co
4331	if (config->otg) {
4332	syscon &= ~OTG_IDLE_EN;
4333	otg_device.dev.platform_data = config;
4334	- if (cpu_is_omap730())
4335	- otg_resources[1].start = INT_730_USB_OTG;
4336	+ if (cpu_is_omap7xx())
4337	+ otg_resources[1].start = INT_7XX_USB_OTG;
4338	status = platform_device_register(&otg_device);
4339	if (status)
4340	pr_debug("can't register OTG device, %d\n", status);
4341	@@ -731,7 +731,7 @@ static inline void omap_1510_usb_init(st
4342
4343	void __init omap_usb_init(struct omap_usb_config *pdata)
4344	{
4345	- if (cpu_is_omap730() \|\| cpu_is_omap16xx() \|\| cpu_is_omap24xx())
4346	+ if (cpu_is_omap7xx() \|\| cpu_is_omap16xx() \|\| cpu_is_omap24xx())
4347	omap_otg_init(pdata);
4348	else if (cpu_is_omap15xx())
4349	omap_1510_usb_init(pdata);
4350	--- a/drivers/Makefile
4351	+++ b/drivers/Makefile
4352	@@ -72,7 +72,7 @@ obj-$(CONFIG_GAMEPORT) += input/gamepor
4353	obj-$(CONFIG_INPUT) += input/
4354	obj-$(CONFIG_I2O) += message/
4355	obj-$(CONFIG_RTC_LIB) += rtc/
4356	-obj-y += i2c/ media/
4357	+obj-y += i2c/ media/ cbus/
4358	obj-$(CONFIG_PPS) += pps/
4359	obj-$(CONFIG_W1) += w1/
4360	obj-$(CONFIG_POWER_SUPPLY) += power/
4361	--- /dev/null
4362	+++ b/drivers/cbus/Kconfig
4363	@@ -0,0 +1,89 @@
4364	+#
4365	+# CBUS device configuration
4366	+#
4367	+
4368	+menu "CBUS support"
4369	+
4370	+config CBUS
4371	+ depends on ARCH_OMAP
4372	+ bool "CBUS support on OMAP"
4373	+ ---help---
4374	+ CBUS is a proprietary serial protocol by Nokia. It is mainly
4375	+ used for accessing Energy Management auxiliary chips.
4376	+
4377	+ If you want CBUS support, you should say Y here.
4378	+
4379	+config CBUS_TAHVO
4380	+ depends on CBUS
4381	+ bool "Support for Tahvo"
4382	+ ---help---
4383	+ Tahvo is a mixed signal ASIC with some system features
4384	+
4385	+ If you want Tahvo support, you should say Y here.
4386	+
4387	+config CBUS_TAHVO_USER
4388	+ depends on CBUS_TAHVO
4389	+ bool "Support for Tahvo user space functions"
4390	+ ---help---
4391	+ If you want support for Tahvo's user space read/write etc. functions,
4392	+ you should say Y here.
4393	+
4394	+config CBUS_TAHVO_USB
4395	+ depends on CBUS_TAHVO && USB
4396	+ tristate "Support for Tahvo USB transceiver"
4397	+ ---help---
4398	+ If you want Tahvo support for USB transceiver, say Y or M here.
4399	+
4400	+config CBUS_TAHVO_USB_HOST_BY_DEFAULT
4401	+ depends on CBUS_TAHVO_USB && USB_OTG
4402	+ boolean "Device in USB host mode by default"
4403	+ ---help---
4404	+ Say Y here, if you want the device to enter USB host mode
4405	+ by default on bootup.
4406	+
4407	+config CBUS_RETU
4408	+ depends on CBUS
4409	+ bool "Support for Retu"
4410	+ ---help---
4411	+ Retu is a mixed signal ASIC with some system features
4412	+
4413	+ If you want Retu support, you should say Y here.
4414	+
4415	+config CBUS_RETU_USER
4416	+ depends on CBUS_RETU
4417	+ bool "Support for Retu user space functions"
4418	+ ---help---
4419	+ If you want support for Retu's user space read/write etc. functions,
4420	+ you should say Y here.
4421	+
4422	+config CBUS_RETU_POWERBUTTON
4423	+ depends on CBUS_RETU
4424	+ bool "Support for Retu power button"
4425	+ ---help---
4426	+ The power button on Nokia 770 is connected to the Retu ASIC.
4427	+
4428	+ If you want support for the Retu power button, you should say Y here.
4429	+
4430	+config CBUS_RETU_RTC
4431	+ depends on CBUS_RETU && SYSFS
4432	+ tristate "Support for Retu pseudo-RTC"
4433	+ ---help---
4434	+ Say Y here if you want support for the device that alleges to be an
4435	+ RTC in Retu. This will expose a sysfs interface for it.
4436	+
4437	+config CBUS_RETU_WDT
4438	+ depends on CBUS_RETU && SYSFS
4439	+ tristate "Support for Retu watchdog timer"
4440	+ ---help---
4441	+ Say Y here if you want support for the watchdog in Retu. This will
4442	+ expose a sysfs interface to grok it.
4443	+
4444	+config CBUS_RETU_HEADSET
4445	+ depends on CBUS_RETU && SYSFS
4446	+ tristate "Support for headset detection with Retu/Vilma"
4447	+ ---help---
4448	+ Say Y here if you want support detecting a headset that's connected
4449	+ to Retu/Vilma. Detection state and events are exposed through
4450	+ sysfs.
4451	+
4452	+endmenu
4453	--- /dev/null
4454	+++ b/drivers/cbus/Makefile
4455	@@ -0,0 +1,14 @@
4456	+#
4457	+# Makefile for CBUS.
4458	+#
4459	+
4460	+obj-$(CONFIG_CBUS) += cbus.o
4461	+obj-$(CONFIG_CBUS_TAHVO) += tahvo.o
4462	+obj-$(CONFIG_CBUS_RETU) += retu.o
4463	+obj-$(CONFIG_CBUS_TAHVO_USB) += tahvo-usb.o
4464	+obj-$(CONFIG_CBUS_RETU_POWERBUTTON) += retu-pwrbutton.o
4465	+obj-$(CONFIG_CBUS_RETU_RTC) += retu-rtc.o
4466	+obj-$(CONFIG_CBUS_RETU_WDT) += retu-wdt.o
4467	+obj-$(CONFIG_CBUS_TAHVO_USER) += tahvo-user.o
4468	+obj-$(CONFIG_CBUS_RETU_USER) += retu-user.o
4469	+obj-$(CONFIG_CBUS_RETU_HEADSET) += retu-headset.o
4470	--- /dev/null
4471	+++ b/drivers/cbus/cbus.c
4472	@@ -0,0 +1,293 @@
4473	+/*
4474	+ * drivers/cbus/cbus.c
4475	+ *
4476	+ * Support functions for CBUS serial protocol
4477	+ *
4478	+ * Copyright (C) 2004, 2005 Nokia Corporation
4479	+ *
4480	+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com>,
4481	+ * David Weinehall <david.weinehall@nokia.com>, and
4482	+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
4483	+ *
4484	+ * This file is subject to the terms and conditions of the GNU General
4485	+ * Public License. See the file "COPYING" in the main directory of this
4486	+ * archive for more details.
4487	+ *
4488	+ * This program is distributed in the hope that it will be useful,
4489	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4490	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4491	+ * GNU General Public License for more details.
4492	+ *
4493	+ * You should have received a copy of the GNU General Public License
4494	+ * along with this program; if not, write to the Free Software
4495	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4496	+ */
4497	+
4498	+#include <linux/device.h>
4499	+#include <linux/init.h>
4500	+#include <linux/kernel.h>
4501	+#include <linux/delay.h>
4502	+#include <linux/spinlock.h>
4503	+#include <linux/gpio.h>
4504	+
4505	+#include <mach/board.h>
4506	+#include <mach/board-nokia.h>
4507	+
4508	+#include <asm/io.h>
4509	+
4510	+#include "cbus.h"
4511	+
4512	+struct cbus_host *cbus_host = NULL;
4513	+
4514	+#ifdef CONFIG_ARCH_OMAP1
4515	+/* We use our own MPUIO functions to get closer to 1MHz bus speed */
4516	+
4517	+static inline void cbus_set_gpio_direction(u32 base, int mpuio, int is_input)
4518	+{
4519	+ u16 w;
4520	+
4521	+ mpuio &= 0x0f;
4522	+ w = __raw_readw(base + OMAP_MPUIO_IO_CNTL);
4523	+ if (is_input)
4524	+ w \|= 1 << mpuio;
4525	+ else
4526	+ w &= ~(1 << mpuio);
4527	+ __raw_writew(w, base + OMAP_MPUIO_IO_CNTL);
4528	+
4529	+}
4530	+
4531	+static inline void cbus_set_gpio_dataout(u32 base, int mpuio, int enable)
4532	+{
4533	+ u16 w;
4534	+
4535	+ mpuio &= 0x0f;
4536	+ w = __raw_readw(base + OMAP_MPUIO_OUTPUT);
4537	+ if (enable)
4538	+ w \|= 1 << mpuio;
4539	+ else
4540	+ w &= ~(1 << mpuio);
4541	+ __raw_writew(w, base + OMAP_MPUIO_OUTPUT);
4542	+}
4543	+
4544	+static inline int cbus_get_gpio_datain(u32 base, int mpuio)
4545	+{
4546	+ mpuio &= 0x0f;
4547	+
4548	+ return (__raw_readw(base + OMAP_MPUIO_INPUT_LATCH) & (1 << mpuio)) != 0;
4549	+}
4550	+
4551	+static void cbus_send_bit(struct cbus_host *host, u32 base, int bit,
4552	+ int set_to_input)
4553	+{
4554	+ cbus_set_gpio_dataout(base, host->dat_gpio, bit ? 1 : 0);
4555	+ cbus_set_gpio_dataout(base, host->clk_gpio, 1);
4556	+
4557	+ /* The data bit is read on the rising edge of CLK */
4558	+ if (set_to_input)
4559	+ cbus_set_gpio_direction(base, host->dat_gpio, 1);
4560	+
4561	+ cbus_set_gpio_dataout(base, host->clk_gpio, 0);
4562	+}
4563	+
4564	+static u8 cbus_receive_bit(struct cbus_host *host, u32 base)
4565	+{
4566	+ u8 ret;
4567	+
4568	+ cbus_set_gpio_dataout(base, host->clk_gpio, 1);
4569	+ ret = cbus_get_gpio_datain(base, host->dat_gpio);
4570	+ cbus_set_gpio_dataout(base, host->clk_gpio, 0);
4571	+
4572	+ return ret;
4573	+}
4574	+
4575	+#define cbus_output(base, gpio, val) cbus_set_gpio_direction(base, gpio, 0)
4576	+
4577	+#else
4578	+
4579	+#define cbus_output(base, gpio, val) gpio_direction_output(gpio, val)
4580	+#define cbus_set_gpio_dataout(base, gpio, enable) gpio_set_value(gpio, enable)
4581	+#define cbus_get_gpio_datain(base, int, gpio) gpio_get_value(gpio)
4582	+
4583	+static void _cbus_send_bit(struct cbus_host *host, int bit, int set_to_input)
4584	+{
4585	+ gpio_set_value(host->dat_gpio, bit ? 1 : 0);
4586	+ gpio_set_value(host->clk_gpio, 1);
4587	+
4588	+ /* The data bit is read on the rising edge of CLK */
4589	+ if (set_to_input)
4590	+ gpio_direction_input(host->dat_gpio);
4591	+
4592	+ gpio_set_value(host->clk_gpio, 0);
4593	+}
4594	+
4595	+static u8 _cbus_receive_bit(struct cbus_host *host)
4596	+{
4597	+ u8 ret;
4598	+
4599	+ gpio_set_value(host->clk_gpio, 1);
4600	+ ret = gpio_get_value(host->dat_gpio);
4601	+ gpio_set_value(host->clk_gpio, 0);
4602	+
4603	+ return ret;
4604	+}
4605	+
4606	+#define cbus_send_bit(host, base, bit, set_to_input) _cbus_send_bit(host, bit, set_to_input)
4607	+#define cbus_receive_bit(host, base) _cbus_receive_bit(host)
4608	+
4609	+#endif
4610	+
4611	+static int cbus_transfer(struct cbus_host *host, int dev, int reg, int data)
4612	+{
4613	+ int i;
4614	+ int is_read = 0;
4615	+ unsigned long flags;
4616	+ u32 base;
4617	+
4618	+#ifdef CONFIG_ARCH_OMAP1
4619	+ base = OMAP1_IO_ADDRESS(OMAP_MPUIO_BASE);
4620	+#else
4621	+ base = 0;
4622	+#endif
4623	+
4624	+ if (data < 0)
4625	+ is_read = 1;
4626	+
4627	+ /* We don't want interrupts disturbing our transfer */
4628	+ spin_lock_irqsave(&host->lock, flags);
4629	+
4630	+ /* Reset state and start of transfer, SEL stays down during transfer */
4631	+ cbus_set_gpio_dataout(base, host->sel_gpio, 0);
4632	+
4633	+ /* Set the DAT pin to output */
4634	+ cbus_output(base, host->dat_gpio, 1);
4635	+
4636	+ /* Send the device address */
4637	+ for (i = 3; i > 0; i--)
4638	+ cbus_send_bit(host, base, dev & (1 << (i - 1)), 0);
4639	+
4640	+ /* Send the rw flag */
4641	+ cbus_send_bit(host, base, is_read, 0);
4642	+
4643	+ /* Send the register address */
4644	+ for (i = 5; i > 0; i--) {
4645	+ int set_to_input = 0;
4646	+
4647	+ if (is_read && i == 1)
4648	+ set_to_input = 1;
4649	+
4650	+ cbus_send_bit(host, base, reg & (1 << (i - 1)), set_to_input);
4651	+ }
4652	+
4653	+ if (!is_read) {
4654	+ for (i = 16; i > 0; i--)
4655	+ cbus_send_bit(host, base, data & (1 << (i - 1)), 0);
4656	+ } else {
4657	+ cbus_set_gpio_dataout(base, host->clk_gpio, 1);
4658	+ data = 0;
4659	+
4660	+ for (i = 16; i > 0; i--) {
4661	+ u8 bit = cbus_receive_bit(host, base);
4662	+
4663	+ if (bit)
4664	+ data \|= 1 << (i - 1);
4665	+ }
4666	+ }
4667	+
4668	+ /* Indicate end of transfer, SEL goes up until next transfer */
4669	+ cbus_set_gpio_dataout(base, host->sel_gpio, 1);
4670	+ cbus_set_gpio_dataout(base, host->clk_gpio, 1);
4671	+ cbus_set_gpio_dataout(base, host->clk_gpio, 0);
4672	+
4673	+ spin_unlock_irqrestore(&host->lock, flags);
4674	+
4675	+ return is_read ? data : 0;
4676	+}
4677	+
4678	+/*
4679	+ * Read a given register from the device
4680	+ */
4681	+int cbus_read_reg(struct cbus_host *host, int dev, int reg)
4682	+{
4683	+ return cbus_host ? cbus_transfer(host, dev, reg, -1) : -ENODEV;
4684	+}
4685	+
4686	+/*
4687	+ * Write to a given register of the device
4688	+ */
4689	+int cbus_write_reg(struct cbus_host *host, int dev, int reg, u16 val)
4690	+{
4691	+ return cbus_host ? cbus_transfer(host, dev, reg, (int)val) : -ENODEV;
4692	+}
4693	+
4694	+int __init cbus_bus_init(void)
4695	+{
4696	+ const struct omap_cbus_config * cbus_config;
4697	+ struct cbus_host *chost;
4698	+ int ret;
4699	+
4700	+ chost = kmalloc(sizeof (*chost), GFP_KERNEL);
4701	+ if (chost == NULL)
4702	+ return -ENOMEM;
4703	+
4704	+ memset(chost, 0, sizeof (*chost));
4705	+
4706	+ spin_lock_init(&chost->lock);
4707	+
4708	+ cbus_config = omap_get_config(OMAP_TAG_CBUS, struct omap_cbus_config);
4709	+
4710	+ if (cbus_config == NULL) {
4711	+ printk(KERN_ERR "cbus: Unable to retrieve config data\n");
4712	+ return -ENODATA;
4713	+ }
4714	+
4715	+ chost->clk_gpio = cbus_config->clk_gpio;
4716	+ chost->dat_gpio = cbus_config->dat_gpio;
4717	+ chost->sel_gpio = cbus_config->sel_gpio;
4718	+
4719	+#ifdef CONFIG_ARCH_OMAP1
4720	+ if (!OMAP_GPIO_IS_MPUIO(chost->clk_gpio) \|\|
4721	+ !OMAP_GPIO_IS_MPUIO(chost->dat_gpio) \|\|
4722	+ !OMAP_GPIO_IS_MPUIO(chost->sel_gpio)) {
4723	+ printk(KERN_ERR "cbus: Only MPUIO pins supported\n");
4724	+ ret = -ENODEV;
4725	+ goto exit1;
4726	+ }
4727	+#endif
4728	+
4729	+ if ((ret = gpio_request(chost->clk_gpio, "CBUS clk")) < 0)
4730	+ goto exit1;
4731	+
4732	+ if ((ret = gpio_request(chost->dat_gpio, "CBUS data")) < 0)
4733	+ goto exit2;
4734	+
4735	+ if ((ret = gpio_request(chost->sel_gpio, "CBUS sel")) < 0)
4736	+ goto exit3;
4737	+
4738	+ gpio_direction_output(chost->clk_gpio, 0);
4739	+ gpio_direction_input(chost->dat_gpio);
4740	+ gpio_direction_output(chost->sel_gpio, 1);
4741	+
4742	+ gpio_set_value(chost->clk_gpio, 1);
4743	+ gpio_set_value(chost->clk_gpio, 0);
4744	+
4745	+ cbus_host = chost;
4746	+
4747	+ return 0;
4748	+exit3:
4749	+ gpio_free(chost->dat_gpio);
4750	+exit2:
4751	+ gpio_free(chost->clk_gpio);
4752	+exit1:
4753	+ kfree(chost);
4754	+ return ret;
4755	+}
4756	+
4757	+subsys_initcall(cbus_bus_init);
4758	+
4759	+EXPORT_SYMBOL(cbus_host);
4760	+EXPORT_SYMBOL(cbus_read_reg);
4761	+EXPORT_SYMBOL(cbus_write_reg);
4762	+
4763	+MODULE_DESCRIPTION("CBUS serial protocol");
4764	+MODULE_LICENSE("GPL");
4765	+MODULE_AUTHOR("Juha Yrj�l�, David Weinehall, and Mikko Ylinen");
4766	--- /dev/null
4767	+++ b/drivers/cbus/cbus.h
4768	@@ -0,0 +1,36 @@
4769	+/*
4770	+ * drivers/cbus/cbus.h
4771	+ *
4772	+ * Copyright (C) 2004, 2005 Nokia Corporation
4773	+ *
4774	+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com> and
4775	+ * David Weinehall <david.weinehall@nokia.com>
4776	+ *
4777	+ * This file is subject to the terms and conditions of the GNU General
4778	+ * Public License. See the file "COPYING" in the main directory of this
4779	+ * archive for more details.
4780	+ *
4781	+ * This program is distributed in the hope that it will be useful,
4782	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4783	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4784	+ * GNU General Public License for more details.
4785	+ *
4786	+ * You should have received a copy of the GNU General Public License
4787	+ * along with this program; if not, write to the Free Software
4788	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4789	+ */
4790	+
4791	+#ifndef __DRIVERS_CBUS_CBUS_H
4792	+#define __DRIVERS_CBUS_CBUS_H
4793	+
4794	+struct cbus_host {
4795	+ int clk_gpio, dat_gpio, sel_gpio;
4796	+ spinlock_t lock;
4797	+};
4798	+
4799	+extern struct cbus_host *cbus_host;
4800	+
4801	+extern int cbus_read_reg(struct cbus_host *host, int dev, int reg);
4802	+extern int cbus_write_reg(struct cbus_host *host, int dev, int reg, u16 val);
4803	+
4804	+#endif /* __DRIVERS_CBUS_CBUS_H */
4805	--- /dev/null
4806	+++ b/drivers/cbus/retu-headset.c
4807	@@ -0,0 +1,355 @@
4808	+/**
4809	+ * Retu/Vilma headset detection
4810	+ *
4811	+ * Copyright (C) 2006 Nokia Corporation
4812	+ *
4813	+ * Written by Juha Yrj�l�
4814	+ *
4815	+ * This file is subject to the terms and conditions of the GNU General
4816	+ * Public License. See the file "COPYING" in the main directory of this
4817	+ * archive for more details.
4818	+ *
4819	+ * This program is distributed in the hope that it will be useful,
4820	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4821	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4822	+ * GNU General Public License for more details.
4823	+ *
4824	+ * You should have received a copy of the GNU General Public License
4825	+ * along with this program; if not, write to the Free Software
4826	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4827	+ */
4828	+
4829	+#include <linux/module.h>
4830	+#include <linux/init.h>
4831	+#include <linux/kernel.h>
4832	+#include <linux/delay.h>
4833	+#include <linux/input.h>
4834	+#include <linux/platform_device.h>
4835	+
4836	+#include "retu.h"
4837	+
4838	+#define RETU_ADC_CHANNEL_HOOKDET 0x05
4839	+
4840	+#define RETU_HEADSET_KEY KEY_PHONE
4841	+
4842	+struct retu_headset {
4843	+ spinlock_t lock;
4844	+ struct mutex mutex;
4845	+ struct platform_device *pdev;
4846	+ struct input_dev *idev;
4847	+ unsigned bias_enabled;
4848	+ unsigned detection_enabled;
4849	+ unsigned pressed;
4850	+ struct timer_list enable_timer;
4851	+ struct timer_list detect_timer;
4852	+};
4853	+
4854	+static void retu_headset_set_bias(int enable)
4855	+{
4856	+ if (enable) {
4857	+ retu_set_clear_reg_bits(RETU_REG_AUDTXR,
4858	+ (1 << 0) \| (1 << 1), 0);
4859	+ msleep(2);
4860	+ retu_set_clear_reg_bits(RETU_REG_AUDTXR, 1 << 3, 0);
4861	+ } else {
4862	+ retu_set_clear_reg_bits(RETU_REG_AUDTXR, 0,
4863	+ (1 << 0) \| (1 << 1) \| (1 << 3));
4864	+ }
4865	+}
4866	+
4867	+static void retu_headset_enable(struct retu_headset *hs)
4868	+{
4869	+ mutex_lock(&hs->mutex);
4870	+ if (!hs->bias_enabled) {
4871	+ hs->bias_enabled = 1;
4872	+ retu_headset_set_bias(1);
4873	+ }
4874	+ mutex_unlock(&hs->mutex);
4875	+}
4876	+
4877	+static void retu_headset_disable(struct retu_headset *hs)
4878	+{
4879	+ mutex_lock(&hs->mutex);
4880	+ if (hs->bias_enabled) {
4881	+ hs->bias_enabled = 0;
4882	+ retu_headset_set_bias(0);
4883	+ }
4884	+ mutex_unlock(&hs->mutex);
4885	+}
4886	+
4887	+static void retu_headset_det_enable(struct retu_headset *hs)
4888	+{
4889	+ mutex_lock(&hs->mutex);
4890	+ if (!hs->detection_enabled) {
4891	+ hs->detection_enabled = 1;
4892	+ retu_set_clear_reg_bits(RETU_REG_CC1, (1 << 10) \| (1 << 8), 0);
4893	+ retu_enable_irq(RETU_INT_HOOK);
4894	+ }
4895	+ mutex_unlock(&hs->mutex);
4896	+}
4897	+
4898	+static void retu_headset_det_disable(struct retu_headset *hs)
4899	+{
4900	+ unsigned long flags;
4901	+
4902	+ mutex_lock(&hs->mutex);
4903	+ if (hs->detection_enabled) {
4904	+ hs->detection_enabled = 0;
4905	+ retu_disable_irq(RETU_INT_HOOK);
4906	+ del_timer_sync(&hs->enable_timer);
4907	+ del_timer_sync(&hs->detect_timer);
4908	+ spin_lock_irqsave(&hs->lock, flags);
4909	+ if (hs->pressed)
4910	+ input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
4911	+ spin_unlock_irqrestore(&hs->lock, flags);
4912	+ retu_set_clear_reg_bits(RETU_REG_CC1, 0, (1 << 10) \| (1 << 8));
4913	+ }
4914	+ mutex_unlock(&hs->mutex);
4915	+}
4916	+
4917	+static ssize_t retu_headset_hookdet_show(struct device *dev,
4918	+ struct device_attribute *attr,
4919	+ char *buf)
4920	+{
4921	+ int val;
4922	+
4923	+ val = retu_read_adc(RETU_ADC_CHANNEL_HOOKDET);
4924	+ return sprintf(buf, "%d\n", val);
4925	+}
4926	+
4927	+static DEVICE_ATTR(hookdet, S_IRUGO, retu_headset_hookdet_show, NULL);
4928	+
4929	+static ssize_t retu_headset_enable_show(struct device *dev,
4930	+ struct device_attribute *attr,
4931	+ char *buf)
4932	+{
4933	+ struct retu_headset *hs = dev_get_drvdata(dev);
4934	+
4935	+ return sprintf(buf, "%u\n", hs->bias_enabled);
4936	+}
4937	+
4938	+static ssize_t retu_headset_enable_store(struct device *dev,
4939	+ struct device_attribute *attr,
4940	+ const char *buf, size_t count)
4941	+{
4942	+ struct retu_headset *hs = dev_get_drvdata(dev);
4943	+ int enable;
4944	+
4945	+ if (sscanf(buf, "%u", &enable) != 1)
4946	+ return -EINVAL;
4947	+ if (enable)
4948	+ retu_headset_enable(hs);
4949	+ else
4950	+ retu_headset_disable(hs);
4951	+ return count;
4952	+}
4953	+
4954	+static DEVICE_ATTR(enable, S_IRUGO \| S_IWUSR \| S_IWGRP,
4955	+ retu_headset_enable_show, retu_headset_enable_store);
4956	+
4957	+static ssize_t retu_headset_enable_det_show(struct device *dev,
4958	+ struct device_attribute *attr,
4959	+ char *buf)
4960	+{
4961	+ struct retu_headset *hs = dev_get_drvdata(dev);
4962	+
4963	+ return sprintf(buf, "%u\n", hs->detection_enabled);
4964	+}
4965	+
4966	+static ssize_t retu_headset_enable_det_store(struct device *dev,
4967	+ struct device_attribute *attr,
4968	+ const char *buf, size_t count)
4969	+{
4970	+ struct retu_headset *hs = dev_get_drvdata(dev);
4971	+ int enable;
4972	+
4973	+ if (sscanf(buf, "%u", &enable) != 1)
4974	+ return -EINVAL;
4975	+ if (enable)
4976	+ retu_headset_det_enable(hs);
4977	+ else
4978	+ retu_headset_det_disable(hs);
4979	+ return count;
4980	+}
4981	+
4982	+static DEVICE_ATTR(enable_det, S_IRUGO \| S_IWUSR \| S_IWGRP,
4983	+ retu_headset_enable_det_show,
4984	+ retu_headset_enable_det_store);
4985	+
4986	+static void retu_headset_hook_interrupt(unsigned long arg)
4987	+{
4988	+ struct retu_headset hs = (struct retu_headset ) arg;
4989	+ unsigned long flags;
4990	+
4991	+ retu_ack_irq(RETU_INT_HOOK);
4992	+ spin_lock_irqsave(&hs->lock, flags);
4993	+ if (!hs->pressed) {
4994	+ /* Headset button was just pressed down. */
4995	+ hs->pressed = 1;
4996	+ input_report_key(hs->idev, RETU_HEADSET_KEY, 1);
4997	+ }
4998	+ spin_unlock_irqrestore(&hs->lock, flags);
4999	+ retu_set_clear_reg_bits(RETU_REG_CC1, 0, (1 << 10) \| (1 << 8));
5000	+ mod_timer(&hs->enable_timer, jiffies + msecs_to_jiffies(50));
5001	+}
5002	+
5003	+static void retu_headset_enable_timer(unsigned long arg)
5004	+{
5005	+ struct retu_headset hs = (struct retu_headset ) arg;
5006	+
5007	+ retu_set_clear_reg_bits(RETU_REG_CC1, (1 << 10) \| (1 << 8), 0);
5008	+ mod_timer(&hs->detect_timer, jiffies + msecs_to_jiffies(350));
5009	+}
5010	+
5011	+static void retu_headset_detect_timer(unsigned long arg)
5012	+{
5013	+ struct retu_headset hs = (struct retu_headset ) arg;
5014	+ unsigned long flags;
5015	+
5016	+ spin_lock_irqsave(&hs->lock, flags);
5017	+ if (hs->pressed) {
5018	+ hs->pressed = 0;
5019	+ input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
5020	+ }
5021	+ spin_unlock_irqrestore(&hs->lock, flags);
5022	+}
5023	+
5024	+static int __init retu_headset_probe(struct platform_device *pdev)
5025	+{
5026	+ struct retu_headset *hs;
5027	+ int r;
5028	+
5029	+ hs = kzalloc(sizeof(*hs), GFP_KERNEL);
5030	+ if (hs == NULL)
5031	+ return -ENOMEM;
5032	+
5033	+ hs->pdev = pdev;
5034	+
5035	+ hs->idev = input_allocate_device();
5036	+ if (hs->idev == NULL) {
5037	+ r = -ENOMEM;
5038	+ goto err1;
5039	+ }
5040	+ hs->idev->name = "retu-headset";
5041	+ hs->idev->dev.parent = &pdev->dev;
5042	+ set_bit(EV_KEY, hs->idev->evbit);
5043	+ set_bit(RETU_HEADSET_KEY, hs->idev->keybit);
5044	+ r = input_register_device(hs->idev);
5045	+ if (r < 0)
5046	+ goto err2;
5047	+
5048	+ r = device_create_file(&pdev->dev, &dev_attr_hookdet);
5049	+ if (r < 0)
5050	+ goto err3;
5051	+ r = device_create_file(&pdev->dev, &dev_attr_enable);
5052	+ if (r < 0)
5053	+ goto err4;
5054	+ r = device_create_file(&pdev->dev, &dev_attr_enable_det);
5055	+ if (r < 0)
5056	+ goto err5;
5057	+ platform_set_drvdata(pdev, hs);
5058	+
5059	+ spin_lock_init(&hs->lock);
5060	+ mutex_init(&hs->mutex);
5061	+ setup_timer(&hs->enable_timer, retu_headset_enable_timer,
5062	+ (unsigned long) hs);
5063	+ setup_timer(&hs->detect_timer, retu_headset_detect_timer,
5064	+ (unsigned long) hs);
5065	+
5066	+ r = retu_request_irq(RETU_INT_HOOK, retu_headset_hook_interrupt,
5067	+ (unsigned long) hs, "hookdet");
5068	+ if (r != 0) {
5069	+ dev_err(&pdev->dev, "hookdet IRQ not available\n");
5070	+ goto err6;
5071	+ }
5072	+ retu_disable_irq(RETU_INT_HOOK);
5073	+ return 0;
5074	+err6:
5075	+ device_remove_file(&pdev->dev, &dev_attr_enable_det);
5076	+err5:
5077	+ device_remove_file(&pdev->dev, &dev_attr_enable);
5078	+err4:
5079	+ device_remove_file(&pdev->dev, &dev_attr_hookdet);
5080	+err3:
5081	+ input_unregister_device(hs->idev);
5082	+err2:
5083	+ input_free_device(hs->idev);
5084	+err1:
5085	+ kfree(hs);
5086	+ return r;
5087	+}
5088	+
5089	+static int retu_headset_remove(struct platform_device *pdev)
5090	+{
5091	+ struct retu_headset *hs = platform_get_drvdata(pdev);
5092	+
5093	+ device_remove_file(&pdev->dev, &dev_attr_hookdet);
5094	+ device_remove_file(&pdev->dev, &dev_attr_enable);
5095	+ device_remove_file(&pdev->dev, &dev_attr_enable_det);
5096	+ retu_headset_disable(hs);
5097	+ retu_headset_det_disable(hs);
5098	+ retu_free_irq(RETU_INT_HOOK);
5099	+ input_unregister_device(hs->idev);
5100	+ input_free_device(hs->idev);
5101	+ return 0;
5102	+}
5103	+
5104	+static int retu_headset_suspend(struct platform_device *pdev,
5105	+ pm_message_t mesg)
5106	+{
5107	+ struct retu_headset *hs = platform_get_drvdata(pdev);
5108	+
5109	+ mutex_lock(&hs->mutex);
5110	+ if (hs->bias_enabled)
5111	+ retu_headset_set_bias(0);
5112	+ mutex_unlock(&hs->mutex);
5113	+
5114	+ return 0;
5115	+}
5116	+
5117	+static int retu_headset_resume(struct platform_device *pdev)
5118	+{
5119	+ struct retu_headset *hs = platform_get_drvdata(pdev);
5120	+
5121	+ mutex_lock(&hs->mutex);
5122	+ if (hs->bias_enabled)
5123	+ retu_headset_set_bias(1);
5124	+ mutex_unlock(&hs->mutex);
5125	+
5126	+ return 0;
5127	+}
5128	+
5129	+static struct platform_driver retu_headset_driver = {
5130	+ .probe = retu_headset_probe,
5131	+ .remove = retu_headset_remove,
5132	+ .suspend = retu_headset_suspend,
5133	+ .resume = retu_headset_resume,
5134	+ .driver = {
5135	+ .name = "retu-headset",
5136	+ },
5137	+};
5138	+
5139	+static int __init retu_headset_init(void)
5140	+{
5141	+ int r;
5142	+
5143	+ printk(KERN_INFO "Retu/Vilma headset driver initializing\n");
5144	+
5145	+ r = platform_driver_register(&retu_headset_driver);
5146	+ if (r < 0)
5147	+ return r;
5148	+
5149	+ return 0;
5150	+}
5151	+
5152	+static void __exit retu_headset_exit(void)
5153	+{
5154	+ platform_driver_unregister(&retu_headset_driver);
5155	+}
5156	+
5157	+module_init(retu_headset_init);
5158	+module_exit(retu_headset_exit);
5159	+
5160	+MODULE_DESCRIPTION("Retu/Vilma headset detection");
5161	+MODULE_LICENSE("GPL");
5162	+MODULE_AUTHOR("Juha Yrj�l�");
5163	--- /dev/null
5164	+++ b/drivers/cbus/retu-pwrbutton.c
5165	@@ -0,0 +1,118 @@
5166	+/**
5167	+ * drivers/cbus/retu-pwrbutton.c
5168	+ *
5169	+ * Driver for sending retu power button event to input-layer
5170	+ *
5171	+ * Copyright (C) 2004 Nokia Corporation
5172	+ *
5173	+ * Written by Ari Saastamoinen <ari.saastamoinen@elektrobit.com>
5174	+ *
5175	+ * Contact Juha Yrj�l� <juha.yrjola@nokia.com>
5176	+ *
5177	+ * This file is subject to the terms and conditions of the GNU General
5178	+ * Public License. See the file "COPYING" in the main directory of this
5179	+ * archive for more details.
5180	+ *
5181	+ * This program is distributed in the hope that it will be useful,
5182	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5183	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5184	+ * GNU General Public License for more details.
5185	+ *
5186	+ * You should have received a copy of the GNU General Public License
5187	+ * along with this program; if not, write to the Free Software
5188	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5189	+ */
5190	+
5191	+#include <linux/module.h>
5192	+#include <linux/init.h>
5193	+#include <linux/kernel.h>
5194	+#include <linux/errno.h>
5195	+#include <linux/input.h>
5196	+#include <linux/timer.h>
5197	+#include <linux/jiffies.h>
5198	+#include <linux/bitops.h>
5199	+
5200	+#include "retu.h"
5201	+
5202	+#define RETU_STATUS_PWRONX (1 << 5)
5203	+
5204	+#define PWRBTN_DELAY 20
5205	+#define PWRBTN_UP 0
5206	+#define PWRBTN_PRESSED 1
5207	+
5208	+static int pwrbtn_state;
5209	+static struct input_dev *pwrbtn_dev;
5210	+static struct timer_list pwrbtn_timer;
5211	+
5212	+static void retubutton_timer_func(unsigned long arg)
5213	+{
5214	+ int state;
5215	+
5216	+ if (retu_read_reg(RETU_REG_STATUS) & RETU_STATUS_PWRONX)
5217	+ state = PWRBTN_UP;
5218	+ else
5219	+ state = PWRBTN_PRESSED;
5220	+
5221	+ if (pwrbtn_state != state) {
5222	+ input_report_key(pwrbtn_dev, KEY_POWER, state);
5223	+ pwrbtn_state = state;
5224	+ }
5225	+}
5226	+
5227	+/**
5228	+ * Interrupt function is called whenever power button key is pressed
5229	+ * or released.
5230	+ */
5231	+static void retubutton_irq(unsigned long arg)
5232	+{
5233	+ retu_ack_irq(RETU_INT_PWR);
5234	+ mod_timer(&pwrbtn_timer, jiffies + msecs_to_jiffies(PWRBTN_DELAY));
5235	+}
5236	+
5237	+/**
5238	+ * Init function.
5239	+ * Allocates interrupt for power button and registers itself to input layer.
5240	+ */
5241	+static int __init retubutton_init(void)
5242	+{
5243	+ int irq;
5244	+
5245	+ printk(KERN_INFO "Retu power button driver initialized\n");
5246	+ irq = RETU_INT_PWR;
5247	+
5248	+ init_timer(&pwrbtn_timer);
5249	+ pwrbtn_timer.function = retubutton_timer_func;
5250	+
5251	+ if (retu_request_irq(irq, &retubutton_irq, 0, "PwrOnX") < 0) {
5252	+ printk(KERN_ERR "%s@%s: Cannot allocate irq\n",
5253	+ __FUNCTION__, __FILE__);
5254	+ return -EBUSY;
5255	+ }
5256	+
5257	+ pwrbtn_dev = input_allocate_device();
5258	+ if (!pwrbtn_dev)
5259	+ return -ENOMEM;
5260	+
5261	+ pwrbtn_dev->evbit[0] = BIT_MASK(EV_KEY);
5262	+ pwrbtn_dev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER);
5263	+ pwrbtn_dev->name = "retu-pwrbutton";
5264	+
5265	+ return input_register_device(pwrbtn_dev);
5266	+}
5267	+
5268	+/**
5269	+ * Cleanup function which is called when driver is unloaded
5270	+ */
5271	+static void __exit retubutton_exit(void)
5272	+{
5273	+ retu_free_irq(RETU_INT_PWR);
5274	+ del_timer_sync(&pwrbtn_timer);
5275	+ input_unregister_device(pwrbtn_dev);
5276	+}
5277	+
5278	+module_init(retubutton_init);
5279	+module_exit(retubutton_exit);
5280	+
5281	+MODULE_DESCRIPTION("Retu Power Button");
5282	+MODULE_LICENSE("GPL");
5283	+MODULE_AUTHOR("Ari Saastamoinen");
5284	--- /dev/null
5285	+++ b/drivers/cbus/retu-rtc.c
5286	@@ -0,0 +1,477 @@
5287	+/**
5288	+ * drivers/cbus/retu-rtc.c
5289	+ *
5290	+ * Support for Retu RTC
5291	+ *
5292	+ * Copyright (C) 2004, 2005 Nokia Corporation
5293	+ *
5294	+ * Written by Paul Mundt <paul.mundt@nokia.com> and
5295	+ * Igor Stoppa <igor.stoppa@nokia.com>
5296	+ *
5297	+ * The Retu RTC is essentially a partial read-only RTC that gives us Retu's
5298	+ * idea of what time actually is. It's left as a userspace excercise to map
5299	+ * this back to time in the real world and ensure that calibration settings
5300	+ * are sane to compensate for any horrible drift (on account of not being able
5301	+ * to set the clock to anything).
5302	+ *
5303	+ * Days are semi-writeable. Namely, Retu will only track 255 days for us
5304	+ * consecutively, after which the counter is explicitly stuck at 255 until
5305	+ * someone comes along and clears it with a write. In the event that no one
5306	+ * comes along and clears it, we no longer have any idea what day it is.
5307	+ *
5308	+ * This file is subject to the terms and conditions of the GNU General
5309	+ * Public License. See the file "COPYING" in the main directory of this
5310	+ * archive for more details.
5311	+ *
5312	+ * This program is distributed in the hope that it will be useful,
5313	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5314	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5315	+ * GNU General Public License for more details.
5316	+ *
5317	+ * You should have received a copy of the GNU General Public License
5318	+ * along with this program; if not, write to the Free Software
5319	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5320	+ */
5321	+
5322	+#include <linux/device.h>
5323	+#include <linux/init.h>
5324	+#include <linux/kernel.h>
5325	+#include <linux/module.h>
5326	+#include <linux/completion.h>
5327	+#include <linux/platform_device.h>
5328	+#include <linux/mutex.h>
5329	+#include <linux/workqueue.h>
5330	+
5331	+#include "cbus.h"
5332	+#include "retu.h"
5333	+
5334	+static struct mutex retu_rtc_mutex;
5335	+static u16 retu_rtc_alarm_expired;
5336	+static u16 retu_rtc_reset_occurred;
5337	+
5338	+static DECLARE_COMPLETION(retu_rtc_exited);
5339	+static DECLARE_COMPLETION(retu_rtc_sync);
5340	+
5341	+static void retu_rtc_barrier(void);
5342	+
5343	+static void retu_rtc_device_release(struct device *dev)
5344	+{
5345	+ complete(&retu_rtc_exited);
5346	+}
5347	+
5348	+static ssize_t retu_rtc_time_show(struct device dev, struct device_attribute attr,
5349	+ char *buf)
5350	+{
5351	+ u16 dsr, hmr, dsr2;
5352	+
5353	+ mutex_lock(&retu_rtc_mutex);
5354	+
5355	+ do {
5356	+ u16 dummy;
5357	+
5358	+ /*
5359	+ * Not being in_interrupt() for a retu rtc IRQ, we need to
5360	+ * read twice for consistency..
5361	+ */
5362	+ dummy = retu_read_reg(RETU_REG_RTCDSR);
5363	+ dsr = retu_read_reg(RETU_REG_RTCDSR);
5364	+
5365	+ dummy = retu_read_reg(RETU_REG_RTCHMR);
5366	+ hmr = retu_read_reg(RETU_REG_RTCHMR);
5367	+
5368	+ dummy = retu_read_reg(RETU_REG_RTCDSR);
5369	+ dsr2 = retu_read_reg(RETU_REG_RTCDSR);
5370	+ } while ((dsr != dsr2));
5371	+
5372	+ mutex_unlock(&retu_rtc_mutex);
5373	+
5374	+ /*
5375	+ * Format a 32-bit date-string for userspace
5376	+ *
5377	+ * days \| hours \| minutes \| seconds
5378	+ *
5379	+ * 8 bits for each.
5380	+ *
5381	+ * This mostly sucks because days and seconds are tracked in RTCDSR
5382	+ * while hours and minutes are tracked in RTCHMR. And yes, there
5383	+ * really are no words that can describe an 8 bit day register (or
5384	+ * rather, none that will be reprinted here).
5385	+ */
5386	+ return sprintf(buf, "0x%08x\n", (((dsr >> 8) & 0xff) << 24) \|
5387	+ (((hmr >> 8) & 0x1f) << 16) \|
5388	+ ((hmr & 0x3f) << 8) \| (dsr & 0x3f));
5389	+}
5390	+
5391	+static ssize_t retu_rtc_time_store(struct device dev, struct device_attribute attr,
5392	+ const char *buf, size_t count)
5393	+{
5394	+ mutex_lock(&retu_rtc_mutex);
5395	+ /*
5396	+ * Writing anything to the day counter forces it to 0
5397	+ * The seconds counter would be cleared by resetting the minutes counter,
5398	+ * however this won't happen, since we are using the hh:mm counters as
5399	+ * a set of free running counters and the day counter as a multiple
5400	+ * overflow holder.
5401	+ */
5402	+
5403	+ /* Reset day counter, but keep Temperature Shutdown state */
5404	+ retu_write_reg(RETU_REG_RTCDSR,
5405	+ retu_read_reg(RETU_REG_RTCDSR) & (1 << 6));
5406	+
5407	+ mutex_unlock(&retu_rtc_mutex);
5408	+
5409	+ return count;
5410	+}
5411	+
5412	+static DEVICE_ATTR(time, S_IRUGO \| S_IWUSR, retu_rtc_time_show,
5413	+ retu_rtc_time_store);
5414	+
5415	+
5416	+static ssize_t retu_rtc_reset_show(struct device dev, struct device_attribute attr, char *buf)
5417	+{
5418	+ /*
5419	+ * Returns the status of the rtc
5420	+ *
5421	+ * 0: no reset has occurred or the status has been cleared
5422	+ * 1: a reset has occurred
5423	+ *
5424	+ * RTC needs to be reset only when both main battery
5425	+ * _AND_ backup battery are discharged
5426	+ */
5427	+ return sprintf(buf, "%u\n", retu_rtc_reset_occurred);
5428	+}
5429	+
5430	+static void retu_rtc_do_reset(void)
5431	+{
5432	+ u16 ccr1;
5433	+
5434	+ ccr1 = retu_read_reg(RETU_REG_CC1);
5435	+ /* RTC in reset */
5436	+ retu_write_reg(RETU_REG_CC1, ccr1 \| 0x0001);
5437	+ /* RTC in normal operating mode */
5438	+ retu_write_reg(RETU_REG_CC1, ccr1 & ~0x0001);
5439	+
5440	+ retu_rtc_barrier();
5441	+ /* Disable alarm and RTC WD */
5442	+ retu_write_reg(RETU_REG_RTCHMAR, 0x7f3f);
5443	+ /* Set Calibration register to default value */
5444	+ retu_write_reg(RETU_REG_RTCCALR, 0x00c0);
5445	+
5446	+ retu_rtc_alarm_expired = 0;
5447	+ retu_rtc_reset_occurred = 1;
5448	+}
5449	+
5450	+static ssize_t retu_rtc_reset_store(struct device dev, struct device_attribute attr,
5451	+ const char *buf, size_t count)
5452	+{
5453	+ unsigned choice;
5454	+
5455	+ if(sscanf(buf, "%u", &choice) != 1)
5456	+ return count;
5457	+ mutex_lock(&retu_rtc_mutex);
5458	+ if (choice == 0)
5459	+ retu_rtc_reset_occurred = 0;
5460	+ else if (choice == 1)
5461	+ retu_rtc_do_reset();
5462	+ mutex_unlock(&retu_rtc_mutex);
5463	+ return count;
5464	+}
5465	+
5466	+static DEVICE_ATTR(reset, S_IRUGO \| S_IWUSR, retu_rtc_reset_show,
5467	+ retu_rtc_reset_store);
5468	+
5469	+static ssize_t retu_rtc_alarm_show(struct device dev, struct device_attribute attr,
5470	+ char *buf)
5471	+{
5472	+ u16 chmar;
5473	+ ssize_t retval;
5474	+
5475	+ mutex_lock(&retu_rtc_mutex);
5476	+ /*
5477	+ * Format a 16-bit date-string for userspace
5478	+ *
5479	+ * hours \| minutes
5480	+ * 8 bits for each.
5481	+ */
5482	+ chmar = retu_read_reg(RETU_REG_RTCHMAR);
5483	+ /* No shifting needed, only masking unrelated bits */
5484	+ retval = sprintf(buf, "0x%04x\n", chmar & 0x1f3f);
5485	+ mutex_unlock(&retu_rtc_mutex);
5486	+
5487	+ return retval;
5488	+}
5489	+
5490	+static ssize_t retu_rtc_alarm_store(struct device dev, struct device_attribute attr,
5491	+ const char *buf, size_t count)
5492	+{
5493	+ u16 chmar;
5494	+ unsigned alrm;
5495	+ unsigned hours;
5496	+ unsigned minutes;
5497	+
5498	+ mutex_lock(&retu_rtc_mutex);
5499	+
5500	+ if(sscanf(buf, "%x", &alrm) != 1)
5501	+ return count;
5502	+ hours = (alrm >> 8) & 0x001f;
5503	+ minutes = (alrm >> 0) & 0x003f;
5504	+ if ((hours < 24 && minutes < 60) \|\| (hours == 24 && minutes == 60)) {
5505	+ /*
5506	+ * OK, the time format for the alarm is valid (including the
5507	+ * disabling values)
5508	+ */
5509	+ /* Keeps the RTC watchdog status */
5510	+ chmar = retu_read_reg(RETU_REG_RTCHMAR) & 0x6000;
5511	+ chmar \|= alrm & 0x1f3f; /* Stores the requested alarm */
5512	+ retu_rtc_barrier();
5513	+ retu_write_reg(RETU_REG_RTCHMAR, chmar);
5514	+ /* If the alarm is being disabled */
5515	+ if (hours == 24 && minutes == 60) {
5516	+ /* disable the interrupt */
5517	+ retu_disable_irq(RETU_INT_RTCA);
5518	+ retu_rtc_alarm_expired = 0;
5519	+ } else
5520	+ /* enable the interrupt */
5521	+ retu_enable_irq(RETU_INT_RTCA);
5522	+ }
5523	+ mutex_unlock(&retu_rtc_mutex);
5524	+
5525	+ return count;
5526	+}
5527	+
5528	+static DEVICE_ATTR(alarm, S_IRUGO \| S_IWUSR, retu_rtc_alarm_show,
5529	+ retu_rtc_alarm_store);
5530	+
5531	+static ssize_t retu_rtc_alarm_expired_show(struct device dev, struct device_attribute attr,
5532	+ char *buf)
5533	+{
5534	+ ssize_t retval;
5535	+
5536	+ retval = sprintf(buf, "%u\n", retu_rtc_alarm_expired);
5537	+
5538	+ return retval;
5539	+}
5540	+
5541	+static ssize_t retu_rtc_alarm_expired_store(struct device dev, struct device_attribute attr,
5542	+ const char *buf, size_t count)
5543	+{
5544	+ retu_rtc_alarm_expired = 0;
5545	+
5546	+ return count;
5547	+}
5548	+
5549	+static DEVICE_ATTR(alarm_expired, S_IRUGO \| S_IWUSR, retu_rtc_alarm_expired_show,
5550	+ retu_rtc_alarm_expired_store);
5551	+
5552	+
5553	+static ssize_t retu_rtc_cal_show(struct device dev, struct device_attribute attr,
5554	+ char *buf)
5555	+{
5556	+ u16 rtccalr1;
5557	+
5558	+ mutex_lock(&retu_rtc_mutex);
5559	+ rtccalr1 = retu_read_reg(RETU_REG_RTCCALR);
5560	+ mutex_unlock(&retu_rtc_mutex);
5561	+
5562	+ /*
5563	+ * Shows the status of the Calibration Register.
5564	+ *
5565	+ * Default, after power loss: 0x0000
5566	+ * Default, for R&D: 0x00C0
5567	+ * Default, for factory: 0x00??
5568	+ *
5569	+ */
5570	+ return sprintf(buf, "0x%04x\n", rtccalr1 & 0x00ff);
5571	+}
5572	+
5573	+static ssize_t retu_rtc_cal_store(struct device dev, struct device_attribute attr,
5574	+ const char *buf, size_t count)
5575	+{
5576	+ unsigned calibration_value;
5577	+
5578	+ if (sscanf(buf, "%x", &calibration_value) != 1)
5579	+ return count;
5580	+
5581	+ mutex_lock(&retu_rtc_mutex);
5582	+ retu_rtc_barrier();
5583	+ retu_write_reg(RETU_REG_RTCCALR, calibration_value & 0x00ff);
5584	+ mutex_unlock(&retu_rtc_mutex);
5585	+
5586	+ return count;
5587	+}
5588	+
5589	+static DEVICE_ATTR(cal, S_IRUGO \| S_IWUSR, retu_rtc_cal_show,
5590	+ retu_rtc_cal_store);
5591	+
5592	+static struct platform_device retu_rtc_device;
5593	+
5594	+static void retu_rtca_disable(void)
5595	+{
5596	+ retu_disable_irq(RETU_INT_RTCA);
5597	+ retu_rtc_alarm_expired = 1;
5598	+ retu_rtc_barrier();
5599	+ retu_write_reg(RETU_REG_RTCHMAR, (24 << 8) \| 60);
5600	+}
5601	+
5602	+static void retu_rtca_expired(struct work_struct *unused)
5603	+{
5604	+ retu_rtca_disable();
5605	+ sysfs_notify(&retu_rtc_device.dev.kobj, NULL, "alarm_expired");
5606	+}
5607	+
5608	+DECLARE_WORK(retu_rtca_work, retu_rtca_expired);
5609	+
5610	+/*
5611	+ * RTCHMR RTCHMAR RTCCAL must be accessed within 0.9 s since the seconds
5612	+ * interrupt has been signaled in the IDR register
5613	+ */
5614	+static void retu_rtcs_interrupt(unsigned long unused)
5615	+{
5616	+ retu_ack_irq(RETU_INT_RTCS);
5617	+ complete_all(&retu_rtc_sync);
5618	+}
5619	+
5620	+static void retu_rtca_interrupt(unsigned long unused)
5621	+{
5622	+ retu_ack_irq(RETU_INT_RTCA);
5623	+ schedule_work(&retu_rtca_work);
5624	+}
5625	+
5626	+static int retu_rtc_init_irq(void)
5627	+{
5628	+ int ret;
5629	+
5630	+ ret = retu_request_irq(RETU_INT_RTCS, retu_rtcs_interrupt, 0, "RTCS");
5631	+ if (ret != 0)
5632	+ return ret;
5633	+ /*
5634	+ * We will take care of enabling and disabling the interrupt
5635	+ * elsewhere, so leave it off by default..
5636	+ */
5637	+ retu_disable_irq(RETU_INT_RTCS);
5638	+
5639	+ ret = retu_request_irq(RETU_INT_RTCA, retu_rtca_interrupt, 0, "RTCA");
5640	+ if (ret != 0) {
5641	+ retu_free_irq(RETU_INT_RTCS);
5642	+ return ret;
5643	+ }
5644	+ retu_disable_irq(RETU_INT_RTCA);
5645	+
5646	+ return 0;
5647	+}
5648	+
5649	+
5650	+static int __devinit retu_rtc_probe(struct device *dev)
5651	+{
5652	+ int r;
5653	+
5654	+ retu_rtc_alarm_expired = retu_read_reg(RETU_REG_IDR) &
5655	+ (0x1 << RETU_INT_RTCA);
5656	+
5657	+ if ((r = retu_rtc_init_irq()) != 0)
5658	+ return r;
5659	+
5660	+ mutex_init(&retu_rtc_mutex);
5661	+
5662	+ /* If the calibration register is zero, we've probably lost
5663	+ * power */
5664	+ if (retu_read_reg(RETU_REG_RTCCALR) & 0x00ff)
5665	+ retu_rtc_reset_occurred = 0;
5666	+ else
5667	+ retu_rtc_do_reset();
5668	+
5669	+ if ((r = device_create_file(dev, &dev_attr_time)) != 0)
5670	+ return r;
5671	+ else if ((r = device_create_file(dev, &dev_attr_reset)) != 0)
5672	+ goto err_unregister_time;
5673	+ else if ((r = device_create_file(dev, &dev_attr_alarm)) != 0)
5674	+ goto err_unregister_reset;
5675	+ else if ((r = device_create_file(dev, &dev_attr_alarm_expired)) != 0)
5676	+ goto err_unregister_alarm;
5677	+ else if ((r = device_create_file(dev, &dev_attr_cal)) != 0)
5678	+ goto err_unregister_alarm_expired;
5679	+ else
5680	+ return r;
5681	+
5682	+err_unregister_alarm_expired:
5683	+ device_remove_file(dev, &dev_attr_alarm_expired);
5684	+err_unregister_alarm:
5685	+ device_remove_file(dev, &dev_attr_alarm);
5686	+err_unregister_reset:
5687	+ device_remove_file(dev, &dev_attr_reset);
5688	+err_unregister_time:
5689	+ device_remove_file(dev, &dev_attr_time);
5690	+ return r;
5691	+}
5692	+
5693	+static int __devexit retu_rtc_remove(struct device *dev)
5694	+{
5695	+ retu_disable_irq(RETU_INT_RTCS);
5696	+ retu_free_irq(RETU_INT_RTCS);
5697	+ retu_free_irq(RETU_INT_RTCA);
5698	+ device_remove_file(dev, &dev_attr_cal);
5699	+ device_remove_file(dev, &dev_attr_alarm_expired);
5700	+ device_remove_file(dev, &dev_attr_alarm);
5701	+ device_remove_file(dev, &dev_attr_reset);
5702	+ device_remove_file(dev, &dev_attr_time);
5703	+ return 0;
5704	+}
5705	+
5706	+static struct device_driver retu_rtc_driver = {
5707	+ .name = "retu-rtc",
5708	+ .bus = &platform_bus_type,
5709	+ .probe = retu_rtc_probe,
5710	+ .remove = __devexit_p(retu_rtc_remove),
5711	+};
5712	+
5713	+static struct platform_device retu_rtc_device = {
5714	+ .name = "retu-rtc",
5715	+ .id = -1,
5716	+ .dev = {
5717	+ .release = retu_rtc_device_release,
5718	+ },
5719	+};
5720	+
5721	+/* This function provides syncronization with the RTCS interrupt handler */
5722	+static void retu_rtc_barrier(void)
5723	+{
5724	+ INIT_COMPLETION(retu_rtc_sync);
5725	+ retu_ack_irq(RETU_INT_RTCS);
5726	+ retu_enable_irq(RETU_INT_RTCS);
5727	+ wait_for_completion(&retu_rtc_sync);
5728	+ retu_disable_irq(RETU_INT_RTCS);
5729	+}
5730	+
5731	+static int __init retu_rtc_init(void)
5732	+{
5733	+ int ret;
5734	+
5735	+ init_completion(&retu_rtc_exited);
5736	+
5737	+ if ((ret = driver_register(&retu_rtc_driver)) != 0)
5738	+ return ret;
5739	+
5740	+ if ((ret = platform_device_register(&retu_rtc_device)) != 0)
5741	+ goto err_unregister_driver;
5742	+
5743	+ return 0;
5744	+
5745	+err_unregister_driver:
5746	+ driver_unregister(&retu_rtc_driver);
5747	+ return ret;
5748	+}
5749	+
5750	+static void __exit retu_rtc_exit(void)
5751	+{
5752	+ platform_device_unregister(&retu_rtc_device);
5753	+ driver_unregister(&retu_rtc_driver);
5754	+
5755	+ wait_for_completion(&retu_rtc_exited);
5756	+}
5757	+
5758	+module_init(retu_rtc_init);
5759	+module_exit(retu_rtc_exit);
5760	+
5761	+MODULE_DESCRIPTION("Retu RTC");
5762	+MODULE_LICENSE("GPL");
5763	+MODULE_AUTHOR("Paul Mundt and Igor Stoppa");
5764	--- /dev/null
5765	+++ b/drivers/cbus/retu-user.c
5766	@@ -0,0 +1,423 @@
5767	+/**
5768	+ * drivers/cbus/retu-user.c
5769	+ *
5770	+ * Retu user space interface functions
5771	+ *
5772	+ * Copyright (C) 2004, 2005 Nokia Corporation
5773	+ *
5774	+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
5775	+ *
5776	+ * This file is subject to the terms and conditions of the GNU General
5777	+ * Public License. See the file "COPYING" in the main directory of this
5778	+ * archive for more details.
5779	+ *
5780	+ * This program is distributed in the hope that it will be useful,
5781	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
5782	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5783	+ * GNU General Public License for more details.
5784	+ *
5785	+ * You should have received a copy of the GNU General Public License
5786	+ * along with this program; if not, write to the Free Software
5787	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5788	+ */
5789	+
5790	+#include <linux/types.h>
5791	+#include <linux/kernel.h>
5792	+#include <linux/interrupt.h>
5793	+#include <linux/module.h>
5794	+#include <linux/init.h>
5795	+#include <linux/fs.h>
5796	+#include <linux/miscdevice.h>
5797	+#include <linux/poll.h>
5798	+#include <linux/list.h>
5799	+#include <linux/spinlock.h>
5800	+#include <linux/mutex.h>
5801	+
5802	+#include <asm/uaccess.h>
5803	+
5804	+#include "retu.h"
5805	+
5806	+#include "user_retu_tahvo.h"
5807	+
5808	+/* Maximum size of IRQ node buffer/pool */
5809	+#define RETU_MAX_IRQ_BUF_LEN 16
5810	+
5811	+#define PFX "retu-user: "
5812	+
5813	+/* Bitmap for marking the interrupt sources as having the handlers */
5814	+static u32 retu_irq_bits;
5815	+
5816	+/* For allowing only one user process to subscribe to the retu interrupts */
5817	+static struct file *retu_irq_subscr = NULL;
5818	+
5819	+/* For poll and IRQ passing */
5820	+struct retu_irq {
5821	+ u32 id;
5822	+ struct list_head node;
5823	+};
5824	+
5825	+static spinlock_t retu_irqs_lock;
5826	+static struct retu_irq *retu_irq_block;
5827	+static LIST_HEAD(retu_irqs);
5828	+static LIST_HEAD(retu_irqs_reserve);
5829	+
5830	+/* Wait queue - used when user wants to read the device */
5831	+DECLARE_WAIT_QUEUE_HEAD(retu_user_waitqueue);
5832	+
5833	+/* Semaphore to protect irq subscription sequence */
5834	+static struct mutex retu_mutex;
5835	+
5836	+/* This array specifies RETU register types (read/write/toggle) */
5837	+static const u8 retu_access_bits[] = {
5838	+ 1,
5839	+ 4,
5840	+ 3,
5841	+ 3,
5842	+ 1,
5843	+ 3,
5844	+ 3,
5845	+ 0,
5846	+ 3,
5847	+ 3,
5848	+ 3,
5849	+ 3,
5850	+ 3,
5851	+ 3,
5852	+ 3,
5853	+ 4,
5854	+ 4,
5855	+ 3,
5856	+ 0,
5857	+ 0,
5858	+ 0,
5859	+ 0,
5860	+ 1,
5861	+ 3,
5862	+ 3,
5863	+ 3,
5864	+ 3,
5865	+ 3,
5866	+ 3,
5867	+ 3,
5868	+ 3,
5869	+ 3
5870	+};
5871	+
5872	+/*
5873	+ * The handler for all RETU interrupts.
5874	+ *
5875	+ * arg is the interrupt source in RETU.
5876	+ */
5877	+static void retu_user_irq_handler(unsigned long arg)
5878	+{
5879	+ struct retu_irq *irq;
5880	+
5881	+ retu_ack_irq(arg);
5882	+
5883	+ spin_lock(&retu_irqs_lock);
5884	+ if (list_empty(&retu_irqs_reserve)) {
5885	+ spin_unlock(&retu_irqs_lock);
5886	+ return;
5887	+ }
5888	+ irq = list_entry((&retu_irqs_reserve)->next, struct retu_irq, node);
5889	+ irq->id = arg;
5890	+ list_move_tail(&irq->node, &retu_irqs);
5891	+ spin_unlock(&retu_irqs_lock);
5892	+
5893	+ /* wake up waiting thread */
5894	+ wake_up(&retu_user_waitqueue);
5895	+}
5896	+
5897	+/*
5898	+ * This routine sets up the interrupt handler and marks an interrupt source
5899	+ * in RETU as a candidate for signal delivery to the user process.
5900	+ */
5901	+static int retu_user_subscribe_to_irq(int id, struct file *filp)
5902	+{
5903	+ int ret;
5904	+
5905	+ mutex_lock(&retu_mutex);
5906	+ if ((retu_irq_subscr != NULL) && (retu_irq_subscr != filp)) {
5907	+ mutex_unlock(&retu_mutex);
5908	+ return -EBUSY;
5909	+ }
5910	+ /* Store the file pointer of the first user process registering IRQs */
5911	+ retu_irq_subscr = filp;
5912	+ mutex_unlock(&retu_mutex);
5913	+
5914	+ if (retu_irq_bits & (1 << id))
5915	+ return 0;
5916	+
5917	+ ret = retu_request_irq(id, retu_user_irq_handler, id, "");
5918	+ if (ret < 0)
5919	+ return ret;
5920	+
5921	+ /* Mark that this interrupt has a handler */
5922	+ retu_irq_bits \|= 1 << id;
5923	+
5924	+ return 0;
5925	+}
5926	+
5927	+/*
5928	+ * Unregisters all RETU interrupt handlers.
5929	+ */
5930	+static void retu_unreg_irq_handlers(void)
5931	+{
5932	+ int id;
5933	+
5934	+ if (!retu_irq_bits)
5935	+ return;
5936	+
5937	+ for (id = 0; id < MAX_RETU_IRQ_HANDLERS; id++)
5938	+ if (retu_irq_bits & (1 << id))
5939	+ retu_free_irq(id);
5940	+
5941	+ retu_irq_bits = 0;
5942	+}
5943	+
5944	+/*
5945	+ * Write to RETU register.
5946	+ * Returns 0 upon success, a negative error value otherwise.
5947	+ */
5948	+static int retu_user_write_with_mask(u32 field, u16 value)
5949	+{
5950	+ u32 mask;
5951	+ u32 reg;
5952	+ u_short tmp;
5953	+ unsigned long flags;
5954	+
5955	+ mask = MASK(field);
5956	+ reg = REG(field);
5957	+
5958	+ /* Detect bad mask and reg */
5959	+ if (mask == 0 \|\| reg > RETU_REG_MAX \|\|
5960	+ retu_access_bits[reg] == READ_ONLY) {
5961	+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
5962	+ reg, mask);
5963	+ return -EINVAL;
5964	+ }
5965	+
5966	+ /* Justify value according to mask */
5967	+ while (!(mask & 1)) {
5968	+ value = value << 1;
5969	+ mask = mask >> 1;
5970	+ }
5971	+
5972	+ spin_lock_irqsave(&retu_lock, flags);
5973	+ if (retu_access_bits[reg] == TOGGLE) {
5974	+ /* No need to detect previous content of register */
5975	+ tmp = 0;
5976	+ } else {
5977	+ /* Read current value of register */
5978	+ tmp = retu_read_reg(reg);
5979	+ }
5980	+
5981	+ /* Generate new value */
5982	+ tmp = (tmp & ~MASK(field)) \| (value & MASK(field));
5983	+ /* Write data to RETU */
5984	+ retu_write_reg(reg, tmp);
5985	+ spin_unlock_irqrestore(&retu_lock, flags);
5986	+
5987	+ return 0;
5988	+}
5989	+
5990	+/*
5991	+ * Read RETU register.
5992	+ */
5993	+static u32 retu_user_read_with_mask(u32 field)
5994	+{
5995	+ u_short value;
5996	+ u32 mask, reg;
5997	+
5998	+ mask = MASK(field);
5999	+ reg = REG(field);
6000	+
6001	+ /* Detect bad mask and reg */
6002	+ if (mask == 0 \|\| reg > RETU_REG_MAX) {
6003	+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
6004	+ reg, mask);
6005	+ return -EINVAL;
6006	+ }
6007	+
6008	+ /* Read the register */
6009	+ value = retu_read_reg(reg) & mask;
6010	+
6011	+ /* Right justify value */
6012	+ while (!(mask & 1)) {
6013	+ value = value >> 1;
6014	+ mask = mask >> 1;
6015	+ }
6016	+
6017	+ return value;
6018	+}
6019	+
6020	+/*
6021	+ * Close device
6022	+ */
6023	+static int retu_close(struct inode inode, struct file filp)
6024	+{
6025	+ /* Unregister all interrupts that have been registered */
6026	+ if (retu_irq_subscr == filp) {
6027	+ retu_unreg_irq_handlers();
6028	+ retu_irq_subscr = NULL;
6029	+ }
6030	+
6031	+ return 0;
6032	+}
6033	+
6034	+/*
6035	+ * Device control (ioctl)
6036	+ */
6037	+static int retu_ioctl(struct inode inode, struct file filp,
6038	+ unsigned int cmd, unsigned long arg)
6039	+{
6040	+ struct retu_tahvo_write_parms par;
6041	+ int ret;
6042	+
6043	+ switch (cmd) {
6044	+ case URT_IOCT_IRQ_SUBSCR:
6045	+ return retu_user_subscribe_to_irq(arg, filp);
6046	+ case RETU_IOCH_READ:
6047	+ return retu_user_read_with_mask(arg);
6048	+ case RETU_IOCX_WRITE:
6049	+ ret = copy_from_user(&par, (void __user *) arg, sizeof(par));
6050	+ if (ret)
6051	+ printk(KERN_ERR "copy_from_user failed: %d\n", ret);
6052	+ par.result = retu_user_write_with_mask(par.field, par.value);
6053	+ ret = copy_to_user((void __user *) arg, &par, sizeof(par));
6054	+ if (ret)
6055	+ printk(KERN_ERR "copy_to_user failed: %d\n", ret);
6056	+ break;
6057	+ case RETU_IOCH_ADC_READ:
6058	+ return retu_read_adc(arg);
6059	+ default:
6060	+ return -ENOIOCTLCMD;
6061	+ }
6062	+ return 0;
6063	+}
6064	+
6065	+/*
6066	+ * Read from device
6067	+ */
6068	+static ssize_t retu_read(struct file filp, char buf, size_t count,
6069	+ loff_t * offp)
6070	+{
6071	+ struct retu_irq *irq;
6072	+
6073	+ u32 nr, i;
6074	+
6075	+ /* read not permitted if neither filp nor anyone has registered IRQs */
6076	+ if (retu_irq_subscr != filp)
6077	+ return -EPERM;
6078	+
6079	+ if ((count < sizeof(u32)) \|\| ((count % sizeof(u32)) != 0))
6080	+ return -EINVAL;
6081	+
6082	+ nr = count / sizeof(u32);
6083	+
6084	+ for (i = 0; i < nr; i++) {
6085	+ unsigned long flags;
6086	+ u32 irq_id;
6087	+ int ret;
6088	+
6089	+ ret = wait_event_interruptible(retu_user_waitqueue,
6090	+ !list_empty(&retu_irqs));
6091	+ if (ret < 0)
6092	+ return ret;
6093	+
6094	+ spin_lock_irqsave(&retu_irqs_lock, flags);
6095	+ irq = list_entry((&retu_irqs)->next, struct retu_irq, node);
6096	+ irq_id = irq->id;
6097	+ list_move(&irq->node, &retu_irqs_reserve);
6098	+ spin_unlock_irqrestore(&retu_irqs_lock, flags);
6099	+
6100	+ ret = copy_to_user(buf + i * sizeof(irq_id), &irq_id,
6101	+ sizeof(irq_id));
6102	+ if (ret)
6103	+ printk(KERN_ERR "copy_to_user failed: %d\n", ret);
6104	+ }
6105	+
6106	+ return count;
6107	+}
6108	+
6109	+/*
6110	+ * Poll method
6111	+ */
6112	+static unsigned retu_poll(struct file filp, struct poll_table_struct pt)
6113	+{
6114	+ if (!list_empty(&retu_irqs))
6115	+ return POLLIN;
6116	+
6117	+ poll_wait(filp, &retu_user_waitqueue, pt);
6118	+
6119	+ if (!list_empty(&retu_irqs))
6120	+ return POLLIN;
6121	+ else
6122	+ return 0;
6123	+}
6124	+
6125	+static struct file_operations retu_user_fileops = {
6126	+ .owner = THIS_MODULE,
6127	+ .ioctl = retu_ioctl,
6128	+ .read = retu_read,
6129	+ .release = retu_close,
6130	+ .poll = retu_poll
6131	+};
6132	+
6133	+static struct miscdevice retu_device = {
6134	+ .minor = MISC_DYNAMIC_MINOR,
6135	+ .name = "retu",
6136	+ .fops = &retu_user_fileops
6137	+};
6138	+
6139	+/*
6140	+ * Initialization
6141	+ *
6142	+ * @return 0 if successful, error value otherwise.
6143	+ */
6144	+int retu_user_init(void)
6145	+{
6146	+ struct retu_irq *irq;
6147	+ int res, i;
6148	+
6149	+ irq = kmalloc(sizeof(irq) RETU_MAX_IRQ_BUF_LEN, GFP_KERNEL);
6150	+ if (irq == NULL) {
6151	+ printk(KERN_ERR PFX "kmalloc failed\n");
6152	+ return -ENOMEM;
6153	+ }
6154	+ memset(irq, 0, sizeof(irq) RETU_MAX_IRQ_BUF_LEN);
6155	+ for (i = 0; i < RETU_MAX_IRQ_BUF_LEN; i++)
6156	+ list_add(&irq[i].node, &retu_irqs_reserve);
6157	+
6158	+ retu_irq_block = irq;
6159	+
6160	+ spin_lock_init(&retu_irqs_lock);
6161	+ mutex_init(&retu_mutex);
6162	+
6163	+ /* Request a misc device */
6164	+ res = misc_register(&retu_device);
6165	+ if (res < 0) {
6166	+ printk(KERN_ERR PFX "unable to register misc device for %s\n",
6167	+ retu_device.name);
6168	+ kfree(irq);
6169	+ return res;
6170	+ }
6171	+
6172	+ return 0;
6173	+}
6174	+
6175	+/*
6176	+ * Cleanup.
6177	+ */
6178	+void retu_user_cleanup(void)
6179	+{
6180	+ /* Unregister our misc device */
6181	+ misc_deregister(&retu_device);
6182	+ /* Unregister and disable all RETU interrupts used by this module */
6183	+ retu_unreg_irq_handlers();
6184	+ kfree(retu_irq_block);
6185	+}
6186	+
6187	+MODULE_DESCRIPTION("Retu ASIC user space functions");
6188	+MODULE_LICENSE("GPL");
6189	+MODULE_AUTHOR("Mikko Ylinen");
6190	--- /dev/null
6191	+++ b/drivers/cbus/retu-wdt.c
6192	@@ -0,0 +1,202 @@
6193	+/**
6194	+ * drivers/cbus/retu-wdt.c
6195	+ *
6196	+ * Driver for Retu watchdog
6197	+ *
6198	+ * Copyright (C) 2004, 2005 Nokia Corporation
6199	+ *
6200	+ * Written by Amit Kucheria <amit.kucheria@nokia.com>
6201	+ *
6202	+ * This file is subject to the terms and conditions of the GNU General
6203	+ * Public License. See the file "COPYING" in the main directory of this
6204	+ * archive for more details.
6205	+ *
6206	+ * This program is distributed in the hope that it will be useful,
6207	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
6208	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6209	+ * GNU General Public License for more details.
6210	+ *
6211	+ * You should have received a copy of the GNU General Public License
6212	+ * along with this program; if not, write to the Free Software
6213	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6214	+ */
6215	+
6216	+#include <linux/kernel.h>
6217	+#include <linux/module.h>
6218	+#include <linux/device.h>
6219	+#include <linux/init.h>
6220	+
6221	+#include <linux/completion.h>
6222	+#include <linux/errno.h>
6223	+#include <linux/moduleparam.h>
6224	+#include <linux/platform_device.h>
6225	+
6226	+#include "cbus.h"
6227	+#include "retu.h"
6228	+
6229	+/* Watchdog timeout in seconds */
6230	+#define RETU_WDT_MIN_TIMER 0
6231	+#define RETU_WDT_DEFAULT_TIMER 32
6232	+#define RETU_WDT_MAX_TIMER 63
6233	+
6234	+static struct completion retu_wdt_completion;
6235	+static DEFINE_MUTEX(retu_wdt_mutex);
6236	+
6237	+/* Current period of watchdog */
6238	+static unsigned int period_val = RETU_WDT_DEFAULT_TIMER;
6239	+static int counter_param = RETU_WDT_MAX_TIMER;
6240	+
6241	+static int retu_modify_counter(unsigned int new)
6242	+{
6243	+ int ret = 0;
6244	+
6245	+ if (new < RETU_WDT_MIN_TIMER \|\| new > RETU_WDT_MAX_TIMER)
6246	+ return -EINVAL;
6247	+
6248	+ mutex_lock(&retu_wdt_mutex);
6249	+
6250	+ period_val = new;
6251	+ retu_write_reg(RETU_REG_WATCHDOG, (u16)period_val);
6252	+
6253	+ mutex_unlock(&retu_wdt_mutex);
6254	+ return ret;
6255	+}
6256	+
6257	+static ssize_t retu_wdt_period_show(struct device *dev,
6258	+ struct device_attribute attr, char buf)
6259	+{
6260	+ /* Show current max counter */
6261	+ return sprintf(buf, "%u\n", (u16)period_val);
6262	+}
6263	+
6264	+static ssize_t retu_wdt_period_store(struct device *dev,
6265	+ struct device_attribute *attr,
6266	+ const char *buf, size_t count)
6267	+{
6268	+ unsigned int new_period;
6269	+ int ret;
6270	+
6271	+ if (sscanf(buf, "%u", &new_period) != 1) {
6272	+ printk(KERN_ALERT "retu_wdt_period_store: Invalid input\n");
6273	+ return -EINVAL;
6274	+ }
6275	+
6276	+ ret = retu_modify_counter(new_period);
6277	+ if (ret < 0)
6278	+ return ret;
6279	+
6280	+ return strnlen(buf, count);
6281	+}
6282	+
6283	+static ssize_t retu_wdt_counter_show(struct device *dev,
6284	+ struct device_attribute attr, char buf)
6285	+{
6286	+ u16 counter;
6287	+
6288	+ /* Show current value in watchdog counter */
6289	+ counter = retu_read_reg(RETU_REG_WATCHDOG);
6290	+
6291	+ /* Only the 5 LSB are important */
6292	+ return snprintf(buf, PAGE_SIZE, "%u\n", (counter & 0x3F));
6293	+}
6294	+
6295	+static DEVICE_ATTR(period, S_IRUGO \| S_IWUSR, retu_wdt_period_show, \
6296	+ retu_wdt_period_store);
6297	+static DEVICE_ATTR(counter, S_IRUGO, retu_wdt_counter_show, NULL);
6298	+
6299	+static int __devinit retu_wdt_probe(struct device *dev)
6300	+{
6301	+ int ret;
6302	+
6303	+ ret = device_create_file(dev, &dev_attr_period);
6304	+ if (ret) {
6305	+ printk(KERN_ERR "retu_wdt_probe: Error creating "
6306	+ "sys device file: period\n");
6307	+ return ret;
6308	+ }
6309	+
6310	+ ret = device_create_file(dev, &dev_attr_counter);
6311	+ if (ret) {
6312	+ device_remove_file(dev, &dev_attr_period);
6313	+ printk(KERN_ERR "retu_wdt_probe: Error creating "
6314	+ "sys device file: counter\n");
6315	+ }
6316	+
6317	+ return ret;
6318	+}
6319	+
6320	+static int __devexit retu_wdt_remove(struct device *dev)
6321	+{
6322	+ device_remove_file(dev, &dev_attr_period);
6323	+ device_remove_file(dev, &dev_attr_counter);
6324	+ return 0;
6325	+}
6326	+
6327	+static void retu_wdt_device_release(struct device *dev)
6328	+{
6329	+ complete(&retu_wdt_completion);
6330	+}
6331	+
6332	+static struct platform_device retu_wdt_device = {
6333	+ .name = "retu-watchdog",
6334	+ .id = -1,
6335	+ .dev = {
6336	+ .release = retu_wdt_device_release,
6337	+ },
6338	+};
6339	+
6340	+static struct device_driver retu_wdt_driver = {
6341	+ .name = "retu-watchdog",
6342	+ .bus = &platform_bus_type,
6343	+ .probe = retu_wdt_probe,
6344	+ .remove = __devexit_p(retu_wdt_remove),
6345	+};
6346	+
6347	+static int __init retu_wdt_init(void)
6348	+{
6349	+ int ret;
6350	+
6351	+ init_completion(&retu_wdt_completion);
6352	+
6353	+ ret = driver_register(&retu_wdt_driver);
6354	+ if (ret)
6355	+ return ret;
6356	+
6357	+ ret = platform_device_register(&retu_wdt_device);
6358	+ if (ret)
6359	+ goto exit1;
6360	+
6361	+ /* passed as module parameter? */
6362	+ ret = retu_modify_counter(counter_param);
6363	+ if (ret == -EINVAL) {
6364	+ ret = retu_modify_counter(RETU_WDT_DEFAULT_TIMER);
6365	+ printk(KERN_INFO
6366	+ "retu_wdt_init: Intializing to default value\n");
6367	+ }
6368	+
6369	+ printk(KERN_INFO "Retu watchdog driver initialized\n");
6370	+ return ret;
6371	+
6372	+exit1:
6373	+ driver_unregister(&retu_wdt_driver);
6374	+ wait_for_completion(&retu_wdt_completion);
6375	+
6376	+ return ret;
6377	+}
6378	+
6379	+static void __exit retu_wdt_exit(void)
6380	+{
6381	+ platform_device_unregister(&retu_wdt_device);
6382	+ driver_unregister(&retu_wdt_driver);
6383	+
6384	+ wait_for_completion(&retu_wdt_completion);
6385	+}
6386	+
6387	+module_init(retu_wdt_init);
6388	+module_exit(retu_wdt_exit);
6389	+module_param(counter_param, int, 0);
6390	+
6391	+MODULE_DESCRIPTION("Retu WatchDog");
6392	+MODULE_AUTHOR("Amit Kucheria");
6393	+MODULE_LICENSE("GPL");
6394	+
6395	--- /dev/null
6396	+++ b/drivers/cbus/retu.c
6397	@@ -0,0 +1,467 @@
6398	+/**
6399	+ * drivers/cbus/retu.c
6400	+ *
6401	+ * Support functions for Retu ASIC
6402	+ *
6403	+ * Copyright (C) 2004, 2005 Nokia Corporation
6404	+ *
6405	+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com>,
6406	+ * David Weinehall <david.weinehall@nokia.com>, and
6407	+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
6408	+ *
6409	+ * This file is subject to the terms and conditions of the GNU General
6410	+ * Public License. See the file "COPYING" in the main directory of this
6411	+ * archive for more details.
6412	+ *
6413	+ * This program is distributed in the hope that it will be useful,
6414	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
6415	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6416	+ * GNU General Public License for more details.
6417	+ *
6418	+ * You should have received a copy of the GNU General Public License
6419	+ * along with this program; if not, write to the Free Software
6420	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6421	+ */
6422	+
6423	+#include <linux/module.h>
6424	+#include <linux/init.h>
6425	+
6426	+#include <linux/kernel.h>
6427	+#include <linux/errno.h>
6428	+#include <linux/device.h>
6429	+#include <linux/miscdevice.h>
6430	+#include <linux/poll.h>
6431	+#include <linux/fs.h>
6432	+#include <linux/irq.h>
6433	+#include <linux/interrupt.h>
6434	+#include <linux/platform_device.h>
6435	+#include <linux/gpio.h>
6436	+
6437	+#include <asm/uaccess.h>
6438	+
6439	+#include <mach/mux.h>
6440	+#include <mach/board.h>
6441	+#include <mach/board-nokia.h>
6442	+
6443	+#include "cbus.h"
6444	+#include "retu.h"
6445	+
6446	+#define RETU_ID 0x01
6447	+#define PFX "retu: "
6448	+
6449	+static int retu_initialized;
6450	+static int retu_irq_pin;
6451	+static int retu_is_vilma;
6452	+
6453	+static struct tasklet_struct retu_tasklet;
6454	+spinlock_t retu_lock = SPIN_LOCK_UNLOCKED;
6455	+
6456	+static struct completion device_release;
6457	+
6458	+struct retu_irq_handler_desc {
6459	+ int (*func)(unsigned long);
6460	+ unsigned long arg;
6461	+ char name[8];
6462	+};
6463	+
6464	+static struct retu_irq_handler_desc retu_irq_handlers[MAX_RETU_IRQ_HANDLERS];
6465	+
6466	+/**
6467	+ * retu_read_reg - Read a value from a register in Retu
6468	+ * @reg: the register to read from
6469	+ *
6470	+ * This function returns the contents of the specified register
6471	+ */
6472	+int retu_read_reg(int reg)
6473	+{
6474	+ BUG_ON(!retu_initialized);
6475	+ return cbus_read_reg(cbus_host, RETU_ID, reg);
6476	+}
6477	+
6478	+/**
6479	+ * retu_write_reg - Write a value to a register in Retu
6480	+ * @reg: the register to write to
6481	+ * @reg: the value to write to the register
6482	+ *
6483	+ * This function writes a value to the specified register
6484	+ */
6485	+void retu_write_reg(int reg, u16 val)
6486	+{
6487	+ BUG_ON(!retu_initialized);
6488	+ cbus_write_reg(cbus_host, RETU_ID, reg, val);
6489	+}
6490	+
6491	+void retu_set_clear_reg_bits(int reg, u16 set, u16 clear)
6492	+{
6493	+ unsigned long flags;
6494	+ u16 w;
6495	+
6496	+ spin_lock_irqsave(&retu_lock, flags);
6497	+ w = retu_read_reg(reg);
6498	+ w &= ~clear;
6499	+ w \|= set;
6500	+ retu_write_reg(reg, w);
6501	+ spin_unlock_irqrestore(&retu_lock, flags);
6502	+}
6503	+
6504	+#define ADC_MAX_CHAN_NUMBER 13
6505	+
6506	+int retu_read_adc(int channel)
6507	+{
6508	+ unsigned long flags;
6509	+ int res;
6510	+
6511	+ if (channel < 0 \|\| channel > ADC_MAX_CHAN_NUMBER)
6512	+ return -EINVAL;
6513	+
6514	+ spin_lock_irqsave(&retu_lock, flags);
6515	+
6516	+ if ((channel == 8) && retu_is_vilma) {
6517	+ int scr = retu_read_reg(RETU_REG_ADCSCR);
6518	+ int ch = (retu_read_reg(RETU_REG_ADCR) >> 10) & 0xf;
6519	+ if (((scr & 0xff) != 0) && (ch != 8))
6520	+ retu_write_reg (RETU_REG_ADCSCR, (scr & ~0xff));
6521	+ }
6522	+
6523	+ /* Select the channel and read result */
6524	+ retu_write_reg(RETU_REG_ADCR, channel << 10);
6525	+ res = retu_read_reg(RETU_REG_ADCR) & 0x3ff;
6526	+
6527	+ if (retu_is_vilma)
6528	+ retu_write_reg(RETU_REG_ADCR, (1 << 13));
6529	+
6530	+ /* Unlock retu */
6531	+ spin_unlock_irqrestore(&retu_lock, flags);
6532	+
6533	+ return res;
6534	+}
6535	+
6536	+
6537	+static u16 retu_disable_bogus_irqs(u16 mask)
6538	+{
6539	+ int i;
6540	+
6541	+ for (i = 0; i < MAX_RETU_IRQ_HANDLERS; i++) {
6542	+ if (mask & (1 << i))
6543	+ continue;
6544	+ if (retu_irq_handlers[i].func != NULL)
6545	+ continue;
6546	+ /* an IRQ was enabled but we don't have a handler for it */
6547	+ printk(KERN_INFO PFX "disabling bogus IRQ %d\n", i);
6548	+ mask \|= (1 << i);
6549	+ }
6550	+ return mask;
6551	+}
6552	+
6553	+/*
6554	+ * Disable given RETU interrupt
6555	+ */
6556	+void retu_disable_irq(int id)
6557	+{
6558	+ unsigned long flags;
6559	+ u16 mask;
6560	+
6561	+ spin_lock_irqsave(&retu_lock, flags);
6562	+ mask = retu_read_reg(RETU_REG_IMR);
6563	+ mask \|= 1 << id;
6564	+ mask = retu_disable_bogus_irqs(mask);
6565	+ retu_write_reg(RETU_REG_IMR, mask);
6566	+ spin_unlock_irqrestore(&retu_lock, flags);
6567	+}
6568	+
6569	+/*
6570	+ * Enable given RETU interrupt
6571	+ */
6572	+void retu_enable_irq(int id)
6573	+{
6574	+ unsigned long flags;
6575	+ u16 mask;
6576	+
6577	+ if (id == 3) {
6578	+ printk("Enabling Retu IRQ %d\n", id);
6579	+ dump_stack();
6580	+ }
6581	+ spin_lock_irqsave(&retu_lock, flags);
6582	+ mask = retu_read_reg(RETU_REG_IMR);
6583	+ mask &= ~(1 << id);
6584	+ mask = retu_disable_bogus_irqs(mask);
6585	+ retu_write_reg(RETU_REG_IMR, mask);
6586	+ spin_unlock_irqrestore(&retu_lock, flags);
6587	+}
6588	+
6589	+/*
6590	+ * Acknowledge given RETU interrupt
6591	+ */
6592	+void retu_ack_irq(int id)
6593	+{
6594	+ retu_write_reg(RETU_REG_IDR, 1 << id);
6595	+}
6596	+
6597	+/*
6598	+ * RETU interrupt handler. Only schedules the tasklet.
6599	+ */
6600	+static irqreturn_t retu_irq_handler(int irq, void *dev_id)
6601	+{
6602	+ tasklet_schedule(&retu_tasklet);
6603	+ return IRQ_HANDLED;
6604	+}
6605	+
6606	+/*
6607	+ * Tasklet handler
6608	+ */
6609	+static void retu_tasklet_handler(unsigned long data)
6610	+{
6611	+ struct retu_irq_handler_desc *hnd;
6612	+ u16 id;
6613	+ u16 im;
6614	+ int i;
6615	+
6616	+ for (;;) {
6617	+ id = retu_read_reg(RETU_REG_IDR);
6618	+ im = ~retu_read_reg(RETU_REG_IMR);
6619	+ id &= im;
6620	+
6621	+ if (!id)
6622	+ break;
6623	+
6624	+ for (i = 0; id != 0; i++, id >>= 1) {
6625	+ if (!(id & 1))
6626	+ continue;
6627	+ hnd = &retu_irq_handlers[i];
6628	+ if (hnd->func == NULL) {
6629	+ /* Spurious retu interrupt - disable and ack it */
6630	+ printk(KERN_INFO "Spurious Retu interrupt "
6631	+ "(id %d)\n", i);
6632	+ retu_disable_irq(i);
6633	+ retu_ack_irq(i);
6634	+ continue;
6635	+ }
6636	+ hnd->func(hnd->arg);
6637	+ /*
6638	+ * Don't acknowledge the interrupt here
6639	+ * It must be done explicitly
6640	+ */
6641	+ }
6642	+ }
6643	+}
6644	+
6645	+/*
6646	+ * Register the handler for a given RETU interrupt source.
6647	+ */
6648	+int retu_request_irq(int id, void irq_handler, unsigned long arg, char name)
6649	+{
6650	+ struct retu_irq_handler_desc *hnd;
6651	+
6652	+ if (irq_handler == NULL \|\| id >= MAX_RETU_IRQ_HANDLERS \|\|
6653	+ name == NULL) {
6654	+ printk(KERN_ERR PFX "Invalid arguments to %s\n",
6655	+ __FUNCTION__);
6656	+ return -EINVAL;
6657	+ }
6658	+ hnd = &retu_irq_handlers[id];
6659	+ if (hnd->func != NULL) {
6660	+ printk(KERN_ERR PFX "IRQ %d already reserved\n", id);
6661	+ return -EBUSY;
6662	+ }
6663	+ printk(KERN_INFO PFX "Registering interrupt %d for device %s\n",
6664	+ id, name);
6665	+ hnd->func = irq_handler;
6666	+ hnd->arg = arg;
6667	+ strlcpy(hnd->name, name, sizeof(hnd->name));
6668	+
6669	+ retu_ack_irq(id);
6670	+ retu_enable_irq(id);
6671	+
6672	+ return 0;
6673	+}
6674	+
6675	+/*
6676	+ * Unregister the handler for a given RETU interrupt source.
6677	+ */
6678	+void retu_free_irq(int id)
6679	+{
6680	+ struct retu_irq_handler_desc *hnd;
6681	+
6682	+ if (id >= MAX_RETU_IRQ_HANDLERS) {
6683	+ printk(KERN_ERR PFX "Invalid argument to %s\n",
6684	+ __FUNCTION__);
6685	+ return;
6686	+ }
6687	+ hnd = &retu_irq_handlers[id];
6688	+ if (hnd->func == NULL) {
6689	+ printk(KERN_ERR PFX "IRQ %d already freed\n", id);
6690	+ return;
6691	+ }
6692	+
6693	+ retu_disable_irq(id);
6694	+ hnd->func = NULL;
6695	+}
6696	+
6697	+/**
6698	+ * retu_power_off - Shut down power to system
6699	+ *
6700	+ * This function puts the system in power off state
6701	+ */
6702	+static void retu_power_off(void)
6703	+{
6704	+ /* Ignore power button state */
6705	+ retu_write_reg(RETU_REG_CC1, retu_read_reg(RETU_REG_CC1) \| 2);
6706	+ /* Expire watchdog immediately */
6707	+ retu_write_reg(RETU_REG_WATCHDOG, 0);
6708	+ /* Wait for poweroff*/
6709	+ for (;;);
6710	+}
6711	+
6712	+/**
6713	+ * retu_probe - Probe for Retu ASIC
6714	+ * @dev: the Retu device
6715	+ *
6716	+ * Probe for the Retu ASIC and allocate memory
6717	+ * for its device-struct if found
6718	+ */
6719	+static int __devinit retu_probe(struct device *dev)
6720	+{
6721	+ const struct omap_em_asic_bb5_config * em_asic_config;
6722	+ int rev, ret;
6723	+
6724	+ /* Prepare tasklet */
6725	+ tasklet_init(&retu_tasklet, retu_tasklet_handler, 0);
6726	+
6727	+ em_asic_config = omap_get_config(OMAP_TAG_EM_ASIC_BB5,
6728	+ struct omap_em_asic_bb5_config);
6729	+ if (em_asic_config == NULL) {
6730	+ printk(KERN_ERR PFX "Unable to retrieve config data\n");
6731	+ return -ENODATA;
6732	+ }
6733	+
6734	+ retu_irq_pin = em_asic_config->retu_irq_gpio;
6735	+
6736	+ if ((ret = gpio_request(retu_irq_pin, "RETU irq")) < 0) {
6737	+ printk(KERN_ERR PFX "Unable to reserve IRQ GPIO\n");
6738	+ return ret;
6739	+ }
6740	+
6741	+ /* Set the pin as input */
6742	+ gpio_direction_input(retu_irq_pin);
6743	+
6744	+ /* Rising edge triggers the IRQ */
6745	+ set_irq_type(gpio_to_irq(retu_irq_pin), IRQ_TYPE_EDGE_RISING);
6746	+
6747	+ retu_initialized = 1;
6748	+
6749	+ rev = retu_read_reg(RETU_REG_ASICR) & 0xff;
6750	+ if (rev & (1 << 7))
6751	+ retu_is_vilma = 1;
6752	+
6753	+ printk(KERN_INFO "%s v%d.%d found\n", retu_is_vilma ? "Vilma" : "Retu",
6754	+ (rev >> 4) & 0x07, rev & 0x0f);
6755	+
6756	+ /* Mask all RETU interrupts */
6757	+ retu_write_reg(RETU_REG_IMR, 0xffff);
6758	+
6759	+ ret = request_irq(gpio_to_irq(retu_irq_pin), retu_irq_handler, 0,
6760	+ "retu", 0);
6761	+ if (ret < 0) {
6762	+ printk(KERN_ERR PFX "Unable to register IRQ handler\n");
6763	+ gpio_free(retu_irq_pin);
6764	+ return ret;
6765	+ }
6766	+ set_irq_wake(gpio_to_irq(retu_irq_pin), 1);
6767	+
6768	+ /* Register power off function */
6769	+ pm_power_off = retu_power_off;
6770	+
6771	+#ifdef CONFIG_CBUS_RETU_USER
6772	+ /* Initialize user-space interface */
6773	+ if (retu_user_init() < 0) {
6774	+ printk(KERN_ERR "Unable to initialize driver\n");
6775	+ free_irq(gpio_to_irq(retu_irq_pin), 0);
6776	+ gpio_free(retu_irq_pin);
6777	+ return ret;
6778	+ }
6779	+#endif
6780	+
6781	+ return 0;
6782	+}
6783	+
6784	+static int retu_remove(struct device *dev)
6785	+{
6786	+#ifdef CONFIG_CBUS_RETU_USER
6787	+ retu_user_cleanup();
6788	+#endif
6789	+ /* Mask all RETU interrupts */
6790	+ retu_write_reg(RETU_REG_IMR, 0xffff);
6791	+ free_irq(gpio_to_irq(retu_irq_pin), 0);
6792	+ gpio_free(retu_irq_pin);
6793	+ tasklet_kill(&retu_tasklet);
6794	+
6795	+ return 0;
6796	+}
6797	+
6798	+static void retu_device_release(struct device *dev)
6799	+{
6800	+ complete(&device_release);
6801	+}
6802	+
6803	+static struct device_driver retu_driver = {
6804	+ .name = "retu",
6805	+ .bus = &platform_bus_type,
6806	+ .probe = retu_probe,
6807	+ .remove = retu_remove,
6808	+};
6809	+
6810	+static struct platform_device retu_device = {
6811	+ .name = "retu",
6812	+ .id = -1,
6813	+ .dev = {
6814	+ .release = retu_device_release,
6815	+ }
6816	+};
6817	+
6818	+/**
6819	+ * retu_init - initialise Retu driver
6820	+ *
6821	+ * Initialise the Retu driver and return 0 if everything worked ok
6822	+ */
6823	+static int __init retu_init(void)
6824	+{
6825	+ int ret = 0;
6826	+
6827	+ printk(KERN_INFO "Retu/Vilma driver initialising\n");
6828	+
6829	+ init_completion(&device_release);
6830	+
6831	+ if ((ret = driver_register(&retu_driver)) < 0)
6832	+ return ret;
6833	+
6834	+ if ((ret = platform_device_register(&retu_device)) < 0) {
6835	+ driver_unregister(&retu_driver);
6836	+ return ret;
6837	+ }
6838	+ return 0;
6839	+}
6840	+
6841	+/*
6842	+ * Cleanup
6843	+ */
6844	+static void __exit retu_exit(void)
6845	+{
6846	+ platform_device_unregister(&retu_device);
6847	+ driver_unregister(&retu_driver);
6848	+ wait_for_completion(&device_release);
6849	+}
6850	+
6851	+EXPORT_SYMBOL(retu_request_irq);
6852	+EXPORT_SYMBOL(retu_free_irq);
6853	+EXPORT_SYMBOL(retu_enable_irq);
6854	+EXPORT_SYMBOL(retu_disable_irq);
6855	+EXPORT_SYMBOL(retu_ack_irq);
6856	+EXPORT_SYMBOL(retu_read_reg);
6857	+EXPORT_SYMBOL(retu_write_reg);
6858	+
6859	+subsys_initcall(retu_init);
6860	+module_exit(retu_exit);
6861	+
6862	+MODULE_DESCRIPTION("Retu ASIC control");
6863	+MODULE_LICENSE("GPL");
6864	+MODULE_AUTHOR("Juha Yrj�l�, David Weinehall, and Mikko Ylinen");
6865	--- /dev/null
6866	+++ b/drivers/cbus/retu.h
6867	@@ -0,0 +1,77 @@
6868	+/**
6869	+ * drivers/cbus/retu.h
6870	+ *
6871	+ * Copyright (C) 2004, 2005 Nokia Corporation
6872	+ *
6873	+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com> and
6874	+ * David Weinehall <david.weinehall@nokia.com>
6875	+ *
6876	+ * This file is subject to the terms and conditions of the GNU General
6877	+ * Public License. See the file "COPYING" in the main directory of this
6878	+ * archive for more details.
6879	+ *
6880	+ * This program is distributed in the hope that it will be useful,
6881	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
6882	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6883	+ * GNU General Public License for more details.
6884	+
6885	+ * You should have received a copy of the GNU General Public License
6886	+ * along with this program; if not, write to the Free Software
6887	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6888	+ */
6889	+
6890	+#ifndef __DRIVERS_CBUS_RETU_H
6891	+#define __DRIVERS_CBUS_RETU_H
6892	+
6893	+#include <linux/types.h>
6894	+
6895	+/* Registers */
6896	+#define RETU_REG_ASICR 0x00 /* ASIC ID & revision */
6897	+#define RETU_REG_IDR 0x01 /* Interrupt ID */
6898	+#define RETU_REG_IMR 0x02 /* Interrupt mask */
6899	+#define RETU_REG_RTCDSR 0x03 /* RTC seconds register */
6900	+#define RETU_REG_RTCHMR 0x04 /* RTC hours and minutes register */
6901	+#define RETU_REG_RTCHMAR 0x05 /* RTC hours and minutes alarm and time set register */
6902	+#define RETU_REG_RTCCALR 0x06 /* RTC calibration register */
6903	+#define RETU_REG_ADCR 0x08 /* ADC result */
6904	+#define RETU_REG_ADCSCR 0x09 /* ADC sample ctrl */
6905	+#define RETU_REG_CC1 0x0d /* Common control register 1 */
6906	+#define RETU_REG_CC2 0x0e /* Common control register 2 */
6907	+#define RETU_REG_CTRL_CLR 0x0f /* Regulator clear register */
6908	+#define RETU_REG_CTRL_SET 0x10 /* Regulator set register */
6909	+#define RETU_REG_STATUS 0x16 /* Status register */
6910	+#define RETU_REG_WATCHDOG 0x17 /* Watchdog register */
6911	+#define RETU_REG_AUDTXR 0x18 /* Audio Codec Tx register */
6912	+#define RETU_REG_MAX 0x1f
6913	+
6914	+/* Interrupt sources */
6915	+#define RETU_INT_PWR 0
6916	+#define RETU_INT_CHAR 1
6917	+#define RETU_INT_RTCS 2
6918	+#define RETU_INT_RTCM 3
6919	+#define RETU_INT_RTCD 4
6920	+#define RETU_INT_RTCA 5
6921	+#define RETU_INT_HOOK 6
6922	+#define RETU_INT_HEAD 7
6923	+#define RETU_INT_ADCS 8
6924	+
6925	+#define MAX_RETU_IRQ_HANDLERS 16
6926	+
6927	+int retu_read_reg(int reg);
6928	+void retu_write_reg(int reg, u16 val);
6929	+void retu_set_clear_reg_bits(int reg, u16 set, u16 clear);
6930	+int retu_read_adc(int channel);
6931	+int retu_request_irq(int id, void irq_handler, unsigned long arg, char name);
6932	+void retu_free_irq(int id);
6933	+void retu_enable_irq(int id);
6934	+void retu_disable_irq(int id);
6935	+void retu_ack_irq(int id);
6936	+
6937	+#ifdef CONFIG_CBUS_RETU_USER
6938	+int retu_user_init(void);
6939	+void retu_user_cleanup(void);
6940	+#endif
6941	+
6942	+extern spinlock_t retu_lock;
6943	+
6944	+#endif /* __DRIVERS_CBUS_RETU_H */
6945	--- /dev/null
6946	+++ b/drivers/cbus/tahvo-usb.c
6947	@@ -0,0 +1,777 @@
6948	+/**
6949	+ * drivers/cbus/tahvo-usb.c
6950	+ *
6951	+ * Tahvo USB transeiver
6952	+ *
6953	+ * Copyright (C) 2005-2006 Nokia Corporation
6954	+ *
6955	+ * Parts copied from drivers/i2c/chips/isp1301_omap.c
6956	+ * Copyright (C) 2004 Texas Instruments
6957	+ * Copyright (C) 2004 David Brownell
6958	+ *
6959	+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com>,
6960	+ * Tony Lindgren <tony@atomide.com>, and
6961	+ * Timo Ter�s <timo.teras@nokia.com>
6962	+ *
6963	+ * This file is subject to the terms and conditions of the GNU General
6964	+ * Public License. See the file "COPYING" in the main directory of this
6965	+ * archive for more details.
6966	+ *
6967	+ * This program is distributed in the hope that it will be useful,
6968	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
6969	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6970	+ * GNU General Public License for more details.
6971	+ *
6972	+ * You should have received a copy of the GNU General Public License
6973	+ * along with this program; if not, write to the Free Software
6974	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6975	+ */
6976	+
6977	+#include <linux/kernel.h>
6978	+#include <linux/module.h>
6979	+#include <linux/init.h>
6980	+#include <linux/slab.h>
6981	+#include <linux/io.h>
6982	+#include <linux/interrupt.h>
6983	+#include <linux/platform_device.h>
6984	+#include <linux/usb/ch9.h>
6985	+#include <linux/usb/gadget.h>
6986	+#include <linux/usb.h>
6987	+#include <linux/usb/otg.h>
6988	+#include <linux/i2c.h>
6989	+#include <linux/workqueue.h>
6990	+#include <linux/kobject.h>
6991	+#include <linux/clk.h>
6992	+#include <linux/mutex.h>
6993	+
6994	+#include <asm/irq.h>
6995	+#include <mach/usb.h>
6996	+
6997	+#include "cbus.h"
6998	+#include "tahvo.h"
6999	+
7000	+#define DRIVER_NAME "tahvo-usb"
7001	+
7002	+#define USBR_SLAVE_CONTROL (1 << 8)
7003	+#define USBR_VPPVIO_SW (1 << 7)
7004	+#define USBR_SPEED (1 << 6)
7005	+#define USBR_REGOUT (1 << 5)
7006	+#define USBR_MASTER_SW2 (1 << 4)
7007	+#define USBR_MASTER_SW1 (1 << 3)
7008	+#define USBR_SLAVE_SW (1 << 2)
7009	+#define USBR_NSUSPEND (1 << 1)
7010	+#define USBR_SEMODE (1 << 0)
7011	+
7012	+/* bits in OTG_CTRL */
7013	+
7014	+/* Bits that are controlled by OMAP OTG and are read-only */
7015	+#define OTG_CTRL_OMAP_MASK (OTG_PULLDOWN\|OTG_PULLUP\|OTG_DRV_VBUS\|\
7016	+ OTG_PD_VBUS\|OTG_PU_VBUS\|OTG_PU_ID)
7017	+/* Bits that are controlled by transceiver */
7018	+#define OTG_CTRL_XCVR_MASK (OTG_ASESSVLD\|OTG_BSESSEND\|\
7019	+ OTG_BSESSVLD\|OTG_VBUSVLD\|OTG_ID)
7020	+/* Bits that are controlled by system */
7021	+#define OTG_CTRL_SYS_MASK (OTG_A_BUSREQ\|OTG_A_SETB_HNPEN\|OTG_B_BUSREQ\|\
7022	+ OTG_B_HNPEN\|OTG_BUSDROP)
7023	+
7024	+#if defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OTG)
7025	+#error tahvo-otg.c does not work with OCHI yet!
7026	+#endif
7027	+
7028	+#define TAHVO_MODE_HOST 0
7029	+#define TAHVO_MODE_PERIPHERAL 1
7030	+
7031	+#ifdef CONFIG_USB_OTG
7032	+#define TAHVO_MODE(tu) (tu)->tahvo_mode
7033	+#elif defined(CONFIG_USB_GADGET_OMAP)
7034	+#define TAHVO_MODE(tu) TAHVO_MODE_PERIPHERAL
7035	+#else
7036	+#define TAHVO_MODE(tu) TAHVO_MODE_HOST
7037	+#endif
7038	+
7039	+struct tahvo_usb {
7040	+ struct platform_device *pt_dev;
7041	+ struct otg_transceiver otg;
7042	+ int vbus_state;
7043	+ struct work_struct irq_work;
7044	+ struct mutex serialize;
7045	+#ifdef CONFIG_USB_OTG
7046	+ int tahvo_mode;
7047	+#endif
7048	+};
7049	+static struct platform_device tahvo_usb_device;
7050	+
7051	+/*
7052	+ * ---------------------------------------------------------------------------
7053	+ * OTG related functions
7054	+ *
7055	+ * These shoud be separated into omap-otg.c driver module, as they are used
7056	+ * by various transceivers. These functions are needed in the UDC-only case
7057	+ * as well. These functions are copied from GPL isp1301_omap.c
7058	+ * ---------------------------------------------------------------------------
7059	+ */
7060	+static struct platform_device *tahvo_otg_dev;
7061	+
7062	+static irqreturn_t omap_otg_irq(int irq, void *arg)
7063	+{
7064	+ struct platform_device otg_dev = (struct platform_device ) arg;
7065	+ struct tahvo_usb tu = (struct tahvo_usb ) otg_dev->dev.driver_data;
7066	+ u16 otg_irq;
7067	+
7068	+ otg_irq = omap_readw(OTG_IRQ_SRC);
7069	+ if (otg_irq & OPRT_CHG) {
7070	+ omap_writew(OPRT_CHG, OTG_IRQ_SRC);
7071	+ } else if (otg_irq & B_SRP_TMROUT) {
7072	+ omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
7073	+ } else if (otg_irq & B_HNP_FAIL) {
7074	+ omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
7075	+ } else if (otg_irq & A_SRP_DETECT) {
7076	+ omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
7077	+ } else if (otg_irq & A_REQ_TMROUT) {
7078	+ omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
7079	+ } else if (otg_irq & A_VBUS_ERR) {
7080	+ omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
7081	+ } else if (otg_irq & DRIVER_SWITCH) {
7082	+ if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) &&
7083	+ tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) {
7084	+ /* role is host */
7085	+ usb_bus_start_enum(tu->otg.host,
7086	+ tu->otg.host->otg_port);
7087	+ }
7088	+ omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
7089	+ } else
7090	+ return IRQ_NONE;
7091	+
7092	+ return IRQ_HANDLED;
7093	+
7094	+}
7095	+
7096	+static int omap_otg_init(void)
7097	+{
7098	+ u32 l;
7099	+
7100	+#ifdef CONFIG_USB_OTG
7101	+ if (!tahvo_otg_dev) {
7102	+ printk("tahvo-usb: no tahvo_otg_dev\n");
7103	+ return -ENODEV;
7104	+ }
7105	+#endif
7106	+
7107	+ l = omap_readl(OTG_SYSCON_1);
7108	+ l &= ~OTG_IDLE_EN;
7109	+ omap_writel(l, OTG_SYSCON_1);
7110	+ udelay(100);
7111	+
7112	+ /* some of these values are board-specific... */
7113	+ l = omap_readl(OTG_SYSCON_2);
7114	+ l \|= OTG_EN
7115	+ /* for B-device: */
7116	+ \| SRP_GPDATA /* 9msec Bdev D+ pulse */
7117	+ \| SRP_GPDVBUS /* discharge after VBUS pulse */
7118	+ // \| (3 << 24) /* 2msec VBUS pulse */
7119	+ /* for A-device: */
7120	+ \| (0 << 20) /* 200ms nominal A_WAIT_VRISE timer */
7121	+ \| SRP_DPW /* detect 167+ns SRP pulses */
7122	+ \| SRP_DATA \| SRP_VBUS; /* accept both kinds of SRP pulse */
7123	+ omap_writel(l, OTG_SYSCON_2);
7124	+
7125	+ omap_writew(DRIVER_SWITCH \| OPRT_CHG
7126	+ \| B_SRP_TMROUT \| B_HNP_FAIL
7127	+ \| A_VBUS_ERR \| A_SRP_DETECT \| A_REQ_TMROUT,
7128	+ OTG_IRQ_EN);
7129	+ l = omap_readl(OTG_SYSCON_2);
7130	+ l \|= OTG_EN;
7131	+ omap_writel(l, OTG_SYSCON_2);
7132	+
7133	+ return 0;
7134	+}
7135	+
7136	+static int omap_otg_probe(struct device *dev)
7137	+{
7138	+ int ret;
7139	+
7140	+ tahvo_otg_dev = to_platform_device(dev);
7141	+ ret = omap_otg_init();
7142	+ if (ret != 0) {
7143	+ printk(KERN_ERR "tahvo-usb: omap_otg_init failed\n");
7144	+ return ret;
7145	+ }
7146	+
7147	+ return request_irq(tahvo_otg_dev->resource[1].start,
7148	+ omap_otg_irq, IRQF_DISABLED, DRIVER_NAME,
7149	+ &tahvo_usb_device);
7150	+}
7151	+
7152	+static int omap_otg_remove(struct device *dev)
7153	+{
7154	+ free_irq(tahvo_otg_dev->resource[1].start, &tahvo_usb_device);
7155	+ tahvo_otg_dev = NULL;
7156	+
7157	+ return 0;
7158	+}
7159	+
7160	+struct device_driver omap_otg_driver = {
7161	+ .name = "omap_otg",
7162	+ .bus = &platform_bus_type,
7163	+ .probe = omap_otg_probe,
7164	+ .remove = omap_otg_remove,
7165	+};
7166	+
7167	+/*
7168	+ * ---------------------------------------------------------------------------
7169	+ * Tahvo related functions
7170	+ * These are Nokia proprietary code, except for the OTG register settings,
7171	+ * which are copied from isp1301.c
7172	+ * ---------------------------------------------------------------------------
7173	+ */
7174	+static ssize_t vbus_state_show(struct device *device,
7175	+ struct device_attribute attr, char buf)
7176	+{
7177	+ struct tahvo_usb tu = (struct tahvo_usb) device->driver_data;
7178	+ return sprintf(buf, "%d\n", tu->vbus_state);
7179	+}
7180	+static DEVICE_ATTR(vbus_state, 0444, vbus_state_show, NULL);
7181	+
7182	+int vbus_active = 0;
7183	+
7184	+#if 0
7185	+
7186	+static int host_suspend(struct tahvo_usb *tu)
7187	+{
7188	+ struct device *dev;
7189	+
7190	+ if (!tu->otg.host)
7191	+ return -ENODEV;
7192	+
7193	+ /* Currently ASSUMES only the OTG port matters;
7194	+ * other ports could be active...
7195	+ */
7196	+ dev = tu->otg.host->controller;
7197	+ return dev->driver->suspend(dev, PMSG_SUSPEND);
7198	+}
7199	+
7200	+static int host_resume(struct tahvo_usb *tu)
7201	+{
7202	+ struct device *dev;
7203	+
7204	+ if (!tu->otg.host)
7205	+ return -ENODEV;
7206	+
7207	+ dev = tu->otg.host->controller;
7208	+ return dev->driver->resume(dev);
7209	+}
7210	+
7211	+#else
7212	+
7213	+static int host_suspend(struct tahvo_usb *tu)
7214	+{
7215	+ return 0;
7216	+}
7217	+
7218	+static int host_resume(struct tahvo_usb *tu)
7219	+{
7220	+ return 0;
7221	+}
7222	+
7223	+#endif
7224	+
7225	+static void check_vbus_state(struct tahvo_usb *tu)
7226	+{
7227	+ int reg, prev_state;
7228	+
7229	+ reg = tahvo_read_reg(TAHVO_REG_IDSR);
7230	+ if (reg & 0x01) {
7231	+ u32 l;
7232	+
7233	+ vbus_active = 1;
7234	+ switch (tu->otg.state) {
7235	+ case OTG_STATE_B_IDLE:
7236	+ /* Enable the gadget driver */
7237	+ if (tu->otg.gadget)
7238	+ usb_gadget_vbus_connect(tu->otg.gadget);
7239	+ /* Set B-session valid and not B-sessio ended to indicate
7240	+ * Vbus to be ok. */
7241	+ l = omap_readl(OTG_CTRL);
7242	+ l &= ~OTG_BSESSEND;
7243	+ l \|= OTG_BSESSVLD;
7244	+ omap_writel(l, OTG_CTRL);
7245	+
7246	+ tu->otg.state = OTG_STATE_B_PERIPHERAL;
7247	+ break;
7248	+ case OTG_STATE_A_IDLE:
7249	+ /* Session is now valid assuming the USB hub is driving Vbus */
7250	+ tu->otg.state = OTG_STATE_A_HOST;
7251	+ host_resume(tu);
7252	+ break;
7253	+ default:
7254	+ break;
7255	+ }
7256	+ printk("USB cable connected\n");
7257	+ } else {
7258	+ switch (tu->otg.state) {
7259	+ case OTG_STATE_B_PERIPHERAL:
7260	+ if (tu->otg.gadget)
7261	+ usb_gadget_vbus_disconnect(tu->otg.gadget);
7262	+ tu->otg.state = OTG_STATE_B_IDLE;
7263	+ break;
7264	+ case OTG_STATE_A_HOST:
7265	+ tu->otg.state = OTG_STATE_A_IDLE;
7266	+ break;
7267	+ default:
7268	+ break;
7269	+ }
7270	+ printk("USB cable disconnected\n");
7271	+ vbus_active = 0;
7272	+ }
7273	+
7274	+ prev_state = tu->vbus_state;
7275	+ tu->vbus_state = reg & 0x01;
7276	+ if (prev_state != tu->vbus_state)
7277	+ sysfs_notify(&tu->pt_dev->dev.kobj, NULL, "vbus_state");
7278	+}
7279	+
7280	+static void tahvo_usb_become_host(struct tahvo_usb *tu)
7281	+{
7282	+ u32 l;
7283	+
7284	+ /* Clear system and transceiver controlled bits
7285	+ * also mark the A-session is always valid */
7286	+ omap_otg_init();
7287	+
7288	+ l = omap_readl(OTG_CTRL);
7289	+ l &= ~(OTG_CTRL_XCVR_MASK \| OTG_CTRL_SYS_MASK);
7290	+ l \|= OTG_ASESSVLD;
7291	+ omap_writel(l, OTG_CTRL);
7292	+
7293	+ /* Power up the transceiver in USB host mode */
7294	+ tahvo_write_reg(TAHVO_REG_USBR, USBR_REGOUT \| USBR_NSUSPEND \|
7295	+ USBR_MASTER_SW2 \| USBR_MASTER_SW1);
7296	+ tu->otg.state = OTG_STATE_A_IDLE;
7297	+
7298	+ check_vbus_state(tu);
7299	+}
7300	+
7301	+static void tahvo_usb_stop_host(struct tahvo_usb *tu)
7302	+{
7303	+ host_suspend(tu);
7304	+ tu->otg.state = OTG_STATE_A_IDLE;
7305	+}
7306	+
7307	+static void tahvo_usb_become_peripheral(struct tahvo_usb *tu)
7308	+{
7309	+ u32 l;
7310	+
7311	+ /* Clear system and transceiver controlled bits
7312	+ * and enable ID to mark peripheral mode and
7313	+ * BSESSEND to mark no Vbus */
7314	+ omap_otg_init();
7315	+ l = omap_readl(OTG_CTRL);
7316	+ l &= ~(OTG_CTRL_XCVR_MASK \| OTG_CTRL_SYS_MASK \| OTG_BSESSVLD);
7317	+ l \|= OTG_ID \| OTG_BSESSEND;
7318	+ omap_writel(l, OTG_CTRL);
7319	+
7320	+ /* Power up transceiver and set it in USB perhiperal mode */
7321	+ tahvo_write_reg(TAHVO_REG_USBR, USBR_SLAVE_CONTROL \| USBR_REGOUT \| USBR_NSUSPEND \| USBR_SLAVE_SW);
7322	+ tu->otg.state = OTG_STATE_B_IDLE;
7323	+
7324	+ check_vbus_state(tu);
7325	+}
7326	+
7327	+static void tahvo_usb_stop_peripheral(struct tahvo_usb *tu)
7328	+{
7329	+ u32 l;
7330	+
7331	+ l = omap_readl(OTG_CTRL);
7332	+ l &= ~OTG_BSESSVLD;
7333	+ l \|= OTG_BSESSEND;
7334	+ omap_writel(l, OTG_CTRL);
7335	+
7336	+ if (tu->otg.gadget)
7337	+ usb_gadget_vbus_disconnect(tu->otg.gadget);
7338	+ tu->otg.state = OTG_STATE_B_IDLE;
7339	+
7340	+}
7341	+
7342	+static void tahvo_usb_power_off(struct tahvo_usb *tu)
7343	+{
7344	+ u32 l;
7345	+ int id;
7346	+
7347	+ /* Disable gadget controller if any */
7348	+ if (tu->otg.gadget)
7349	+ usb_gadget_vbus_disconnect(tu->otg.gadget);
7350	+
7351	+ host_suspend(tu);
7352	+
7353	+ /* Disable OTG and interrupts */
7354	+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
7355	+ id = OTG_ID;
7356	+ else
7357	+ id = 0;
7358	+ l = omap_readl(OTG_CTRL);
7359	+ l &= ~(OTG_CTRL_XCVR_MASK \| OTG_CTRL_SYS_MASK \| OTG_BSESSVLD);
7360	+ l \|= id \| OTG_BSESSEND;
7361	+ omap_writel(l, OTG_CTRL);
7362	+ omap_writew(0, OTG_IRQ_EN);
7363	+
7364	+ l = omap_readl(OTG_SYSCON_2);
7365	+ l &= ~OTG_EN;
7366	+ omap_writel(l, OTG_SYSCON_2);
7367	+
7368	+ l = omap_readl(OTG_SYSCON_1);
7369	+ l \|= OTG_IDLE_EN;
7370	+ omap_writel(l, OTG_SYSCON_1);
7371	+
7372	+ /* Power off transceiver */
7373	+ tahvo_write_reg(TAHVO_REG_USBR, 0);
7374	+ tu->otg.state = OTG_STATE_UNDEFINED;
7375	+}
7376	+
7377	+
7378	+static int tahvo_usb_set_power(struct otg_transceiver *dev, unsigned mA)
7379	+{
7380	+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
7381	+
7382	+ dev_dbg(&tu->pt_dev->dev, "set_power %d mA\n", mA);
7383	+
7384	+ if (dev->state == OTG_STATE_B_PERIPHERAL) {
7385	+ /* REVISIT: Can Tahvo charge battery from VBUS? */
7386	+ }
7387	+ return 0;
7388	+}
7389	+
7390	+static int tahvo_usb_set_suspend(struct otg_transceiver *dev, int suspend)
7391	+{
7392	+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
7393	+ u16 w;
7394	+
7395	+ dev_dbg(&tu->pt_dev->dev, "set_suspend\n");
7396	+
7397	+ w = tahvo_read_reg(TAHVO_REG_USBR);
7398	+ if (suspend)
7399	+ w &= ~USBR_NSUSPEND;
7400	+ else
7401	+ w \|= USBR_NSUSPEND;
7402	+ tahvo_write_reg(TAHVO_REG_USBR, w);
7403	+
7404	+ return 0;
7405	+}
7406	+
7407	+static int tahvo_usb_start_srp(struct otg_transceiver *dev)
7408	+{
7409	+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
7410	+ u32 otg_ctrl;
7411	+
7412	+ dev_dbg(&tu->pt_dev->dev, "start_srp\n");
7413	+
7414	+ if (!dev \|\| tu->otg.state != OTG_STATE_B_IDLE)
7415	+ return -ENODEV;
7416	+
7417	+ otg_ctrl = omap_readl(OTG_CTRL);
7418	+ if (!(otg_ctrl & OTG_BSESSEND))
7419	+ return -EINVAL;
7420	+
7421	+ otg_ctrl \|= OTG_B_BUSREQ;
7422	+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_SYS_MASK;
7423	+ omap_writel(otg_ctrl, OTG_CTRL);
7424	+ tu->otg.state = OTG_STATE_B_SRP_INIT;
7425	+
7426	+ return 0;
7427	+}
7428	+
7429	+static int tahvo_usb_start_hnp(struct otg_transceiver *otg)
7430	+{
7431	+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
7432	+
7433	+ dev_dbg(&tu->pt_dev->dev, "start_hnp\n");
7434	+#ifdef CONFIG_USB_OTG
7435	+ /* REVISIT: Add this for OTG */
7436	+#endif
7437	+ return -EINVAL;
7438	+}
7439	+
7440	+static int tahvo_usb_set_host(struct otg_transceiver otg, struct usb_bus host)
7441	+{
7442	+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
7443	+ u32 l;
7444	+
7445	+ dev_dbg(&tu->pt_dev->dev, "set_host %p\n", host);
7446	+
7447	+ if (otg == NULL)
7448	+ return -ENODEV;
7449	+
7450	+#if defined(CONFIG_USB_OTG) \|\| !defined(CONFIG_USB_GADGET_OMAP)
7451	+
7452	+ mutex_lock(&tu->serialize);
7453	+
7454	+ if (host == NULL) {
7455	+ if (TAHVO_MODE(tu) == TAHVO_MODE_HOST)
7456	+ tahvo_usb_power_off(tu);
7457	+ tu->otg.host = NULL;
7458	+ mutex_unlock(&tu->serialize);
7459	+ return 0;
7460	+ }
7461	+
7462	+ l = omap_readl(OTG_SYSCON_1);
7463	+ l &= ~(OTG_IDLE_EN \| HST_IDLE_EN \| DEV_IDLE_EN);
7464	+ omap_writel(l, OTG_SYSCON_1);
7465	+
7466	+ if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) {
7467	+ tu->otg.host = NULL;
7468	+ tahvo_usb_become_host(tu);
7469	+ } else
7470	+ host_suspend(tu);
7471	+
7472	+ tu->otg.host = host;
7473	+
7474	+ mutex_unlock(&tu->serialize);
7475	+#else
7476	+ /* No host mode configured, so do not allow host controlled to be set */
7477	+ return -EINVAL;
7478	+#endif
7479	+
7480	+ return 0;
7481	+}
7482	+
7483	+static int tahvo_usb_set_peripheral(struct otg_transceiver otg, struct usb_gadget gadget)
7484	+{
7485	+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
7486	+
7487	+ dev_dbg(&tu->pt_dev->dev, "set_peripheral %p\n", gadget);
7488	+
7489	+ if (!otg)
7490	+ return -ENODEV;
7491	+
7492	+#if defined(CONFIG_USB_OTG) \|\| defined(CONFIG_USB_GADGET_OMAP)
7493	+
7494	+ mutex_lock(&tu->serialize);
7495	+
7496	+ if (!gadget) {
7497	+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
7498	+ tahvo_usb_power_off(tu);
7499	+ tu->otg.gadget = NULL;
7500	+ mutex_unlock(&tu->serialize);
7501	+ return 0;
7502	+ }
7503	+
7504	+ tu->otg.gadget = gadget;
7505	+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
7506	+ tahvo_usb_become_peripheral(tu);
7507	+
7508	+ mutex_unlock(&tu->serialize);
7509	+#else
7510	+ /* No gadget mode configured, so do not allow host controlled to be set */
7511	+ return -EINVAL;
7512	+#endif
7513	+
7514	+ return 0;
7515	+}
7516	+
7517	+static void tahvo_usb_irq_work(struct work_struct *work)
7518	+{
7519	+ struct tahvo_usb *tu = container_of(work, struct tahvo_usb, irq_work);
7520	+
7521	+ mutex_lock(&tu->serialize);
7522	+ check_vbus_state(tu);
7523	+ mutex_unlock(&tu->serialize);
7524	+}
7525	+
7526	+static void tahvo_usb_vbus_interrupt(unsigned long arg)
7527	+{
7528	+ struct tahvo_usb tu = (struct tahvo_usb ) arg;
7529	+
7530	+ tahvo_ack_irq(TAHVO_INT_VBUSON);
7531	+ /* Seems we need this to acknowledge the interrupt */
7532	+ tahvo_read_reg(TAHVO_REG_IDSR);
7533	+ schedule_work(&tu->irq_work);
7534	+}
7535	+
7536	+#ifdef CONFIG_USB_OTG
7537	+static ssize_t otg_mode_show(struct device *device,
7538	+ struct device_attribute attr, char buf)
7539	+{
7540	+ struct tahvo_usb tu = (struct tahvo_usb) device->driver_data;
7541	+ switch (tu->tahvo_mode) {
7542	+ case TAHVO_MODE_HOST:
7543	+ return sprintf(buf, "host\n");
7544	+ case TAHVO_MODE_PERIPHERAL:
7545	+ return sprintf(buf, "peripheral\n");
7546	+ }
7547	+ return sprintf(buf, "unknown\n");
7548	+}
7549	+
7550	+static ssize_t otg_mode_store(struct device *device,
7551	+ struct device_attribute *attr,
7552	+ const char *buf, size_t count)
7553	+{
7554	+ struct tahvo_usb tu = (struct tahvo_usb) device->driver_data;
7555	+ int r;
7556	+
7557	+ r = strlen(buf);
7558	+ mutex_lock(&tu->serialize);
7559	+ if (strncmp(buf, "host", 4) == 0) {
7560	+ if (tu->tahvo_mode == TAHVO_MODE_PERIPHERAL)
7561	+ tahvo_usb_stop_peripheral(tu);
7562	+ tu->tahvo_mode = TAHVO_MODE_HOST;
7563	+ if (tu->otg.host) {
7564	+ printk(KERN_INFO "Selected HOST mode: host controller present.\n");
7565	+ tahvo_usb_become_host(tu);
7566	+ } else {
7567	+ printk(KERN_INFO "Selected HOST mode: no host controller, powering off.\n");
7568	+ tahvo_usb_power_off(tu);
7569	+ }
7570	+ } else if (strncmp(buf, "peripheral", 10) == 0) {
7571	+ if (tu->tahvo_mode == TAHVO_MODE_HOST)
7572	+ tahvo_usb_stop_host(tu);
7573	+ tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
7574	+ if (tu->otg.gadget) {
7575	+ printk(KERN_INFO "Selected PERIPHERAL mode: gadget driver present.\n");
7576	+ tahvo_usb_become_peripheral(tu);
7577	+ } else {
7578	+ printk(KERN_INFO "Selected PERIPHERAL mode: no gadget driver, powering off.\n");
7579	+ tahvo_usb_power_off(tu);
7580	+ }
7581	+ } else
7582	+ r = -EINVAL;
7583	+
7584	+ mutex_unlock(&tu->serialize);
7585	+ return r;
7586	+}
7587	+
7588	+static DEVICE_ATTR(otg_mode, 0644, otg_mode_show, otg_mode_store);
7589	+#endif
7590	+
7591	+static int tahvo_usb_probe(struct device *dev)
7592	+{
7593	+ struct tahvo_usb *tu;
7594	+ int ret;
7595	+
7596	+ dev_dbg(dev, "probe\n");
7597	+
7598	+ /* Create driver data */
7599	+ tu = kmalloc(sizeof(*tu), GFP_KERNEL);
7600	+ if (!tu)
7601	+ return -ENOMEM;
7602	+ memset(tu, 0, sizeof(*tu));
7603	+ tu->pt_dev = container_of(dev, struct platform_device, dev);
7604	+#ifdef CONFIG_USB_OTG
7605	+ /* Default mode */
7606	+#ifdef CONFIG_CBUS_TAHVO_USB_HOST_BY_DEFAULT
7607	+ tu->tahvo_mode = TAHVO_MODE_HOST;
7608	+#else
7609	+ tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
7610	+#endif
7611	+#endif
7612	+
7613	+ INIT_WORK(&tu->irq_work, tahvo_usb_irq_work);
7614	+ mutex_init(&tu->serialize);
7615	+
7616	+ /* Set initial state, so that we generate kevents only on
7617	+ * state changes */
7618	+ tu->vbus_state = tahvo_read_reg(TAHVO_REG_IDSR) & 0x01;
7619	+
7620	+ /* We cannot enable interrupt until omap_udc is initialized */
7621	+ ret = tahvo_request_irq(TAHVO_INT_VBUSON, tahvo_usb_vbus_interrupt,
7622	+ (unsigned long) tu, "vbus_interrupt");
7623	+ if (ret != 0) {
7624	+ kfree(tu);
7625	+ printk(KERN_ERR "Could not register Tahvo interrupt for VBUS\n");
7626	+ return ret;
7627	+ }
7628	+
7629	+ /* Attributes */
7630	+ ret = device_create_file(dev, &dev_attr_vbus_state);
7631	+#ifdef CONFIG_USB_OTG
7632	+ ret \|= device_create_file(dev, &dev_attr_otg_mode);
7633	+#endif
7634	+ if (ret)
7635	+ printk(KERN_ERR "attribute creation failed: %d\n", ret);
7636	+
7637	+ /* Create OTG interface */
7638	+ tahvo_usb_power_off(tu);
7639	+ tu->otg.state = OTG_STATE_UNDEFINED;
7640	+ tu->otg.label = DRIVER_NAME;
7641	+ tu->otg.set_host = tahvo_usb_set_host;
7642	+ tu->otg.set_peripheral = tahvo_usb_set_peripheral;
7643	+ tu->otg.set_power = tahvo_usb_set_power;
7644	+ tu->otg.set_suspend = tahvo_usb_set_suspend;
7645	+ tu->otg.start_srp = tahvo_usb_start_srp;
7646	+ tu->otg.start_hnp = tahvo_usb_start_hnp;
7647	+
7648	+ ret = otg_set_transceiver(&tu->otg);
7649	+ if (ret < 0) {
7650	+ printk(KERN_ERR "Cannot register USB transceiver\n");
7651	+ kfree(tu);
7652	+ tahvo_free_irq(TAHVO_INT_VBUSON);
7653	+ return ret;
7654	+ }
7655	+
7656	+ dev->driver_data = tu;
7657	+
7658	+ /* Act upon current vbus state once at startup. A vbus state irq may or
7659	+ * may not be generated in addition to this. */
7660	+ schedule_work(&tu->irq_work);
7661	+ return 0;
7662	+}
7663	+
7664	+static int tahvo_usb_remove(struct device *dev)
7665	+{
7666	+ dev_dbg(dev, "remove\n");
7667	+
7668	+ tahvo_free_irq(TAHVO_INT_VBUSON);
7669	+ flush_scheduled_work();
7670	+ otg_set_transceiver(0);
7671	+ device_remove_file(dev, &dev_attr_vbus_state);
7672	+#ifdef CONFIG_USB_OTG
7673	+ device_remove_file(dev, &dev_attr_otg_mode);
7674	+#endif
7675	+ return 0;
7676	+}
7677	+
7678	+static struct device_driver tahvo_usb_driver = {
7679	+ .name = "tahvo-usb",
7680	+ .bus = &platform_bus_type,
7681	+ .probe = tahvo_usb_probe,
7682	+ .remove = tahvo_usb_remove,
7683	+};
7684	+
7685	+static struct platform_device tahvo_usb_device = {
7686	+ .name = "tahvo-usb",
7687	+ .id = -1,
7688	+};
7689	+
7690	+static int __init tahvo_usb_init(void)
7691	+{
7692	+ int ret = 0;
7693	+
7694	+ printk(KERN_INFO "Tahvo USB transceiver driver initializing\n");
7695	+ ret = driver_register(&tahvo_usb_driver);
7696	+ if (ret)
7697	+ return ret;
7698	+ ret = platform_device_register(&tahvo_usb_device);
7699	+ if (ret < 0) {
7700	+ driver_unregister(&tahvo_usb_driver);
7701	+ return ret;
7702	+ }
7703	+ ret = driver_register(&omap_otg_driver);
7704	+ if (ret) {
7705	+ platform_device_unregister(&tahvo_usb_device);
7706	+ driver_unregister(&tahvo_usb_driver);
7707	+ return ret;
7708	+ }
7709	+ return 0;
7710	+}
7711	+
7712	+subsys_initcall(tahvo_usb_init);
7713	+
7714	+static void __exit tahvo_usb_exit(void)
7715	+{
7716	+ driver_unregister(&omap_otg_driver);
7717	+ platform_device_unregister(&tahvo_usb_device);
7718	+ driver_unregister(&tahvo_usb_driver);
7719	+}
7720	+module_exit(tahvo_usb_exit);
7721	+
7722	+MODULE_DESCRIPTION("Tahvo USB OTG Transceiver Driver");
7723	+MODULE_LICENSE("GPL");
7724	+MODULE_AUTHOR("Juha Yrj�l�, Tony Lindgren, and Timo Ter�s");
7725	--- /dev/null
7726	+++ b/drivers/cbus/tahvo-user.c
7727	@@ -0,0 +1,405 @@
7728	+/**
7729	+ * drivers/cbus/tahvo-user.c
7730	+ *
7731	+ * Tahvo user space interface functions
7732	+ *
7733	+ * Copyright (C) 2004, 2005 Nokia Corporation
7734	+ *
7735	+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
7736	+ *
7737	+ * This file is subject to the terms and conditions of the GNU General
7738	+ * Public License. See the file "COPYING" in the main directory of this
7739	+ * archive for more details.
7740	+ *
7741	+ * This program is distributed in the hope that it will be useful,
7742	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
7743	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7744	+ * GNU General Public License for more details.
7745	+ *
7746	+ * You should have received a copy of the GNU General Public License
7747	+ * along with this program; if not, write to the Free Software
7748	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7749	+ */
7750	+
7751	+#include <linux/types.h>
7752	+#include <linux/kernel.h>
7753	+#include <linux/interrupt.h>
7754	+#include <linux/module.h>
7755	+#include <linux/init.h>
7756	+#include <linux/fs.h>
7757	+#include <linux/miscdevice.h>
7758	+#include <linux/poll.h>
7759	+#include <linux/list.h>
7760	+#include <linux/spinlock.h>
7761	+#include <linux/mutex.h>
7762	+
7763	+#include <asm/uaccess.h>
7764	+
7765	+#include "tahvo.h"
7766	+
7767	+#include "user_retu_tahvo.h"
7768	+
7769	+/* Maximum size of IRQ node buffer/pool */
7770	+#define TAHVO_MAX_IRQ_BUF_LEN 16
7771	+
7772	+#define PFX "tahvo-user: "
7773	+
7774	+/* Bitmap for marking the interrupt sources as having the handlers */
7775	+static u32 tahvo_irq_bits;
7776	+
7777	+/* For allowing only one user process to subscribe to the tahvo interrupts */
7778	+static struct file *tahvo_irq_subscr = NULL;
7779	+
7780	+/* For poll and IRQ passing */
7781	+struct tahvo_irq {
7782	+ u32 id;
7783	+ struct list_head node;
7784	+};
7785	+
7786	+static spinlock_t tahvo_irqs_lock;
7787	+static struct tahvo_irq *tahvo_irq_block;
7788	+static LIST_HEAD(tahvo_irqs);
7789	+static LIST_HEAD(tahvo_irqs_reserve);
7790	+
7791	+/* Wait queue - used when user wants to read the device */
7792	+DECLARE_WAIT_QUEUE_HEAD(tahvo_user_waitqueue);
7793	+
7794	+/* Semaphore to protect irq subscription sequence */
7795	+static struct mutex tahvo_mutex;
7796	+
7797	+/* This array specifies TAHVO register types (read/write/toggle) */
7798	+static const u8 tahvo_access_bits[] = {
7799	+ 1,
7800	+ 4,
7801	+ 1,
7802	+ 3,
7803	+ 3,
7804	+ 3,
7805	+ 3,
7806	+ 3,
7807	+ 3,
7808	+ 3,
7809	+ 3,
7810	+ 3,
7811	+ 3,
7812	+ 1
7813	+};
7814	+
7815	+/*
7816	+ * The handler for all TAHVO interrupts.
7817	+ *
7818	+ * arg is the interrupt source in TAHVO.
7819	+ */
7820	+static void tahvo_user_irq_handler(unsigned long arg)
7821	+{
7822	+ struct tahvo_irq *irq;
7823	+
7824	+ /* user has to re-enable the interrupt once ready
7825	+ * for receiving them again */
7826	+ tahvo_disable_irq(arg);
7827	+ tahvo_ack_irq(arg);
7828	+
7829	+ spin_lock(&tahvo_irqs_lock);
7830	+ if (list_empty(&tahvo_irqs_reserve)) {
7831	+ spin_unlock(&tahvo_irqs_lock);
7832	+ return;
7833	+ }
7834	+ irq = list_entry((&tahvo_irqs_reserve)->next, struct tahvo_irq, node);
7835	+ irq->id = arg;
7836	+ list_move_tail(&irq->node, &tahvo_irqs);
7837	+ spin_unlock(&tahvo_irqs_lock);
7838	+
7839	+ /* wake up waiting thread */
7840	+ wake_up(&tahvo_user_waitqueue);
7841	+}
7842	+
7843	+/*
7844	+ * This routine sets up the interrupt handler and marks an interrupt source
7845	+ * in TAHVO as a candidate for signal delivery to the user process.
7846	+ */
7847	+static int tahvo_user_subscribe_to_irq(int id, struct file *filp)
7848	+{
7849	+ int ret;
7850	+
7851	+ mutex_lock(&tahvo_mutex);
7852	+ if ((tahvo_irq_subscr != NULL) && (tahvo_irq_subscr != filp)) {
7853	+ mutex_unlock(&tahvo_mutex);
7854	+ return -EBUSY;
7855	+ }
7856	+ /* Store the file pointer of the first user process registering IRQs */
7857	+ tahvo_irq_subscr = filp;
7858	+ mutex_unlock(&tahvo_mutex);
7859	+
7860	+ if (tahvo_irq_bits & (1 << id))
7861	+ return 0;
7862	+
7863	+ ret = tahvo_request_irq(id, tahvo_user_irq_handler, id, "");
7864	+ if (ret < 0)
7865	+ return ret;
7866	+
7867	+ /* Mark that this interrupt has a handler */
7868	+ tahvo_irq_bits \|= 1 << id;
7869	+
7870	+ return 0;
7871	+}
7872	+
7873	+/*
7874	+ * Unregister all TAHVO interrupt handlers
7875	+ */
7876	+static void tahvo_unreg_irq_handlers(void)
7877	+{
7878	+ int id;
7879	+
7880	+ if (!tahvo_irq_bits)
7881	+ return;
7882	+
7883	+ for (id = 0; id < MAX_TAHVO_IRQ_HANDLERS; id++)
7884	+ if (tahvo_irq_bits & (1 << id))
7885	+ tahvo_free_irq(id);
7886	+
7887	+ tahvo_irq_bits = 0;
7888	+}
7889	+
7890	+/*
7891	+ * Write to TAHVO register.
7892	+ * Returns 0 upon success, a negative error value otherwise.
7893	+ */
7894	+static int tahvo_user_write_with_mask(u32 field, u16 value)
7895	+{
7896	+ u32 mask;
7897	+ u32 reg;
7898	+ u_short tmp;
7899	+ unsigned long flags;
7900	+
7901	+ mask = MASK(field);
7902	+ reg = REG(field);
7903	+
7904	+ /* Detect bad mask and reg */
7905	+ if (mask == 0 \|\| reg > TAHVO_REG_MAX \|\|
7906	+ tahvo_access_bits[reg] == READ_ONLY) {
7907	+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
7908	+ reg, mask);
7909	+ return -EINVAL;
7910	+ }
7911	+
7912	+ /* Justify value according to mask */
7913	+ while (!(mask & 1)) {
7914	+ value = value << 1;
7915	+ mask = mask >> 1;
7916	+ }
7917	+
7918	+ spin_lock_irqsave(&tahvo_lock, flags);
7919	+ if (tahvo_access_bits[reg] == TOGGLE) {
7920	+ /* No need to detect previous content of register */
7921	+ tmp = 0;
7922	+ } else {
7923	+ /* Read current value of register */
7924	+ tmp = tahvo_read_reg(reg);
7925	+ }
7926	+ /* Generate a new value */
7927	+ tmp = (tmp & ~MASK(field)) \| (value & MASK(field));
7928	+ /* Write data to TAHVO */
7929	+ tahvo_write_reg(reg, tmp);
7930	+ spin_unlock_irqrestore(&tahvo_lock, flags);
7931	+
7932	+ return 0;
7933	+}
7934	+
7935	+/*
7936	+ * Read TAHVO register.
7937	+ */
7938	+static u32 tahvo_user_read_with_mask(u32 field)
7939	+{
7940	+ u_short value;
7941	+ u32 mask, reg;
7942	+
7943	+ mask = MASK(field);
7944	+ reg = REG(field);
7945	+
7946	+ /* Detect bad mask and reg */
7947	+ if (mask == 0 \|\| reg > TAHVO_REG_MAX) {
7948	+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
7949	+ reg, mask);
7950	+ return -EINVAL;
7951	+ }
7952	+
7953	+ /* Read the register */
7954	+ value = tahvo_read_reg(reg) & mask;
7955	+
7956	+ /* Right justify value */
7957	+ while (!(mask & 1)) {
7958	+ value = value >> 1;
7959	+ mask = mask >> 1;
7960	+ }
7961	+
7962	+ return value;
7963	+}
7964	+
7965	+/*
7966	+ * Close device
7967	+ */
7968	+static int tahvo_close(struct inode inode, struct file filp)
7969	+{
7970	+ /* Unregister all interrupts that have been registered */
7971	+ if (tahvo_irq_subscr == filp) {
7972	+ tahvo_unreg_irq_handlers();
7973	+ tahvo_irq_subscr = NULL;
7974	+ }
7975	+
7976	+ return 0;
7977	+}
7978	+
7979	+/*
7980	+ * Device control (ioctl)
7981	+ */
7982	+static int tahvo_ioctl(struct inode inode, struct file filp,
7983	+ unsigned int cmd, unsigned long arg)
7984	+{
7985	+ struct retu_tahvo_write_parms par;
7986	+ int ret;
7987	+
7988	+ switch (cmd) {
7989	+ case URT_IOCT_IRQ_SUBSCR:
7990	+ return tahvo_user_subscribe_to_irq(arg, filp);
7991	+ case TAHVO_IOCH_READ:
7992	+ return tahvo_user_read_with_mask(arg);
7993	+ case TAHVO_IOCX_WRITE:
7994	+ ret = copy_from_user(&par, (void __user *) arg, sizeof(par));
7995	+ if (ret)
7996	+ printk(KERN_ERR "copy_from_user failed: %d\n", ret);
7997	+ par.result = tahvo_user_write_with_mask(par.field, par.value);
7998	+ ret = copy_to_user((void __user *) arg, &par, sizeof(par));
7999	+ if (ret)
8000	+ printk(KERN_ERR "copy_to_user failed: %d\n", ret);
8001	+ break;
8002	+ default:
8003	+ return -ENOIOCTLCMD;
8004	+ }
8005	+ return 0;
8006	+}
8007	+
8008	+/*
8009	+ * Read from device
8010	+ */
8011	+static ssize_t tahvo_read(struct file filp, char buf, size_t count,
8012	+ loff_t * offp)
8013	+{
8014	+ struct tahvo_irq *irq;
8015	+
8016	+ u32 nr, i;
8017	+
8018	+ /* read not permitted if neither filp nor anyone has registered IRQs */
8019	+ if (tahvo_irq_subscr != filp)
8020	+ return -EPERM;
8021	+
8022	+ if ((count < sizeof(u32)) \|\| ((count % sizeof(u32)) != 0))
8023	+ return -EINVAL;
8024	+
8025	+ nr = count / sizeof(u32);
8026	+
8027	+ for (i = 0; i < nr; i++) {
8028	+ unsigned long flags;
8029	+ u32 irq_id;
8030	+ int ret;
8031	+
8032	+ ret = wait_event_interruptible(tahvo_user_waitqueue,
8033	+ !list_empty(&tahvo_irqs));
8034	+ if (ret < 0)
8035	+ return ret;
8036	+
8037	+ spin_lock_irqsave(&tahvo_irqs_lock, flags);
8038	+ irq = list_entry((&tahvo_irqs)->next, struct tahvo_irq, node);
8039	+ irq_id = irq->id;
8040	+ list_move(&irq->node, &tahvo_irqs_reserve);
8041	+ spin_unlock_irqrestore(&tahvo_irqs_lock, flags);
8042	+
8043	+ ret = copy_to_user(buf + i * sizeof(irq_id), &irq_id,
8044	+ sizeof(irq_id));
8045	+ if (ret)
8046	+ printk(KERN_ERR "copy_to_user failed: %d\n", ret);
8047	+ }
8048	+
8049	+ return count;
8050	+}
8051	+
8052	+/*
8053	+ * Poll method
8054	+ */
8055	+static unsigned tahvo_poll(struct file filp, struct poll_table_struct pt)
8056	+{
8057	+ if (!list_empty(&tahvo_irqs))
8058	+ return POLLIN;
8059	+
8060	+ poll_wait(filp, &tahvo_user_waitqueue, pt);
8061	+
8062	+ if (!list_empty(&tahvo_irqs))
8063	+ return POLLIN;
8064	+ else
8065	+ return 0;
8066	+}
8067	+
8068	+static struct file_operations tahvo_user_fileops = {
8069	+ .owner = THIS_MODULE,
8070	+ .ioctl = tahvo_ioctl,
8071	+ .read = tahvo_read,
8072	+ .release = tahvo_close,
8073	+ .poll = tahvo_poll
8074	+};
8075	+
8076	+static struct miscdevice tahvo_device = {
8077	+ .minor = MISC_DYNAMIC_MINOR,
8078	+ .name = "tahvo",
8079	+ .fops = &tahvo_user_fileops
8080	+};
8081	+
8082	+/*
8083	+ * Initialization
8084	+ *
8085	+ * @return 0 if successful, error value otherwise.
8086	+ */
8087	+int tahvo_user_init(void)
8088	+{
8089	+ struct tahvo_irq *irq;
8090	+ int res, i;
8091	+
8092	+ irq = kmalloc(sizeof(irq) TAHVO_MAX_IRQ_BUF_LEN, GFP_KERNEL);
8093	+ if (irq == NULL) {
8094	+ printk(KERN_ERR PFX "kmalloc failed\n");
8095	+ return -ENOMEM;
8096	+ }
8097	+ memset(irq, 0, sizeof(irq) TAHVO_MAX_IRQ_BUF_LEN);
8098	+ for (i = 0; i < TAHVO_MAX_IRQ_BUF_LEN; i++)
8099	+ list_add(&irq[i].node, &tahvo_irqs_reserve);
8100	+
8101	+ tahvo_irq_block = irq;
8102	+
8103	+ spin_lock_init(&tahvo_irqs_lock);
8104	+ mutex_init(&tahvo_mutex);
8105	+
8106	+ /* Request a misc device */
8107	+ res = misc_register(&tahvo_device);
8108	+ if (res < 0) {
8109	+ printk(KERN_ERR PFX "unable to register misc device for %s\n",
8110	+ tahvo_device.name);
8111	+ kfree(irq);
8112	+ return res;
8113	+ }
8114	+
8115	+ return 0;
8116	+}
8117	+
8118	+/*
8119	+ * Cleanup.
8120	+ */
8121	+void tahvo_user_cleanup(void)
8122	+{
8123	+ /* Unregister our misc device */
8124	+ misc_deregister(&tahvo_device);
8125	+ /* Unregister and disable all TAHVO interrupts */
8126	+ tahvo_unreg_irq_handlers();
8127	+ kfree(tahvo_irq_block);
8128	+}
8129	+
8130	+MODULE_DESCRIPTION("Tahvo ASIC user space functions");
8131	+MODULE_LICENSE("GPL");
8132	+MODULE_AUTHOR("Mikko Ylinen");
8133	--- /dev/null
8134	+++ b/drivers/cbus/tahvo.c
8135	@@ -0,0 +1,442 @@
8136	+/**
8137	+ * drivers/cbus/tahvo.c
8138	+ *
8139	+ * Support functions for Tahvo ASIC
8140	+ *
8141	+ * Copyright (C) 2004, 2005 Nokia Corporation
8142	+ *
8143	+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com>,
8144	+ * David Weinehall <david.weinehall@nokia.com>, and
8145	+ * Mikko Ylinen <mikko.k.ylinen@nokia.com>
8146	+ *
8147	+ * This file is subject to the terms and conditions of the GNU General
8148	+ * Public License. See the file "COPYING" in the main directory of this
8149	+ * archive for more details.
8150	+ *
8151	+ * This program is distributed in the hope that it will be useful,
8152	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
8153	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8154	+ * GNU General Public License for more details.
8155	+ *
8156	+ * You should have received a copy of the GNU General Public License
8157	+ * along with this program; if not, write to the Free Software
8158	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8159	+ */
8160	+
8161	+#include <linux/module.h>
8162	+#include <linux/init.h>
8163	+
8164	+#include <linux/kernel.h>
8165	+#include <linux/errno.h>
8166	+#include <linux/device.h>
8167	+#include <linux/miscdevice.h>
8168	+#include <linux/poll.h>
8169	+#include <linux/fs.h>
8170	+#include <linux/irq.h>
8171	+#include <linux/interrupt.h>
8172	+#include <linux/platform_device.h>
8173	+#include <linux/gpio.h>
8174	+
8175	+#include <asm/uaccess.h>
8176	+
8177	+#include <mach/mux.h>
8178	+#include <mach/board.h>
8179	+#include <mach/board-nokia.h>
8180	+
8181	+#include "cbus.h"
8182	+#include "tahvo.h"
8183	+
8184	+#define TAHVO_ID 0x02
8185	+#define PFX "tahvo: "
8186	+
8187	+static int tahvo_initialized;
8188	+static int tahvo_irq_pin;
8189	+static int tahvo_is_betty;
8190	+
8191	+static struct tasklet_struct tahvo_tasklet;
8192	+spinlock_t tahvo_lock = SPIN_LOCK_UNLOCKED;
8193	+
8194	+static struct completion device_release;
8195	+
8196	+struct tahvo_irq_handler_desc {
8197	+ int (*func)(unsigned long);
8198	+ unsigned long arg;
8199	+ char name[8];
8200	+};
8201	+
8202	+static struct tahvo_irq_handler_desc tahvo_irq_handlers[MAX_TAHVO_IRQ_HANDLERS];
8203	+
8204	+/**
8205	+ * tahvo_read_reg - Read a value from a register in Tahvo
8206	+ * @reg: the register to read from
8207	+ *
8208	+ * This function returns the contents of the specified register
8209	+ */
8210	+int tahvo_read_reg(int reg)
8211	+{
8212	+ BUG_ON(!tahvo_initialized);
8213	+ return cbus_read_reg(cbus_host, TAHVO_ID, reg);
8214	+}
8215	+
8216	+/**
8217	+ * tahvo_write_reg - Write a value to a register in Tahvo
8218	+ * @reg: the register to write to
8219	+ * @reg: the value to write to the register
8220	+ *
8221	+ * This function writes a value to the specified register
8222	+ */
8223	+void tahvo_write_reg(int reg, u16 val)
8224	+{
8225	+ BUG_ON(!tahvo_initialized);
8226	+ cbus_write_reg(cbus_host, TAHVO_ID, reg, val);
8227	+}
8228	+
8229	+/**
8230	+ * tahvo_set_clear_reg_bits - set and clear register bits atomically
8231	+ * @reg: the register to write to
8232	+ * @bits: the bits to set
8233	+ *
8234	+ * This function sets and clears the specified Tahvo register bits atomically
8235	+ */
8236	+void tahvo_set_clear_reg_bits(int reg, u16 set, u16 clear)
8237	+{
8238	+ unsigned long flags;
8239	+ u16 w;
8240	+
8241	+ spin_lock_irqsave(&tahvo_lock, flags);
8242	+ w = tahvo_read_reg(reg);
8243	+ w &= ~clear;
8244	+ w \|= set;
8245	+ tahvo_write_reg(reg, w);
8246	+ spin_unlock_irqrestore(&tahvo_lock, flags);
8247	+}
8248	+
8249	+/*
8250	+ * Disable given TAHVO interrupt
8251	+ */
8252	+void tahvo_disable_irq(int id)
8253	+{
8254	+ unsigned long flags;
8255	+ u16 mask;
8256	+
8257	+ spin_lock_irqsave(&tahvo_lock, flags);
8258	+ mask = tahvo_read_reg(TAHVO_REG_IMR);
8259	+ mask \|= 1 << id;
8260	+ tahvo_write_reg(TAHVO_REG_IMR, mask);
8261	+ spin_unlock_irqrestore(&tahvo_lock, flags);
8262	+}
8263	+
8264	+/*
8265	+ * Enable given TAHVO interrupt
8266	+ */
8267	+void tahvo_enable_irq(int id)
8268	+{
8269	+ unsigned long flags;
8270	+ u16 mask;
8271	+
8272	+ spin_lock_irqsave(&tahvo_lock, flags);
8273	+ mask = tahvo_read_reg(TAHVO_REG_IMR);
8274	+ mask &= ~(1 << id);
8275	+ tahvo_write_reg(TAHVO_REG_IMR, mask);
8276	+ spin_unlock_irqrestore(&tahvo_lock, flags);
8277	+}
8278	+
8279	+/*
8280	+ * Acknowledge given TAHVO interrupt
8281	+ */
8282	+void tahvo_ack_irq(int id)
8283	+{
8284	+ tahvo_write_reg(TAHVO_REG_IDR, 1 << id);
8285	+}
8286	+
8287	+static int tahvo_7bit_backlight;
8288	+
8289	+int tahvo_get_backlight_level(void)
8290	+{
8291	+ int mask;
8292	+
8293	+ if (tahvo_7bit_backlight)
8294	+ mask = 0x7f;
8295	+ else
8296	+ mask = 0x0f;
8297	+ return tahvo_read_reg(TAHVO_REG_LEDPWMR) & mask;
8298	+}
8299	+
8300	+int tahvo_get_max_backlight_level(void)
8301	+{
8302	+ if (tahvo_7bit_backlight)
8303	+ return 0x7f;
8304	+ else
8305	+ return 0x0f;
8306	+}
8307	+
8308	+void tahvo_set_backlight_level(int level)
8309	+{
8310	+ int max_level;
8311	+
8312	+ max_level = tahvo_get_max_backlight_level();
8313	+ if (level > max_level)
8314	+ level = max_level;
8315	+ tahvo_write_reg(TAHVO_REG_LEDPWMR, level);
8316	+}
8317	+
8318	+/*
8319	+ * TAHVO interrupt handler. Only schedules the tasklet.
8320	+ */
8321	+static irqreturn_t tahvo_irq_handler(int irq, void *dev_id)
8322	+{
8323	+ tasklet_schedule(&tahvo_tasklet);
8324	+ return IRQ_HANDLED;
8325	+}
8326	+
8327	+/*
8328	+ * Tasklet handler
8329	+ */
8330	+static void tahvo_tasklet_handler(unsigned long data)
8331	+{
8332	+ struct tahvo_irq_handler_desc *hnd;
8333	+ u16 id;
8334	+ u16 im;
8335	+ int i;
8336	+
8337	+ for (;;) {
8338	+ id = tahvo_read_reg(TAHVO_REG_IDR);
8339	+ im = ~tahvo_read_reg(TAHVO_REG_IMR);
8340	+ id &= im;
8341	+
8342	+ if (!id)
8343	+ break;
8344	+
8345	+ for (i = 0; id != 0; i++, id >>= 1) {
8346	+ if (!(id & 1))
8347	+ continue;
8348	+ hnd = &tahvo_irq_handlers[i];
8349	+ if (hnd->func == NULL) {
8350	+ /* Spurious tahvo interrupt - just ack it */
8351	+ printk(KERN_INFO "Spurious Tahvo interrupt "
8352	+ "(id %d)\n", i);
8353	+ tahvo_disable_irq(i);
8354	+ tahvo_ack_irq(i);
8355	+ continue;
8356	+ }
8357	+ hnd->func(hnd->arg);
8358	+ /*
8359	+ * Don't acknowledge the interrupt here
8360	+ * It must be done explicitly
8361	+ */
8362	+ }
8363	+ }
8364	+}
8365	+
8366	+/*
8367	+ * Register the handler for a given TAHVO interrupt source.
8368	+ */
8369	+int tahvo_request_irq(int id, void irq_handler, unsigned long arg, char name)
8370	+{
8371	+ struct tahvo_irq_handler_desc *hnd;
8372	+
8373	+ if (irq_handler == NULL \|\| id >= MAX_TAHVO_IRQ_HANDLERS \|\|
8374	+ name == NULL) {
8375	+ printk(KERN_ERR PFX "Invalid arguments to %s\n",
8376	+ __FUNCTION__);
8377	+ return -EINVAL;
8378	+ }
8379	+ hnd = &tahvo_irq_handlers[id];
8380	+ if (hnd->func != NULL) {
8381	+ printk(KERN_ERR PFX "IRQ %d already reserved\n", id);
8382	+ return -EBUSY;
8383	+ }
8384	+ printk(KERN_INFO PFX "Registering interrupt %d for device %s\n",
8385	+ id, name);
8386	+ hnd->func = irq_handler;
8387	+ hnd->arg = arg;
8388	+ strlcpy(hnd->name, name, sizeof(hnd->name));
8389	+
8390	+ tahvo_ack_irq(id);
8391	+ tahvo_enable_irq(id);
8392	+
8393	+ return 0;
8394	+}
8395	+
8396	+/*
8397	+ * Unregister the handler for a given TAHVO interrupt source.
8398	+ */
8399	+void tahvo_free_irq(int id)
8400	+{
8401	+ struct tahvo_irq_handler_desc *hnd;
8402	+
8403	+ if (id >= MAX_TAHVO_IRQ_HANDLERS) {
8404	+ printk(KERN_ERR PFX "Invalid argument to %s\n",
8405	+ __FUNCTION__);
8406	+ return;
8407	+ }
8408	+ hnd = &tahvo_irq_handlers[id];
8409	+ if (hnd->func == NULL) {
8410	+ printk(KERN_ERR PFX "IRQ %d already freed\n", id);
8411	+ return;
8412	+ }
8413	+
8414	+ tahvo_disable_irq(id);
8415	+ hnd->func = NULL;
8416	+}
8417	+
8418	+/**
8419	+ * tahvo_probe - Probe for Tahvo ASIC
8420	+ * @dev: the Tahvo device
8421	+ *
8422	+ * Probe for the Tahvo ASIC and allocate memory
8423	+ * for its device-struct if found
8424	+ */
8425	+static int __devinit tahvo_probe(struct device *dev)
8426	+{
8427	+ const struct omap_em_asic_bb5_config * em_asic_config;
8428	+ int rev, id, ret;
8429	+
8430	+ /* Prepare tasklet */
8431	+ tasklet_init(&tahvo_tasklet, tahvo_tasklet_handler, 0);
8432	+
8433	+ em_asic_config = omap_get_config(OMAP_TAG_EM_ASIC_BB5,
8434	+ struct omap_em_asic_bb5_config);
8435	+ if (em_asic_config == NULL) {
8436	+ printk(KERN_ERR PFX "Unable to retrieve config data\n");
8437	+ return -ENODATA;
8438	+ }
8439	+
8440	+ tahvo_initialized = 1;
8441	+
8442	+ rev = tahvo_read_reg(TAHVO_REG_ASICR);
8443	+
8444	+ id = (rev >> 8) & 0xff;
8445	+ if (id == 0x03) {
8446	+ if ((rev & 0xff) >= 0x50)
8447	+ tahvo_7bit_backlight = 1;
8448	+ } else if (id == 0x0b) {
8449	+ tahvo_is_betty = 1;
8450	+ tahvo_7bit_backlight = 1;
8451	+ } else {
8452	+ printk(KERN_ERR "Tahvo/Betty chip not found");
8453	+ return -ENODEV;
8454	+ }
8455	+
8456	+ printk(KERN_INFO "%s v%d.%d found\n", tahvo_is_betty ? "Betty" : "Tahvo",
8457	+ (rev >> 4) & 0x0f, rev & 0x0f);
8458	+
8459	+ tahvo_irq_pin = em_asic_config->tahvo_irq_gpio;
8460	+
8461	+ if ((ret = gpio_request(tahvo_irq_pin, "TAHVO irq")) < 0) {
8462	+ printk(KERN_ERR PFX "Unable to reserve IRQ GPIO\n");
8463	+ return ret;
8464	+ }
8465	+
8466	+ /* Set the pin as input */
8467	+ gpio_direction_input(tahvo_irq_pin);
8468	+
8469	+ /* Rising edge triggers the IRQ */
8470	+ set_irq_type(gpio_to_irq(tahvo_irq_pin), IRQ_TYPE_EDGE_RISING);
8471	+
8472	+ /* Mask all TAHVO interrupts */
8473	+ tahvo_write_reg(TAHVO_REG_IMR, 0xffff);
8474	+
8475	+ ret = request_irq(gpio_to_irq(tahvo_irq_pin), tahvo_irq_handler, 0,
8476	+ "tahvo", 0);
8477	+ if (ret < 0) {
8478	+ printk(KERN_ERR PFX "Unable to register IRQ handler\n");
8479	+ gpio_free(tahvo_irq_pin);
8480	+ return ret;
8481	+ }
8482	+#ifdef CONFIG_CBUS_TAHVO_USER
8483	+ /* Initialize user-space interface */
8484	+ if (tahvo_user_init() < 0) {
8485	+ printk(KERN_ERR "Unable to initialize driver\n");
8486	+ free_irq(gpio_to_irq(tahvo_irq_pin), 0);
8487	+ gpio_free(tahvo_irq_pin);
8488	+ return ret;
8489	+ }
8490	+#endif
8491	+ return 0;
8492	+}
8493	+
8494	+static int tahvo_remove(struct device *dev)
8495	+{
8496	+#ifdef CONFIG_CBUS_TAHVO_USER
8497	+ tahvo_user_cleanup();
8498	+#endif
8499	+ /* Mask all TAHVO interrupts */
8500	+ tahvo_write_reg(TAHVO_REG_IMR, 0xffff);
8501	+ free_irq(gpio_to_irq(tahvo_irq_pin), 0);
8502	+ gpio_free(tahvo_irq_pin);
8503	+ tasklet_kill(&tahvo_tasklet);
8504	+
8505	+ return 0;
8506	+}
8507	+
8508	+static void tahvo_device_release(struct device *dev)
8509	+{
8510	+ complete(&device_release);
8511	+}
8512	+
8513	+static struct device_driver tahvo_driver = {
8514	+ .name = "tahvo",
8515	+ .bus = &platform_bus_type,
8516	+ .probe = tahvo_probe,
8517	+ .remove = tahvo_remove,
8518	+};
8519	+
8520	+static struct platform_device tahvo_device = {
8521	+ .name = "tahvo",
8522	+ .id = -1,
8523	+ .dev = {
8524	+ .release = tahvo_device_release,
8525	+ }
8526	+};
8527	+
8528	+/**
8529	+ * tahvo_init - initialise Tahvo driver
8530	+ *
8531	+ * Initialise the Tahvo driver and return 0 if everything worked ok
8532	+ */
8533	+static int __init tahvo_init(void)
8534	+{
8535	+ int ret = 0;
8536	+
8537	+ printk(KERN_INFO "Tahvo/Betty driver initialising\n");
8538	+
8539	+ init_completion(&device_release);
8540	+
8541	+ if ((ret = driver_register(&tahvo_driver)) < 0)
8542	+ return ret;
8543	+
8544	+ if ((ret = platform_device_register(&tahvo_device)) < 0) {
8545	+ driver_unregister(&tahvo_driver);
8546	+ return ret;
8547	+ }
8548	+ return 0;
8549	+}
8550	+
8551	+/*
8552	+ * Cleanup
8553	+ */
8554	+static void __exit tahvo_exit(void)
8555	+{
8556	+ platform_device_unregister(&tahvo_device);
8557	+ driver_unregister(&tahvo_driver);
8558	+ wait_for_completion(&device_release);
8559	+}
8560	+
8561	+EXPORT_SYMBOL(tahvo_request_irq);
8562	+EXPORT_SYMBOL(tahvo_free_irq);
8563	+EXPORT_SYMBOL(tahvo_enable_irq);
8564	+EXPORT_SYMBOL(tahvo_disable_irq);
8565	+EXPORT_SYMBOL(tahvo_ack_irq);
8566	+EXPORT_SYMBOL(tahvo_read_reg);
8567	+EXPORT_SYMBOL(tahvo_write_reg);
8568	+EXPORT_SYMBOL(tahvo_get_backlight_level);
8569	+EXPORT_SYMBOL(tahvo_get_max_backlight_level);
8570	+EXPORT_SYMBOL(tahvo_set_backlight_level);
8571	+
8572	+subsys_initcall(tahvo_init);
8573	+module_exit(tahvo_exit);
8574	+
8575	+MODULE_DESCRIPTION("Tahvo ASIC control");
8576	+MODULE_LICENSE("GPL");
8577	+MODULE_AUTHOR("Juha Yrj�l�, David Weinehall, and Mikko Ylinen");
8578	--- /dev/null
8579	+++ b/drivers/cbus/tahvo.h
8580	@@ -0,0 +1,61 @@
8581	+/*
8582	+ * drivers/cbus/tahvo.h
8583	+ *
8584	+ * Copyright (C) 2004, 2005 Nokia Corporation
8585	+ *
8586	+ * Written by Juha Yrj�l� <juha.yrjola@nokia.com> and
8587	+ * David Weinehall <david.weinehall@nokia.com>
8588	+ *
8589	+ * This file is subject to the terms and conditions of the GNU General
8590	+ * Public License. See the file "COPYING" in the main directory of this
8591	+ * archive for more details.
8592	+ *
8593	+ * This program is distributed in the hope that it will be useful,
8594	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
8595	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8596	+ * GNU General Public License for more details.
8597	+
8598	+ * You should have received a copy of the GNU General Public License
8599	+ * along with this program; if not, write to the Free Software
8600	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8601	+ */
8602	+
8603	+#ifndef __DRIVERS_CBUS_TAHVO_H
8604	+#define __DRIVERS_CBUS_TAHVO_H
8605	+
8606	+#include <linux/types.h>
8607	+
8608	+/* Registers */
8609	+#define TAHVO_REG_ASICR 0x00 /* ASIC ID & revision */
8610	+#define TAHVO_REG_IDR 0x01 /* Interrupt ID */
8611	+#define TAHVO_REG_IDSR 0x02 /* Interrupt status */
8612	+#define TAHVO_REG_IMR 0x03 /* Interrupt mask */
8613	+#define TAHVO_REG_LEDPWMR 0x05 /* LED PWM */
8614	+#define TAHVO_REG_USBR 0x06 /* USB control */
8615	+#define TAHVO_REG_MAX 0x0d
8616	+
8617	+/* Interrupt sources */
8618	+#define TAHVO_INT_VBUSON 0
8619	+
8620	+#define MAX_TAHVO_IRQ_HANDLERS 8
8621	+
8622	+int tahvo_read_reg(int reg);
8623	+void tahvo_write_reg(int reg, u16 val);
8624	+void tahvo_set_clear_reg_bits(int reg, u16 set, u16 clear);
8625	+int tahvo_request_irq(int id, void irq_handler, unsigned long arg, char name);
8626	+void tahvo_free_irq(int id);
8627	+void tahvo_enable_irq(int id);
8628	+void tahvo_disable_irq(int id);
8629	+void tahvo_ack_irq(int id);
8630	+int tahvo_get_backlight_level(void);
8631	+int tahvo_get_max_backlight_level(void);
8632	+void tahvo_set_backlight_level(int level);
8633	+
8634	+#ifdef CONFIG_CBUS_TAHVO_USER
8635	+int tahvo_user_init(void);
8636	+void tahvo_user_cleanup(void);
8637	+#endif
8638	+
8639	+extern spinlock_t tahvo_lock;
8640	+
8641	+#endif /* __DRIVERS_CBUS_TAHVO_H */
8642	--- /dev/null
8643	+++ b/drivers/cbus/user_retu_tahvo.h
8644	@@ -0,0 +1,75 @@
8645	+/**
8646	+ * drivers/cbus/user_retu_tahvo.h
8647	+ *
8648	+ * Copyright (C) 2004, 2005 Nokia Corporation
8649	+ *
8650	+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
8651	+ *
8652	+ * Definitions and types used by both retu-user and tahvo-user.
8653	+ *
8654	+ * This file is subject to the terms and conditions of the GNU General
8655	+ * Public License. See the file "COPYING" in the main directory of this
8656	+ * archive for more details.
8657	+ *
8658	+ * This program is distributed in the hope that it will be useful,
8659	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
8660	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8661	+ * GNU General Public License for more details.
8662	+
8663	+ * You should have received a copy of the GNU General Public License
8664	+ * along with this program; if not, write to the Free Software
8665	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8666	+ */
8667	+
8668	+#ifndef _USER_RETU_TAHVO_H
8669	+#define _USER_RETU_TAHVO_H
8670	+
8671	+/* Chip IDs */
8672	+#define CHIP_RETU 1
8673	+#define CHIP_TAHVO 2
8674	+
8675	+/* Register access type bits */
8676	+#define READ_ONLY 1
8677	+#define WRITE_ONLY 2
8678	+#define READ_WRITE 3
8679	+#define TOGGLE 4
8680	+
8681	+#define MASK(field) ((u16)(field & 0xFFFF))
8682	+#define REG(field) ((u16)((field >> 16) & 0x3F))
8683	+
8684	+/* IOCTL definitions. These should be kept in sync with user space ********/
8685	+
8686	+#define URT_IOC_MAGIC '`'
8687	+
8688	+/*
8689	+ * IOCTL function naming conventions:
8690	+ * ==================================
8691	+ * 0 -- No argument and return value
8692	+ * S -- Set through a pointer
8693	+ * T -- Tell directly with the argument value
8694	+ * G -- Reply by setting through a pointer
8695	+ * Q -- response is on the return value
8696	+ * X -- S and G atomically
8697	+ * H -- T and Q atomically
8698	+ */
8699	+
8700	+/* General */
8701	+#define URT_IOCT_IRQ_SUBSCR _IO(URT_IOC_MAGIC, 0)
8702	+
8703	+/* RETU */
8704	+#define RETU_IOCH_READ _IO(URT_IOC_MAGIC, 1)
8705	+#define RETU_IOCX_WRITE _IO(URT_IOC_MAGIC, 2)
8706	+#define RETU_IOCH_ADC_READ _IO(URT_IOC_MAGIC, 3)
8707	+
8708	+/* TAHVO */
8709	+#define TAHVO_IOCH_READ _IO(URT_IOC_MAGIC, 4)
8710	+#define TAHVO_IOCX_WRITE _IO(URT_IOC_MAGIC, 5)
8711	+
8712	+/* This structure is used for writing RETU/TAHVO registers */
8713	+struct retu_tahvo_write_parms {
8714	+ u32 field;
8715	+ u16 value;
8716	+ u8 result;
8717	+};
8718	+
8719	+#endif
8720	--- a/drivers/spi/omap_uwire.c
8721	+++ b/drivers/spi/omap_uwire.c
8722	@@ -52,7 +52,7 @@
8723	#include <asm/mach-types.h>
8724
8725	#include <mach/mux.h>
8726	-#include <mach/omap730.h> /* OMAP730_IO_CONF registers */
8727	+#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
8728
8729
8730	/* FIXME address is now a platform device resource,
8731	@@ -504,7 +504,7 @@ static int __init uwire_probe(struct pla
8732	}
8733	clk_enable(uwire->ck);
8734
8735	- if (cpu_is_omap730())
8736	+ if (cpu_is_omap7xx())
8737	uwire_idx_shift = 1;
8738	else
8739	uwire_idx_shift = 2;
8740	@@ -573,8 +573,8 @@ static int __init omap_uwire_init(void)
8741	}
8742	if (machine_is_omap_perseus2()) {
8743	/* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
8744	- int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000;
8745	- omap_writel(val \| 0x00AAA000, OMAP730_IO_CONF_9);
8746	+ int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
8747	+ omap_writel(val \| 0x00AAA000, OMAP7XX_IO_CONF_9);
8748	}
8749
8750	return platform_driver_probe(&uwire_driver, uwire_probe);
8751	--- a/drivers/usb/Kconfig
8752	+++ b/drivers/usb/Kconfig
8753	@@ -60,6 +60,7 @@ config USB_ARCH_HAS_EHCI
8754	default y if ARCH_IXP4XX
8755	default y if ARCH_W90X900
8756	default y if ARCH_AT91SAM9G45
8757	+ default y if ARCH_OMAP34XX
8758	default PCI
8759
8760	# ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
8761	--- a/drivers/usb/host/ehci-hcd.c
8762	+++ b/drivers/usb/host/ehci-hcd.c
8763	@@ -1111,6 +1111,11 @@ MODULE_LICENSE ("GPL");
8764	#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
8765	#endif
8766
8767	+#ifdef CONFIG_ARCH_OMAP34XX
8768	+#include "ehci-omap.c"
8769	+#define PLATFORM_DRIVER ehci_hcd_omap_driver
8770	+#endif
8771	+
8772	#ifdef CONFIG_PPC_PS3
8773	#include "ehci-ps3.c"
8774	#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
8775	--- /dev/null
8776	+++ b/drivers/usb/host/ehci-omap.c
8777	@@ -0,0 +1,755 @@
8778	+/*
8779	+ * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
8780	+ *
8781	+ * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
8782	+ * Tested on OMAP3430 ES2.0 SDP
8783	+ *
8784	+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
8785	+ * Author: Vikram Pandita <vikram.pandita@ti.com>
8786	+ *
8787	+ * Copyright (C) 2009 Nokia Corporation
8788	+ * Contact: Felipe Balbi <felipe.balbi@nokia.com>
8789	+ *
8790	+ * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
8791	+ *
8792	+ * This program is free software; you can redistribute it and/or modify
8793	+ * it under the terms of the GNU General Public License as published by
8794	+ * the Free Software Foundation; either version 2 of the License, or
8795	+ * (at your option) any later version.
8796	+ *
8797	+ * This program is distributed in the hope that it will be useful,
8798	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
8799	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8800	+ * GNU General Public License for more details.
8801	+ *
8802	+ * You should have received a copy of the GNU General Public License
8803	+ * along with this program; if not, write to the Free Software
8804	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8805	+ *
8806	+ * TODO (last updated Feb 23rd, 2009):
8807	+ * - add kernel-doc
8808	+ * - enable AUTOIDLE
8809	+ * - move DPLL5 programming to clock fw
8810	+ * - add suspend/resume
8811	+ * - move workarounds to board-files
8812	+ */
8813	+
8814	+#include <linux/platform_device.h>
8815	+#include <linux/clk.h>
8816	+#include <linux/gpio.h>
8817	+#include <mach/usb.h>
8818	+
8819	+/*
8820	+ * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
8821	+ * Use ehci_omap_readl()/ehci_omap_writel() functions
8822	+ */
8823	+
8824	+/* TLL Register Set */
8825	+#define OMAP_USBTLL_REVISION (0x00)
8826	+#define OMAP_USBTLL_SYSCONFIG (0x10)
8827	+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
8828	+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
8829	+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
8830	+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
8831	+#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
8832	+
8833	+#define OMAP_USBTLL_SYSSTATUS (0x14)
8834	+#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
8835	+
8836	+#define OMAP_USBTLL_IRQSTATUS (0x18)
8837	+#define OMAP_USBTLL_IRQENABLE (0x1C)
8838	+
8839	+#define OMAP_TLL_SHARED_CONF (0x30)
8840	+#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
8841	+#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
8842	+#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
8843	+#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
8844	+#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
8845	+
8846	+#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
8847	+#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
8848	+#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
8849	+#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
8850	+#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
8851	+#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
8852	+
8853	+#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
8854	+#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
8855	+#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
8856	+#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
8857	+#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
8858	+#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
8859	+#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
8860	+#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
8861	+#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
8862	+
8863	+#define OMAP_TLL_CHANNEL_COUNT 3
8864	+#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1)
8865	+#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2)
8866	+#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4)
8867	+
8868	+/* UHH Register Set */
8869	+#define OMAP_UHH_REVISION (0x00)
8870	+#define OMAP_UHH_SYSCONFIG (0x10)
8871	+#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
8872	+#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
8873	+#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
8874	+#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
8875	+#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
8876	+#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
8877	+
8878	+#define OMAP_UHH_SYSSTATUS (0x14)
8879	+#define OMAP_UHH_HOSTCONFIG (0x40)
8880	+#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
8881	+#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
8882	+#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
8883	+#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
8884	+#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
8885	+#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
8886	+#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
8887	+#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
8888	+#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
8889	+#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
8890	+#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
8891	+
8892	+#define OMAP_UHH_DEBUG_CSR (0x44)
8893	+
8894	+/* EHCI Register Set */
8895	+#define EHCI_INSNREG05_ULPI (0xA4)
8896	+#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31
8897	+#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24
8898	+#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22
8899	+#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16
8900	+#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8
8901	+#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0
8902	+
8903	+/-------------------------------------------------------------------------/
8904	+
8905	+static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val)
8906	+{
8907	+ __raw_writel(val, base + reg);
8908	+}
8909	+
8910	+static inline u32 ehci_omap_readl(void __iomem *base, u32 reg)
8911	+{
8912	+ return __raw_readl(base + reg);
8913	+}
8914	+
8915	+static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val)
8916	+{
8917	+ __raw_writeb(val, base + reg);
8918	+}
8919	+
8920	+static inline u8 ehci_omap_readb(void __iomem *base, u8 reg)
8921	+{
8922	+ return __raw_readb(base + reg);
8923	+}
8924	+
8925	+/-------------------------------------------------------------------------/
8926	+
8927	+struct ehci_hcd_omap {
8928	+ struct ehci_hcd *ehci;
8929	+ struct device *dev;
8930	+
8931	+ struct clk *usbhost_ick;
8932	+ struct clk *usbhost2_120m_fck;
8933	+ struct clk *usbhost1_48m_fck;
8934	+ struct clk *usbtll_fck;
8935	+ struct clk *usbtll_ick;
8936	+
8937	+ /* FIXME the following two workarounds are
8938	+ * board specific not silicon-specific so these
8939	+ * should be moved to board-file instead.
8940	+ *
8941	+ * Maybe someone from TI will know better which
8942	+ * board is affected and needs the workarounds
8943	+ * to be applied
8944	+ */
8945	+
8946	+ /* gpio for resetting phy */
8947	+ int reset_gpio_port[OMAP3_HS_USB_PORTS];
8948	+
8949	+ /* phy reset workaround */
8950	+ int phy_reset;
8951	+
8952	+ /* desired phy_mode: TLL, PHY */
8953	+ enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
8954	+
8955	+ void __iomem *uhh_base;
8956	+ void __iomem *tll_base;
8957	+ void __iomem *ehci_base;
8958	+};
8959	+
8960	+/-------------------------------------------------------------------------/
8961	+
8962	+static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask)
8963	+{
8964	+ unsigned reg;
8965	+ int i;
8966	+
8967	+ /* Program the 3 TLL channels upfront */
8968	+ for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
8969	+ reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
8970	+
8971	+ /* Disable AutoIdle, BitStuffing and use SDR Mode */
8972	+ reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
8973	+ \| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
8974	+ \| OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
8975	+ ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
8976	+ }
8977	+
8978	+ /* Program Common TLL register */
8979	+ reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
8980	+ reg \|= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
8981	+ \| OMAP_TLL_SHARED_CONF_USB_DIVRATION
8982	+ \| OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
8983	+ reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
8984	+
8985	+ ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
8986	+
8987	+ /* Enable channels now */
8988	+ for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
8989	+ reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
8990	+
8991	+ /* Enable only the reg that is needed */
8992	+ if (!(tll_channel_mask & 1<<i))
8993	+ continue;
8994	+
8995	+ reg \|= OMAP_TLL_CHANNEL_CONF_CHANEN;
8996	+ ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
8997	+
8998	+ ehci_omap_writeb(omap->tll_base,
8999	+ OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
9000	+ dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
9001	+ i+1, ehci_omap_readb(omap->tll_base,
9002	+ OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
9003	+ }
9004	+}
9005	+
9006	+/-------------------------------------------------------------------------/
9007	+
9008	+/* omap_start_ehc
9009	+ * - Start the TI USBHOST controller
9010	+ */
9011	+static int omap_start_ehc(struct ehci_hcd_omap omap, struct usb_hcd hcd)
9012	+{
9013	+ unsigned long timeout = jiffies + msecs_to_jiffies(1000);
9014	+ u8 tll_ch_mask = 0;
9015	+ unsigned reg = 0;
9016	+ int ret = 0;
9017	+
9018	+ dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
9019	+
9020	+ /* Enable Clocks for USBHOST */
9021	+ omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
9022	+ if (IS_ERR(omap->usbhost_ick)) {
9023	+ ret = PTR_ERR(omap->usbhost_ick);
9024	+ goto err_host_ick;
9025	+ }
9026	+ clk_enable(omap->usbhost_ick);
9027	+
9028	+ omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck");
9029	+ if (IS_ERR(omap->usbhost2_120m_fck)) {
9030	+ ret = PTR_ERR(omap->usbhost2_120m_fck);
9031	+ goto err_host_120m_fck;
9032	+ }
9033	+ clk_enable(omap->usbhost2_120m_fck);
9034	+
9035	+ omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck");
9036	+ if (IS_ERR(omap->usbhost1_48m_fck)) {
9037	+ ret = PTR_ERR(omap->usbhost1_48m_fck);
9038	+ goto err_host_48m_fck;
9039	+ }
9040	+ clk_enable(omap->usbhost1_48m_fck);
9041	+
9042	+ if (omap->phy_reset) {
9043	+ /* Refer: ISSUE1 */
9044	+ if (gpio_is_valid(omap->reset_gpio_port[0])) {
9045	+ gpio_request(omap->reset_gpio_port[0],
9046	+ "USB1 PHY reset");
9047	+ gpio_direction_output(omap->reset_gpio_port[0], 0);
9048	+ }
9049	+
9050	+ if (gpio_is_valid(omap->reset_gpio_port[1])) {
9051	+ gpio_request(omap->reset_gpio_port[1],
9052	+ "USB2 PHY reset");
9053	+ gpio_direction_output(omap->reset_gpio_port[1], 0);
9054	+ }
9055	+
9056	+ /* Hold the PHY in RESET for enough time till DIR is high */
9057	+ udelay(10);
9058	+ }
9059	+
9060	+ /* Configure TLL for 60Mhz clk for ULPI */
9061	+ omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
9062	+ if (IS_ERR(omap->usbtll_fck)) {
9063	+ ret = PTR_ERR(omap->usbtll_fck);
9064	+ goto err_tll_fck;
9065	+ }
9066	+ clk_enable(omap->usbtll_fck);
9067	+
9068	+ omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
9069	+ if (IS_ERR(omap->usbtll_ick)) {
9070	+ ret = PTR_ERR(omap->usbtll_ick);
9071	+ goto err_tll_ick;
9072	+ }
9073	+ clk_enable(omap->usbtll_ick);
9074	+
9075	+ /* perform TLL soft reset, and wait until reset is complete */
9076	+ ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
9077	+ OMAP_USBTLL_SYSCONFIG_SOFTRESET);
9078	+
9079	+ /* Wait for TLL reset to complete */
9080	+ while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
9081	+ & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
9082	+ cpu_relax();
9083	+
9084	+ if (time_after(jiffies, timeout)) {
9085	+ dev_dbg(omap->dev, "operation timed out\n");
9086	+ ret = -EINVAL;
9087	+ goto err_sys_status;
9088	+ }
9089	+ }
9090	+
9091	+ dev_dbg(omap->dev, "TLL RESET DONE\n");
9092	+
9093	+ /* (1<<3) = no idle mode only for initial debugging */
9094	+ ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
9095	+ OMAP_USBTLL_SYSCONFIG_ENAWAKEUP \|
9096	+ OMAP_USBTLL_SYSCONFIG_SIDLEMODE \|
9097	+ OMAP_USBTLL_SYSCONFIG_CACTIVITY);
9098	+
9099	+
9100	+ /* Put UHH in NoIdle/NoStandby mode */
9101	+ reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
9102	+ reg \|= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
9103	+ \| OMAP_UHH_SYSCONFIG_SIDLEMODE
9104	+ \| OMAP_UHH_SYSCONFIG_CACTIVITY
9105	+ \| OMAP_UHH_SYSCONFIG_MIDLEMODE);
9106	+ reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
9107	+
9108	+ ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
9109	+
9110	+ reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
9111	+
9112	+ /* setup ULPI bypass and burst configurations */
9113	+ reg \|= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
9114	+ \| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
9115	+ \| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
9116	+ reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
9117	+
9118	+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
9119	+ reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
9120	+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
9121	+ reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
9122	+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
9123	+ reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
9124	+
9125	+ /* Bypass the TLL module for PHY mode operation */
9126	+ if (omap_rev() <= OMAP3430_REV_ES2_1) {
9127	+ dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1 \n");
9128	+ if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) \|\|
9129	+ (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) \|\|
9130	+ (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
9131	+ reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
9132	+ else
9133	+ reg \|= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
9134	+ } else {
9135	+ dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
9136	+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
9137	+ reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
9138	+ else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
9139	+ reg \|= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
9140	+
9141	+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
9142	+ reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
9143	+ else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
9144	+ reg \|= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
9145	+
9146	+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
9147	+ reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
9148	+ else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
9149	+ reg \|= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
9150	+
9151	+ }
9152	+ ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
9153	+ dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
9154	+
9155	+
9156	+ if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) \|\|
9157	+ (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) \|\|
9158	+ (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
9159	+
9160	+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
9161	+ tll_ch_mask \|= OMAP_TLL_CHANNEL_1_EN_MASK;
9162	+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
9163	+ tll_ch_mask \|= OMAP_TLL_CHANNEL_2_EN_MASK;
9164	+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
9165	+ tll_ch_mask \|= OMAP_TLL_CHANNEL_3_EN_MASK;
9166	+
9167	+ /* Enable UTMI mode for required TLL channels */
9168	+ omap_usb_utmi_init(omap, tll_ch_mask);
9169	+ }
9170	+
9171	+ if (omap->phy_reset) {
9172	+ /* Refer ISSUE1:
9173	+ * Hold the PHY in RESET for enough time till
9174	+ * PHY is settled and ready
9175	+ */
9176	+ udelay(10);
9177	+
9178	+ if (gpio_is_valid(omap->reset_gpio_port[0]))
9179	+ gpio_set_value(omap->reset_gpio_port[0], 1);
9180	+
9181	+ if (gpio_is_valid(omap->reset_gpio_port[1]))
9182	+ gpio_set_value(omap->reset_gpio_port[1], 1);
9183	+ }
9184	+
9185	+ return 0;
9186	+
9187	+err_sys_status:
9188	+ clk_disable(omap->usbtll_ick);
9189	+ clk_put(omap->usbtll_ick);
9190	+
9191	+err_tll_ick:
9192	+ clk_disable(omap->usbtll_fck);
9193	+ clk_put(omap->usbtll_fck);
9194	+
9195	+err_tll_fck:
9196	+ clk_disable(omap->usbhost1_48m_fck);
9197	+ clk_put(omap->usbhost1_48m_fck);
9198	+
9199	+ if (omap->phy_reset) {
9200	+ if (gpio_is_valid(omap->reset_gpio_port[0]))
9201	+ gpio_free(omap->reset_gpio_port[0]);
9202	+
9203	+ if (gpio_is_valid(omap->reset_gpio_port[1]))
9204	+ gpio_free(omap->reset_gpio_port[1]);
9205	+ }
9206	+
9207	+err_host_48m_fck:
9208	+ clk_disable(omap->usbhost2_120m_fck);
9209	+ clk_put(omap->usbhost2_120m_fck);
9210	+
9211	+err_host_120m_fck:
9212	+ clk_disable(omap->usbhost_ick);
9213	+ clk_put(omap->usbhost_ick);
9214	+
9215	+err_host_ick:
9216	+ return ret;
9217	+}
9218	+
9219	+static void omap_stop_ehc(struct ehci_hcd_omap omap, struct usb_hcd hcd)
9220	+{
9221	+ unsigned long timeout = jiffies + msecs_to_jiffies(100);
9222	+
9223	+ dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
9224	+
9225	+ /* Reset OMAP modules for insmod/rmmod to work */
9226	+ ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
9227	+ OMAP_UHH_SYSCONFIG_SOFTRESET);
9228	+ while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
9229	+ & (1 << 0))) {
9230	+ cpu_relax();
9231	+
9232	+ if (time_after(jiffies, timeout))
9233	+ dev_dbg(omap->dev, "operation timed out\n");
9234	+ }
9235	+
9236	+ while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
9237	+ & (1 << 1))) {
9238	+ cpu_relax();
9239	+
9240	+ if (time_after(jiffies, timeout))
9241	+ dev_dbg(omap->dev, "operation timed out\n");
9242	+ }
9243	+
9244	+ while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
9245	+ & (1 << 2))) {
9246	+ cpu_relax();
9247	+
9248	+ if (time_after(jiffies, timeout))
9249	+ dev_dbg(omap->dev, "operation timed out\n");
9250	+ }
9251	+
9252	+ ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
9253	+
9254	+ while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
9255	+ & (1 << 0))) {
9256	+ cpu_relax();
9257	+
9258	+ if (time_after(jiffies, timeout))
9259	+ dev_dbg(omap->dev, "operation timed out\n");
9260	+ }
9261	+
9262	+ if (omap->usbtll_fck != NULL) {
9263	+ clk_disable(omap->usbtll_fck);
9264	+ clk_put(omap->usbtll_fck);
9265	+ omap->usbtll_fck = NULL;
9266	+ }
9267	+
9268	+ if (omap->usbhost_ick != NULL) {
9269	+ clk_disable(omap->usbhost_ick);
9270	+ clk_put(omap->usbhost_ick);
9271	+ omap->usbhost_ick = NULL;
9272	+ }
9273	+
9274	+ if (omap->usbhost1_48m_fck != NULL) {
9275	+ clk_disable(omap->usbhost1_48m_fck);
9276	+ clk_put(omap->usbhost1_48m_fck);
9277	+ omap->usbhost1_48m_fck = NULL;
9278	+ }
9279	+
9280	+ if (omap->usbhost2_120m_fck != NULL) {
9281	+ clk_disable(omap->usbhost2_120m_fck);
9282	+ clk_put(omap->usbhost2_120m_fck);
9283	+ omap->usbhost2_120m_fck = NULL;
9284	+ }
9285	+
9286	+ if (omap->usbtll_ick != NULL) {
9287	+ clk_disable(omap->usbtll_ick);
9288	+ clk_put(omap->usbtll_ick);
9289	+ omap->usbtll_ick = NULL;
9290	+ }
9291	+
9292	+ if (omap->phy_reset) {
9293	+ if (gpio_is_valid(omap->reset_gpio_port[0]))
9294	+ gpio_free(omap->reset_gpio_port[0]);
9295	+
9296	+ if (gpio_is_valid(omap->reset_gpio_port[1]))
9297	+ gpio_free(omap->reset_gpio_port[1]);
9298	+ }
9299	+
9300	+ dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
9301	+}
9302	+
9303	+/-------------------------------------------------------------------------/
9304	+
9305	+static const struct hc_driver ehci_omap_hc_driver;
9306	+
9307	+/* configure so an HC device and id are always provided */
9308	+/* always called with process context; sleeping is OK */
9309	+
9310	+/**
9311	+ * ehci_hcd_omap_probe - initialize TI-based HCDs
9312	+ *
9313	+ * Allocates basic resources for this USB host controller, and
9314	+ * then invokes the start() method for the HCD associated with it
9315	+ * through the hotplug entry's driver_data.
9316	+ */
9317	+static int ehci_hcd_omap_probe(struct platform_device *pdev)
9318	+{
9319	+ struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data;
9320	+ struct ehci_hcd_omap *omap;
9321	+ struct resource *res;
9322	+ struct usb_hcd *hcd;
9323	+
9324	+ int irq = platform_get_irq(pdev, 0);
9325	+ int ret = -ENODEV;
9326	+
9327	+ if (!pdata) {
9328	+ dev_dbg(&pdev->dev, "missing platform_data\n");
9329	+ goto err_pdata;
9330	+ }
9331	+
9332	+ if (usb_disabled())
9333	+ goto err_disabled;
9334	+
9335	+ omap = kzalloc(sizeof(*omap), GFP_KERNEL);
9336	+ if (!omap) {
9337	+ ret = -ENOMEM;
9338	+ goto err_create_hcd;
9339	+ }
9340	+
9341	+ hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev,
9342	+ dev_name(&pdev->dev));
9343	+ if (!hcd) {
9344	+ dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret);
9345	+ ret = -ENOMEM;
9346	+ goto err_create_hcd;
9347	+ }
9348	+
9349	+ platform_set_drvdata(pdev, omap);
9350	+ omap->dev = &pdev->dev;
9351	+ omap->phy_reset = pdata->phy_reset;
9352	+ omap->reset_gpio_port[0] = pdata->reset_gpio_port[0];
9353	+ omap->reset_gpio_port[1] = pdata->reset_gpio_port[1];
9354	+ omap->reset_gpio_port[2] = pdata->reset_gpio_port[2];
9355	+ omap->port_mode[0] = pdata->port_mode[0];
9356	+ omap->port_mode[1] = pdata->port_mode[1];
9357	+ omap->port_mode[2] = pdata->port_mode[2];
9358	+ omap->ehci = hcd_to_ehci(hcd);
9359	+ omap->ehci->sbrn = 0x20;
9360	+
9361	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9362	+
9363	+ hcd->rsrc_start = res->start;
9364	+ hcd->rsrc_len = resource_size(res);
9365	+
9366	+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
9367	+ if (!hcd->regs) {
9368	+ dev_err(&pdev->dev, "EHCI ioremap failed\n");
9369	+ ret = -ENOMEM;
9370	+ goto err_ioremap;
9371	+ }
9372	+
9373	+ /* we know this is the memory we want, no need to ioremap again */
9374	+ omap->ehci->caps = hcd->regs;
9375	+ omap->ehci_base = hcd->regs;
9376	+
9377	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9378	+ omap->uhh_base = ioremap(res->start, resource_size(res));
9379	+ if (!omap->uhh_base) {
9380	+ dev_err(&pdev->dev, "UHH ioremap failed\n");
9381	+ ret = -ENOMEM;
9382	+ goto err_uhh_ioremap;
9383	+ }
9384	+
9385	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
9386	+ omap->tll_base = ioremap(res->start, resource_size(res));
9387	+ if (!omap->tll_base) {
9388	+ dev_err(&pdev->dev, "TLL ioremap failed\n");
9389	+ ret = -ENOMEM;
9390	+ goto err_tll_ioremap;
9391	+ }
9392	+
9393	+ ret = omap_start_ehc(omap, hcd);
9394	+ if (ret) {
9395	+ dev_dbg(&pdev->dev, "failed to start ehci\n");
9396	+ goto err_start;
9397	+ }
9398	+
9399	+ omap->ehci->regs = hcd->regs
9400	+ + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase));
9401	+
9402	+ /* cache this readonly data; minimize chip reads */
9403	+ omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params);
9404	+
9405	+ /* SET 1 micro-frame Interrupt interval */
9406	+ writel(readl(&omap->ehci->regs->command) \| (1 << 16),
9407	+ &omap->ehci->regs->command);
9408	+
9409	+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED \| IRQF_SHARED);
9410	+ if (ret) {
9411	+ dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
9412	+ goto err_add_hcd;
9413	+ }
9414	+
9415	+ return 0;
9416	+
9417	+err_add_hcd:
9418	+ omap_stop_ehc(omap, hcd);
9419	+
9420	+err_start:
9421	+ iounmap(omap->tll_base);
9422	+
9423	+err_tll_ioremap:
9424	+ iounmap(omap->uhh_base);
9425	+
9426	+err_uhh_ioremap:
9427	+ iounmap(hcd->regs);
9428	+
9429	+err_ioremap:
9430	+ usb_put_hcd(hcd);
9431	+
9432	+err_create_hcd:
9433	+err_disabled:
9434	+err_pdata:
9435	+ return ret;
9436	+}
9437	+
9438	+/* may be called without controller electrically present */
9439	+/* may be called with controller, bus, and devices active */
9440	+
9441	+/**
9442	+ * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs
9443	+ * @pdev: USB Host Controller being removed
9444	+ *
9445	+ * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
9446	+ * the HCD's stop() method. It is always called from a thread
9447	+ * context, normally "rmmod", "apmd", or something similar.
9448	+ */
9449	+static int ehci_hcd_omap_remove(struct platform_device *pdev)
9450	+{
9451	+ struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
9452	+ struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
9453	+
9454	+ usb_remove_hcd(hcd);
9455	+ omap_stop_ehc(omap, hcd);
9456	+ iounmap(hcd->regs);
9457	+ iounmap(omap->tll_base);
9458	+ iounmap(omap->uhh_base);
9459	+ usb_put_hcd(hcd);
9460	+
9461	+ return 0;
9462	+}
9463	+
9464	+static void ehci_hcd_omap_shutdown(struct platform_device *pdev)
9465	+{
9466	+ struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
9467	+ struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
9468	+
9469	+ if (hcd->driver->shutdown)
9470	+ hcd->driver->shutdown(hcd);
9471	+}
9472	+
9473	+static struct platform_driver ehci_hcd_omap_driver = {
9474	+ .probe = ehci_hcd_omap_probe,
9475	+ .remove = ehci_hcd_omap_remove,
9476	+ .shutdown = ehci_hcd_omap_shutdown,
9477	+ /.suspend = ehci_hcd_omap_suspend, /
9478	+ /.resume = ehci_hcd_omap_resume, /
9479	+ .driver = {
9480	+ .name = "ehci-omap",
9481	+ }
9482	+};
9483	+
9484	+/-------------------------------------------------------------------------/
9485	+
9486	+static const struct hc_driver ehci_omap_hc_driver = {
9487	+ .description = hcd_name,
9488	+ .product_desc = "OMAP-EHCI Host Controller",
9489	+ .hcd_priv_size = sizeof(struct ehci_hcd),
9490	+
9491	+ /*
9492	+ * generic hardware linkage
9493	+ */
9494	+ .irq = ehci_irq,
9495	+ .flags = HCD_MEMORY \| HCD_USB2,
9496	+
9497	+ /*
9498	+ * basic lifecycle operations
9499	+ */
9500	+ .reset = ehci_init,
9501	+ .start = ehci_run,
9502	+ .stop = ehci_stop,
9503	+ .shutdown = ehci_shutdown,
9504	+
9505	+ /*
9506	+ * managing i/o requests and associated device resources
9507	+ */
9508	+ .urb_enqueue = ehci_urb_enqueue,
9509	+ .urb_dequeue = ehci_urb_dequeue,
9510	+ .endpoint_disable = ehci_endpoint_disable,
9511	+ .endpoint_reset = ehci_endpoint_reset,
9512	+
9513	+ /*
9514	+ * scheduling support
9515	+ */
9516	+ .get_frame_number = ehci_get_frame,
9517	+
9518	+ /*
9519	+ * root hub support
9520	+ */
9521	+ .hub_status_data = ehci_hub_status_data,
9522	+ .hub_control = ehci_hub_control,
9523	+ .bus_suspend = ehci_bus_suspend,
9524	+ .bus_resume = ehci_bus_resume,
9525	+
9526	+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
9527	+};
9528	+
9529	+MODULE_ALIAS("platform:omap-ehci");
9530	+MODULE_AUTHOR("Texas Instruments, Inc.");
9531	+MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
9532	+
9533	--- a/drivers/video/omap/dispc.c
9534	+++ b/drivers/video/omap/dispc.c
9535	@@ -210,6 +210,7 @@ static u32 inline dispc_read_reg(int idx
9536	/* Select RFBI or bypass mode */
9537	static void enable_rfbi_mode(int enable)
9538	{
9539	+ void __iomem *rfbi_control;
9540	u32 l;
9541
9542	l = dispc_read_reg(DISPC_CONTROL);
9543	@@ -222,9 +223,15 @@ static void enable_rfbi_mode(int enable)
9544	dispc_write_reg(DISPC_CONTROL, l);
9545
9546	/* Set bypass mode in RFBI module */
9547	- l = __raw_readl(OMAP2_IO_ADDRESS(RFBI_CONTROL));
9548	+ rfbi_control = ioremap(RFBI_CONTROL, SZ_1K);
9549	+ if (!rfbi_control) {
9550	+ pr_err("Unable to ioremap rfbi_control\n");
9551	+ return;
9552	+ }
9553	+ l = __raw_readl(rfbi_control);
9554	l \|= enable ? 0 : (1 << 1);
9555	- __raw_writel(l, OMAP2_IO_ADDRESS(RFBI_CONTROL));
9556	+ __raw_writel(l, rfbi_control);
9557	+ iounmap(rfbi_control);
9558	}
9559
9560	static void set_lcd_data_lines(int data_lines)
9561	@@ -1373,6 +1380,7 @@ static int omap_dispc_init(struct omapfb
9562	int r;
9563	u32 l;
9564	struct lcd_panel *panel = fbdev->panel;
9565	+ void __iomem *ram_fw_base;
9566	int tmo = 10000;
9567	int skip_init = 0;
9568	int i;
9569	@@ -1453,7 +1461,13 @@ static int omap_dispc_init(struct omapfb
9570	}
9571
9572	/* L3 firewall setting: enable access to OCM RAM */
9573	- __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0));
9574	+ ram_fw_base = ioremap(0x68005000, SZ_1K);
9575	+ if (!ram_fw_base) {
9576	+ dev_err(dispc.fbdev->dev, "Cannot ioremap to enable OCM RAM\n");
9577	+ goto fail1;
9578	+ }
9579	+ __raw_writel(0x402000b0, ram_fw_base + 0xa0);
9580	+ iounmap(ram_fw_base);
9581
9582	if ((r = alloc_palette_ram()) < 0)
9583	goto fail2;
9584

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