| 1 | /* |
| 2 | * Ralink SoC specific GPIO support |
| 3 | * |
| 4 | * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/io.h> |
| 13 | |
| 14 | #include <asm/mach-ralink/ramips_gpio.h> |
| 15 | #include <ralink_soc.h> |
| 16 | |
| 17 | static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip) |
| 18 | { |
| 19 | struct ramips_gpio_chip *rg; |
| 20 | |
| 21 | rg = container_of(chip, struct ramips_gpio_chip, chip); |
| 22 | return rg; |
| 23 | } |
| 24 | |
| 25 | static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val) |
| 26 | { |
| 27 | __raw_writel(val, rg->regs_base + rg->regs[reg]); |
| 28 | } |
| 29 | |
| 30 | static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg) |
| 31 | { |
| 32 | return __raw_readl(rg->regs_base + rg->regs[reg]); |
| 33 | } |
| 34 | |
| 35 | static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 36 | { |
| 37 | struct ramips_gpio_chip *rg = to_ramips_gpio(chip); |
| 38 | unsigned long flags; |
| 39 | u32 t; |
| 40 | |
| 41 | spin_lock_irqsave(&rg->lock, flags); |
| 42 | t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR); |
| 43 | t &= ~(1 << offset); |
| 44 | ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t); |
| 45 | spin_unlock_irqrestore(&rg->lock, flags); |
| 46 | |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | static int ramips_gpio_direction_output(struct gpio_chip *chip, |
| 51 | unsigned offset, int value) |
| 52 | { |
| 53 | struct ramips_gpio_chip *rg = to_ramips_gpio(chip); |
| 54 | unsigned long flags; |
| 55 | u32 reg; |
| 56 | u32 t; |
| 57 | |
| 58 | reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET; |
| 59 | |
| 60 | spin_lock_irqsave(&rg->lock, flags); |
| 61 | ramips_gpio_wr(rg, reg, 1 << offset); |
| 62 | |
| 63 | t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR); |
| 64 | t |= 1 << offset; |
| 65 | ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t); |
| 66 | spin_unlock_irqrestore(&rg->lock, flags); |
| 67 | |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 72 | { |
| 73 | struct ramips_gpio_chip *rg = to_ramips_gpio(chip); |
| 74 | u32 reg; |
| 75 | |
| 76 | reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET; |
| 77 | ramips_gpio_wr(rg, reg, 1 << offset); |
| 78 | } |
| 79 | |
| 80 | static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 81 | { |
| 82 | struct ramips_gpio_chip *rg = to_ramips_gpio(chip); |
| 83 | u32 t; |
| 84 | |
| 85 | t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA); |
| 86 | return !!(t & (1 << offset)); |
| 87 | } |
| 88 | |
| 89 | static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg) |
| 90 | { |
| 91 | spin_lock_init(&rg->lock); |
| 92 | |
| 93 | rg->regs_base = ioremap(rg->map_base, rg->map_size); |
| 94 | |
| 95 | rg->chip.direction_input = ramips_gpio_direction_input; |
| 96 | rg->chip.direction_output = ramips_gpio_direction_output; |
| 97 | rg->chip.get = ramips_gpio_get; |
| 98 | rg->chip.set = ramips_gpio_set; |
| 99 | |
| 100 | /* set polarity to low for all lines */ |
| 101 | ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0); |
| 102 | |
| 103 | gpiochip_add(&rg->chip); |
| 104 | } |
| 105 | |
| 106 | __init int ramips_gpio_init(struct ramips_gpio_data *data) |
| 107 | { |
| 108 | int i; |
| 109 | |
| 110 | for (i = 0; i < data->num_chips; i++) |
| 111 | ramips_gpio_chip_add(&data->chips[i]); |
| 112 | |
| 113 | return 0; |
| 114 | } |
| 115 | |
