Root/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

1/*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16#ifndef __ASM_MACH_AR71XX_H
17#define __ASM_MACH_AR71XX_H
18
19#include <linux/types.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/bitops.h>
23
24#ifndef __ASSEMBLER__
25
26#define AR71XX_PCI_MEM_BASE 0x10000000
27#define AR71XX_PCI_MEM_SIZE 0x08000000
28#define AR71XX_APB_BASE 0x18000000
29#define AR71XX_GE0_BASE 0x19000000
30#define AR71XX_GE0_SIZE 0x01000000
31#define AR71XX_GE1_BASE 0x1a000000
32#define AR71XX_GE1_SIZE 0x01000000
33#define AR71XX_EHCI_BASE 0x1b000000
34#define AR71XX_EHCI_SIZE 0x01000000
35#define AR71XX_OHCI_BASE 0x1c000000
36#define AR71XX_OHCI_SIZE 0x01000000
37#define AR7240_OHCI_BASE 0x1b000000
38#define AR7240_OHCI_SIZE 0x01000000
39#define AR71XX_SPI_BASE 0x1f000000
40#define AR71XX_SPI_SIZE 0x01000000
41
42#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
43#define AR71XX_DDR_CTRL_SIZE 0x10000
44#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
45#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
46#define AR71XX_UART_SIZE 0x10000
47#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
48#define AR71XX_USB_CTRL_SIZE 0x10000
49#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
50#define AR71XX_GPIO_SIZE 0x10000
51#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
52#define AR71XX_PLL_SIZE 0x10000
53#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
54#define AR71XX_RESET_SIZE 0x10000
55#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
56#define AR71XX_MII_SIZE 0x10000
57#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
58#define AR71XX_SLIC_SIZE 0x10000
59#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
60#define AR71XX_DMA_SIZE 0x10000
61#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
62#define AR71XX_STEREO_SIZE 0x10000
63
64#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
65#define AR724X_PCI_CRP_SIZE 0x100
66
67#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
68#define AR724X_PCI_CTRL_SIZE 0x100
69
70#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
71#define AR91XX_WMAC_SIZE 0x30000
72
73#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
74#define AR933X_UART_SIZE 0x14
75#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
76#define AR933X_WMAC_SIZE 0x20000
77
78#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
79#define AR934X_WMAC_SIZE 0x20000
80
81#define AR71XX_MEM_SIZE_MIN 0x0200000
82#define AR71XX_MEM_SIZE_MAX 0x10000000
83
84#define AR71XX_CPU_IRQ_BASE 0
85#define AR71XX_MISC_IRQ_BASE 8
86#define AR71XX_MISC_IRQ_COUNT 32
87#define AR71XX_GPIO_IRQ_BASE 40
88#define AR71XX_GPIO_IRQ_COUNT 32
89#define AR71XX_PCI_IRQ_BASE 72
90#define AR71XX_PCI_IRQ_COUNT 8
91
92#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
93#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
94#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
95#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
96#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
97#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
98
99#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
100#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
101#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
102#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
103#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
104#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
105#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
106#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
107#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8)
108#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9)
109#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10)
110#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11)
111#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12)
112
113#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
114
115#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
116#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
117#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
118#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
119
120extern u32 ar71xx_ahb_freq;
121extern u32 ar71xx_cpu_freq;
122extern u32 ar71xx_ddr_freq;
123extern u32 ar71xx_ref_freq;
124
125enum ar71xx_soc_type {
126    AR71XX_SOC_UNKNOWN,
127    AR71XX_SOC_AR7130,
128    AR71XX_SOC_AR7141,
129    AR71XX_SOC_AR7161,
130    AR71XX_SOC_AR7240,
131    AR71XX_SOC_AR7241,
132    AR71XX_SOC_AR7242,
133    AR71XX_SOC_AR9130,
134    AR71XX_SOC_AR9132,
135    AR71XX_SOC_AR9330,
136    AR71XX_SOC_AR9331,
137    AR71XX_SOC_AR9341,
138    AR71XX_SOC_AR9342,
139    AR71XX_SOC_AR9344,
140};
141extern u32 ar71xx_soc_rev;
142
143extern enum ar71xx_soc_type ar71xx_soc;
144
145/*
146 * PLL block
147 */
148#define AR71XX_PLL_REG_CPU_CONFIG 0x00
149#define AR71XX_PLL_REG_SEC_CONFIG 0x04
150#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
151#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
152
153#define AR71XX_PLL_DIV_SHIFT 3
154#define AR71XX_PLL_DIV_MASK 0x1f
155#define AR71XX_CPU_DIV_SHIFT 16
156#define AR71XX_CPU_DIV_MASK 0x3
157#define AR71XX_DDR_DIV_SHIFT 18
158#define AR71XX_DDR_DIV_MASK 0x3
159#define AR71XX_AHB_DIV_SHIFT 20
160#define AR71XX_AHB_DIV_MASK 0x7
161
162#define AR71XX_ETH0_PLL_SHIFT 17
163#define AR71XX_ETH1_PLL_SHIFT 19
164
165#define AR724X_PLL_REG_CPU_CONFIG 0x00
166#define AR724X_PLL_REG_PCIE_CONFIG 0x18
167
168#define AR724X_PLL_DIV_SHIFT 0
169#define AR724X_PLL_DIV_MASK 0x3ff
170#define AR724X_PLL_REF_DIV_SHIFT 10
171#define AR724X_PLL_REF_DIV_MASK 0xf
172#define AR724X_AHB_DIV_SHIFT 19
173#define AR724X_AHB_DIV_MASK 0x1
174#define AR724X_DDR_DIV_SHIFT 22
175#define AR724X_DDR_DIV_MASK 0x3
176
177#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
178
179#define AR91XX_PLL_REG_CPU_CONFIG 0x00
180#define AR91XX_PLL_REG_ETH_CONFIG 0x04
181#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
182#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
183
184#define AR91XX_PLL_DIV_SHIFT 0
185#define AR91XX_PLL_DIV_MASK 0x3ff
186#define AR91XX_DDR_DIV_SHIFT 22
187#define AR91XX_DDR_DIV_MASK 0x3
188#define AR91XX_AHB_DIV_SHIFT 19
189#define AR91XX_AHB_DIV_MASK 0x1
190
191#define AR91XX_ETH0_PLL_SHIFT 20
192#define AR91XX_ETH1_PLL_SHIFT 22
193
194#define AR933X_PLL_CPU_CONFIG_REG 0x00
195#define AR933X_PLL_CLOCK_CTRL_REG 0x08
196
197#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
198#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
199#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
200#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
201#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
202#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
203
204#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
205#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
206#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
207#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
208#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
209#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
210#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
211
212#define AR934X_PLL_REG_CPU_CONFIG 0x00
213#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
214
215#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
216#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19
217#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000
218
219#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \
220    (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \
221    AR934X_CPU_PLL_CFG_OUTDIV_LSB)
222
223#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25
224#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23
225#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000
226
227#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \
228    (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \
229    AR934X_DDR_PLL_CFG_OUTDIV_LSB)
230
231#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \
232    (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \
233    AR934X_DDR_PLL_CFG_OUTDIV_MASK)
234
235#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16
236#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12
237#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000
238
239#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \
240    (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \
241    AR934X_CPU_PLL_CFG_REFDIV_LSB)
242
243#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \
244    (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \
245    AR934X_CPU_PLL_CFG_REFDIV_MASK)
246
247#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2
248
249#define AR934X_CPU_PLL_CFG_NINT_MSB 11
250#define AR934X_CPU_PLL_CFG_NINT_LSB 6
251#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0
252
253#define AR934X_CPU_PLL_CFG_NINT_GET(x) \
254    (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \
255    AR934X_CPU_PLL_CFG_NINT_LSB)
256
257#define AR934X_CPU_PLL_CFG_NINT_SET(x) \
258    (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \
259    AR934X_CPU_PLL_CFG_NINT_MASK)
260
261#define AR934X_CPU_PLL_CFG_NINT_RESET 20
262
263#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5
264#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0
265#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f
266
267#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \
268    (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \
269    AR934X_CPU_PLL_CFG_NFRAC_LSB)
270
271#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \
272    (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \
273    AR934X_CPU_PLL_CFG_NFRAC_MASK)
274
275#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20
276#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16
277#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000
278
279#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \
280    (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \
281    AR934X_DDR_PLL_CFG_REFDIV_LSB)
282
283#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \
284    (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \
285    AR934X_DDR_PLL_CFG_REFDIV_MASK)
286
287#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2
288
289#define AR934X_DDR_PLL_CFG_NINT_MSB 15
290#define AR934X_DDR_PLL_CFG_NINT_LSB 10
291#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00
292
293#define AR934X_DDR_PLL_CFG_NINT_GET(x) \
294    (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \
295    AR934X_DDR_PLL_CFG_NINT_LSB)
296
297#define AR934X_DDR_PLL_CFG_NINT_SET(x) \
298    (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \
299    AR934X_DDR_PLL_CFG_NINT_MASK)
300
301#define AR934X_DDR_PLL_CFG_NINT_RESET 20
302
303#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9
304#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0
305#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff
306
307#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \
308    (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \
309    AR934X_DDR_PLL_CFG_NFRAC_LSB)
310
311#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \
312    (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \
313    AR934X_DDR_PLL_CFG_NFRAC_MASK)
314
315#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512
316
317#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19
318#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15
319#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000
320
321#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \
322    (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \
323    AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB)
324
325#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \
326    (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \
327    AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
328
329#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0
330
331#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14
332#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10
333#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00
334
335#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \
336    (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \
337    AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB)
338
339#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \
340    (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \
341    AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
342
343#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0
344
345#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9
346#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5
347#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0
348
349#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \
350    (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \
351    AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB)
352
353#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \
354    (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \
355    AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
356
357#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0
358
359#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24
360#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24
361#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
362
363#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \
364    (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \
365    AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB)
366
367#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \
368    (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \
369    AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
370
371#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
372
373extern void __iomem *ar71xx_pll_base;
374
375static inline void ar71xx_pll_wr(unsigned reg, u32 val)
376{
377    __raw_writel(val, ar71xx_pll_base + reg);
378}
379
380static inline u32 ar71xx_pll_rr(unsigned reg)
381{
382    return __raw_readl(ar71xx_pll_base + reg);
383}
384
385/*
386 * USB_CONFIG block
387 */
388#define USB_CTRL_REG_FLADJ 0x00
389#define USB_CTRL_REG_CONFIG 0x04
390
391extern void __iomem *ar71xx_usb_ctrl_base;
392
393static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
394{
395    __raw_writel(val, ar71xx_usb_ctrl_base + reg);
396}
397
398static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
399{
400    return __raw_readl(ar71xx_usb_ctrl_base + reg);
401}
402
403/*
404 * GPIO block
405 */
406#define GPIO_REG_OE 0x00
407#define GPIO_REG_IN 0x04
408#define GPIO_REG_OUT 0x08
409#define GPIO_REG_SET 0x0c
410#define GPIO_REG_CLEAR 0x10
411#define GPIO_REG_INT_MODE 0x14
412#define GPIO_REG_INT_TYPE 0x18
413#define GPIO_REG_INT_POLARITY 0x1c
414#define GPIO_REG_INT_PENDING 0x20
415#define GPIO_REG_INT_ENABLE 0x24
416#define GPIO_REG_FUNC 0x28
417
418#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
419#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
420#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
421#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
422#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
423#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
424#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
425
426#define AR71XX_GPIO_COUNT 16
427
428#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
429#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
430#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
431#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
432#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
433#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
434#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
435#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
436#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
437#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
438#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
439#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
440#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
441#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
442#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
443#define AR724X_GPIO_FUNC_UART_EN BIT(1)
444#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
445
446#define AR724X_GPIO_COUNT 18
447
448#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
449#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
450#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
451#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
452#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
453#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
454#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
455#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
456#define AR91XX_GPIO_FUNC_UART_EN BIT(8)
457#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
458
459#define AR91XX_GPIO_COUNT 22
460
461#define AR933X_GPIO_COUNT 30
462
463#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
464#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
465
466#define AR934X_GPIO_COUNT 32
467#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
468
469extern void __iomem *ar71xx_gpio_base;
470
471static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
472{
473    __raw_writel(value, ar71xx_gpio_base + reg);
474}
475
476static inline u32 ar71xx_gpio_rr(unsigned reg)
477{
478    return __raw_readl(ar71xx_gpio_base + reg);
479}
480
481void ar71xx_gpio_init(void) __init;
482void ar71xx_gpio_function_enable(u32 mask);
483void ar71xx_gpio_function_disable(u32 mask);
484void ar71xx_gpio_function_setup(u32 set, u32 clear);
485
486/*
487 * DDR_CTRL block
488 */
489#define AR71XX_DDR_REG_PCI_WIN0 0x7c
490#define AR71XX_DDR_REG_PCI_WIN1 0x80
491#define AR71XX_DDR_REG_PCI_WIN2 0x84
492#define AR71XX_DDR_REG_PCI_WIN3 0x88
493#define AR71XX_DDR_REG_PCI_WIN4 0x8c
494#define AR71XX_DDR_REG_PCI_WIN5 0x90
495#define AR71XX_DDR_REG_PCI_WIN6 0x94
496#define AR71XX_DDR_REG_PCI_WIN7 0x98
497#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
498#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
499#define AR71XX_DDR_REG_FLUSH_USB 0xa4
500#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
501
502#define AR724X_DDR_REG_FLUSH_GE0 0x7c
503#define AR724X_DDR_REG_FLUSH_GE1 0x80
504#define AR724X_DDR_REG_FLUSH_USB 0x84
505#define AR724X_DDR_REG_FLUSH_PCIE 0x88
506
507#define AR91XX_DDR_REG_FLUSH_GE0 0x7c
508#define AR91XX_DDR_REG_FLUSH_GE1 0x80
509#define AR91XX_DDR_REG_FLUSH_USB 0x84
510#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
511
512#define AR933X_DDR_REG_FLUSH_GE0 0x7c
513#define AR933X_DDR_REG_FLUSH_GE1 0x80
514#define AR933X_DDR_REG_FLUSH_USB 0x84
515#define AR933X_DDR_REG_FLUSH_WMAC 0x88
516
517#define AR934X_DDR_REG_FLUSH_GE0 0x9c
518#define AR934X_DDR_REG_FLUSH_GE1 0xa0
519#define AR934X_DDR_REG_FLUSH_USB 0xa4
520#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
521
522
523#define PCI_WIN0_OFFS 0x10000000
524#define PCI_WIN1_OFFS 0x11000000
525#define PCI_WIN2_OFFS 0x12000000
526#define PCI_WIN3_OFFS 0x13000000
527#define PCI_WIN4_OFFS 0x14000000
528#define PCI_WIN5_OFFS 0x15000000
529#define PCI_WIN6_OFFS 0x16000000
530#define PCI_WIN7_OFFS 0x07000000
531
532extern void __iomem *ar71xx_ddr_base;
533
534static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
535{
536    __raw_writel(val, ar71xx_ddr_base + reg);
537}
538
539static inline u32 ar71xx_ddr_rr(unsigned reg)
540{
541    return __raw_readl(ar71xx_ddr_base + reg);
542}
543
544void ar71xx_ddr_flush(u32 reg);
545
546/*
547 * PCI block
548 */
549#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
550#define AR71XX_PCI_CFG_SIZE 0x100
551
552#define PCI_REG_CRP_AD_CBE 0x00
553#define PCI_REG_CRP_WRDATA 0x04
554#define PCI_REG_CRP_RDDATA 0x08
555#define PCI_REG_CFG_AD 0x0c
556#define PCI_REG_CFG_CBE 0x10
557#define PCI_REG_CFG_WRDATA 0x14
558#define PCI_REG_CFG_RDDATA 0x18
559#define PCI_REG_PCI_ERR 0x1c
560#define PCI_REG_PCI_ERR_ADDR 0x20
561#define PCI_REG_AHB_ERR 0x24
562#define PCI_REG_AHB_ERR_ADDR 0x28
563
564#define PCI_CRP_CMD_WRITE 0x00010000
565#define PCI_CRP_CMD_READ 0x00000000
566#define PCI_CFG_CMD_READ 0x0000000a
567#define PCI_CFG_CMD_WRITE 0x0000000b
568
569#define PCI_IDSEL_ADL_START 17
570
571#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
572#define AR724X_PCI_CFG_SIZE 0x1000
573
574#define AR724X_PCI_REG_APP 0x00
575#define AR724X_PCI_REG_RESET 0x18
576#define AR724X_PCI_REG_INT_STATUS 0x4c
577#define AR724X_PCI_REG_INT_MASK 0x50
578
579#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
580#define AR724X_PCI_RESET_LINK_UP BIT(0)
581
582#define AR724X_PCI_INT_DEV0 BIT(14)
583
584/*
585 * RESET block
586 */
587#define AR71XX_RESET_REG_TIMER 0x00
588#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
589#define AR71XX_RESET_REG_WDOG_CTRL 0x08
590#define AR71XX_RESET_REG_WDOG 0x0c
591#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
592#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
593#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
594#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
595#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
596#define AR71XX_RESET_REG_RESET_MODULE 0x24
597#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
598#define AR71XX_RESET_REG_PERFC0 0x30
599#define AR71XX_RESET_REG_PERFC1 0x34
600#define AR71XX_RESET_REG_REV_ID 0x90
601
602#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
603#define AR91XX_RESET_REG_RESET_MODULE 0x1c
604#define AR91XX_RESET_REG_PERF_CTRL 0x20
605#define AR91XX_RESET_REG_PERFC0 0x24
606#define AR91XX_RESET_REG_PERFC1 0x28
607
608#define AR724X_RESET_REG_RESET_MODULE 0x1c
609
610#define AR933X_RESET_REG_RESET_MODULE 0x1c
611#define AR933X_RESET_REG_BOOTSTRAP 0xac
612#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
613#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
614
615#define AR934X_RESET_REG_RESET_MODULE 0x1c
616#define AR934X_RESET_REG_BOOTSTRAP 0xb0
617/* 0 - 25MHz 1 - 40 MHz */
618#define AR934X_REF_CLK_40 (1 << 4)
619
620#define WDOG_CTRL_LAST_RESET BIT(31)
621#define WDOG_CTRL_ACTION_MASK 3
622#define WDOG_CTRL_ACTION_NONE 0 /* no action */
623#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
624#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
625#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
626
627#define MISC_INT_ENET_LINK BIT(12)
628#define MISC_INT_DDR_PERF BIT(11)
629#define MISC_INT_TIMER4 BIT(10)
630#define MISC_INT_TIMER3 BIT(9)
631#define MISC_INT_TIMER2 BIT(8)
632#define MISC_INT_DMA BIT(7)
633#define MISC_INT_OHCI BIT(6)
634#define MISC_INT_PERFC BIT(5)
635#define MISC_INT_WDOG BIT(4)
636#define MISC_INT_UART BIT(3)
637#define MISC_INT_GPIO BIT(2)
638#define MISC_INT_ERROR BIT(1)
639#define MISC_INT_TIMER BIT(0)
640
641#define PCI_INT_CORE BIT(4)
642#define PCI_INT_DEV2 BIT(2)
643#define PCI_INT_DEV1 BIT(1)
644#define PCI_INT_DEV0 BIT(0)
645
646#define RESET_MODULE_EXTERNAL BIT(28)
647#define RESET_MODULE_FULL_CHIP BIT(24)
648#define RESET_MODULE_AMBA2WMAC BIT(22)
649#define RESET_MODULE_CPU_NMI BIT(21)
650#define RESET_MODULE_CPU_COLD BIT(20)
651#define RESET_MODULE_DMA BIT(19)
652#define RESET_MODULE_SLIC BIT(18)
653#define RESET_MODULE_STEREO BIT(17)
654#define RESET_MODULE_DDR BIT(16)
655#define RESET_MODULE_GE1_MAC BIT(13)
656#define RESET_MODULE_GE1_PHY BIT(12)
657#define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
658#define RESET_MODULE_GE0_MAC BIT(9)
659#define RESET_MODULE_GE0_PHY BIT(8)
660#define RESET_MODULE_USB_OHCI_DLL BIT(6)
661#define RESET_MODULE_USB_HOST BIT(5)
662#define RESET_MODULE_USB_PHY BIT(4)
663#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
664#define RESET_MODULE_PCI_BUS BIT(1)
665#define RESET_MODULE_PCI_CORE BIT(0)
666
667#define AR724X_RESET_GE1_MDIO BIT(23)
668#define AR724X_RESET_GE0_MDIO BIT(22)
669#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
670#define AR724X_RESET_PCIE_PHY BIT(7)
671#define AR724X_RESET_PCIE BIT(6)
672#define AR724X_RESET_USB_HOST BIT(5)
673#define AR724X_RESET_USB_PHY BIT(4)
674#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
675
676#define AR933X_RESET_WMAC BIT(11)
677#define AR933X_RESET_GE1_MDIO BIT(23)
678#define AR933X_RESET_GE0_MDIO BIT(22)
679#define AR933X_RESET_GE1_MAC BIT(13)
680#define AR933X_RESET_GE0_MAC BIT(9)
681#define AR933X_RESET_USB_HOST BIT(5)
682#define AR933X_RESET_USB_PHY BIT(4)
683#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
684
685#define REV_ID_MAJOR_MASK 0xfff0
686#define REV_ID_MAJOR_AR71XX 0x00a0
687#define REV_ID_MAJOR_AR913X 0x00b0
688#define REV_ID_MAJOR_AR7240 0x00c0
689#define REV_ID_MAJOR_AR7241 0x0100
690#define REV_ID_MAJOR_AR7242 0x1100
691#define REV_ID_MAJOR_AR9330 0x0110
692#define REV_ID_MAJOR_AR9331 0x1110
693#define REV_ID_MAJOR_AR9341 0x0120
694#define REV_ID_MAJOR_AR9342 0x1120
695#define REV_ID_MAJOR_AR9344 0x2120
696
697#define AR71XX_REV_ID_MINOR_MASK 0x3
698#define AR71XX_REV_ID_MINOR_AR7130 0x0
699#define AR71XX_REV_ID_MINOR_AR7141 0x1
700#define AR71XX_REV_ID_MINOR_AR7161 0x2
701#define AR71XX_REV_ID_REVISION_MASK 0x3
702#define AR71XX_REV_ID_REVISION_SHIFT 2
703
704#define AR91XX_REV_ID_MINOR_MASK 0x3
705#define AR91XX_REV_ID_MINOR_AR9130 0x0
706#define AR91XX_REV_ID_MINOR_AR9132 0x1
707#define AR91XX_REV_ID_REVISION_MASK 0x3
708#define AR91XX_REV_ID_REVISION_SHIFT 2
709
710#define AR724X_REV_ID_REVISION_MASK 0x3
711
712#define AR933X_REV_ID_REVISION_MASK 0xf
713
714#define AR934X_REV_ID_REVISION_MASK 0xf
715
716extern void __iomem *ar71xx_reset_base;
717
718static inline void ar71xx_reset_wr(unsigned reg, u32 val)
719{
720    __raw_writel(val, ar71xx_reset_base + reg);
721}
722
723static inline u32 ar71xx_reset_rr(unsigned reg)
724{
725    return __raw_readl(ar71xx_reset_base + reg);
726}
727
728void ar71xx_device_stop(u32 mask);
729void ar71xx_device_start(u32 mask);
730void ar71xx_device_reset_rmw(u32 clear, u32 set);
731int ar71xx_device_stopped(u32 mask);
732
733/*
734 * SPI block
735 */
736#define SPI_REG_FS 0x00 /* Function Select */
737#define SPI_REG_CTRL 0x04 /* SPI Control */
738#define SPI_REG_IOC 0x08 /* SPI I/O Control */
739#define SPI_REG_RDS 0x0c /* Read Data Shift */
740
741#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
742
743#define SPI_CTRL_RD BIT(6) /* Remap Disable */
744#define SPI_CTRL_DIV_MASK 0x3f
745
746#define SPI_IOC_DO BIT(0) /* Data Out pin */
747#define SPI_IOC_CLK BIT(8) /* CLK pin */
748#define SPI_IOC_CS(n) BIT(16 + (n))
749#define SPI_IOC_CS0 SPI_IOC_CS(0)
750#define SPI_IOC_CS1 SPI_IOC_CS(1)
751#define SPI_IOC_CS2 SPI_IOC_CS(2)
752#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
753
754void ar71xx_flash_acquire(void);
755void ar71xx_flash_release(void);
756
757/*
758 * MII_CTRL block
759 */
760#define MII_REG_MII0_CTRL 0x00
761#define MII_REG_MII1_CTRL 0x04
762
763#define MII0_CTRL_IF_GMII 0
764#define MII0_CTRL_IF_MII 1
765#define MII0_CTRL_IF_RGMII 2
766#define MII0_CTRL_IF_RMII 3
767
768#define MII1_CTRL_IF_RGMII 0
769#define MII1_CTRL_IF_RMII 1
770
771#endif /* __ASSEMBLER__ */
772
773#endif /* __ASM_MACH_AR71XX_H */
774

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive