Root/target/linux/brcm63xx/patches-3.1/001-6345_cpu.patch

1--- a/arch/mips/bcm63xx/cpu.c
2+++ b/arch/mips/bcm63xx/cpu.c
3@@ -260,8 +260,10 @@ static unsigned int detect_memory_size(v
4     unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
5     u32 val;
6 
7- if (BCMCPU_IS_6345())
8- return (8 * 1024 * 1024);
9+ if (BCMCPU_IS_6345()) {
10+ val = bcm_sdram_readl(SDRAM_MBASE_REG);
11+ return (val * 8 * 1024 * 1024);
12+ }
13 
14     if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
15         val = bcm_sdram_readl(SDRAM_CFG_REG);
16--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
17+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
18@@ -734,6 +734,8 @@
19 #define SDRAM_CFG_BANK_SHIFT 13
20 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
21 
22+#define SDRAM_MBASE_REG 0xc
23+
24 #define SDRAM_PRIO_REG 0x2C
25 #define SDRAM_PRIO_MIPS_SHIFT 29
26 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
27--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
28+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
29@@ -709,15 +709,9 @@ void __init board_prom_init(void)
30     char cfe_version[32];
31     u32 val;
32 
33- /* read base address of boot chip select (0)
34- * 6345 does not have MPI but boots from standard
35- * MIPS Flash address */
36- if (BCMCPU_IS_6345())
37- val = 0x1fc00000;
38- else {
39- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
40- val &= MPI_CSBASE_BASE_MASK;
41- }
42+ /* read base address of boot chip select (0) */
43+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
44+ val &= MPI_CSBASE_BASE_MASK;
45     boot_addr = (u8 *)KSEG1ADDR(val);
46 
47     /* dump cfe version */
48@@ -893,12 +887,9 @@ int __init board_register_devices(void)
49         bcm63xx_dsp_register(&board.dsp);
50 
51     /* read base address of boot chip select (0) */
52- if (BCMCPU_IS_6345())
53- val = 0x1fc00000;
54- else {
55- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
56- val &= MPI_CSBASE_BASE_MASK;
57- }
58+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
59+ val &= MPI_CSBASE_BASE_MASK;
60+
61     mtd_resources[0].start = val;
62     mtd_resources[0].end = 0x1FFFFFFF;
63 
64--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
65+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
66@@ -163,7 +163,7 @@ enum bcm63xx_regs_set {
67 #define BCM_6345_ENET0_BASE (0xfffe1800)
68 #define BCM_6345_ENETDMA_BASE (0xfffe2800)
69 #define BCM_6345_PCMCIA_BASE (0xfffe2028)
70-#define BCM_6345_MPI_BASE (0xdeadbeef)
71+#define BCM_6345_MPI_BASE (0xfffe2000)
72 #define BCM_6345_OHCI0_BASE (0xfffe2100)
73 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
74 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
75--- a/arch/mips/bcm63xx/gpio.c
76+++ b/arch/mips/bcm63xx/gpio.c
77@@ -4,7 +4,7 @@
78  * for more details.
79  *
80  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
81- * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
82+ * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
83  */
84 
85 #include <linux/kernel.h>
86@@ -33,7 +33,10 @@ static void bcm63xx_gpio_set(struct gpio
87         BUG();
88 
89     if (gpio < 32) {
90- reg = GPIO_DATA_LO_REG;
91+ if (!BCMCPU_IS_6345())
92+ reg = GPIO_DATA_LO_REG;
93+ else
94+ reg = GPIO_DATA_HI_REG;
95         mask = 1 << gpio;
96         v = &gpio_out_low;
97     } else {
98@@ -60,7 +63,10 @@ static int bcm63xx_gpio_get(struct gpio_
99         BUG();
100 
101     if (gpio < 32) {
102- reg = GPIO_DATA_LO_REG;
103+ if (!BCMCPU_IS_6345())
104+ reg = GPIO_DATA_LO_REG;
105+ else
106+ reg = GPIO_DATA_HI_REG;
107         mask = 1 << gpio;
108     } else {
109         reg = GPIO_DATA_HI_REG;
110@@ -125,7 +131,11 @@ static struct gpio_chip bcm63xx_gpio_chi
111 
112 int __init bcm63xx_gpio_init(void)
113 {
114- gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG);
115+ if (!BCMCPU_IS_6345())
116+ gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG);
117+ else
118+ gpio_out_low = bcm_gpio_readl(GPIO_DATA_HI_REG);
119+
120     gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
121     bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
122     pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
123

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