| 1 | --- a/drivers/ssb/driver_chipcommon.c |
| 2 | +++ b/drivers/ssb/driver_chipcommon.c |
| 3 | @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb |
| 4 | if (!ccdev) |
| 5 | return; |
| 6 | bus = ccdev->bus; |
| 7 | + |
| 8 | + /* We support SLOW only on 6..9 */ |
| 9 | + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW) |
| 10 | + mode = SSB_CLKMODE_DYNAMIC; |
| 11 | + |
| 12 | + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) |
| 13 | + return; /* PMU controls clockmode, separated function needed */ |
| 14 | + SSB_WARN_ON(ccdev->id.revision >= 20); |
| 15 | + |
| 16 | /* chipcommon cores prior to rev6 don't support dynamic clock control */ |
| 17 | if (ccdev->id.revision < 6) |
| 18 | return; |
| 19 | - /* chipcommon cores rev10 are a whole new ball game */ |
| 20 | + |
| 21 | + /* ChipCommon cores rev10+ need testing */ |
| 22 | if (ccdev->id.revision >= 10) |
| 23 | return; |
| 24 | + |
| 25 | if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) |
| 26 | return; |
| 27 | |
| 28 | switch (mode) { |
| 29 | - case SSB_CLKMODE_SLOW: |
| 30 | + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */ |
| 31 | tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 32 | tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 33 | chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 34 | break; |
| 35 | case SSB_CLKMODE_FAST: |
| 36 | - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ |
| 37 | - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 38 | - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 39 | - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; |
| 40 | - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 41 | + if (ccdev->id.revision < 10) { |
| 42 | + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ |
| 43 | + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 44 | + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 45 | + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; |
| 46 | + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 47 | + } else { |
| 48 | + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, |
| 49 | + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) | |
| 50 | + SSB_CHIPCO_SYSCLKCTL_FORCEHT)); |
| 51 | + /* udelay(150); TODO: not available in early init */ |
| 52 | + } |
| 53 | break; |
| 54 | case SSB_CLKMODE_DYNAMIC: |
| 55 | - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 56 | - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 57 | - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; |
| 58 | - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; |
| 59 | - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) |
| 60 | - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; |
| 61 | - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 62 | - |
| 63 | - /* for dynamic control, we have to release our xtal_pu "force on" */ |
| 64 | - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) |
| 65 | - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); |
| 66 | + if (ccdev->id.revision < 10) { |
| 67 | + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); |
| 68 | + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; |
| 69 | + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; |
| 70 | + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; |
| 71 | + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != |
| 72 | + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) |
| 73 | + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; |
| 74 | + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); |
| 75 | + |
| 76 | + /* For dynamic control, we have to release our xtal_pu |
| 77 | + * "force on" */ |
| 78 | + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) |
| 79 | + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); |
| 80 | + } else { |
| 81 | + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, |
| 82 | + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & |
| 83 | + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT)); |
| 84 | + } |
| 85 | break; |
| 86 | default: |
| 87 | SSB_WARN_ON(1); |
| 88 | @@ -209,6 +235,24 @@ static void chipco_powercontrol_init(str |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */ |
| 93 | +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc) |
| 94 | +{ |
| 95 | + struct ssb_bus *bus = cc->dev->bus; |
| 96 | + |
| 97 | + switch (bus->chip_id) { |
| 98 | + case 0x4312: |
| 99 | + case 0x4322: |
| 100 | + case 0x4328: |
| 101 | + return 7000; |
| 102 | + case 0x4325: |
| 103 | + /* TODO: */ |
| 104 | + default: |
| 105 | + return 15000; |
| 106 | + } |
| 107 | +} |
| 108 | + |
| 109 | +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */ |
| 110 | static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) |
| 111 | { |
| 112 | struct ssb_bus *bus = cc->dev->bus; |
| 113 | @@ -218,6 +262,12 @@ static void calc_fast_powerup_delay(stru |
| 114 | |
| 115 | if (bus->bustype != SSB_BUSTYPE_PCI) |
| 116 | return; |
| 117 | + |
| 118 | + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { |
| 119 | + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc); |
| 120 | + return; |
| 121 | + } |
| 122 | + |
| 123 | if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) |
| 124 | return; |
| 125 | |
| 126 | @@ -236,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip |
| 127 | if (cc->dev->id.revision >= 11) |
| 128 | cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); |
| 129 | ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); |
| 130 | + |
| 131 | + if (cc->dev->id.revision >= 20) { |
| 132 | + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0); |
| 133 | + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0); |
| 134 | + } |
| 135 | + |
| 136 | ssb_pmu_init(cc); |
| 137 | chipco_powercontrol_init(cc); |
| 138 | ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); |
| 139 | @@ -373,6 +429,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c |
| 140 | { |
| 141 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); |
| 142 | } |
| 143 | +EXPORT_SYMBOL(ssb_chipco_gpio_control); |
| 144 | |
| 145 | u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) |
| 146 | { |
| 147 | --- a/drivers/ssb/driver_chipcommon_pmu.c |
| 148 | +++ b/drivers/ssb/driver_chipcommon_pmu.c |
| 149 | @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_ |
| 150 | case 0x5354: |
| 151 | ssb_pmu0_pllinit_r0(cc, crystalfreq); |
| 152 | break; |
| 153 | + case 0x4322: |
| 154 | + if (cc->pmu.rev == 2) { |
| 155 | + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A); |
| 156 | + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0); |
| 157 | + } |
| 158 | + break; |
| 159 | default: |
| 160 | ssb_printk(KERN_ERR PFX |
| 161 | "ERROR: PLL init unknown for device %04X\n", |
| 162 | @@ -411,12 +417,15 @@ static void ssb_pmu_resources_init(struc |
| 163 | u32 min_msk = 0, max_msk = 0; |
| 164 | unsigned int i; |
| 165 | const struct pmu_res_updown_tab_entry *updown_tab = NULL; |
| 166 | - unsigned int updown_tab_size; |
| 167 | + unsigned int updown_tab_size = 0; |
| 168 | const struct pmu_res_depend_tab_entry *depend_tab = NULL; |
| 169 | - unsigned int depend_tab_size; |
| 170 | + unsigned int depend_tab_size = 0; |
| 171 | |
| 172 | switch (bus->chip_id) { |
| 173 | case 0x4312: |
| 174 | + min_msk = 0xCBB; |
| 175 | + break; |
| 176 | + case 0x4322: |
| 177 | /* We keep the default settings: |
| 178 | * min_msk = 0xCBB |
| 179 | * max_msk = 0x7FFFF |
| 180 | @@ -495,9 +504,9 @@ static void ssb_pmu_resources_init(struc |
| 181 | chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk); |
| 182 | } |
| 183 | |
| 184 | +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */ |
| 185 | void ssb_pmu_init(struct ssb_chipcommon *cc) |
| 186 | { |
| 187 | - struct ssb_bus *bus = cc->dev->bus; |
| 188 | u32 pmucap; |
| 189 | |
| 190 | if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU)) |
| 191 | @@ -509,15 +518,12 @@ void ssb_pmu_init(struct ssb_chipcommon |
| 192 | ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n", |
| 193 | cc->pmu.rev, pmucap); |
| 194 | |
| 195 | - if (cc->pmu.rev >= 1) { |
| 196 | - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) { |
| 197 | - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL, |
| 198 | - ~SSB_CHIPCO_PMU_CTL_NOILPONW); |
| 199 | - } else { |
| 200 | - chipco_set32(cc, SSB_CHIPCO_PMU_CTL, |
| 201 | - SSB_CHIPCO_PMU_CTL_NOILPONW); |
| 202 | - } |
| 203 | - } |
| 204 | + if (cc->pmu.rev == 1) |
| 205 | + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL, |
| 206 | + ~SSB_CHIPCO_PMU_CTL_NOILPONW); |
| 207 | + else |
| 208 | + chipco_set32(cc, SSB_CHIPCO_PMU_CTL, |
| 209 | + SSB_CHIPCO_PMU_CTL_NOILPONW); |
| 210 | ssb_pmu_pll_init(cc); |
| 211 | ssb_pmu_resources_init(cc); |
| 212 | } |
| 213 | --- a/drivers/ssb/driver_gige.c |
| 214 | +++ b/drivers/ssb/driver_gige.c |
| 215 | @@ -12,6 +12,7 @@ |
| 216 | #include <linux/ssb/ssb_driver_gige.h> |
| 217 | #include <linux/pci.h> |
| 218 | #include <linux/pci_regs.h> |
| 219 | +#include <linux/slab.h> |
| 220 | |
| 221 | |
| 222 | /* |
| 223 | @@ -105,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige |
| 224 | gige_write32(dev, SSB_GIGE_PCICFG + offset, value); |
| 225 | } |
| 226 | |
| 227 | -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
| 228 | - int reg, int size, u32 *val) |
| 229 | +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus, |
| 230 | + unsigned int devfn, int reg, |
| 231 | + int size, u32 *val) |
| 232 | { |
| 233 | struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops); |
| 234 | unsigned long flags; |
| 235 | @@ -135,8 +137,9 @@ static int ssb_gige_pci_read_config(stru |
| 236 | return PCIBIOS_SUCCESSFUL; |
| 237 | } |
| 238 | |
| 239 | -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
| 240 | - int reg, int size, u32 val) |
| 241 | +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus, |
| 242 | + unsigned int devfn, int reg, |
| 243 | + int size, u32 val) |
| 244 | { |
| 245 | struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops); |
| 246 | unsigned long flags; |
| 247 | @@ -165,7 +168,8 @@ static int ssb_gige_pci_write_config(str |
| 248 | return PCIBIOS_SUCCESSFUL; |
| 249 | } |
| 250 | |
| 251 | -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id) |
| 252 | +static int __devinit ssb_gige_probe(struct ssb_device *sdev, |
| 253 | + const struct ssb_device_id *id) |
| 254 | { |
| 255 | struct ssb_gige *dev; |
| 256 | u32 base, tmslow, tmshigh; |
| 257 | --- a/drivers/ssb/driver_mipscore.c |
| 258 | +++ b/drivers/ssb/driver_mipscore.c |
| 259 | @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco |
| 260 | set_irq(dev, irq++); |
| 261 | } |
| 262 | break; |
| 263 | - /* fallthrough */ |
| 264 | case SSB_DEV_PCI: |
| 265 | case SSB_DEV_ETHERNET: |
| 266 | case SSB_DEV_ETHERNET_GBIT: |
| 267 | @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco |
| 268 | set_irq(dev, irq++); |
| 269 | break; |
| 270 | } |
| 271 | + /* fallthrough */ |
| 272 | + case SSB_DEV_EXTIF: |
| 273 | + set_irq(dev, 0); |
| 274 | + break; |
| 275 | } |
| 276 | } |
| 277 | ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); |
| 278 | --- a/drivers/ssb/driver_pcicore.c |
| 279 | +++ b/drivers/ssb/driver_pcicore.c |
| 280 | @@ -15,6 +15,11 @@ |
| 281 | |
| 282 | #include "ssb_private.h" |
| 283 | |
| 284 | +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address); |
| 285 | +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data); |
| 286 | +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address); |
| 287 | +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
| 288 | + u8 address, u16 data); |
| 289 | |
| 290 | static inline |
| 291 | u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) |
| 292 | @@ -246,20 +251,12 @@ static struct pci_controller ssb_pcicore |
| 293 | .pci_ops = &ssb_pcicore_pciops, |
| 294 | .io_resource = &ssb_pcicore_io_resource, |
| 295 | .mem_resource = &ssb_pcicore_mem_resource, |
| 296 | - .mem_offset = 0x24000000, |
| 297 | }; |
| 298 | |
| 299 | -static u32 ssb_pcicore_pcibus_iobase = 0x100; |
| 300 | -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA; |
| 301 | - |
| 302 | /* This function is called when doing a pci_enable_device(). |
| 303 | * We must first check if the device is a device on the PCI-core bridge. */ |
| 304 | int ssb_pcicore_plat_dev_init(struct pci_dev *d) |
| 305 | { |
| 306 | - struct resource *res; |
| 307 | - int pos, size; |
| 308 | - u32 *base; |
| 309 | - |
| 310 | if (d->bus->ops != &ssb_pcicore_pciops) { |
| 311 | /* This is not a device on the PCI-core bridge. */ |
| 312 | return -ENODEV; |
| 313 | @@ -268,27 +265,6 @@ int ssb_pcicore_plat_dev_init(struct pci |
| 314 | ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", |
| 315 | pci_name(d)); |
| 316 | |
| 317 | - /* Fix up resource bases */ |
| 318 | - for (pos = 0; pos < 6; pos++) { |
| 319 | - res = &d->resource[pos]; |
| 320 | - if (res->flags & IORESOURCE_IO) |
| 321 | - base = &ssb_pcicore_pcibus_iobase; |
| 322 | - else |
| 323 | - base = &ssb_pcicore_pcibus_membase; |
| 324 | - res->flags |= IORESOURCE_PCI_FIXED; |
| 325 | - if (res->end) { |
| 326 | - size = res->end - res->start + 1; |
| 327 | - if (*base & (size - 1)) |
| 328 | - *base = (*base + size) & ~(size - 1); |
| 329 | - res->start = *base; |
| 330 | - res->end = res->start + size - 1; |
| 331 | - *base += size; |
| 332 | - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start); |
| 333 | - } |
| 334 | - /* Fix up PCI bridge BAR0 only */ |
| 335 | - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0) |
| 336 | - break; |
| 337 | - } |
| 338 | /* Fix up interrupt lines */ |
| 339 | d->irq = ssb_mips_irq(extpci_core->dev) + 2; |
| 340 | pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); |
| 341 | @@ -338,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st |
| 342 | return ssb_mips_irq(extpci_core->dev) + 2; |
| 343 | } |
| 344 | |
| 345 | -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) |
| 346 | +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) |
| 347 | { |
| 348 | u32 val; |
| 349 | |
| 350 | @@ -403,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st |
| 351 | register_pci_controller(&ssb_pcicore_controller); |
| 352 | } |
| 353 | |
| 354 | -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) |
| 355 | +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc) |
| 356 | { |
| 357 | struct ssb_bus *bus = pc->dev->bus; |
| 358 | u16 chipid_top; |
| 359 | @@ -432,25 +408,133 @@ static int pcicore_is_in_hostmode(struct |
| 360 | } |
| 361 | #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ |
| 362 | |
| 363 | +/************************************************** |
| 364 | + * Workarounds. |
| 365 | + **************************************************/ |
| 366 | + |
| 367 | +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc) |
| 368 | +{ |
| 369 | + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0)); |
| 370 | + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) { |
| 371 | + tmp &= ~0xF000; |
| 372 | + tmp |= (pc->dev->core_index << 12); |
| 373 | + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp); |
| 374 | + } |
| 375 | +} |
| 376 | + |
| 377 | +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc) |
| 378 | +{ |
| 379 | + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; |
| 380 | +} |
| 381 | + |
| 382 | +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc) |
| 383 | +{ |
| 384 | + const u8 serdes_pll_device = 0x1D; |
| 385 | + const u8 serdes_rx_device = 0x1F; |
| 386 | + u16 tmp; |
| 387 | + |
| 388 | + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, |
| 389 | + ssb_pcicore_polarity_workaround(pc)); |
| 390 | + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); |
| 391 | + if (tmp & 0x4000) |
| 392 | + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); |
| 393 | +} |
| 394 | + |
| 395 | +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc) |
| 396 | +{ |
| 397 | + struct ssb_device *pdev = pc->dev; |
| 398 | + struct ssb_bus *bus = pdev->bus; |
| 399 | + u32 tmp; |
| 400 | + |
| 401 | + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
| 402 | + tmp |= SSB_PCICORE_SBTOPCI_PREF; |
| 403 | + tmp |= SSB_PCICORE_SBTOPCI_BURST; |
| 404 | + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
| 405 | + |
| 406 | + if (pdev->id.revision < 5) { |
| 407 | + tmp = ssb_read32(pdev, SSB_IMCFGLO); |
| 408 | + tmp &= ~SSB_IMCFGLO_SERTO; |
| 409 | + tmp |= 2; |
| 410 | + tmp &= ~SSB_IMCFGLO_REQTO; |
| 411 | + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; |
| 412 | + ssb_write32(pdev, SSB_IMCFGLO, tmp); |
| 413 | + ssb_commit_settings(bus); |
| 414 | + } else if (pdev->id.revision >= 11) { |
| 415 | + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
| 416 | + tmp |= SSB_PCICORE_SBTOPCI_MRM; |
| 417 | + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
| 418 | + } |
| 419 | +} |
| 420 | + |
| 421 | +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc) |
| 422 | +{ |
| 423 | + u32 tmp; |
| 424 | + u8 rev = pc->dev->id.revision; |
| 425 | + |
| 426 | + if (rev == 0 || rev == 1) { |
| 427 | + /* TLP Workaround register. */ |
| 428 | + tmp = ssb_pcie_read(pc, 0x4); |
| 429 | + tmp |= 0x8; |
| 430 | + ssb_pcie_write(pc, 0x4, tmp); |
| 431 | + } |
| 432 | + if (rev == 1) { |
| 433 | + /* DLLP Link Control register. */ |
| 434 | + tmp = ssb_pcie_read(pc, 0x100); |
| 435 | + tmp |= 0x40; |
| 436 | + ssb_pcie_write(pc, 0x100, tmp); |
| 437 | + } |
| 438 | + |
| 439 | + if (rev == 0) { |
| 440 | + const u8 serdes_rx_device = 0x1F; |
| 441 | + |
| 442 | + ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 443 | + 2 /* Timer */, 0x8128); |
| 444 | + ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 445 | + 6 /* CDR */, 0x0100); |
| 446 | + ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 447 | + 7 /* CDR BW */, 0x1466); |
| 448 | + } else if (rev == 3 || rev == 4 || rev == 5) { |
| 449 | + /* TODO: DLLP Power Management Threshold */ |
| 450 | + ssb_pcicore_serdes_workaround(pc); |
| 451 | + /* TODO: ASPM */ |
| 452 | + } else if (rev == 7) { |
| 453 | + /* TODO: No PLL down */ |
| 454 | + } |
| 455 | + |
| 456 | + if (rev >= 6) { |
| 457 | + /* Miscellaneous Configuration Fixup */ |
| 458 | + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5)); |
| 459 | + if (!(tmp & 0x8000)) |
| 460 | + pcicore_write16(pc, SSB_PCICORE_SPROM(5), |
| 461 | + tmp | 0x8000); |
| 462 | + } |
| 463 | +} |
| 464 | |
| 465 | /************************************************** |
| 466 | * Generic and Clientmode operation code. |
| 467 | **************************************************/ |
| 468 | |
| 469 | -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) |
| 470 | +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) |
| 471 | { |
| 472 | + ssb_pcicore_fix_sprom_core_index(pc); |
| 473 | + |
| 474 | /* Disable PCI interrupts. */ |
| 475 | ssb_write32(pc->dev, SSB_INTVEC, 0); |
| 476 | + |
| 477 | + /* Additional PCIe always once-executed workarounds */ |
| 478 | + if (pc->dev->id.coreid == SSB_DEV_PCIE) { |
| 479 | + ssb_pcicore_serdes_workaround(pc); |
| 480 | + /* TODO: ASPM */ |
| 481 | + /* TODO: Clock Request Update */ |
| 482 | + } |
| 483 | } |
| 484 | |
| 485 | -void ssb_pcicore_init(struct ssb_pcicore *pc) |
| 486 | +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc) |
| 487 | { |
| 488 | struct ssb_device *dev = pc->dev; |
| 489 | - struct ssb_bus *bus; |
| 490 | |
| 491 | if (!dev) |
| 492 | return; |
| 493 | - bus = dev->bus; |
| 494 | if (!ssb_device_is_enabled(dev)) |
| 495 | ssb_device_enable(dev, 0); |
| 496 | |
| 497 | @@ -475,58 +559,104 @@ static void ssb_pcie_write(struct ssb_pc |
| 498 | pcicore_write32(pc, 0x134, data); |
| 499 | } |
| 500 | |
| 501 | -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
| 502 | - u8 address, u16 data) |
| 503 | +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) |
| 504 | { |
| 505 | const u16 mdio_control = 0x128; |
| 506 | const u16 mdio_data = 0x12C; |
| 507 | u32 v; |
| 508 | int i; |
| 509 | |
| 510 | + v = (1 << 30); /* Start of Transaction */ |
| 511 | + v |= (1 << 28); /* Write Transaction */ |
| 512 | + v |= (1 << 17); /* Turnaround */ |
| 513 | + v |= (0x1F << 18); |
| 514 | + v |= (phy << 4); |
| 515 | + pcicore_write32(pc, mdio_data, v); |
| 516 | + |
| 517 | + udelay(10); |
| 518 | + for (i = 0; i < 200; i++) { |
| 519 | + v = pcicore_read32(pc, mdio_control); |
| 520 | + if (v & 0x100 /* Trans complete */) |
| 521 | + break; |
| 522 | + msleep(1); |
| 523 | + } |
| 524 | +} |
| 525 | + |
| 526 | +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) |
| 527 | +{ |
| 528 | + const u16 mdio_control = 0x128; |
| 529 | + const u16 mdio_data = 0x12C; |
| 530 | + int max_retries = 10; |
| 531 | + u16 ret = 0; |
| 532 | + u32 v; |
| 533 | + int i; |
| 534 | + |
| 535 | v = 0x80; /* Enable Preamble Sequence */ |
| 536 | v |= 0x2; /* MDIO Clock Divisor */ |
| 537 | pcicore_write32(pc, mdio_control, v); |
| 538 | |
| 539 | + if (pc->dev->id.revision >= 10) { |
| 540 | + max_retries = 200; |
| 541 | + ssb_pcie_mdio_set_phy(pc, device); |
| 542 | + } |
| 543 | + |
| 544 | v = (1 << 30); /* Start of Transaction */ |
| 545 | - v |= (1 << 28); /* Write Transaction */ |
| 546 | + v |= (1 << 29); /* Read Transaction */ |
| 547 | v |= (1 << 17); /* Turnaround */ |
| 548 | - v |= (u32)device << 22; |
| 549 | + if (pc->dev->id.revision < 10) |
| 550 | + v |= (u32)device << 22; |
| 551 | v |= (u32)address << 18; |
| 552 | - v |= data; |
| 553 | pcicore_write32(pc, mdio_data, v); |
| 554 | /* Wait for the device to complete the transaction */ |
| 555 | udelay(10); |
| 556 | - for (i = 0; i < 10; i++) { |
| 557 | + for (i = 0; i < max_retries; i++) { |
| 558 | v = pcicore_read32(pc, mdio_control); |
| 559 | - if (v & 0x100 /* Trans complete */) |
| 560 | + if (v & 0x100 /* Trans complete */) { |
| 561 | + udelay(10); |
| 562 | + ret = pcicore_read32(pc, mdio_data); |
| 563 | break; |
| 564 | + } |
| 565 | msleep(1); |
| 566 | } |
| 567 | pcicore_write32(pc, mdio_control, 0); |
| 568 | + return ret; |
| 569 | } |
| 570 | |
| 571 | -static void ssb_broadcast_value(struct ssb_device *dev, |
| 572 | - u32 address, u32 data) |
| 573 | +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, |
| 574 | + u8 address, u16 data) |
| 575 | { |
| 576 | - /* This is used for both, PCI and ChipCommon core, so be careful. */ |
| 577 | - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); |
| 578 | - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); |
| 579 | + const u16 mdio_control = 0x128; |
| 580 | + const u16 mdio_data = 0x12C; |
| 581 | + int max_retries = 10; |
| 582 | + u32 v; |
| 583 | + int i; |
| 584 | |
| 585 | - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); |
| 586 | - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ |
| 587 | - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); |
| 588 | - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ |
| 589 | -} |
| 590 | + v = 0x80; /* Enable Preamble Sequence */ |
| 591 | + v |= 0x2; /* MDIO Clock Divisor */ |
| 592 | + pcicore_write32(pc, mdio_control, v); |
| 593 | |
| 594 | -static void ssb_commit_settings(struct ssb_bus *bus) |
| 595 | -{ |
| 596 | - struct ssb_device *dev; |
| 597 | + if (pc->dev->id.revision >= 10) { |
| 598 | + max_retries = 200; |
| 599 | + ssb_pcie_mdio_set_phy(pc, device); |
| 600 | + } |
| 601 | |
| 602 | - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; |
| 603 | - if (WARN_ON(!dev)) |
| 604 | - return; |
| 605 | - /* This forces an update of the cached registers. */ |
| 606 | - ssb_broadcast_value(dev, 0xFD8, 0); |
| 607 | + v = (1 << 30); /* Start of Transaction */ |
| 608 | + v |= (1 << 28); /* Write Transaction */ |
| 609 | + v |= (1 << 17); /* Turnaround */ |
| 610 | + if (pc->dev->id.revision < 10) |
| 611 | + v |= (u32)device << 22; |
| 612 | + v |= (u32)address << 18; |
| 613 | + v |= data; |
| 614 | + pcicore_write32(pc, mdio_data, v); |
| 615 | + /* Wait for the device to complete the transaction */ |
| 616 | + udelay(10); |
| 617 | + for (i = 0; i < max_retries; i++) { |
| 618 | + v = pcicore_read32(pc, mdio_control); |
| 619 | + if (v & 0x100 /* Trans complete */) |
| 620 | + break; |
| 621 | + msleep(1); |
| 622 | + } |
| 623 | + pcicore_write32(pc, mdio_control, 0); |
| 624 | } |
| 625 | |
| 626 | int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, |
| 627 | @@ -551,13 +681,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc |
| 628 | might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); |
| 629 | |
| 630 | /* Enable interrupts for this device. */ |
| 631 | - if (bus->host_pci && |
| 632 | - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) { |
| 633 | + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) { |
| 634 | u32 coremask; |
| 635 | |
| 636 | /* Calculate the "coremask" for the device. */ |
| 637 | coremask = (1 << dev->core_index); |
| 638 | |
| 639 | + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI); |
| 640 | err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); |
| 641 | if (err) |
| 642 | goto out; |
| 643 | @@ -579,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc |
| 644 | if (pc->setup_done) |
| 645 | goto out; |
| 646 | if (pdev->id.coreid == SSB_DEV_PCI) { |
| 647 | - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
| 648 | - tmp |= SSB_PCICORE_SBTOPCI_PREF; |
| 649 | - tmp |= SSB_PCICORE_SBTOPCI_BURST; |
| 650 | - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
| 651 | - |
| 652 | - if (pdev->id.revision < 5) { |
| 653 | - tmp = ssb_read32(pdev, SSB_IMCFGLO); |
| 654 | - tmp &= ~SSB_IMCFGLO_SERTO; |
| 655 | - tmp |= 2; |
| 656 | - tmp &= ~SSB_IMCFGLO_REQTO; |
| 657 | - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; |
| 658 | - ssb_write32(pdev, SSB_IMCFGLO, tmp); |
| 659 | - ssb_commit_settings(bus); |
| 660 | - } else if (pdev->id.revision >= 11) { |
| 661 | - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); |
| 662 | - tmp |= SSB_PCICORE_SBTOPCI_MRM; |
| 663 | - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); |
| 664 | - } |
| 665 | + ssb_pcicore_pci_setup_workarounds(pc); |
| 666 | } else { |
| 667 | WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); |
| 668 | - //TODO: Better make defines for all these magic PCIE values. |
| 669 | - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) { |
| 670 | - /* TLP Workaround register. */ |
| 671 | - tmp = ssb_pcie_read(pc, 0x4); |
| 672 | - tmp |= 0x8; |
| 673 | - ssb_pcie_write(pc, 0x4, tmp); |
| 674 | - } |
| 675 | - if (pdev->id.revision == 0) { |
| 676 | - const u8 serdes_rx_device = 0x1F; |
| 677 | - |
| 678 | - ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 679 | - 2 /* Timer */, 0x8128); |
| 680 | - ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 681 | - 6 /* CDR */, 0x0100); |
| 682 | - ssb_pcie_mdio_write(pc, serdes_rx_device, |
| 683 | - 7 /* CDR BW */, 0x1466); |
| 684 | - } else if (pdev->id.revision == 1) { |
| 685 | - /* DLLP Link Control register. */ |
| 686 | - tmp = ssb_pcie_read(pc, 0x100); |
| 687 | - tmp |= 0x40; |
| 688 | - ssb_pcie_write(pc, 0x100, tmp); |
| 689 | - } |
| 690 | + ssb_pcicore_pcie_setup_workarounds(pc); |
| 691 | } |
| 692 | pc->setup_done = 1; |
| 693 | out: |
| 694 | --- a/drivers/ssb/main.c |
| 695 | +++ b/drivers/ssb/main.c |
| 696 | @@ -18,6 +18,7 @@ |
| 697 | #include <linux/dma-mapping.h> |
| 698 | #include <linux/pci.h> |
| 699 | #include <linux/mmc/sdio_func.h> |
| 700 | +#include <linux/slab.h> |
| 701 | |
| 702 | #include <pcmcia/cs_types.h> |
| 703 | #include <pcmcia/cs.h> |
| 704 | @@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de |
| 705 | put_device(dev->dev); |
| 706 | } |
| 707 | |
| 708 | +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv) |
| 709 | +{ |
| 710 | + if (drv) |
| 711 | + get_driver(&drv->drv); |
| 712 | + return drv; |
| 713 | +} |
| 714 | + |
| 715 | +static inline void ssb_driver_put(struct ssb_driver *drv) |
| 716 | +{ |
| 717 | + if (drv) |
| 718 | + put_driver(&drv->drv); |
| 719 | +} |
| 720 | + |
| 721 | static int ssb_device_resume(struct device *dev) |
| 722 | { |
| 723 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); |
| 724 | @@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus) |
| 725 | EXPORT_SYMBOL(ssb_bus_suspend); |
| 726 | |
| 727 | #ifdef CONFIG_SSB_SPROM |
| 728 | -int ssb_devices_freeze(struct ssb_bus *bus) |
| 729 | +/** ssb_devices_freeze - Freeze all devices on the bus. |
| 730 | + * |
| 731 | + * After freezing no device driver will be handling a device |
| 732 | + * on this bus anymore. ssb_devices_thaw() must be called after |
| 733 | + * a successful freeze to reactivate the devices. |
| 734 | + * |
| 735 | + * @bus: The bus. |
| 736 | + * @ctx: Context structure. Pass this to ssb_devices_thaw(). |
| 737 | + */ |
| 738 | +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) |
| 739 | { |
| 740 | - struct ssb_device *dev; |
| 741 | - struct ssb_driver *drv; |
| 742 | - int err = 0; |
| 743 | - int i; |
| 744 | - pm_message_t state = PMSG_FREEZE; |
| 745 | + struct ssb_device *sdev; |
| 746 | + struct ssb_driver *sdrv; |
| 747 | + unsigned int i; |
| 748 | + |
| 749 | + memset(ctx, 0, sizeof(*ctx)); |
| 750 | + ctx->bus = bus; |
| 751 | + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); |
| 752 | |
| 753 | - /* First check that we are capable to freeze all devices. */ |
| 754 | for (i = 0; i < bus->nr_devices; i++) { |
| 755 | - dev = &(bus->devices[i]); |
| 756 | - if (!dev->dev || |
| 757 | - !dev->dev->driver || |
| 758 | - !device_is_registered(dev->dev)) |
| 759 | - continue; |
| 760 | - drv = drv_to_ssb_drv(dev->dev->driver); |
| 761 | - if (!drv) |
| 762 | + sdev = ssb_device_get(&bus->devices[i]); |
| 763 | + |
| 764 | + if (!sdev->dev || !sdev->dev->driver || |
| 765 | + !device_is_registered(sdev->dev)) { |
| 766 | + ssb_device_put(sdev); |
| 767 | continue; |
| 768 | - if (!drv->suspend) { |
| 769 | - /* Nope, can't suspend this one. */ |
| 770 | - return -EOPNOTSUPP; |
| 771 | } |
| 772 | - } |
| 773 | - /* Now suspend all devices */ |
| 774 | - for (i = 0; i < bus->nr_devices; i++) { |
| 775 | - dev = &(bus->devices[i]); |
| 776 | - if (!dev->dev || |
| 777 | - !dev->dev->driver || |
| 778 | - !device_is_registered(dev->dev)) |
| 779 | - continue; |
| 780 | - drv = drv_to_ssb_drv(dev->dev->driver); |
| 781 | - if (!drv) |
| 782 | + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver)); |
| 783 | + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) { |
| 784 | + ssb_device_put(sdev); |
| 785 | continue; |
| 786 | - err = drv->suspend(dev, state); |
| 787 | - if (err) { |
| 788 | - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n", |
| 789 | - dev_name(dev->dev)); |
| 790 | - goto err_unwind; |
| 791 | } |
| 792 | + sdrv->remove(sdev); |
| 793 | + ctx->device_frozen[i] = 1; |
| 794 | } |
| 795 | |
| 796 | return 0; |
| 797 | -err_unwind: |
| 798 | - for (i--; i >= 0; i--) { |
| 799 | - dev = &(bus->devices[i]); |
| 800 | - if (!dev->dev || |
| 801 | - !dev->dev->driver || |
| 802 | - !device_is_registered(dev->dev)) |
| 803 | - continue; |
| 804 | - drv = drv_to_ssb_drv(dev->dev->driver); |
| 805 | - if (!drv) |
| 806 | - continue; |
| 807 | - if (drv->resume) |
| 808 | - drv->resume(dev); |
| 809 | - } |
| 810 | - return err; |
| 811 | } |
| 812 | |
| 813 | -int ssb_devices_thaw(struct ssb_bus *bus) |
| 814 | +/** ssb_devices_thaw - Unfreeze all devices on the bus. |
| 815 | + * |
| 816 | + * This will re-attach the device drivers and re-init the devices. |
| 817 | + * |
| 818 | + * @ctx: The context structure from ssb_devices_freeze() |
| 819 | + */ |
| 820 | +int ssb_devices_thaw(struct ssb_freeze_context *ctx) |
| 821 | { |
| 822 | - struct ssb_device *dev; |
| 823 | - struct ssb_driver *drv; |
| 824 | - int err; |
| 825 | - int i; |
| 826 | + struct ssb_bus *bus = ctx->bus; |
| 827 | + struct ssb_device *sdev; |
| 828 | + struct ssb_driver *sdrv; |
| 829 | + unsigned int i; |
| 830 | + int err, result = 0; |
| 831 | |
| 832 | for (i = 0; i < bus->nr_devices; i++) { |
| 833 | - dev = &(bus->devices[i]); |
| 834 | - if (!dev->dev || |
| 835 | - !dev->dev->driver || |
| 836 | - !device_is_registered(dev->dev)) |
| 837 | + if (!ctx->device_frozen[i]) |
| 838 | continue; |
| 839 | - drv = drv_to_ssb_drv(dev->dev->driver); |
| 840 | - if (!drv) |
| 841 | + sdev = &bus->devices[i]; |
| 842 | + |
| 843 | + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) |
| 844 | continue; |
| 845 | - if (SSB_WARN_ON(!drv->resume)) |
| 846 | + sdrv = drv_to_ssb_drv(sdev->dev->driver); |
| 847 | + if (SSB_WARN_ON(!sdrv || !sdrv->probe)) |
| 848 | continue; |
| 849 | - err = drv->resume(dev); |
| 850 | + |
| 851 | + err = sdrv->probe(sdev, &sdev->id); |
| 852 | if (err) { |
| 853 | ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", |
| 854 | - dev_name(dev->dev)); |
| 855 | + dev_name(sdev->dev)); |
| 856 | + result = err; |
| 857 | } |
| 858 | + ssb_driver_put(sdrv); |
| 859 | + ssb_device_put(sdev); |
| 860 | } |
| 861 | |
| 862 | - return 0; |
| 863 | + return result; |
| 864 | } |
| 865 | #endif /* CONFIG_SSB_SPROM */ |
| 866 | |
| 867 | @@ -380,6 +385,35 @@ static int ssb_device_uevent(struct devi |
| 868 | ssb_dev->id.revision); |
| 869 | } |
| 870 | |
| 871 | +#define ssb_config_attr(attrib, field, format_string) \ |
| 872 | +static ssize_t \ |
| 873 | +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ |
| 874 | +{ \ |
| 875 | + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ |
| 876 | +} |
| 877 | + |
| 878 | +ssb_config_attr(core_num, core_index, "%u\n") |
| 879 | +ssb_config_attr(coreid, id.coreid, "0x%04x\n") |
| 880 | +ssb_config_attr(vendor, id.vendor, "0x%04x\n") |
| 881 | +ssb_config_attr(revision, id.revision, "%u\n") |
| 882 | +ssb_config_attr(irq, irq, "%u\n") |
| 883 | +static ssize_t |
| 884 | +name_show(struct device *dev, struct device_attribute *attr, char *buf) |
| 885 | +{ |
| 886 | + return sprintf(buf, "%s\n", |
| 887 | + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); |
| 888 | +} |
| 889 | + |
| 890 | +static struct device_attribute ssb_device_attrs[] = { |
| 891 | + __ATTR_RO(name), |
| 892 | + __ATTR_RO(core_num), |
| 893 | + __ATTR_RO(coreid), |
| 894 | + __ATTR_RO(vendor), |
| 895 | + __ATTR_RO(revision), |
| 896 | + __ATTR_RO(irq), |
| 897 | + __ATTR_NULL, |
| 898 | +}; |
| 899 | + |
| 900 | static struct bus_type ssb_bustype = { |
| 901 | .name = "ssb", |
| 902 | .match = ssb_bus_match, |
| 903 | @@ -389,6 +423,7 @@ static struct bus_type ssb_bustype = { |
| 904 | .suspend = ssb_device_suspend, |
| 905 | .resume = ssb_device_resume, |
| 906 | .uevent = ssb_device_uevent, |
| 907 | + .dev_attrs = ssb_device_attrs, |
| 908 | }; |
| 909 | |
| 910 | static void ssb_buses_lock(void) |
| 911 | @@ -481,6 +516,7 @@ static int ssb_devices_register(struct s |
| 912 | #ifdef CONFIG_SSB_PCIHOST |
| 913 | sdev->irq = bus->host_pci->irq; |
| 914 | dev->parent = &bus->host_pci->dev; |
| 915 | + sdev->dma_dev = dev->parent; |
| 916 | #endif |
| 917 | break; |
| 918 | case SSB_BUSTYPE_PCMCIA: |
| 919 | @@ -490,13 +526,13 @@ static int ssb_devices_register(struct s |
| 920 | #endif |
| 921 | break; |
| 922 | case SSB_BUSTYPE_SDIO: |
| 923 | -#ifdef CONFIG_SSB_SDIO |
| 924 | - sdev->irq = bus->host_sdio->dev.irq; |
| 925 | +#ifdef CONFIG_SSB_SDIOHOST |
| 926 | dev->parent = &bus->host_sdio->dev; |
| 927 | #endif |
| 928 | break; |
| 929 | case SSB_BUSTYPE_SSB: |
| 930 | dev->dma_mask = &dev->coherent_dma_mask; |
| 931 | + sdev->dma_dev = dev; |
| 932 | break; |
| 933 | } |
| 934 | |
| 935 | @@ -523,7 +559,7 @@ error: |
| 936 | } |
| 937 | |
| 938 | /* Needs ssb_buses_lock() */ |
| 939 | -static int ssb_attach_queued_buses(void) |
| 940 | +static int __devinit ssb_attach_queued_buses(void) |
| 941 | { |
| 942 | struct ssb_bus *bus, *n; |
| 943 | int err = 0; |
| 944 | @@ -734,9 +770,9 @@ out: |
| 945 | return err; |
| 946 | } |
| 947 | |
| 948 | -static int ssb_bus_register(struct ssb_bus *bus, |
| 949 | - ssb_invariants_func_t get_invariants, |
| 950 | - unsigned long baseaddr) |
| 951 | +static int __devinit ssb_bus_register(struct ssb_bus *bus, |
| 952 | + ssb_invariants_func_t get_invariants, |
| 953 | + unsigned long baseaddr) |
| 954 | { |
| 955 | int err; |
| 956 | |
| 957 | @@ -817,8 +853,8 @@ err_disable_xtal: |
| 958 | } |
| 959 | |
| 960 | #ifdef CONFIG_SSB_PCIHOST |
| 961 | -int ssb_bus_pcibus_register(struct ssb_bus *bus, |
| 962 | - struct pci_dev *host_pci) |
| 963 | +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus, |
| 964 | + struct pci_dev *host_pci) |
| 965 | { |
| 966 | int err; |
| 967 | |
| 968 | @@ -830,6 +866,9 @@ int ssb_bus_pcibus_register(struct ssb_b |
| 969 | if (!err) { |
| 970 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " |
| 971 | "PCI device %s\n", dev_name(&host_pci->dev)); |
| 972 | + } else { |
| 973 | + ssb_printk(KERN_ERR PFX "Failed to register PCI version" |
| 974 | + " of SSB with error %d\n", err); |
| 975 | } |
| 976 | |
| 977 | return err; |
| 978 | @@ -838,9 +877,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register); |
| 979 | #endif /* CONFIG_SSB_PCIHOST */ |
| 980 | |
| 981 | #ifdef CONFIG_SSB_PCMCIAHOST |
| 982 | -int ssb_bus_pcmciabus_register(struct ssb_bus *bus, |
| 983 | - struct pcmcia_device *pcmcia_dev, |
| 984 | - unsigned long baseaddr) |
| 985 | +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus, |
| 986 | + struct pcmcia_device *pcmcia_dev, |
| 987 | + unsigned long baseaddr) |
| 988 | { |
| 989 | int err; |
| 990 | |
| 991 | @@ -860,8 +899,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register |
| 992 | #endif /* CONFIG_SSB_PCMCIAHOST */ |
| 993 | |
| 994 | #ifdef CONFIG_SSB_SDIOHOST |
| 995 | -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, |
| 996 | - unsigned int quirks) |
| 997 | +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus, |
| 998 | + struct sdio_func *func, |
| 999 | + unsigned int quirks) |
| 1000 | { |
| 1001 | int err; |
| 1002 | |
| 1003 | @@ -881,9 +921,9 @@ int ssb_bus_sdiobus_register(struct ssb_ |
| 1004 | EXPORT_SYMBOL(ssb_bus_sdiobus_register); |
| 1005 | #endif /* CONFIG_SSB_PCMCIAHOST */ |
| 1006 | |
| 1007 | -int ssb_bus_ssbbus_register(struct ssb_bus *bus, |
| 1008 | - unsigned long baseaddr, |
| 1009 | - ssb_invariants_func_t get_invariants) |
| 1010 | +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus, |
| 1011 | + unsigned long baseaddr, |
| 1012 | + ssb_invariants_func_t get_invariants) |
| 1013 | { |
| 1014 | int err; |
| 1015 | |
| 1016 | @@ -964,8 +1004,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 |
| 1017 | switch (plltype) { |
| 1018 | case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ |
| 1019 | if (m & SSB_CHIPCO_CLK_T6_MMASK) |
| 1020 | - return SSB_CHIPCO_CLK_T6_M0; |
| 1021 | - return SSB_CHIPCO_CLK_T6_M1; |
| 1022 | + return SSB_CHIPCO_CLK_T6_M1; |
| 1023 | + return SSB_CHIPCO_CLK_T6_M0; |
| 1024 | case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ |
| 1025 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ |
| 1026 | case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ |
| 1027 | @@ -1080,23 +1120,22 @@ static u32 ssb_tmslow_reject_bitmask(str |
| 1028 | { |
| 1029 | u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; |
| 1030 | |
| 1031 | - /* The REJECT bit changed position in TMSLOW between |
| 1032 | - * Backplane revisions. */ |
| 1033 | + /* The REJECT bit seems to be different for Backplane rev 2.3 */ |
| 1034 | switch (rev) { |
| 1035 | case SSB_IDLOW_SSBREV_22: |
| 1036 | - return SSB_TMSLOW_REJECT_22; |
| 1037 | + case SSB_IDLOW_SSBREV_24: |
| 1038 | + case SSB_IDLOW_SSBREV_26: |
| 1039 | + return SSB_TMSLOW_REJECT; |
| 1040 | case SSB_IDLOW_SSBREV_23: |
| 1041 | return SSB_TMSLOW_REJECT_23; |
| 1042 | - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */ |
| 1043 | - case SSB_IDLOW_SSBREV_25: /* same here */ |
| 1044 | - case SSB_IDLOW_SSBREV_26: /* same here */ |
| 1045 | + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ |
| 1046 | case SSB_IDLOW_SSBREV_27: /* same here */ |
| 1047 | - return SSB_TMSLOW_REJECT_23; /* this is a guess */ |
| 1048 | + return SSB_TMSLOW_REJECT; /* this is a guess */ |
| 1049 | default: |
| 1050 | printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); |
| 1051 | WARN_ON(1); |
| 1052 | } |
| 1053 | - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23); |
| 1054 | + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23); |
| 1055 | } |
| 1056 | |
| 1057 | int ssb_device_is_enabled(struct ssb_device *dev) |
| 1058 | @@ -1155,10 +1194,10 @@ void ssb_device_enable(struct ssb_device |
| 1059 | } |
| 1060 | EXPORT_SYMBOL(ssb_device_enable); |
| 1061 | |
| 1062 | -/* Wait for a bit in a register to get set or unset. |
| 1063 | +/* Wait for bitmask in a register to get set or cleared. |
| 1064 | * timeout is in units of ten-microseconds */ |
| 1065 | -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask, |
| 1066 | - int timeout, int set) |
| 1067 | +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, |
| 1068 | + int timeout, int set) |
| 1069 | { |
| 1070 | int i; |
| 1071 | u32 val; |
| 1072 | @@ -1166,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic |
| 1073 | for (i = 0; i < timeout; i++) { |
| 1074 | val = ssb_read32(dev, reg); |
| 1075 | if (set) { |
| 1076 | - if (val & bitmask) |
| 1077 | + if ((val & bitmask) == bitmask) |
| 1078 | return 0; |
| 1079 | } else { |
| 1080 | if (!(val & bitmask)) |
| 1081 | @@ -1183,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic |
| 1082 | |
| 1083 | void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) |
| 1084 | { |
| 1085 | - u32 reject; |
| 1086 | + u32 reject, val; |
| 1087 | |
| 1088 | if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) |
| 1089 | return; |
| 1090 | |
| 1091 | reject = ssb_tmslow_reject_bitmask(dev); |
| 1092 | - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); |
| 1093 | - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1); |
| 1094 | - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); |
| 1095 | - ssb_write32(dev, SSB_TMSLOW, |
| 1096 | - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | |
| 1097 | - reject | SSB_TMSLOW_RESET | |
| 1098 | - core_specific_flags); |
| 1099 | - ssb_flush_tmslow(dev); |
| 1100 | + |
| 1101 | + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { |
| 1102 | + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); |
| 1103 | + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); |
| 1104 | + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); |
| 1105 | + |
| 1106 | + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { |
| 1107 | + val = ssb_read32(dev, SSB_IMSTATE); |
| 1108 | + val |= SSB_IMSTATE_REJECT; |
| 1109 | + ssb_write32(dev, SSB_IMSTATE, val); |
| 1110 | + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, |
| 1111 | + 0); |
| 1112 | + } |
| 1113 | + |
| 1114 | + ssb_write32(dev, SSB_TMSLOW, |
| 1115 | + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | |
| 1116 | + reject | SSB_TMSLOW_RESET | |
| 1117 | + core_specific_flags); |
| 1118 | + ssb_flush_tmslow(dev); |
| 1119 | + |
| 1120 | + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { |
| 1121 | + val = ssb_read32(dev, SSB_IMSTATE); |
| 1122 | + val &= ~SSB_IMSTATE_REJECT; |
| 1123 | + ssb_write32(dev, SSB_IMSTATE, val); |
| 1124 | + } |
| 1125 | + } |
| 1126 | |
| 1127 | ssb_write32(dev, SSB_TMSLOW, |
| 1128 | reject | SSB_TMSLOW_RESET | |
| 1129 | @@ -1211,7 +1268,10 @@ u32 ssb_dma_translation(struct ssb_devic |
| 1130 | case SSB_BUSTYPE_SSB: |
| 1131 | return 0; |
| 1132 | case SSB_BUSTYPE_PCI: |
| 1133 | - return SSB_PCI_DMA; |
| 1134 | + if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) |
| 1135 | + return SSB_PCIE_DMA_H32; |
| 1136 | + else |
| 1137 | + return SSB_PCI_DMA; |
| 1138 | default: |
| 1139 | __ssb_dma_not_implemented(dev); |
| 1140 | } |
| 1141 | @@ -1328,20 +1388,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown); |
| 1142 | |
| 1143 | int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) |
| 1144 | { |
| 1145 | - struct ssb_chipcommon *cc; |
| 1146 | int err; |
| 1147 | enum ssb_clkmode mode; |
| 1148 | |
| 1149 | err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); |
| 1150 | if (err) |
| 1151 | goto error; |
| 1152 | - cc = &bus->chipco; |
| 1153 | - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; |
| 1154 | - ssb_chipco_set_clockmode(cc, mode); |
| 1155 | |
| 1156 | #ifdef CONFIG_SSB_DEBUG |
| 1157 | bus->powered_up = 1; |
| 1158 | #endif |
| 1159 | + |
| 1160 | + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; |
| 1161 | + ssb_chipco_set_clockmode(&bus->chipco, mode); |
| 1162 | + |
| 1163 | return 0; |
| 1164 | error: |
| 1165 | ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); |
| 1166 | @@ -1349,6 +1409,37 @@ error: |
| 1167 | } |
| 1168 | EXPORT_SYMBOL(ssb_bus_powerup); |
| 1169 | |
| 1170 | +static void ssb_broadcast_value(struct ssb_device *dev, |
| 1171 | + u32 address, u32 data) |
| 1172 | +{ |
| 1173 | +#ifdef CONFIG_SSB_DRIVER_PCICORE |
| 1174 | + /* This is used for both, PCI and ChipCommon core, so be careful. */ |
| 1175 | + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); |
| 1176 | + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); |
| 1177 | +#endif |
| 1178 | + |
| 1179 | + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address); |
| 1180 | + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */ |
| 1181 | + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data); |
| 1182 | + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */ |
| 1183 | +} |
| 1184 | + |
| 1185 | +void ssb_commit_settings(struct ssb_bus *bus) |
| 1186 | +{ |
| 1187 | + struct ssb_device *dev; |
| 1188 | + |
| 1189 | +#ifdef CONFIG_SSB_DRIVER_PCICORE |
| 1190 | + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; |
| 1191 | +#else |
| 1192 | + dev = bus->chipco.dev; |
| 1193 | +#endif |
| 1194 | + if (WARN_ON(!dev)) |
| 1195 | + return; |
| 1196 | + /* This forces an update of the cached registers. */ |
| 1197 | + ssb_broadcast_value(dev, 0xFD8, 0); |
| 1198 | +} |
| 1199 | +EXPORT_SYMBOL(ssb_commit_settings); |
| 1200 | + |
| 1201 | u32 ssb_admatch_base(u32 adm) |
| 1202 | { |
| 1203 | u32 base = 0; |
| 1204 | --- a/drivers/ssb/pci.c |
| 1205 | +++ b/drivers/ssb/pci.c |
| 1206 | @@ -17,6 +17,7 @@ |
| 1207 | |
| 1208 | #include <linux/ssb/ssb.h> |
| 1209 | #include <linux/ssb/ssb_regs.h> |
| 1210 | +#include <linux/slab.h> |
| 1211 | #include <linux/pci.h> |
| 1212 | #include <linux/delay.h> |
| 1213 | |
| 1214 | @@ -167,7 +168,7 @@ err_pci: |
| 1215 | } |
| 1216 | |
| 1217 | /* Get the word-offset for a SSB_SPROM_XXX define. */ |
| 1218 | -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16)) |
| 1219 | +#define SPOFF(offset) ((offset) / sizeof(u16)) |
| 1220 | /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */ |
| 1221 | #define SPEX16(_outvar, _offset, _mask, _shift) \ |
| 1222 | out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) |
| 1223 | @@ -405,6 +406,46 @@ static void sprom_extract_r123(struct ss |
| 1224 | out->antenna_gain.ghz5.a3 = gain; |
| 1225 | } |
| 1226 | |
| 1227 | +/* Revs 4 5 and 8 have partially shared layout */ |
| 1228 | +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in) |
| 1229 | +{ |
| 1230 | + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, |
| 1231 | + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT); |
| 1232 | + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, |
| 1233 | + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT); |
| 1234 | + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, |
| 1235 | + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT); |
| 1236 | + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, |
| 1237 | + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT); |
| 1238 | + |
| 1239 | + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, |
| 1240 | + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT); |
| 1241 | + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, |
| 1242 | + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT); |
| 1243 | + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, |
| 1244 | + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT); |
| 1245 | + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, |
| 1246 | + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT); |
| 1247 | + |
| 1248 | + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, |
| 1249 | + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT); |
| 1250 | + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, |
| 1251 | + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT); |
| 1252 | + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, |
| 1253 | + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT); |
| 1254 | + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, |
| 1255 | + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT); |
| 1256 | + |
| 1257 | + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, |
| 1258 | + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT); |
| 1259 | + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, |
| 1260 | + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT); |
| 1261 | + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, |
| 1262 | + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT); |
| 1263 | + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, |
| 1264 | + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT); |
| 1265 | +} |
| 1266 | + |
| 1267 | static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) |
| 1268 | { |
| 1269 | int i; |
| 1270 | @@ -427,10 +468,14 @@ static void sprom_extract_r45(struct ssb |
| 1271 | SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0); |
| 1272 | SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0); |
| 1273 | SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0); |
| 1274 | + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0); |
| 1275 | + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0); |
| 1276 | } else { |
| 1277 | SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0); |
| 1278 | SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0); |
| 1279 | SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0); |
| 1280 | + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0); |
| 1281 | + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0); |
| 1282 | } |
| 1283 | SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A, |
| 1284 | SSB_SPROM4_ANTAVAIL_A_SHIFT); |
| 1285 | @@ -470,6 +515,8 @@ static void sprom_extract_r45(struct ssb |
| 1286 | memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, |
| 1287 | sizeof(out->antenna_gain.ghz5)); |
| 1288 | |
| 1289 | + sprom_extract_r458(out, in); |
| 1290 | + |
| 1291 | /* TODO - get remaining rev 4 stuff needed */ |
| 1292 | } |
| 1293 | |
| 1294 | @@ -560,6 +607,8 @@ static void sprom_extract_r8(struct ssb_ |
| 1295 | memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24, |
| 1296 | sizeof(out->antenna_gain.ghz5)); |
| 1297 | |
| 1298 | + sprom_extract_r458(out, in); |
| 1299 | + |
| 1300 | /* TODO - get remaining rev 8 stuff needed */ |
| 1301 | } |
| 1302 | |
| 1303 | @@ -572,37 +621,34 @@ static int sprom_extract(struct ssb_bus |
| 1304 | ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision); |
| 1305 | memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ |
| 1306 | memset(out->et1mac, 0xFF, 6); |
| 1307 | + |
| 1308 | if ((bus->chip_id & 0xFF00) == 0x4400) { |
| 1309 | /* Workaround: The BCM44XX chip has a stupid revision |
| 1310 | * number stored in the SPROM. |
| 1311 | * Always extract r1. */ |
| 1312 | out->revision = 1; |
| 1313 | + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision); |
| 1314 | + } |
| 1315 | + |
| 1316 | + switch (out->revision) { |
| 1317 | + case 1: |
| 1318 | + case 2: |
| 1319 | + case 3: |
| 1320 | sprom_extract_r123(out, in); |
| 1321 | - } else if (bus->chip_id == 0x4321) { |
| 1322 | - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */ |
| 1323 | - out->revision = 4; |
| 1324 | + break; |
| 1325 | + case 4: |
| 1326 | + case 5: |
| 1327 | sprom_extract_r45(out, in); |
| 1328 | - } else { |
| 1329 | - switch (out->revision) { |
| 1330 | - case 1: |
| 1331 | - case 2: |
| 1332 | - case 3: |
| 1333 | - sprom_extract_r123(out, in); |
| 1334 | - break; |
| 1335 | - case 4: |
| 1336 | - case 5: |
| 1337 | - sprom_extract_r45(out, in); |
| 1338 | - break; |
| 1339 | - case 8: |
| 1340 | - sprom_extract_r8(out, in); |
| 1341 | - break; |
| 1342 | - default: |
| 1343 | - ssb_printk(KERN_WARNING PFX "Unsupported SPROM" |
| 1344 | - " revision %d detected. Will extract" |
| 1345 | - " v1\n", out->revision); |
| 1346 | - out->revision = 1; |
| 1347 | - sprom_extract_r123(out, in); |
| 1348 | - } |
| 1349 | + break; |
| 1350 | + case 8: |
| 1351 | + sprom_extract_r8(out, in); |
| 1352 | + break; |
| 1353 | + default: |
| 1354 | + ssb_printk(KERN_WARNING PFX "Unsupported SPROM" |
| 1355 | + " revision %d detected. Will extract" |
| 1356 | + " v1\n", out->revision); |
| 1357 | + out->revision = 1; |
| 1358 | + sprom_extract_r123(out, in); |
| 1359 | } |
| 1360 | |
| 1361 | if (out->boardflags_lo == 0xFFFF) |
| 1362 | @@ -616,15 +662,14 @@ static int sprom_extract(struct ssb_bus |
| 1363 | static int ssb_pci_sprom_get(struct ssb_bus *bus, |
| 1364 | struct ssb_sprom *sprom) |
| 1365 | { |
| 1366 | - const struct ssb_sprom *fallback; |
| 1367 | - int err = -ENOMEM; |
| 1368 | + int err; |
| 1369 | u16 *buf; |
| 1370 | |
| 1371 | if (!ssb_is_sprom_available(bus)) { |
| 1372 | ssb_printk(KERN_ERR PFX "No SPROM available!\n"); |
| 1373 | return -ENODEV; |
| 1374 | } |
| 1375 | - if (bus->chipco.dev) { /* can be unavailible! */ |
| 1376 | + if (bus->chipco.dev) { /* can be unavailable! */ |
| 1377 | /* |
| 1378 | * get SPROM offset: SSB_SPROM_BASE1 except for |
| 1379 | * chipcommon rev >= 31 or chip ID is 0x4312 and |
| 1380 | @@ -644,7 +689,7 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 1381 | |
| 1382 | buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); |
| 1383 | if (!buf) |
| 1384 | - goto out; |
| 1385 | + return -ENOMEM; |
| 1386 | bus->sprom_size = SSB_SPROMSIZE_WORDS_R123; |
| 1387 | sprom_do_read(bus, buf); |
| 1388 | err = sprom_check_crc(buf, bus->sprom_size); |
| 1389 | @@ -654,17 +699,24 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 1390 | buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), |
| 1391 | GFP_KERNEL); |
| 1392 | if (!buf) |
| 1393 | - goto out; |
| 1394 | + return -ENOMEM; |
| 1395 | bus->sprom_size = SSB_SPROMSIZE_WORDS_R4; |
| 1396 | sprom_do_read(bus, buf); |
| 1397 | err = sprom_check_crc(buf, bus->sprom_size); |
| 1398 | if (err) { |
| 1399 | /* All CRC attempts failed. |
| 1400 | * Maybe there is no SPROM on the device? |
| 1401 | - * If we have a fallback, use that. */ |
| 1402 | - fallback = ssb_get_fallback_sprom(); |
| 1403 | - if (fallback) { |
| 1404 | - memcpy(sprom, fallback, sizeof(*sprom)); |
| 1405 | + * Now we ask the arch code if there is some sprom |
| 1406 | + * available for this device in some other storage */ |
| 1407 | + err = ssb_fill_sprom_with_fallback(bus, sprom); |
| 1408 | + if (err) { |
| 1409 | + ssb_printk(KERN_WARNING PFX "WARNING: Using" |
| 1410 | + " fallback SPROM failed (err %d)\n", |
| 1411 | + err); |
| 1412 | + } else { |
| 1413 | + ssb_dprintk(KERN_DEBUG PFX "Using SPROM" |
| 1414 | + " revision %d provided by" |
| 1415 | + " platform.\n", sprom->revision); |
| 1416 | err = 0; |
| 1417 | goto out_free; |
| 1418 | } |
| 1419 | @@ -676,19 +728,15 @@ static int ssb_pci_sprom_get(struct ssb_ |
| 1420 | |
| 1421 | out_free: |
| 1422 | kfree(buf); |
| 1423 | -out: |
| 1424 | return err; |
| 1425 | } |
| 1426 | |
| 1427 | static void ssb_pci_get_boardinfo(struct ssb_bus *bus, |
| 1428 | struct ssb_boardinfo *bi) |
| 1429 | { |
| 1430 | - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID, |
| 1431 | - &bi->vendor); |
| 1432 | - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID, |
| 1433 | - &bi->type); |
| 1434 | - pci_read_config_word(bus->host_pci, PCI_REVISION_ID, |
| 1435 | - &bi->rev); |
| 1436 | + bi->vendor = bus->host_pci->subsystem_vendor; |
| 1437 | + bi->type = bus->host_pci->subsystem_device; |
| 1438 | + bi->rev = bus->host_pci->revision; |
| 1439 | } |
| 1440 | |
| 1441 | int ssb_pci_get_invariants(struct ssb_bus *bus, |
| 1442 | --- a/drivers/ssb/pcihost_wrapper.c |
| 1443 | +++ b/drivers/ssb/pcihost_wrapper.c |
| 1444 | @@ -12,6 +12,7 @@ |
| 1445 | */ |
| 1446 | |
| 1447 | #include <linux/pci.h> |
| 1448 | +#include <linux/slab.h> |
| 1449 | #include <linux/ssb/ssb.h> |
| 1450 | |
| 1451 | |
| 1452 | @@ -52,12 +53,13 @@ static int ssb_pcihost_resume(struct pci |
| 1453 | # define ssb_pcihost_resume NULL |
| 1454 | #endif /* CONFIG_PM */ |
| 1455 | |
| 1456 | -static int ssb_pcihost_probe(struct pci_dev *dev, |
| 1457 | - const struct pci_device_id *id) |
| 1458 | +static int __devinit ssb_pcihost_probe(struct pci_dev *dev, |
| 1459 | + const struct pci_device_id *id) |
| 1460 | { |
| 1461 | struct ssb_bus *ssb; |
| 1462 | int err = -ENOMEM; |
| 1463 | const char *name; |
| 1464 | + u32 val; |
| 1465 | |
| 1466 | ssb = kzalloc(sizeof(*ssb), GFP_KERNEL); |
| 1467 | if (!ssb) |
| 1468 | @@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_ |
| 1469 | goto err_pci_disable; |
| 1470 | pci_set_master(dev); |
| 1471 | |
| 1472 | + /* Disable the RETRY_TIMEOUT register (0x41) to keep |
| 1473 | + * PCI Tx retries from interfering with C3 CPU state */ |
| 1474 | + pci_read_config_dword(dev, 0x40, &val); |
| 1475 | + if ((val & 0x0000ff00) != 0) |
| 1476 | + pci_write_config_dword(dev, 0x40, val & 0xffff00ff); |
| 1477 | + |
| 1478 | err = ssb_bus_pcibus_register(ssb, dev); |
| 1479 | if (err) |
| 1480 | goto err_pci_release_regions; |
| 1481 | @@ -102,7 +110,7 @@ static void ssb_pcihost_remove(struct pc |
| 1482 | pci_set_drvdata(dev, NULL); |
| 1483 | } |
| 1484 | |
| 1485 | -int ssb_pcihost_register(struct pci_driver *driver) |
| 1486 | +int __devinit ssb_pcihost_register(struct pci_driver *driver) |
| 1487 | { |
| 1488 | driver->probe = ssb_pcihost_probe; |
| 1489 | driver->remove = ssb_pcihost_remove; |
| 1490 | --- a/drivers/ssb/pcmcia.c |
| 1491 | +++ b/drivers/ssb/pcmcia.c |
| 1492 | @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co |
| 1493 | } \ |
| 1494 | } while (0) |
| 1495 | |
| 1496 | -int ssb_pcmcia_get_invariants(struct ssb_bus *bus, |
| 1497 | - struct ssb_init_invariants *iv) |
| 1498 | +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev, |
| 1499 | + tuple_t *tuple, |
| 1500 | + void *priv) |
| 1501 | { |
| 1502 | - tuple_t tuple; |
| 1503 | - int res; |
| 1504 | - unsigned char buf[32]; |
| 1505 | + struct ssb_sprom *sprom = priv; |
| 1506 | + |
| 1507 | + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID) |
| 1508 | + return -EINVAL; |
| 1509 | + if (tuple->TupleDataLen != ETH_ALEN + 2) |
| 1510 | + return -EINVAL; |
| 1511 | + if (tuple->TupleData[1] != ETH_ALEN) |
| 1512 | + return -EINVAL; |
| 1513 | + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN); |
| 1514 | + return 0; |
| 1515 | +}; |
| 1516 | + |
| 1517 | +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev, |
| 1518 | + tuple_t *tuple, |
| 1519 | + void *priv) |
| 1520 | +{ |
| 1521 | + struct ssb_init_invariants *iv = priv; |
| 1522 | struct ssb_sprom *sprom = &iv->sprom; |
| 1523 | struct ssb_boardinfo *bi = &iv->boardinfo; |
| 1524 | const char *error_description; |
| 1525 | |
| 1526 | + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1"); |
| 1527 | + switch (tuple->TupleData[0]) { |
| 1528 | + case SSB_PCMCIA_CIS_ID: |
| 1529 | + GOTO_ERROR_ON((tuple->TupleDataLen != 5) && |
| 1530 | + (tuple->TupleDataLen != 7), |
| 1531 | + "id tpl size"); |
| 1532 | + bi->vendor = tuple->TupleData[1] | |
| 1533 | + ((u16)tuple->TupleData[2] << 8); |
| 1534 | + break; |
| 1535 | + case SSB_PCMCIA_CIS_BOARDREV: |
| 1536 | + GOTO_ERROR_ON(tuple->TupleDataLen != 2, |
| 1537 | + "boardrev tpl size"); |
| 1538 | + sprom->board_rev = tuple->TupleData[1]; |
| 1539 | + break; |
| 1540 | + case SSB_PCMCIA_CIS_PA: |
| 1541 | + GOTO_ERROR_ON((tuple->TupleDataLen != 9) && |
| 1542 | + (tuple->TupleDataLen != 10), |
| 1543 | + "pa tpl size"); |
| 1544 | + sprom->pa0b0 = tuple->TupleData[1] | |
| 1545 | + ((u16)tuple->TupleData[2] << 8); |
| 1546 | + sprom->pa0b1 = tuple->TupleData[3] | |
| 1547 | + ((u16)tuple->TupleData[4] << 8); |
| 1548 | + sprom->pa0b2 = tuple->TupleData[5] | |
| 1549 | + ((u16)tuple->TupleData[6] << 8); |
| 1550 | + sprom->itssi_a = tuple->TupleData[7]; |
| 1551 | + sprom->itssi_bg = tuple->TupleData[7]; |
| 1552 | + sprom->maxpwr_a = tuple->TupleData[8]; |
| 1553 | + sprom->maxpwr_bg = tuple->TupleData[8]; |
| 1554 | + break; |
| 1555 | + case SSB_PCMCIA_CIS_OEMNAME: |
| 1556 | + /* We ignore this. */ |
| 1557 | + break; |
| 1558 | + case SSB_PCMCIA_CIS_CCODE: |
| 1559 | + GOTO_ERROR_ON(tuple->TupleDataLen != 2, |
| 1560 | + "ccode tpl size"); |
| 1561 | + sprom->country_code = tuple->TupleData[1]; |
| 1562 | + break; |
| 1563 | + case SSB_PCMCIA_CIS_ANTENNA: |
| 1564 | + GOTO_ERROR_ON(tuple->TupleDataLen != 2, |
| 1565 | + "ant tpl size"); |
| 1566 | + sprom->ant_available_a = tuple->TupleData[1]; |
| 1567 | + sprom->ant_available_bg = tuple->TupleData[1]; |
| 1568 | + break; |
| 1569 | + case SSB_PCMCIA_CIS_ANTGAIN: |
| 1570 | + GOTO_ERROR_ON(tuple->TupleDataLen != 2, |
| 1571 | + "antg tpl size"); |
| 1572 | + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1]; |
| 1573 | + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1]; |
| 1574 | + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1]; |
| 1575 | + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1]; |
| 1576 | + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1]; |
| 1577 | + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1]; |
| 1578 | + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1]; |
| 1579 | + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1]; |
| 1580 | + break; |
| 1581 | + case SSB_PCMCIA_CIS_BFLAGS: |
| 1582 | + GOTO_ERROR_ON((tuple->TupleDataLen != 3) && |
| 1583 | + (tuple->TupleDataLen != 5), |
| 1584 | + "bfl tpl size"); |
| 1585 | + sprom->boardflags_lo = tuple->TupleData[1] | |
| 1586 | + ((u16)tuple->TupleData[2] << 8); |
| 1587 | + break; |
| 1588 | + case SSB_PCMCIA_CIS_LEDS: |
| 1589 | + GOTO_ERROR_ON(tuple->TupleDataLen != 5, |
| 1590 | + "leds tpl size"); |
| 1591 | + sprom->gpio0 = tuple->TupleData[1]; |
| 1592 | + sprom->gpio1 = tuple->TupleData[2]; |
| 1593 | + sprom->gpio2 = tuple->TupleData[3]; |
| 1594 | + sprom->gpio3 = tuple->TupleData[4]; |
| 1595 | + break; |
| 1596 | + } |
| 1597 | + return -ENOSPC; /* continue with next entry */ |
| 1598 | + |
| 1599 | +error: |
| 1600 | + ssb_printk(KERN_ERR PFX |
| 1601 | + "PCMCIA: Failed to fetch device invariants: %s\n", |
| 1602 | + error_description); |
| 1603 | + return -ENODEV; |
| 1604 | +} |
| 1605 | + |
| 1606 | + |
| 1607 | +int ssb_pcmcia_get_invariants(struct ssb_bus *bus, |
| 1608 | + struct ssb_init_invariants *iv) |
| 1609 | +{ |
| 1610 | + struct ssb_sprom *sprom = &iv->sprom; |
| 1611 | + int res; |
| 1612 | + |
| 1613 | memset(sprom, 0xFF, sizeof(*sprom)); |
| 1614 | sprom->revision = 1; |
| 1615 | sprom->boardflags_lo = 0; |
| 1616 | sprom->boardflags_hi = 0; |
| 1617 | |
| 1618 | /* First fetch the MAC address. */ |
| 1619 | - memset(&tuple, 0, sizeof(tuple)); |
| 1620 | - tuple.DesiredTuple = CISTPL_FUNCE; |
| 1621 | - tuple.TupleData = buf; |
| 1622 | - tuple.TupleDataMax = sizeof(buf); |
| 1623 | - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple); |
| 1624 | - GOTO_ERROR_ON(res != 0, "MAC first tpl"); |
| 1625 | - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); |
| 1626 | - GOTO_ERROR_ON(res != 0, "MAC first tpl data"); |
| 1627 | - while (1) { |
| 1628 | - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1"); |
| 1629 | - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID) |
| 1630 | - break; |
| 1631 | - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple); |
| 1632 | - GOTO_ERROR_ON(res != 0, "MAC next tpl"); |
| 1633 | - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); |
| 1634 | - GOTO_ERROR_ON(res != 0, "MAC next tpl data"); |
| 1635 | + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE, |
| 1636 | + ssb_pcmcia_get_mac, sprom); |
| 1637 | + if (res != 0) { |
| 1638 | + ssb_printk(KERN_ERR PFX |
| 1639 | + "PCMCIA: Failed to fetch MAC address\n"); |
| 1640 | + return -ENODEV; |
| 1641 | } |
| 1642 | - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size"); |
| 1643 | - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN); |
| 1644 | |
| 1645 | /* Fetch the vendor specific tuples. */ |
| 1646 | - memset(&tuple, 0, sizeof(tuple)); |
| 1647 | - tuple.DesiredTuple = SSB_PCMCIA_CIS; |
| 1648 | - tuple.TupleData = buf; |
| 1649 | - tuple.TupleDataMax = sizeof(buf); |
| 1650 | - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple); |
| 1651 | - GOTO_ERROR_ON(res != 0, "VEN first tpl"); |
| 1652 | - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); |
| 1653 | - GOTO_ERROR_ON(res != 0, "VEN first tpl data"); |
| 1654 | - while (1) { |
| 1655 | - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1"); |
| 1656 | - switch (tuple.TupleData[0]) { |
| 1657 | - case SSB_PCMCIA_CIS_ID: |
| 1658 | - GOTO_ERROR_ON((tuple.TupleDataLen != 5) && |
| 1659 | - (tuple.TupleDataLen != 7), |
| 1660 | - "id tpl size"); |
| 1661 | - bi->vendor = tuple.TupleData[1] | |
| 1662 | - ((u16)tuple.TupleData[2] << 8); |
| 1663 | - break; |
| 1664 | - case SSB_PCMCIA_CIS_BOARDREV: |
| 1665 | - GOTO_ERROR_ON(tuple.TupleDataLen != 2, |
| 1666 | - "boardrev tpl size"); |
| 1667 | - sprom->board_rev = tuple.TupleData[1]; |
| 1668 | - break; |
| 1669 | - case SSB_PCMCIA_CIS_PA: |
| 1670 | - GOTO_ERROR_ON((tuple.TupleDataLen != 9) && |
| 1671 | - (tuple.TupleDataLen != 10), |
| 1672 | - "pa tpl size"); |
| 1673 | - sprom->pa0b0 = tuple.TupleData[1] | |
| 1674 | - ((u16)tuple.TupleData[2] << 8); |
| 1675 | - sprom->pa0b1 = tuple.TupleData[3] | |
| 1676 | - ((u16)tuple.TupleData[4] << 8); |
| 1677 | - sprom->pa0b2 = tuple.TupleData[5] | |
| 1678 | - ((u16)tuple.TupleData[6] << 8); |
| 1679 | - sprom->itssi_a = tuple.TupleData[7]; |
| 1680 | - sprom->itssi_bg = tuple.TupleData[7]; |
| 1681 | - sprom->maxpwr_a = tuple.TupleData[8]; |
| 1682 | - sprom->maxpwr_bg = tuple.TupleData[8]; |
| 1683 | - break; |
| 1684 | - case SSB_PCMCIA_CIS_OEMNAME: |
| 1685 | - /* We ignore this. */ |
| 1686 | - break; |
| 1687 | - case SSB_PCMCIA_CIS_CCODE: |
| 1688 | - GOTO_ERROR_ON(tuple.TupleDataLen != 2, |
| 1689 | - "ccode tpl size"); |
| 1690 | - sprom->country_code = tuple.TupleData[1]; |
| 1691 | - break; |
| 1692 | - case SSB_PCMCIA_CIS_ANTENNA: |
| 1693 | - GOTO_ERROR_ON(tuple.TupleDataLen != 2, |
| 1694 | - "ant tpl size"); |
| 1695 | - sprom->ant_available_a = tuple.TupleData[1]; |
| 1696 | - sprom->ant_available_bg = tuple.TupleData[1]; |
| 1697 | - break; |
| 1698 | - case SSB_PCMCIA_CIS_ANTGAIN: |
| 1699 | - GOTO_ERROR_ON(tuple.TupleDataLen != 2, |
| 1700 | - "antg tpl size"); |
| 1701 | - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1]; |
| 1702 | - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1]; |
| 1703 | - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1]; |
| 1704 | - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1]; |
| 1705 | - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1]; |
| 1706 | - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1]; |
| 1707 | - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1]; |
| 1708 | - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1]; |
| 1709 | - break; |
| 1710 | - case SSB_PCMCIA_CIS_BFLAGS: |
| 1711 | - GOTO_ERROR_ON((tuple.TupleDataLen != 3) && |
| 1712 | - (tuple.TupleDataLen != 5), |
| 1713 | - "bfl tpl size"); |
| 1714 | - sprom->boardflags_lo = tuple.TupleData[1] | |
| 1715 | - ((u16)tuple.TupleData[2] << 8); |
| 1716 | - break; |
| 1717 | - case SSB_PCMCIA_CIS_LEDS: |
| 1718 | - GOTO_ERROR_ON(tuple.TupleDataLen != 5, |
| 1719 | - "leds tpl size"); |
| 1720 | - sprom->gpio0 = tuple.TupleData[1]; |
| 1721 | - sprom->gpio1 = tuple.TupleData[2]; |
| 1722 | - sprom->gpio2 = tuple.TupleData[3]; |
| 1723 | - sprom->gpio3 = tuple.TupleData[4]; |
| 1724 | - break; |
| 1725 | - } |
| 1726 | - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple); |
| 1727 | - if (res == -ENOSPC) |
| 1728 | - break; |
| 1729 | - GOTO_ERROR_ON(res != 0, "VEN next tpl"); |
| 1730 | - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple); |
| 1731 | - GOTO_ERROR_ON(res != 0, "VEN next tpl data"); |
| 1732 | - } |
| 1733 | + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS, |
| 1734 | + ssb_pcmcia_do_get_invariants, iv); |
| 1735 | + if ((res == 0) || (res == -ENOSPC)) |
| 1736 | + return 0; |
| 1737 | |
| 1738 | - return 0; |
| 1739 | -error: |
| 1740 | ssb_printk(KERN_ERR PFX |
| 1741 | - "PCMCIA: Failed to fetch device invariants: %s\n", |
| 1742 | - error_description); |
| 1743 | + "PCMCIA: Failed to fetch device invariants\n"); |
| 1744 | return -ENODEV; |
| 1745 | } |
| 1746 | |
| 1747 | --- a/drivers/ssb/scan.c |
| 1748 | +++ b/drivers/ssb/scan.c |
| 1749 | @@ -260,7 +260,10 @@ static int we_support_multiple_80211_cor |
| 1750 | #ifdef CONFIG_SSB_PCIHOST |
| 1751 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
| 1752 | if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && |
| 1753 | - bus->host_pci->device == 0x4324) |
| 1754 | + ((bus->host_pci->device == 0x4313) || |
| 1755 | + (bus->host_pci->device == 0x431A) || |
| 1756 | + (bus->host_pci->device == 0x4321) || |
| 1757 | + (bus->host_pci->device == 0x4324))) |
| 1758 | return 1; |
| 1759 | } |
| 1760 | #endif /* CONFIG_SSB_PCIHOST */ |
| 1761 | @@ -309,8 +312,7 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 1762 | } else { |
| 1763 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
| 1764 | bus->chip_id = pcidev_to_chipid(bus->host_pci); |
| 1765 | - pci_read_config_word(bus->host_pci, PCI_REVISION_ID, |
| 1766 | - &bus->chip_rev); |
| 1767 | + bus->chip_rev = bus->host_pci->revision; |
| 1768 | bus->chip_package = 0; |
| 1769 | } else { |
| 1770 | bus->chip_id = 0x4710; |
| 1771 | @@ -354,7 +356,7 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 1772 | dev->bus = bus; |
| 1773 | dev->ops = bus->ops; |
| 1774 | |
| 1775 | - ssb_dprintk(KERN_INFO PFX |
| 1776 | + printk(KERN_DEBUG PFX |
| 1777 | "Core %d found: %s " |
| 1778 | "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n", |
| 1779 | i, ssb_core_name(dev->id.coreid), |
| 1780 | @@ -422,6 +424,16 @@ int ssb_bus_scan(struct ssb_bus *bus, |
| 1781 | bus->pcicore.dev = dev; |
| 1782 | #endif /* CONFIG_SSB_DRIVER_PCICORE */ |
| 1783 | break; |
| 1784 | + case SSB_DEV_ETHERNET: |
| 1785 | + if (bus->bustype == SSB_BUSTYPE_PCI) { |
| 1786 | + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && |
| 1787 | + (bus->host_pci->device & 0xFF00) == 0x4300) { |
| 1788 | + /* This is a dangling ethernet core on a |
| 1789 | + * wireless device. Ignore it. */ |
| 1790 | + continue; |
| 1791 | + } |
| 1792 | + } |
| 1793 | + break; |
| 1794 | default: |
| 1795 | break; |
| 1796 | } |
| 1797 | --- a/drivers/ssb/sprom.c |
| 1798 | +++ b/drivers/ssb/sprom.c |
| 1799 | @@ -14,9 +14,10 @@ |
| 1800 | #include "ssb_private.h" |
| 1801 | |
| 1802 | #include <linux/ctype.h> |
| 1803 | +#include <linux/slab.h> |
| 1804 | |
| 1805 | |
| 1806 | -static const struct ssb_sprom *fallback_sprom; |
| 1807 | +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out); |
| 1808 | |
| 1809 | |
| 1810 | static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len, |
| 1811 | @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_ |
| 1812 | u16 *sprom; |
| 1813 | int res = 0, err = -ENOMEM; |
| 1814 | size_t sprom_size_words = bus->sprom_size; |
| 1815 | + struct ssb_freeze_context freeze; |
| 1816 | |
| 1817 | sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL); |
| 1818 | if (!sprom) |
| 1819 | @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_ |
| 1820 | err = -ERESTARTSYS; |
| 1821 | if (mutex_lock_interruptible(&bus->sprom_mutex)) |
| 1822 | goto out_kfree; |
| 1823 | - err = ssb_devices_freeze(bus); |
| 1824 | - if (err == -EOPNOTSUPP) { |
| 1825 | - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. " |
| 1826 | - "No suspend support. Is CONFIG_PM enabled?\n"); |
| 1827 | - goto out_unlock; |
| 1828 | - } |
| 1829 | + err = ssb_devices_freeze(bus, &freeze); |
| 1830 | if (err) { |
| 1831 | ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n"); |
| 1832 | goto out_unlock; |
| 1833 | } |
| 1834 | res = sprom_write(bus, sprom); |
| 1835 | - err = ssb_devices_thaw(bus); |
| 1836 | + err = ssb_devices_thaw(&freeze); |
| 1837 | if (err) |
| 1838 | ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n"); |
| 1839 | out_unlock: |
| 1840 | @@ -148,36 +145,43 @@ out: |
| 1841 | } |
| 1842 | |
| 1843 | /** |
| 1844 | - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found. |
| 1845 | + * ssb_arch_register_fallback_sprom - Registers a method providing a |
| 1846 | + * fallback SPROM if no SPROM is found. |
| 1847 | * |
| 1848 | - * @sprom: The SPROM data structure to register. |
| 1849 | + * @sprom_callback: The callback function. |
| 1850 | * |
| 1851 | - * With this function the architecture implementation may register a fallback |
| 1852 | - * SPROM data structure. The fallback is only used for PCI based SSB devices, |
| 1853 | - * where no valid SPROM can be found in the shadow registers. |
| 1854 | + * With this function the architecture implementation may register a |
| 1855 | + * callback handler which fills the SPROM data structure. The fallback is |
| 1856 | + * only used for PCI based SSB devices, where no valid SPROM can be found |
| 1857 | + * in the shadow registers. |
| 1858 | * |
| 1859 | - * This function is useful for weird architectures that have a half-assed SSB device |
| 1860 | - * hardwired to their PCI bus. |
| 1861 | + * This function is useful for weird architectures that have a half-assed |
| 1862 | + * SSB device hardwired to their PCI bus. |
| 1863 | * |
| 1864 | - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently |
| 1865 | - * don't use this fallback. |
| 1866 | - * Architectures must provide the SPROM for native SSB devices anyway, |
| 1867 | - * so the fallback also isn't used for native devices. |
| 1868 | + * Note that it does only work with PCI attached SSB devices. PCMCIA |
| 1869 | + * devices currently don't use this fallback. |
| 1870 | + * Architectures must provide the SPROM for native SSB devices anyway, so |
| 1871 | + * the fallback also isn't used for native devices. |
| 1872 | * |
| 1873 | - * This function is available for architecture code, only. So it is not exported. |
| 1874 | + * This function is available for architecture code, only. So it is not |
| 1875 | + * exported. |
| 1876 | */ |
| 1877 | -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom) |
| 1878 | +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus, |
| 1879 | + struct ssb_sprom *out)) |
| 1880 | { |
| 1881 | - if (fallback_sprom) |
| 1882 | + if (get_fallback_sprom) |
| 1883 | return -EEXIST; |
| 1884 | - fallback_sprom = sprom; |
| 1885 | + get_fallback_sprom = sprom_callback; |
| 1886 | |
| 1887 | return 0; |
| 1888 | } |
| 1889 | |
| 1890 | -const struct ssb_sprom *ssb_get_fallback_sprom(void) |
| 1891 | +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out) |
| 1892 | { |
| 1893 | - return fallback_sprom; |
| 1894 | + if (!get_fallback_sprom) |
| 1895 | + return -ENOENT; |
| 1896 | + |
| 1897 | + return get_fallback_sprom(bus, out); |
| 1898 | } |
| 1899 | |
| 1900 | /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ |
| 1901 | @@ -188,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b |
| 1902 | /* this routine differs from specs as we do not access SPROM directly |
| 1903 | on PCMCIA */ |
| 1904 | if (bus->bustype == SSB_BUSTYPE_PCI && |
| 1905 | - bus->chipco.dev && /* can be unavailible! */ |
| 1906 | + bus->chipco.dev && /* can be unavailable! */ |
| 1907 | bus->chipco.dev->id.revision >= 31) |
| 1908 | return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM; |
| 1909 | |
| 1910 | --- a/drivers/ssb/ssb_private.h |
| 1911 | +++ b/drivers/ssb/ssb_private.h |
| 1912 | @@ -171,24 +171,33 @@ ssize_t ssb_attr_sprom_store(struct ssb_ |
| 1913 | const char *buf, size_t count, |
| 1914 | int (*sprom_check_crc)(const u16 *sprom, size_t size), |
| 1915 | int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom)); |
| 1916 | -extern const struct ssb_sprom *ssb_get_fallback_sprom(void); |
| 1917 | +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, |
| 1918 | + struct ssb_sprom *out); |
| 1919 | |
| 1920 | |
| 1921 | /* core.c */ |
| 1922 | extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m); |
| 1923 | -extern int ssb_devices_freeze(struct ssb_bus *bus); |
| 1924 | -extern int ssb_devices_thaw(struct ssb_bus *bus); |
| 1925 | extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev); |
| 1926 | int ssb_for_each_bus_call(unsigned long data, |
| 1927 | int (*func)(struct ssb_bus *bus, unsigned long data)); |
| 1928 | extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev); |
| 1929 | |
| 1930 | +struct ssb_freeze_context { |
| 1931 | + /* Pointer to the bus */ |
| 1932 | + struct ssb_bus *bus; |
| 1933 | + /* Boolean list to indicate whether a device is frozen on this bus. */ |
| 1934 | + bool device_frozen[SSB_MAX_NR_CORES]; |
| 1935 | +}; |
| 1936 | +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx); |
| 1937 | +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx); |
| 1938 | + |
| 1939 | + |
| 1940 | |
| 1941 | /* b43_pci_bridge.c */ |
| 1942 | #ifdef CONFIG_SSB_B43_PCI_BRIDGE |
| 1943 | extern int __init b43_pci_ssb_bridge_init(void); |
| 1944 | extern void __exit b43_pci_ssb_bridge_exit(void); |
| 1945 | -#else /* CONFIG_SSB_B43_PCI_BRIDGR */ |
| 1946 | +#else /* CONFIG_SSB_B43_PCI_BRIDGE */ |
| 1947 | static inline int b43_pci_ssb_bridge_init(void) |
| 1948 | { |
| 1949 | return 0; |
| 1950 | @@ -196,6 +205,6 @@ static inline int b43_pci_ssb_bridge_ini |
| 1951 | static inline void b43_pci_ssb_bridge_exit(void) |
| 1952 | { |
| 1953 | } |
| 1954 | -#endif /* CONFIG_SSB_PCIHOST */ |
| 1955 | +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */ |
| 1956 | |
| 1957 | #endif /* LINUX_SSB_PRIVATE_H_ */ |
| 1958 | --- a/include/linux/ssb/ssb.h |
| 1959 | +++ b/include/linux/ssb/ssb.h |
| 1960 | @@ -27,6 +27,8 @@ struct ssb_sprom { |
| 1961 | u8 et1mdcport; /* MDIO for enet1 */ |
| 1962 | u8 board_rev; /* Board revision number from SPROM. */ |
| 1963 | u8 country_code; /* Country Code */ |
| 1964 | + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */ |
| 1965 | + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ |
| 1966 | u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ |
| 1967 | u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */ |
| 1968 | u16 pa0b0; |
| 1969 | @@ -55,6 +57,10 @@ struct ssb_sprom { |
| 1970 | u8 tri5gl; /* 5.2GHz TX isolation */ |
| 1971 | u8 tri5g; /* 5.3GHz TX isolation */ |
| 1972 | u8 tri5gh; /* 5.8GHz TX isolation */ |
| 1973 | + u8 txpid2g[4]; /* 2GHz TX power index */ |
| 1974 | + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ |
| 1975 | + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ |
| 1976 | + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ |
| 1977 | u8 rxpo2g; /* 2GHz RX power offset */ |
| 1978 | u8 rxpo5g; /* 5GHz RX power offset */ |
| 1979 | u8 rssisav2g; /* 2GHz RSSI params */ |
| 1980 | @@ -95,7 +101,7 @@ struct ssb_sprom { |
| 1981 | struct ssb_boardinfo { |
| 1982 | u16 vendor; |
| 1983 | u16 type; |
| 1984 | - u16 rev; |
| 1985 | + u8 rev; |
| 1986 | }; |
| 1987 | |
| 1988 | |
| 1989 | @@ -167,7 +173,7 @@ struct ssb_device { |
| 1990 | * is an optimization. */ |
| 1991 | const struct ssb_bus_ops *ops; |
| 1992 | |
| 1993 | - struct device *dev; |
| 1994 | + struct device *dev, *dma_dev; |
| 1995 | |
| 1996 | struct ssb_bus *bus; |
| 1997 | struct ssb_device_id id; |
| 1998 | @@ -269,7 +275,8 @@ struct ssb_bus { |
| 1999 | |
| 2000 | const struct ssb_bus_ops *ops; |
| 2001 | |
| 2002 | - /* The core in the basic address register window. (PCI bus only) */ |
| 2003 | + /* The core currently mapped into the MMIO window. |
| 2004 | + * Not valid on all host-buses. So don't use outside of SSB. */ |
| 2005 | struct ssb_device *mapped_device; |
| 2006 | union { |
| 2007 | /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ |
| 2008 | @@ -281,14 +288,17 @@ struct ssb_bus { |
| 2009 | * On PCMCIA-host busses this is used to protect the whole MMIO access. */ |
| 2010 | spinlock_t bar_lock; |
| 2011 | |
| 2012 | - /* The bus this backplane is running on. */ |
| 2013 | + /* The host-bus this backplane is running on. */ |
| 2014 | enum ssb_bustype bustype; |
| 2015 | - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ |
| 2016 | - struct pci_dev *host_pci; |
| 2017 | - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ |
| 2018 | - struct pcmcia_device *host_pcmcia; |
| 2019 | - /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */ |
| 2020 | - struct sdio_func *host_sdio; |
| 2021 | + /* Pointers to the host-bus. Check bustype before using any of these pointers. */ |
| 2022 | + union { |
| 2023 | + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ |
| 2024 | + struct pci_dev *host_pci; |
| 2025 | + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ |
| 2026 | + struct pcmcia_device *host_pcmcia; |
| 2027 | + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */ |
| 2028 | + struct sdio_func *host_sdio; |
| 2029 | + }; |
| 2030 | |
| 2031 | /* See enum ssb_quirks */ |
| 2032 | unsigned int quirks; |
| 2033 | @@ -300,7 +310,7 @@ struct ssb_bus { |
| 2034 | |
| 2035 | /* ID information about the Chip. */ |
| 2036 | u16 chip_id; |
| 2037 | - u16 chip_rev; |
| 2038 | + u8 chip_rev; |
| 2039 | u16 sprom_offset; |
| 2040 | u16 sprom_size; /* number of words in sprom */ |
| 2041 | u8 chip_package; |
| 2042 | @@ -396,7 +406,9 @@ extern bool ssb_is_sprom_available(struc |
| 2043 | |
| 2044 | /* Set a fallback SPROM. |
| 2045 | * See kdoc at the function definition for complete documentation. */ |
| 2046 | -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom); |
| 2047 | +extern int ssb_arch_register_fallback_sprom( |
| 2048 | + int (*sprom_callback)(struct ssb_bus *bus, |
| 2049 | + struct ssb_sprom *out)); |
| 2050 | |
| 2051 | /* Suspend a SSB bus. |
| 2052 | * Call this from the parent bus suspend routine. */ |
| 2053 | @@ -667,6 +679,7 @@ extern int ssb_bus_may_powerdown(struct |
| 2054 | * Otherwise static always-on powercontrol will be used. */ |
| 2055 | extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl); |
| 2056 | |
| 2057 | +extern void ssb_commit_settings(struct ssb_bus *bus); |
| 2058 | |
| 2059 | /* Various helper functions */ |
| 2060 | extern u32 ssb_admatch_base(u32 adm); |
| 2061 | --- a/include/linux/ssb/ssb_regs.h |
| 2062 | +++ b/include/linux/ssb/ssb_regs.h |
| 2063 | @@ -85,6 +85,8 @@ |
| 2064 | #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */ |
| 2065 | #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */ |
| 2066 | #define SSB_IMSTATE_TO 0x00040000 /* Timeout */ |
| 2067 | +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */ |
| 2068 | +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */ |
| 2069 | #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */ |
| 2070 | #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ |
| 2071 | #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ |
| 2072 | @@ -95,7 +97,7 @@ |
| 2073 | #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ |
| 2074 | #define SSB_TMSLOW 0x0F98 /* SB Target State Low */ |
| 2075 | #define SSB_TMSLOW_RESET 0x00000001 /* Reset */ |
| 2076 | -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */ |
| 2077 | +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */ |
| 2078 | #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */ |
| 2079 | #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */ |
| 2080 | #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ |
| 2081 | @@ -172,25 +174,25 @@ |
| 2082 | #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16)) |
| 2083 | #define SSB_SPROM_BASE1 0x1000 |
| 2084 | #define SSB_SPROM_BASE31 0x0800 |
| 2085 | -#define SSB_SPROM_REVISION 0x107E |
| 2086 | +#define SSB_SPROM_REVISION 0x007E |
| 2087 | #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ |
| 2088 | #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ |
| 2089 | #define SSB_SPROM_REVISION_CRC_SHIFT 8 |
| 2090 | |
| 2091 | /* SPROM Revision 1 */ |
| 2092 | -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ |
| 2093 | -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ |
| 2094 | -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */ |
| 2095 | -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */ |
| 2096 | -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */ |
| 2097 | -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */ |
| 2098 | -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */ |
| 2099 | +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */ |
| 2100 | +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */ |
| 2101 | +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */ |
| 2102 | +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */ |
| 2103 | +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */ |
| 2104 | +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */ |
| 2105 | +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */ |
| 2106 | #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ |
| 2107 | #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ |
| 2108 | #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5 |
| 2109 | #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ |
| 2110 | #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ |
| 2111 | -#define SSB_SPROM1_BINF 0x105C /* Board info */ |
| 2112 | +#define SSB_SPROM1_BINF 0x005C /* Board info */ |
| 2113 | #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ |
| 2114 | #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ |
| 2115 | #define SSB_SPROM1_BINF_CCODE_SHIFT 8 |
| 2116 | @@ -198,63 +200,63 @@ |
| 2117 | #define SSB_SPROM1_BINF_ANTBG_SHIFT 12 |
| 2118 | #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */ |
| 2119 | #define SSB_SPROM1_BINF_ANTA_SHIFT 14 |
| 2120 | -#define SSB_SPROM1_PA0B0 0x105E |
| 2121 | -#define SSB_SPROM1_PA0B1 0x1060 |
| 2122 | -#define SSB_SPROM1_PA0B2 0x1062 |
| 2123 | -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */ |
| 2124 | +#define SSB_SPROM1_PA0B0 0x005E |
| 2125 | +#define SSB_SPROM1_PA0B1 0x0060 |
| 2126 | +#define SSB_SPROM1_PA0B2 0x0062 |
| 2127 | +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */ |
| 2128 | #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */ |
| 2129 | #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 2130 | #define SSB_SPROM1_GPIOA_P1_SHIFT 8 |
| 2131 | -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */ |
| 2132 | +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */ |
| 2133 | #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */ |
| 2134 | #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 2135 | #define SSB_SPROM1_GPIOB_P3_SHIFT 8 |
| 2136 | -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */ |
| 2137 | +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */ |
| 2138 | #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */ |
| 2139 | #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */ |
| 2140 | #define SSB_SPROM1_MAXPWR_A_SHIFT 8 |
| 2141 | -#define SSB_SPROM1_PA1B0 0x106A |
| 2142 | -#define SSB_SPROM1_PA1B1 0x106C |
| 2143 | -#define SSB_SPROM1_PA1B2 0x106E |
| 2144 | -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */ |
| 2145 | +#define SSB_SPROM1_PA1B0 0x006A |
| 2146 | +#define SSB_SPROM1_PA1B1 0x006C |
| 2147 | +#define SSB_SPROM1_PA1B2 0x006E |
| 2148 | +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */ |
| 2149 | #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/ |
| 2150 | #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */ |
| 2151 | #define SSB_SPROM1_ITSSI_A_SHIFT 8 |
| 2152 | -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */ |
| 2153 | -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */ |
| 2154 | +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */ |
| 2155 | +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */ |
| 2156 | #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */ |
| 2157 | #define SSB_SPROM1_AGAIN_BG_SHIFT 0 |
| 2158 | #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */ |
| 2159 | #define SSB_SPROM1_AGAIN_A_SHIFT 8 |
| 2160 | |
| 2161 | /* SPROM Revision 2 (inherits from rev 1) */ |
| 2162 | -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ |
| 2163 | -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ |
| 2164 | +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */ |
| 2165 | +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */ |
| 2166 | #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */ |
| 2167 | #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */ |
| 2168 | #define SSB_SPROM2_MAXP_A_LO_SHIFT 8 |
| 2169 | -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */ |
| 2170 | -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */ |
| 2171 | -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */ |
| 2172 | -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */ |
| 2173 | -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */ |
| 2174 | -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */ |
| 2175 | -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */ |
| 2176 | +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */ |
| 2177 | +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */ |
| 2178 | +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */ |
| 2179 | +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */ |
| 2180 | +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */ |
| 2181 | +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */ |
| 2182 | +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */ |
| 2183 | #define SSB_SPROM2_OPO_VALUE 0x00FF |
| 2184 | #define SSB_SPROM2_OPO_UNUSED 0xFF00 |
| 2185 | -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ |
| 2186 | +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */ |
| 2187 | |
| 2188 | /* SPROM Revision 3 (inherits most data from rev 2) */ |
| 2189 | -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */ |
| 2190 | -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ |
| 2191 | -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ |
| 2192 | -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ |
| 2193 | -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ |
| 2194 | +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ |
| 2195 | +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ |
| 2196 | +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ |
| 2197 | +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ |
| 2198 | #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */ |
| 2199 | #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 |
| 2200 | #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ |
| 2201 | #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 |
| 2202 | -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */ |
| 2203 | +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */ |
| 2204 | +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */ |
| 2205 | #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ |
| 2206 | #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ |
| 2207 | #define SSB_SPROM3_CCKPO_2M_SHIFT 4 |
| 2208 | @@ -265,100 +267,144 @@ |
| 2209 | #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ |
| 2210 | |
| 2211 | /* SPROM Revision 4 */ |
| 2212 | -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */ |
| 2213 | -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */ |
| 2214 | +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ |
| 2215 | +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ |
| 2216 | +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */ |
| 2217 | +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */ |
| 2218 | +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */ |
| 2219 | +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */ |
| 2220 | +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */ |
| 2221 | +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ |
| 2222 | +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 2223 | +#define SSB_SPROM4_GPIOA_P1_SHIFT 8 |
| 2224 | +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */ |
| 2225 | +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ |
| 2226 | +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 2227 | +#define SSB_SPROM4_GPIOB_P3_SHIFT 8 |
| 2228 | +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */ |
| 2229 | #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ |
| 2230 | #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ |
| 2231 | #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 |
| 2232 | #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ |
| 2233 | #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ |
| 2234 | -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */ |
| 2235 | -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */ |
| 2236 | -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ |
| 2237 | -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 |
| 2238 | -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ |
| 2239 | -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 |
| 2240 | -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */ |
| 2241 | -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */ |
| 2242 | +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ |
| 2243 | +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ |
| 2244 | +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 |
| 2245 | +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ |
| 2246 | +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 |
| 2247 | +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ |
| 2248 | #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ |
| 2249 | #define SSB_SPROM4_AGAIN0_SHIFT 0 |
| 2250 | #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */ |
| 2251 | #define SSB_SPROM4_AGAIN1_SHIFT 8 |
| 2252 | -#define SSB_SPROM4_AGAIN23 0x1060 |
| 2253 | +#define SSB_SPROM4_AGAIN23 0x0060 |
| 2254 | #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */ |
| 2255 | #define SSB_SPROM4_AGAIN2_SHIFT 0 |
| 2256 | #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ |
| 2257 | #define SSB_SPROM4_AGAIN3_SHIFT 8 |
| 2258 | -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ |
| 2259 | -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */ |
| 2260 | +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */ |
| 2261 | +#define SSB_SPROM4_TXPID2G0 0x00FF |
| 2262 | +#define SSB_SPROM4_TXPID2G0_SHIFT 0 |
| 2263 | +#define SSB_SPROM4_TXPID2G1 0xFF00 |
| 2264 | +#define SSB_SPROM4_TXPID2G1_SHIFT 8 |
| 2265 | +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */ |
| 2266 | +#define SSB_SPROM4_TXPID2G2 0x00FF |
| 2267 | +#define SSB_SPROM4_TXPID2G2_SHIFT 0 |
| 2268 | +#define SSB_SPROM4_TXPID2G3 0xFF00 |
| 2269 | +#define SSB_SPROM4_TXPID2G3_SHIFT 8 |
| 2270 | +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */ |
| 2271 | +#define SSB_SPROM4_TXPID5G0 0x00FF |
| 2272 | +#define SSB_SPROM4_TXPID5G0_SHIFT 0 |
| 2273 | +#define SSB_SPROM4_TXPID5G1 0xFF00 |
| 2274 | +#define SSB_SPROM4_TXPID5G1_SHIFT 8 |
| 2275 | +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */ |
| 2276 | +#define SSB_SPROM4_TXPID5G2 0x00FF |
| 2277 | +#define SSB_SPROM4_TXPID5G2_SHIFT 0 |
| 2278 | +#define SSB_SPROM4_TXPID5G3 0xFF00 |
| 2279 | +#define SSB_SPROM4_TXPID5G3_SHIFT 8 |
| 2280 | +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */ |
| 2281 | +#define SSB_SPROM4_TXPID5GL0 0x00FF |
| 2282 | +#define SSB_SPROM4_TXPID5GL0_SHIFT 0 |
| 2283 | +#define SSB_SPROM4_TXPID5GL1 0xFF00 |
| 2284 | +#define SSB_SPROM4_TXPID5GL1_SHIFT 8 |
| 2285 | +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */ |
| 2286 | +#define SSB_SPROM4_TXPID5GL2 0x00FF |
| 2287 | +#define SSB_SPROM4_TXPID5GL2_SHIFT 0 |
| 2288 | +#define SSB_SPROM4_TXPID5GL3 0xFF00 |
| 2289 | +#define SSB_SPROM4_TXPID5GL3_SHIFT 8 |
| 2290 | +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */ |
| 2291 | +#define SSB_SPROM4_TXPID5GH0 0x00FF |
| 2292 | +#define SSB_SPROM4_TXPID5GH0_SHIFT 0 |
| 2293 | +#define SSB_SPROM4_TXPID5GH1 0xFF00 |
| 2294 | +#define SSB_SPROM4_TXPID5GH1_SHIFT 8 |
| 2295 | +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */ |
| 2296 | +#define SSB_SPROM4_TXPID5GH2 0x00FF |
| 2297 | +#define SSB_SPROM4_TXPID5GH2_SHIFT 0 |
| 2298 | +#define SSB_SPROM4_TXPID5GH3 0xFF00 |
| 2299 | +#define SSB_SPROM4_TXPID5GH3_SHIFT 8 |
| 2300 | +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ |
| 2301 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ |
| 2302 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 2303 | #define SSB_SPROM4_ITSSI_BG_SHIFT 8 |
| 2304 | -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */ |
| 2305 | +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */ |
| 2306 | #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ |
| 2307 | #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ |
| 2308 | #define SSB_SPROM4_ITSSI_A_SHIFT 8 |
| 2309 | -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */ |
| 2310 | -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ |
| 2311 | -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 2312 | -#define SSB_SPROM4_GPIOA_P1_SHIFT 8 |
| 2313 | -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */ |
| 2314 | -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ |
| 2315 | -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 2316 | -#define SSB_SPROM4_GPIOB_P3_SHIFT 8 |
| 2317 | -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */ |
| 2318 | -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */ |
| 2319 | -#define SSB_SPROM4_PA0B2 0x1086 |
| 2320 | -#define SSB_SPROM4_PA1B0 0x108E |
| 2321 | -#define SSB_SPROM4_PA1B1 0x1090 |
| 2322 | -#define SSB_SPROM4_PA1B2 0x1092 |
| 2323 | +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */ |
| 2324 | +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */ |
| 2325 | +#define SSB_SPROM4_PA0B2 0x0086 |
| 2326 | +#define SSB_SPROM4_PA1B0 0x008E |
| 2327 | +#define SSB_SPROM4_PA1B1 0x0090 |
| 2328 | +#define SSB_SPROM4_PA1B2 0x0092 |
| 2329 | |
| 2330 | /* SPROM Revision 5 (inherits most data from rev 4) */ |
| 2331 | -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */ |
| 2332 | -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */ |
| 2333 | -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */ |
| 2334 | -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */ |
| 2335 | -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */ |
| 2336 | +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */ |
| 2337 | +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */ |
| 2338 | +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */ |
| 2339 | +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */ |
| 2340 | +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */ |
| 2341 | +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */ |
| 2342 | +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */ |
| 2343 | #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ |
| 2344 | #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 2345 | #define SSB_SPROM5_GPIOA_P1_SHIFT 8 |
| 2346 | -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */ |
| 2347 | +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */ |
| 2348 | #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */ |
| 2349 | #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 2350 | #define SSB_SPROM5_GPIOB_P3_SHIFT 8 |
| 2351 | |
| 2352 | /* SPROM Revision 8 */ |
| 2353 | -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */ |
| 2354 | -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */ |
| 2355 | -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */ |
| 2356 | -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */ |
| 2357 | -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */ |
| 2358 | -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */ |
| 2359 | -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */ |
| 2360 | -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/ |
| 2361 | -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ |
| 2362 | -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 |
| 2363 | -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ |
| 2364 | -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 |
| 2365 | -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */ |
| 2366 | +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */ |
| 2367 | +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */ |
| 2368 | +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */ |
| 2369 | +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */ |
| 2370 | +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */ |
| 2371 | +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */ |
| 2372 | +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */ |
| 2373 | +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */ |
| 2374 | +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ |
| 2375 | +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 2376 | +#define SSB_SPROM8_GPIOA_P1_SHIFT 8 |
| 2377 | +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */ |
| 2378 | +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ |
| 2379 | +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 2380 | +#define SSB_SPROM8_GPIOB_P3_SHIFT 8 |
| 2381 | +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/ |
| 2382 | +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ |
| 2383 | +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 |
| 2384 | +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ |
| 2385 | +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 |
| 2386 | +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */ |
| 2387 | #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */ |
| 2388 | #define SSB_SPROM8_AGAIN0_SHIFT 0 |
| 2389 | #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */ |
| 2390 | #define SSB_SPROM8_AGAIN1_SHIFT 8 |
| 2391 | -#define SSB_SPROM8_AGAIN23 0x10A0 |
| 2392 | +#define SSB_SPROM8_AGAIN23 0x00A0 |
| 2393 | #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */ |
| 2394 | #define SSB_SPROM8_AGAIN2_SHIFT 0 |
| 2395 | #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */ |
| 2396 | #define SSB_SPROM8_AGAIN3_SHIFT 8 |
| 2397 | -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */ |
| 2398 | -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ |
| 2399 | -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 2400 | -#define SSB_SPROM8_GPIOA_P1_SHIFT 8 |
| 2401 | -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */ |
| 2402 | -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ |
| 2403 | -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 2404 | -#define SSB_SPROM8_GPIOB_P3_SHIFT 8 |
| 2405 | -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */ |
| 2406 | +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */ |
| 2407 | #define SSB_SPROM8_RSSISMF2G 0x000F |
| 2408 | #define SSB_SPROM8_RSSISMC2G 0x00F0 |
| 2409 | #define SSB_SPROM8_RSSISMC2G_SHIFT 4 |
| 2410 | @@ -366,7 +412,7 @@ |
| 2411 | #define SSB_SPROM8_RSSISAV2G_SHIFT 8 |
| 2412 | #define SSB_SPROM8_BXA2G 0x1800 |
| 2413 | #define SSB_SPROM8_BXA2G_SHIFT 11 |
| 2414 | -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */ |
| 2415 | +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */ |
| 2416 | #define SSB_SPROM8_RSSISMF5G 0x000F |
| 2417 | #define SSB_SPROM8_RSSISMC5G 0x00F0 |
| 2418 | #define SSB_SPROM8_RSSISMC5G_SHIFT 4 |
| 2419 | @@ -374,47 +420,47 @@ |
| 2420 | #define SSB_SPROM8_RSSISAV5G_SHIFT 8 |
| 2421 | #define SSB_SPROM8_BXA5G 0x1800 |
| 2422 | #define SSB_SPROM8_BXA5G_SHIFT 11 |
| 2423 | -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */ |
| 2424 | +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */ |
| 2425 | #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */ |
| 2426 | #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */ |
| 2427 | #define SSB_SPROM8_TRI5G_SHIFT 8 |
| 2428 | -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */ |
| 2429 | +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */ |
| 2430 | #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */ |
| 2431 | #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */ |
| 2432 | #define SSB_SPROM8_TRI5GH_SHIFT 8 |
| 2433 | -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */ |
| 2434 | +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */ |
| 2435 | #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ |
| 2436 | #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ |
| 2437 | #define SSB_SPROM8_RXPO5G_SHIFT 8 |
| 2438 | -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */ |
| 2439 | +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ |
| 2440 | #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ |
| 2441 | #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 2442 | #define SSB_SPROM8_ITSSI_BG_SHIFT 8 |
| 2443 | -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */ |
| 2444 | -#define SSB_SPROM8_PA0B1 0x10C4 |
| 2445 | -#define SSB_SPROM8_PA0B2 0x10C6 |
| 2446 | -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */ |
| 2447 | +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */ |
| 2448 | +#define SSB_SPROM8_PA0B1 0x00C4 |
| 2449 | +#define SSB_SPROM8_PA0B2 0x00C6 |
| 2450 | +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */ |
| 2451 | #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */ |
| 2452 | #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ |
| 2453 | #define SSB_SPROM8_ITSSI_A_SHIFT 8 |
| 2454 | -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */ |
| 2455 | +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */ |
| 2456 | #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */ |
| 2457 | #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */ |
| 2458 | #define SSB_SPROM8_MAXP_AL_SHIFT 8 |
| 2459 | -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */ |
| 2460 | -#define SSB_SPROM8_PA1B1 0x10CE |
| 2461 | -#define SSB_SPROM8_PA1B2 0x10D0 |
| 2462 | -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */ |
| 2463 | -#define SSB_SPROM8_PA1LOB1 0x10D4 |
| 2464 | -#define SSB_SPROM8_PA1LOB2 0x10D6 |
| 2465 | -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */ |
| 2466 | -#define SSB_SPROM8_PA1HIB1 0x10DA |
| 2467 | -#define SSB_SPROM8_PA1HIB2 0x10DC |
| 2468 | -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */ |
| 2469 | -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */ |
| 2470 | -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */ |
| 2471 | -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */ |
| 2472 | -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */ |
| 2473 | +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */ |
| 2474 | +#define SSB_SPROM8_PA1B1 0x00CE |
| 2475 | +#define SSB_SPROM8_PA1B2 0x00D0 |
| 2476 | +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */ |
| 2477 | +#define SSB_SPROM8_PA1LOB1 0x00D4 |
| 2478 | +#define SSB_SPROM8_PA1LOB2 0x00D6 |
| 2479 | +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */ |
| 2480 | +#define SSB_SPROM8_PA1HIB1 0x00DA |
| 2481 | +#define SSB_SPROM8_PA1HIB2 0x00DC |
| 2482 | +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */ |
| 2483 | +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */ |
| 2484 | +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */ |
| 2485 | +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */ |
| 2486 | +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */ |
| 2487 | |
| 2488 | /* Values for SSB_SPROM1_BINF_CCODE */ |
| 2489 | enum { |
| 2490 | --- a/include/linux/ssb/ssb_driver_chipcommon.h |
| 2491 | +++ b/include/linux/ssb/ssb_driver_chipcommon.h |
| 2492 | @@ -123,6 +123,8 @@ |
| 2493 | #define SSB_CHIPCO_FLASHDATA 0x0048 |
| 2494 | #define SSB_CHIPCO_BCAST_ADDR 0x0050 |
| 2495 | #define SSB_CHIPCO_BCAST_DATA 0x0054 |
| 2496 | +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */ |
| 2497 | +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */ |
| 2498 | #define SSB_CHIPCO_GPIOIN 0x0060 |
| 2499 | #define SSB_CHIPCO_GPIOOUT 0x0064 |
| 2500 | #define SSB_CHIPCO_GPIOOUTEN 0x0068 |
| 2501 | @@ -131,6 +133,9 @@ |
| 2502 | #define SSB_CHIPCO_GPIOIRQ 0x0074 |
| 2503 | #define SSB_CHIPCO_WATCHDOG 0x0080 |
| 2504 | #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ |
| 2505 | +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF |
| 2506 | +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0 |
| 2507 | +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000 |
| 2508 | #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16 |
| 2509 | #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ |
| 2510 | #define SSB_CHIPCO_CLOCK_N 0x0090 |
| 2511 | @@ -189,8 +194,10 @@ |
| 2512 | #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */ |
| 2513 | #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ |
| 2514 | #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ |
| 2515 | -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */ |
| 2516 | -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */ |
| 2517 | +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */ |
| 2518 | +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */ |
| 2519 | +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */ |
| 2520 | +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */ |
| 2521 | #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ |
| 2522 | #define SSB_CHIPCO_UART0_DATA 0x0300 |
| 2523 | #define SSB_CHIPCO_UART0_IMR 0x0304 |
| 2524 | |
