| 1 | --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h |
| 2 | +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h |
| 3 | @@ -40,6 +40,15 @@ |
| 4 | |
| 5 | #define MIPS_CPU_TIMER_IRQ 7 |
| 6 | |
| 7 | +#ifdef CONFIG_SOC_AMAZON_SE |
| 8 | +#define LTQ_DMA_CH0_INT (INT_NUM_IM3_IRL0) |
| 9 | +#define LTQ_DMA_CH1_INT (INT_NUM_IM3_IRL0 + 1) |
| 10 | +#define LTQ_DMA_CH2_INT (INT_NUM_IM3_IRL0 + 2) |
| 11 | +#define LTQ_DMA_CH3_INT (INT_NUM_IM3_IRL0 + 3) |
| 12 | +#define LTQ_DMA_CH4_INT (INT_NUM_IM3_IRL0 + 4) |
| 13 | +#define LTQ_DMA_CH5_INT (INT_NUM_IM3_IRL0 + 5) |
| 14 | +#define LTQ_DMA_CH6_INT (INT_NUM_IM3_IRL0 + 6) |
| 15 | +#else |
| 16 | #define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) |
| 17 | #define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) |
| 18 | #define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) |
| 19 | @@ -47,6 +56,7 @@ |
| 20 | #define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) |
| 21 | #define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) |
| 22 | #define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) |
| 23 | +#endif |
| 24 | #define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) |
| 25 | #define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) |
| 26 | #define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) |
| 27 | --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h |
| 28 | +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h |
| 29 | @@ -128,6 +128,11 @@ |
| 30 | extern void ltq_pmu_enable(unsigned int module); |
| 31 | extern void ltq_pmu_disable(unsigned int module); |
| 32 | |
| 33 | +static inline int ltq_is_ase(void) |
| 34 | +{ |
| 35 | + return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE); |
| 36 | +} |
| 37 | + |
| 38 | static inline int ltq_is_ar9(void) |
| 39 | { |
| 40 | return (ltq_get_soc_type() == SOC_TYPE_AR9); |
| 41 | --- a/arch/mips/lantiq/xway/mach-easy50601.c |
| 42 | +++ b/arch/mips/lantiq/xway/mach-easy50601.c |
| 43 | @@ -41,9 +41,14 @@ |
| 44 | .parts = easy50601_partitions, |
| 45 | }; |
| 46 | |
| 47 | +static struct ltq_eth_data ltq_eth_data = { |
| 48 | + .mii_mode = -1, /* use EPHY */ |
| 49 | +}; |
| 50 | + |
| 51 | static void __init easy50601_init(void) |
| 52 | { |
| 53 | ltq_register_nor(&easy50601_flash_data); |
| 54 | + ltq_register_etop(<q_eth_data); |
| 55 | } |
| 56 | |
| 57 | MIPS_MACHINE(LTQ_MACH_EASY50601, |
| 58 | --- a/drivers/net/lantiq_etop.c |
| 59 | +++ b/drivers/net/lantiq_etop.c |
| 60 | @@ -72,7 +72,11 @@ |
| 61 | |
| 62 | /* use 2 static channels for TX/RX */ |
| 63 | #define LTQ_ETOP_TX_CHANNEL 1 |
| 64 | +#ifdef CONFIG_SOC_AMAZON_SE |
| 65 | +#define LTQ_ETOP_RX_CHANNEL 5 |
| 66 | +#else |
| 67 | #define LTQ_ETOP_RX_CHANNEL 6 |
| 68 | +#endif |
| 69 | #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) |
| 70 | #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) |
| 71 | |
| 72 | @@ -255,6 +259,9 @@ |
| 73 | } |
| 74 | |
| 75 | static int |
| 76 | +ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data); |
| 77 | + |
| 78 | +static int |
| 79 | ltq_etop_hw_init(struct net_device *dev) |
| 80 | { |
| 81 | struct ltq_etop_priv *priv = netdev_priv(dev); |
| 82 | @@ -274,6 +281,16 @@ |
| 83 | break; |
| 84 | |
| 85 | default: |
| 86 | + if (ltq_is_ase()) { |
| 87 | +#define PMU_EPHY 0x80 |
| 88 | +#define LTQ_CGU_IFCCR 0x0018 |
| 89 | + ltq_pmu_enable(PMU_EPHY); |
| 90 | + ltq_etop_w32_mask(0, 1, LTQ_ETOP_CFG); |
| 91 | + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (0x1 << 4), LTQ_CGU_IFCCR); |
| 92 | + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); |
| 93 | + printk("Selected EPHY mode \n"); |
| 94 | + break; |
| 95 | + } |
| 96 | netdev_err(dev, "unknown mii mode %d\n", |
| 97 | priv->pldata->mii_mode); |
| 98 | return -ENOTSUPP; |
| 99 | |
