| 1 | From d9355bb07878f9aa40856cc437c43cedc87662fc Mon Sep 17 00:00:00 2001 |
| 2 | From: John Crispin <blogic@openwrt.org> |
| 3 | Date: Thu, 11 Aug 2011 12:25:55 +0200 |
| 4 | Subject: [PATCH 05/24] MIPS: lantiq: make irq.c support the FALC-ON |
| 5 | |
| 6 | There are minor differences in how irqs work on xway and falcon socs. |
| 7 | Xway needs 2 quirks that we need to disable for falcon to also work with |
| 8 | this code. |
| 9 | |
| 10 | * EBU irq does not need to send a special ack to the EBU |
| 11 | * The EIU does not exist |
| 12 | |
| 13 | Signed-off-by: John Crispin <blogic@openwrt.org> |
| 14 | Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> |
| 15 | Cc: linux-mips@linux-mips.org |
| 16 | --- |
| 17 | arch/mips/lantiq/irq.c | 24 +++++++++++++----------- |
| 18 | 1 files changed, 13 insertions(+), 11 deletions(-) |
| 19 | |
| 20 | diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c |
| 21 | index f9737bb..17c057f 100644 |
| 22 | --- a/arch/mips/lantiq/irq.c |
| 23 | +++ b/arch/mips/lantiq/irq.c |
| 24 | @@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int module) |
| 25 | do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); |
| 26 | |
| 27 | /* if this is a EBU irq, we need to ack it or get a deadlock */ |
| 28 | - if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) |
| 29 | + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) |
| 30 | ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, |
| 31 | LTQ_EBU_PCC_ISTAT); |
| 32 | } |
| 33 | @@ -260,17 +260,19 @@ void __init arch_init_irq(void) |
| 34 | if (!ltq_icu_membase) |
| 35 | panic("Failed to remap icu memory\n"); |
| 36 | |
| 37 | - if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) |
| 38 | - panic("Failed to insert eiu memory\n"); |
| 39 | + if (LTQ_EIU_BASE_ADDR) { |
| 40 | + if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) |
| 41 | + panic("Failed to insert eiu memory\n"); |
| 42 | |
| 43 | - if (request_mem_region(ltq_eiu_resource.start, |
| 44 | - resource_size(<q_eiu_resource), "eiu") < 0) |
| 45 | - panic("Failed to request eiu memory\n"); |
| 46 | + if (request_mem_region(ltq_eiu_resource.start, |
| 47 | + resource_size(<q_eiu_resource), "eiu") < 0) |
| 48 | + panic("Failed to request eiu memory\n"); |
| 49 | |
| 50 | - ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, |
| 51 | + ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, |
| 52 | resource_size(<q_eiu_resource)); |
| 53 | - if (!ltq_eiu_membase) |
| 54 | - panic("Failed to remap eiu memory\n"); |
| 55 | + if (!ltq_eiu_membase) |
| 56 | + panic("Failed to remap eiu memory\n"); |
| 57 | + } |
| 58 | |
| 59 | /* make sure all irqs are turned off by default */ |
| 60 | for (i = 0; i < 5; i++) |
| 61 | @@ -296,8 +298,8 @@ void __init arch_init_irq(void) |
| 62 | |
| 63 | for (i = INT_NUM_IRQ0; |
| 64 | i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) |
| 65 | - if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || |
| 66 | - (i == LTQ_EIU_IR2)) |
| 67 | + if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || |
| 68 | + (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR) |
| 69 | irq_set_chip_and_handler(i, <q_eiu_type, |
| 70 | handle_level_irq); |
| 71 | /* EIU3-5 only exist on ar9 and vr9 */ |
| 72 | -- |
| 73 | 1.7.5.4 |
| 74 | |
| 75 | |
