Root/target/linux/lantiq/patches-3.0/0007-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch

1From 02d9df56be1ba23c7bec51c94e5d2ac0d13d2d78 Mon Sep 17 00:00:00 2001
2From: John Crispin <blogic@openwrt.org>
3Date: Thu, 11 Aug 2011 14:35:02 +0200
4Subject: [PATCH 07/24] MIPS: lantiq: add support for FALC-ON GPIOs
5
6FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds
7the new driver.
8
9Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
10Signed-off-by: John Crispin <blogic@openwrt.org>
11Cc: linux-mips@linux-mips.org
12---
13 arch/mips/lantiq/falcon/Makefile | 2 +-
14 arch/mips/lantiq/falcon/devices.c | 41 ++++
15 arch/mips/lantiq/falcon/devices.h | 2 +
16 arch/mips/lantiq/falcon/gpio.c | 398 +++++++++++++++++++++++++++++++++++++
17 4 files changed, 442 insertions(+), 1 deletions(-)
18 create mode 100644 arch/mips/lantiq/falcon/gpio.c
19
20diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
21index e9c7455..de72209 100644
22--- a/arch/mips/lantiq/falcon/Makefile
23+++ b/arch/mips/lantiq/falcon/Makefile
24@@ -1 +1 @@
25-obj-y := clk.o prom.o reset.o sysctrl.o devices.o
26+obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
27diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
28index c4606f2..4f47b44 100644
29--- a/arch/mips/lantiq/falcon/devices.c
30+++ b/arch/mips/lantiq/falcon/devices.c
31@@ -9,6 +9,7 @@
32 
33 #include <linux/platform_device.h>
34 #include <linux/mtd/nand.h>
35+#include <linux/gpio.h>
36 
37 #include <lantiq_soc.h>
38 
39@@ -85,3 +86,43 @@ falcon_register_nand(void)
40 {
41     platform_device_register(&ltq_flash_nand);
42 }
43+
44+/* gpio */
45+#define DECLARE_GPIO_RES(port) \
46+static struct resource falcon_gpio ## port ## _res[] = { \
47+ MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \
48+ LTQ_GPIO ## port ## _SIZE), \
49+ MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \
50+ LTQ_PADCTRL ## port ## _SIZE), \
51+ IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \
52+}
53+DECLARE_GPIO_RES(0);
54+DECLARE_GPIO_RES(1);
55+DECLARE_GPIO_RES(2);
56+DECLARE_GPIO_RES(3);
57+DECLARE_GPIO_RES(4);
58+
59+void __init
60+falcon_register_gpio(void)
61+{
62+ platform_device_register_simple("falcon_gpio", 0,
63+ falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res));
64+ platform_device_register_simple("falcon_gpio", 1,
65+ falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res));
66+ platform_device_register_simple("falcon_gpio", 2,
67+ falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res));
68+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
69+ ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 |
70+ ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2);
71+}
72+
73+void __init
74+falcon_register_gpio_extra(void)
75+{
76+ platform_device_register_simple("falcon_gpio", 3,
77+ falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res));
78+ platform_device_register_simple("falcon_gpio", 4,
79+ falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
80+ ltq_sysctl_activate(SYSCTL_SYS1,
81+ ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
82+}
83diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
84index e802a7c..18be8b6 100644
85--- a/arch/mips/lantiq/falcon/devices.h
86+++ b/arch/mips/lantiq/falcon/devices.h
87@@ -14,5 +14,7 @@
88 #include "../devices.h"
89 
90 extern void falcon_register_nand(void);
91+extern void falcon_register_gpio(void);
92+extern void falcon_register_gpio_extra(void);
93 
94 #endif
95diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c
96new file mode 100644
97index 0000000..b87582d
98--- /dev/null
99+++ b/arch/mips/lantiq/falcon/gpio.c
100@@ -0,0 +1,398 @@
101+/*
102+ * This program is free software; you can redistribute it and/or modify it
103+ * under the terms of the GNU General Public License version 2 as published
104+ * by the Free Software Foundation.
105+ *
106+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
107+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
108+ */
109+
110+#include <linux/gpio.h>
111+#include <linux/interrupt.h>
112+#include <linux/slab.h>
113+#include <linux/platform_device.h>
114+
115+#include <lantiq_soc.h>
116+
117+/* Multiplexer Control Register */
118+#define LTQ_PADC_MUX(x) (x * 0x4)
119+/* Pad Control Availability Register */
120+#define LTQ_PADC_AVAIL 0x000000F0
121+
122+/* Data Output Register */
123+#define LTQ_GPIO_OUT 0x00000000
124+/* Data Input Register */
125+#define LTQ_GPIO_IN 0x00000004
126+/* Direction Register */
127+#define LTQ_GPIO_DIR 0x00000008
128+/* External Interrupt Control Register 0 */
129+#define LTQ_GPIO_EXINTCR0 0x00000018
130+/* External Interrupt Control Register 1 */
131+#define LTQ_GPIO_EXINTCR1 0x0000001C
132+/* IRN Capture Register */
133+#define LTQ_GPIO_IRNCR 0x00000020
134+/* IRN Interrupt Configuration Register */
135+#define LTQ_GPIO_IRNCFG 0x0000002C
136+/* IRN Interrupt Enable Set Register */
137+#define LTQ_GPIO_IRNRNSET 0x00000030
138+/* IRN Interrupt Enable Clear Register */
139+#define LTQ_GPIO_IRNENCLR 0x00000034
140+/* Output Set Register */
141+#define LTQ_GPIO_OUTSET 0x00000040
142+/* Output Cler Register */
143+#define LTQ_GPIO_OUTCLR 0x00000044
144+/* Direction Clear Register */
145+#define LTQ_GPIO_DIRSET 0x00000048
146+/* Direction Set Register */
147+#define LTQ_GPIO_DIRCLR 0x0000004C
148+
149+/* turn a gpio_chip into a falcon_gpio_port */
150+#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip)
151+/* turn a irq_data into a falcon_gpio_port */
152+#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
153+
154+#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg)
155+#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg)
156+#define ltq_pad_w32_mask(c, clear, set, reg) \
157+ ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg)
158+
159+#define ltq_port_r32(p, reg) ltq_r32(p->port + reg)
160+#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg)
161+#define ltq_port_w32_mask(p, clear, set, reg) \
162+ ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg)
163+
164+#define MAX_PORTS 5
165+#define PINS_PER_PORT 32
166+
167+struct falcon_gpio_port {
168+ struct gpio_chip gpio_chip;
169+ void __iomem *pad;
170+ void __iomem *port;
171+ unsigned int irq_base;
172+ unsigned int chained_irq;
173+};
174+
175+static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
176+
177+int gpio_to_irq(unsigned int gpio)
178+{
179+ return __gpio_to_irq(gpio);
180+}
181+EXPORT_SYMBOL(gpio_to_irq);
182+
183+int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
184+{
185+ int port = pin / 100;
186+ int offset = pin % 100;
187+ struct falcon_gpio_port *gpio_port;
188+
189+ if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS))
190+ return -EINVAL;
191+
192+ gpio_port = &ltq_gpio_port[port];
193+ ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset));
194+
195+ return 0;
196+}
197+EXPORT_SYMBOL(ltq_gpio_mux_set);
198+
199+int ltq_gpio_request(unsigned int pin, unsigned int val,
200+ unsigned int dir, const char *name)
201+{
202+ int port = pin / 100;
203+ int offset = pin % 100;
204+
205+ if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
206+ return -EINVAL;
207+
208+ if (gpio_request(pin, name)) {
209+ pr_err("failed to setup lantiq gpio: %s\n", name);
210+ return -EBUSY;
211+ }
212+
213+ if (dir)
214+ gpio_direction_output(pin, 1);
215+ else
216+ gpio_direction_input(pin);
217+
218+ return ltq_gpio_mux_set(pin, val);
219+}
220+EXPORT_SYMBOL(ltq_gpio_request);
221+
222+static int
223+falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
224+{
225+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR);
226+
227+ return 0;
228+}
229+
230+static void
231+falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
232+{
233+ if (value)
234+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET);
235+ else
236+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR);
237+}
238+
239+static int
240+falcon_gpio_direction_output(struct gpio_chip *chip,
241+ unsigned int offset, int value)
242+{
243+ falcon_gpio_set(chip, offset, value);
244+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET);
245+
246+ return 0;
247+}
248+
249+static int
250+falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
251+{
252+ if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1)
253+ return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1;
254+ else
255+ return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1;
256+}
257+
258+static int
259+falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
260+{
261+ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
262+ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
263+ return -EBUSY;
264+ /* switch on gpio function */
265+ ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset));
266+ return 0;
267+ }
268+
269+ return -ENODEV;
270+}
271+
272+static void
273+falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
274+{
275+ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
276+ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
277+ return;
278+ /* switch off gpio function */
279+ ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset));
280+ }
281+}
282+
283+static int
284+falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
285+{
286+ return ctop(chip)->irq_base + offset;
287+}
288+
289+static void
290+falcon_gpio_disable_irq(struct irq_data *d)
291+{
292+ unsigned int offset = d->irq - itop(d)->irq_base;
293+
294+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
295+}
296+
297+static void
298+falcon_gpio_enable_irq(struct irq_data *d)
299+{
300+ unsigned int offset = d->irq - itop(d)->irq_base;
301+
302+ if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1)
303+ /* switch on gpio function */
304+ ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset));
305+
306+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET);
307+}
308+
309+static void
310+falcon_gpio_ack_irq(struct irq_data *d)
311+{
312+ unsigned int offset = d->irq - itop(d)->irq_base;
313+
314+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
315+}
316+
317+static void
318+falcon_gpio_mask_and_ack_irq(struct irq_data *d)
319+{
320+ unsigned int offset = d->irq - itop(d)->irq_base;
321+
322+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
323+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
324+}
325+
326+static struct irq_chip falcon_gpio_irq_chip;
327+static int
328+falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
329+{
330+ unsigned int offset = d->irq - itop(d)->irq_base;
331+ unsigned int mask = 1 << offset;
332+
333+ if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
334+ return 0;
335+
336+ if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
337+ /* level triggered */
338+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG);
339+ irq_set_chip_and_handler_name(d->irq,
340+ &falcon_gpio_irq_chip, handle_level_irq, "mux");
341+ } else {
342+ /* edge triggered */
343+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG);
344+ irq_set_chip_and_handler_name(d->irq,
345+ &falcon_gpio_irq_chip, handle_simple_irq, "mux");
346+ }
347+
348+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
349+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
350+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1);
351+ } else {
352+ if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
353+ /* positive logic: rising edge, high level */
354+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
355+ else
356+ /* negative logic: falling edge, low level */
357+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0);
358+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1);
359+ }
360+
361+ return gpio_direction_input(itop(d)->gpio_chip.base + offset);
362+}
363+
364+static void
365+falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
366+{
367+ struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
368+ unsigned long irncr;
369+ int offset;
370+
371+ /* acknowledge interrupt */
372+ irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR);
373+ ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR);
374+
375+ desc->irq_data.chip->irq_ack(&desc->irq_data);
376+
377+ for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
378+ generic_handle_irq(gpio_port->irq_base + offset);
379+}
380+
381+static struct irq_chip falcon_gpio_irq_chip = {
382+ .name = "gpio_irq_mux",
383+ .irq_mask = falcon_gpio_disable_irq,
384+ .irq_unmask = falcon_gpio_enable_irq,
385+ .irq_ack = falcon_gpio_ack_irq,
386+ .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
387+ .irq_set_type = falcon_gpio_irq_type,
388+};
389+
390+static struct irqaction gpio_cascade = {
391+ .handler = no_action,
392+ .flags = IRQF_DISABLED,
393+ .name = "gpio_cascade",
394+};
395+
396+static int
397+falcon_gpio_probe(struct platform_device *pdev)
398+{
399+ struct falcon_gpio_port *gpio_port;
400+ int ret, i;
401+ struct resource *gpiores, *padres;
402+ int irq;
403+
404+ if (pdev->id >= MAX_PORTS)
405+ return -ENODEV;
406+
407+ gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
408+ padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
409+ irq = platform_get_irq(pdev, 0);
410+ if (!gpiores || !padres)
411+ return -ENODEV;
412+
413+ gpio_port = &ltq_gpio_port[pdev->id];
414+ gpio_port->gpio_chip.label = "falcon-gpio";
415+ gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
416+ gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
417+ gpio_port->gpio_chip.get = falcon_gpio_get;
418+ gpio_port->gpio_chip.set = falcon_gpio_set;
419+ gpio_port->gpio_chip.request = falcon_gpio_request;
420+ gpio_port->gpio_chip.free = falcon_gpio_free;
421+ gpio_port->gpio_chip.base = 100 * pdev->id;
422+ gpio_port->gpio_chip.ngpio = 32;
423+ gpio_port->gpio_chip.dev = &pdev->dev;
424+
425+ gpio_port->port = ltq_remap_resource(gpiores);
426+ gpio_port->pad = ltq_remap_resource(padres);
427+
428+ if (!gpio_port->port || !gpio_port->pad) {
429+ dev_err(&pdev->dev, "Could not map io ranges\n");
430+ ret = -ENOMEM;
431+ goto err;
432+ }
433+
434+ if (irq > 0) {
435+ /* irq_chip support */
436+ gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
437+ gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id);
438+
439+ for (i = 0; i < 32; i++) {
440+ irq_set_chip_and_handler_name(gpio_port->irq_base + i,
441+ &falcon_gpio_irq_chip, handle_simple_irq,
442+ "mux");
443+ irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
444+ /* set to negative logic (falling edge, low level) */
445+ ltq_port_w32_mask(gpio_port, 0, 1 << i,
446+ LTQ_GPIO_EXINTCR0);
447+ }
448+
449+ gpio_port->chained_irq = irq;
450+ setup_irq(irq, &gpio_cascade);
451+ irq_set_handler_data(irq, gpio_port);
452+ irq_set_chained_handler(irq, falcon_gpio_irq_handler);
453+ }
454+
455+ ret = gpiochip_add(&gpio_port->gpio_chip);
456+ if (ret < 0) {
457+ dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
458+ pdev->id, ret);
459+ goto err;
460+ }
461+ platform_set_drvdata(pdev, gpio_port);
462+ return ret;
463+
464+err:
465+ dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
466+ if (gpiores)
467+ release_resource(gpiores);
468+ if (padres)
469+ release_resource(padres);
470+
471+ if (gpio_port->port)
472+ iounmap(gpio_port->port);
473+ if (gpio_port->pad)
474+ iounmap(gpio_port->pad);
475+ return ret;
476+}
477+
478+static struct platform_driver falcon_gpio_driver = {
479+ .probe = falcon_gpio_probe,
480+ .driver = {
481+ .name = "falcon_gpio",
482+ .owner = THIS_MODULE,
483+ },
484+};
485+
486+int __init
487+falcon_gpio_init(void)
488+{
489+ int ret;
490+
491+ pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
492+ ret = platform_driver_register(&falcon_gpio_driver);
493+ if (ret)
494+ pr_err("falcon_gpio: Error registering platform driver!");
495+ return ret;
496+}
497+
498+postcore_initcall(falcon_gpio_init);
499--
5001.7.5.4
501
502

Archive Download this file

Branches:
backfire
history
master
release_2010-11-17
release_2010-12-14
release_2011-02-23
release_2011-05-28
release_2011-08-27
release_2011-11-13
release_2012-03-18
release_2012-04-09
release_2012-10-11
uclibc_nptl



interactive