Root/target/linux/lantiq/patches-3.0/0016-MIPS-lantiq-adds-xway-nand-driver.patch

1From e2d5b4ba92289cb0fcc9db741d159ef5eb852d9f Mon Sep 17 00:00:00 2001
2From: John Crispin <blogic@openwrt.org>
3Date: Sat, 27 Aug 2011 20:08:14 +0200
4Subject: [PATCH 16/24] MIPS: lantiq: adds xway nand driver
5
6This patch adds a nand driver for XWAY SoCs. The patch makes use of the
7plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the
8endianess swap problem on read. To workaround this problem we make the
9read_byte() callback available via the plat_nand driver causing the nand
10layer to do byte reads.
11
12Signed-off-by: John Crispin <blogic@openwrt.org>
13
14TODO : memory ranges
15       cs lines
16       plat dev
17       ebu2 and not ebu1 ?
18---
19 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +
20 arch/mips/lantiq/xway/Makefile | 2 +-
21 arch/mips/lantiq/xway/nand.c | 185 ++++++++++++++++++++
22 drivers/mtd/nand/plat_nand.c | 1 +
23 include/linux/mtd/nand.h | 1 +
24 5 files changed, 190 insertions(+), 1 deletions(-)
25 create mode 100644 arch/mips/lantiq/xway/nand.c
26
27diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
28index 86ed0d2..729dfa2 100644
29--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
30+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
31@@ -140,6 +140,8 @@
32 /* register access macros for EBU and CGU */
33 #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
34 #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
35+#define ltq_ebu_w32_mask(x, y, z) \
36+ ltq_w32_mask(x, y, ltq_ebu_membase + (z))
37 #define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
38 #define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
39 
40diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
41index 6678402..ac7cc34 100644
42--- a/arch/mips/lantiq/xway/Makefile
43+++ b/arch/mips/lantiq/xway/Makefile
44@@ -1,4 +1,4 @@
45-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
46+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o
47 
48 obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
49 obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
50diff --git a/arch/mips/lantiq/xway/nand.c b/arch/mips/lantiq/xway/nand.c
51new file mode 100644
52index 0000000..ba2443c
53--- /dev/null
54+++ b/arch/mips/lantiq/xway/nand.c
55@@ -0,0 +1,185 @@
56+/*
57+ * This program is free software; you can redistribute it and/or modify it
58+ * under the terms of the GNU General Public License version 2 as published
59+ * by the Free Software Foundation.
60+ *
61+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
62+ */
63+
64+#include <linux/mtd/physmap.h>
65+#include <linux/mtd/nand.h>
66+#include <linux/platform_device.h>
67+
68+#include <lantiq_soc.h>
69+#include <lantiq_irq.h>
70+#include <lantiq_platform.h>
71+
72+#include "devices.h"
73+
74+/* nand registers */
75+#define LTQ_EBU_NAND_WAIT 0xB4
76+#define LTQ_EBU_NAND_ECC0 0xB8
77+#define LTQ_EBU_NAND_ECC_AC 0xBC
78+#define LTQ_EBU_NAND_CON 0xB0
79+#define LTQ_EBU_ADDSEL1 0x24
80+
81+/* gpio definitions */
82+#define PIN_ALE 13
83+#define PIN_CLE 24
84+#define PIN_CS1 23
85+#define PIN_RDY 48 /* NFLASH_READY */
86+#define PIN_RD 49 /* NFLASH_READ_N */
87+
88+#define NAND_CMD_ALE (1 << 2)
89+#define NAND_CMD_CLE (1 << 3)
90+#define NAND_CMD_CS (1 << 4)
91+#define NAND_WRITE_CMD_RESET 0xff
92+#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
93+#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
94+#define NAND_WRITE_DATA (NAND_CMD_CS)
95+#define NAND_READ_DATA (NAND_CMD_CS)
96+#define NAND_WAIT_WR_C (1 << 3)
97+#define NAND_WAIT_RD (0x1)
98+
99+#define ADDSEL1_MASK(x) (x << 4)
100+#define ADDSEL1_REGEN 1
101+#define BUSCON1_SETUP (1 << 22)
102+#define BUSCON1_BCGEN_RES (0x3 << 12)
103+#define BUSCON1_WAITWRC2 (2 << 8)
104+#define BUSCON1_WAITRDC2 (2 << 6)
105+#define BUSCON1_HOLDC1 (1 << 4)
106+#define BUSCON1_RECOVC1 (1 << 2)
107+#define BUSCON1_CMULT4 1
108+#define NAND_CON_NANDM 1
109+#define NAND_CON_CSMUX (1 << 1)
110+#define NAND_CON_CS_P (1 << 4)
111+#define NAND_CON_SE_P (1 << 5)
112+#define NAND_CON_WP_P (1 << 6)
113+#define NAND_CON_PRE_P (1 << 7)
114+#define NAND_CON_IN_CS0 0
115+#define NAND_CON_OUT_CS0 0
116+#define NAND_CON_IN_CS1 (1 << 8)
117+#define NAND_CON_OUT_CS1 (1 << 10)
118+#define NAND_CON_CE (1 << 20)
119+
120+#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000)
121+
122+static const char *part_probes[] = { "cmdlinepart", NULL };
123+
124+static void
125+xway_select_chip(struct mtd_info *mtd, int chip)
126+{
127+ switch (chip) {
128+ case -1:
129+ ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON);
130+ ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON);
131+ break;
132+ case 0:
133+ ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON);
134+ ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON);
135+ /* reset the nand chip */
136+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
137+ ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
138+ break;
139+ default:
140+ BUG();
141+ }
142+}
143+
144+static void
145+xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
146+{
147+ struct nand_chip *this = mtd->priv;
148+
149+ if (ctrl & NAND_CTRL_CHANGE) {
150+ if(ctrl & NAND_CLE)
151+ this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_CMD);
152+ else if(ctrl & NAND_ALE)
153+ this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_ADDR);
154+ }
155+
156+ if(data != NAND_CMD_NONE) {
157+ *(volatile u8*)((u32)this->IO_ADDR_W) = data;
158+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
159+ }
160+}
161+
162+static int
163+xway_dev_ready(struct mtd_info *mtd)
164+{
165+ return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD;
166+}
167+
168+void
169+nand_write(unsigned int addr, unsigned int val)
170+{
171+ ltq_w32(val, ((u32*)(NAND_BASE_ADDRESS | addr)));
172+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
173+}
174+
175+unsigned char
176+ltq_nand_read_byte(struct mtd_info *mtd)
177+{
178+ return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
179+}
180+
181+int xway_nand_probe(struct platform_device *pdev)
182+{
183+// ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1");
184+ ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE");
185+ ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE");
186+ if (ltq_is_ar9() || ltq_is_vr9()) {
187+ ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY");
188+ ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD");
189+ }
190+
191+ ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
192+ | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
193+
194+ ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
195+ | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
196+ | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
197+
198+ ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
199+ | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
200+ | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
201+
202+ ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
203+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
204+
205+ return 0;
206+}
207+
208+static struct platform_nand_data falcon_flash_nand_data = {
209+ .chip = {
210+ .nr_chips = 1,
211+ .chip_delay = 30,
212+ .part_probe_types = part_probes,
213+ },
214+ .ctrl = {
215+ .probe = xway_nand_probe,
216+ .cmd_ctrl = xway_cmd_ctrl,
217+ .dev_ready = xway_dev_ready,
218+ .select_chip = xway_select_chip,
219+ .read_byte = ltq_nand_read_byte,
220+ }
221+};
222+
223+static struct resource ltq_nand_res =
224+ MEM_RES("nand", 0x14000000, 0x3ffffff);
225+
226+static struct platform_device ltq_flash_nand = {
227+ .name = "gen_nand",
228+ .id = -1,
229+ .num_resources = 1,
230+ .resource = &ltq_nand_res,
231+ .dev = {
232+ .platform_data = &falcon_flash_nand_data,
233+ },
234+};
235+
236+void __init
237+xway_register_nand(void)
238+{
239+ platform_device_register(&ltq_flash_nand);
240+}
241diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c
242index 633c04b..c3e3ef6 100644
243--- a/drivers/mtd/nand/plat_nand.c
244+++ b/drivers/mtd/nand/plat_nand.c
245@@ -77,6 +77,7 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
246     data->chip.select_chip = pdata->ctrl.select_chip;
247     data->chip.write_buf = pdata->ctrl.write_buf;
248     data->chip.read_buf = pdata->ctrl.read_buf;
249+ data->chip.read_byte = pdata->ctrl.read_byte;
250     data->chip.chip_delay = pdata->chip.chip_delay;
251     data->chip.options |= pdata->chip.options;
252 
253diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
254index c2b9ac4..597e1a0 100644
255--- a/include/linux/mtd/nand.h
256+++ b/include/linux/mtd/nand.h
257@@ -656,6 +656,7 @@ struct platform_nand_ctrl {
258     void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
259     void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
260     void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
261+ unsigned char (*read_byte)(struct mtd_info *mtd);
262     void *priv;
263 };
264 
265--
2661.7.5.4
267
268

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