Root/target/linux/ramips/files/drivers/spi/ramips_spi.c

1/*
2 * ramips_spi.c -- Ralink RT288x/RT305x SPI controller driver
3 *
4 * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <linux/delay.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/spi/spi.h>
19
20#define DRIVER_NAME "ramips-spi"
21#define RALINK_NUM_CHIPSELECTS 1 /* only one slave is supported*/
22#define RALINK_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
23
24#define RAMIPS_SPI_STAT 0x00
25#define RAMIPS_SPI_CFG 0x10
26#define RAMIPS_SPI_CTL 0x14
27#define RAMIPS_SPI_DATA 0x20
28
29/* SPISTAT register bit field */
30#define SPISTAT_BUSY BIT(0)
31
32/* SPICFG register bit field */
33#define SPICFG_LSBFIRST 0
34#define SPICFG_MSBFIRST BIT(8)
35#define SPICFG_SPICLKPOL BIT(6)
36#define SPICFG_RXCLKEDGE_FALLING BIT(5)
37#define SPICFG_TXCLKEDGE_FALLING BIT(4)
38#define SPICFG_SPICLK_PRESCALE_MASK 0x7
39#define SPICFG_SPICLK_DIV2 0
40#define SPICFG_SPICLK_DIV4 1
41#define SPICFG_SPICLK_DIV8 2
42#define SPICFG_SPICLK_DIV16 3
43#define SPICFG_SPICLK_DIV32 4
44#define SPICFG_SPICLK_DIV64 5
45#define SPICFG_SPICLK_DIV128 6
46#define SPICFG_SPICLK_DISABLE 7
47
48/* SPICTL register bit field */
49#define SPICTL_HIZSDO BIT(3)
50#define SPICTL_STARTWR BIT(2)
51#define SPICTL_STARTRD BIT(1)
52#define SPICTL_SPIENA BIT(0)
53
54#ifdef DEBUG
55#define spi_debug(args...) printk(args)
56#else
57#define spi_debug(args...)
58#endif
59
60struct ramips_spi {
61    struct work_struct work;
62
63    /* Lock access to transfer list.*/
64    spinlock_t lock;
65
66    struct list_head msg_queue;
67    struct spi_master *master;
68    void __iomem *base;
69    unsigned int sys_freq;
70    unsigned int speed;
71
72    struct clk *clk;
73};
74
75static struct workqueue_struct *ramips_spi_wq;
76
77static inline struct ramips_spi *ramips_spidev_to_rs(struct spi_device *spi)
78{
79    return spi_master_get_devdata(spi->master);
80}
81
82static inline u32 ramips_spi_read(struct ramips_spi *rs, u32 reg)
83{
84    return ioread32(rs->base + reg);
85}
86
87static inline void ramips_spi_write(struct ramips_spi *rs, u32 reg, u32 val)
88{
89    iowrite32(val, rs->base + reg);
90}
91
92static inline void ramips_spi_setbits(struct ramips_spi *rs, u32 reg, u32 mask)
93{
94    void __iomem *addr = rs->base + reg;
95    u32 val;
96
97    val = ioread32(addr);
98    val |= mask;
99    iowrite32(val, addr);
100}
101
102static inline void ramips_spi_clrbits(struct ramips_spi *rs, u32 reg, u32 mask)
103{
104    void __iomem *addr = rs->base + reg;
105    u32 val;
106
107    val = ioread32(addr);
108    val &= ~mask;
109    iowrite32(val, addr);
110}
111
112static int ramips_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
113{
114    struct ramips_spi *rs = ramips_spidev_to_rs(spi);
115    u32 rate;
116    u32 prescale;
117    u32 reg;
118
119    spi_debug("%s: speed:%u\n", __func__, speed);
120
121    /*
122     * the supported rates are: 2,4,8...128
123     * round up as we look for equal or less speed
124     */
125    rate = DIV_ROUND_UP(rs->sys_freq, speed);
126    spi_debug("%s: rate-1:%u\n", __func__, rate);
127    rate = roundup_pow_of_two(rate);
128    spi_debug("%s: rate-2:%u\n", __func__, rate);
129
130    /* check if requested speed is too small */
131    if (rate > 128)
132        return -EINVAL;
133
134    if (rate < 2)
135        rate = 2;
136
137    /* Convert the rate to SPI clock divisor value. */
138    prescale = ilog2(rate/2);
139    spi_debug("%s: prescale:%u\n", __func__, prescale);
140
141    reg = ramips_spi_read(rs, RAMIPS_SPI_CFG);
142    reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
143    ramips_spi_write(rs, RAMIPS_SPI_CFG, reg);
144    rs->speed = speed;
145    return 0;
146}
147
148/*
149 * called only when no transfer is active on the bus
150 */
151static int
152ramips_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
153{
154    struct ramips_spi *rs = ramips_spidev_to_rs(spi);
155    unsigned int speed = spi->max_speed_hz;
156    int rc;
157    unsigned int bits_per_word = 8;
158
159    if ((t != NULL) && t->speed_hz)
160        speed = t->speed_hz;
161
162    if ((t != NULL) && t->bits_per_word)
163        bits_per_word = t->bits_per_word;
164
165    if (rs->speed != speed) {
166        spi_debug("%s: speed_hz:%u\n", __func__, speed);
167        rc = ramips_spi_baudrate_set(spi, speed);
168        if (rc)
169            return rc;
170    }
171
172    if (bits_per_word != 8) {
173        spi_debug("%s: bad bits_per_word: %u\n", __func__,
174              bits_per_word);
175        return -EINVAL;
176    }
177
178    return 0;
179}
180
181static void ramips_spi_set_cs(struct ramips_spi *rs, int enable)
182{
183    if (enable)
184        ramips_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
185    else
186        ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
187}
188
189static inline int ramips_spi_wait_till_ready(struct ramips_spi *rs)
190{
191    int i;
192
193    for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
194        u32 status;
195
196        status = ramips_spi_read(rs, RAMIPS_SPI_STAT);
197        if ((status & SPISTAT_BUSY) == 0)
198            return 0;
199
200        udelay(1);
201    }
202
203    return -ETIMEDOUT;
204}
205
206static unsigned int
207ramips_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
208{
209    struct ramips_spi *rs = ramips_spidev_to_rs(spi);
210    unsigned count = 0;
211    u8 *rx = xfer->rx_buf;
212    const u8 *tx = xfer->tx_buf;
213    int err;
214
215    spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
216          (tx != NULL) ? "tx" : " ",
217          (rx != NULL) ? "rx" : " ");
218
219    if (tx) {
220        for (count = 0; count < xfer->len; count++) {
221            ramips_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
222            ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
223            err = ramips_spi_wait_till_ready(rs);
224            if (err) {
225                dev_err(&spi->dev, "TX failed, err=%d\n", err);
226                goto out;
227            }
228        }
229    }
230
231    if (rx) {
232        for (count = 0; count < xfer->len; count++) {
233            ramips_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
234            err = ramips_spi_wait_till_ready(rs);
235            if (err) {
236                dev_err(&spi->dev, "RX failed, err=%d\n", err);
237                goto out;
238            }
239            rx[count] = (u8) ramips_spi_read(rs, RAMIPS_SPI_DATA);
240        }
241    }
242
243out:
244    return count;
245}
246
247static void ramips_spi_work(struct work_struct *work)
248{
249    struct ramips_spi *rs =
250        container_of(work, struct ramips_spi, work);
251
252    spin_lock_irq(&rs->lock);
253    while (!list_empty(&rs->msg_queue)) {
254        struct spi_message *m;
255        struct spi_device *spi;
256        struct spi_transfer *t = NULL;
257        int par_override = 0;
258        int status = 0;
259        int cs_active = 0;
260
261        m = container_of(rs->msg_queue.next, struct spi_message,
262                 queue);
263
264        list_del_init(&m->queue);
265        spin_unlock_irq(&rs->lock);
266
267        spi = m->spi;
268
269        /* Load defaults */
270        status = ramips_spi_setup_transfer(spi, NULL);
271
272        if (status < 0)
273            goto msg_done;
274
275        list_for_each_entry(t, &m->transfers, transfer_list) {
276            if (par_override || t->speed_hz || t->bits_per_word) {
277                par_override = 1;
278                status = ramips_spi_setup_transfer(spi, t);
279                if (status < 0)
280                    break;
281                if (!t->speed_hz && !t->bits_per_word)
282                    par_override = 0;
283            }
284
285            if (!cs_active) {
286                ramips_spi_set_cs(rs, 1);
287                cs_active = 1;
288            }
289
290            if (t->len)
291                m->actual_length +=
292                    ramips_spi_write_read(spi, t);
293
294            if (t->delay_usecs)
295                udelay(t->delay_usecs);
296
297            if (t->cs_change) {
298                ramips_spi_set_cs(rs, 0);
299                cs_active = 0;
300            }
301        }
302
303msg_done:
304        if (cs_active)
305            ramips_spi_set_cs(rs, 0);
306
307        m->status = status;
308        m->complete(m->context);
309
310        spin_lock_irq(&rs->lock);
311    }
312
313    spin_unlock_irq(&rs->lock);
314}
315
316static int ramips_spi_setup(struct spi_device *spi)
317{
318    struct ramips_spi *rs = ramips_spidev_to_rs(spi);
319
320    if ((spi->max_speed_hz == 0) ||
321        (spi->max_speed_hz > (rs->sys_freq / 2)))
322        spi->max_speed_hz = (rs->sys_freq / 2);
323
324    if (spi->max_speed_hz < (rs->sys_freq/128)) {
325        dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
326            spi->max_speed_hz);
327        return -EINVAL;
328    }
329
330    if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
331        dev_err(&spi->dev,
332            "setup: requested bits per words - os wrong %d bpw\n",
333            spi->bits_per_word);
334        return -EINVAL;
335    }
336
337    if (spi->bits_per_word == 0)
338        spi->bits_per_word = 8;
339
340    /*
341     * baudrate & width will be set ramips_spi_setup_transfer
342     */
343    return 0;
344}
345
346static int ramips_spi_transfer(struct spi_device *spi, struct spi_message *m)
347{
348    struct ramips_spi *rs;
349    struct spi_transfer *t = NULL;
350    unsigned long flags;
351
352    m->actual_length = 0;
353    m->status = 0;
354
355    /* reject invalid messages and transfers */
356    if (list_empty(&m->transfers) || !m->complete)
357        return -EINVAL;
358
359    rs = ramips_spidev_to_rs(spi);
360
361    list_for_each_entry(t, &m->transfers, transfer_list) {
362        unsigned int bits_per_word = spi->bits_per_word;
363
364        if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
365            dev_err(&spi->dev,
366                "message rejected : "
367                "invalid transfer data buffers\n");
368            goto msg_rejected;
369        }
370
371        if (t->bits_per_word)
372            bits_per_word = t->bits_per_word;
373
374        if (bits_per_word != 8) {
375            dev_err(&spi->dev,
376                "message rejected : "
377                "invalid transfer bits_per_word (%d bits)\n",
378                bits_per_word);
379            goto msg_rejected;
380        }
381
382        if (t->speed_hz && t->speed_hz < (rs->sys_freq/128)) {
383            dev_err(&spi->dev,
384                "message rejected : "
385                "device min speed (%d Hz) exceeds "
386                "required transfer speed (%d Hz)\n",
387                (rs->sys_freq/128), t->speed_hz);
388            goto msg_rejected;
389        }
390    }
391
392
393    spin_lock_irqsave(&rs->lock, flags);
394    list_add_tail(&m->queue, &rs->msg_queue);
395    queue_work(ramips_spi_wq, &rs->work);
396    spin_unlock_irqrestore(&rs->lock, flags);
397
398    return 0;
399msg_rejected:
400    /* Message rejected and not queued */
401    m->status = -EINVAL;
402    if (m->complete)
403        m->complete(m->context);
404    return -EINVAL;
405}
406
407static void __init ramips_spi_reset(struct ramips_spi *rs)
408{
409    ramips_spi_write(rs, RAMIPS_SPI_CFG,
410             SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
411             SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
412    ramips_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
413}
414
415static int __init ramips_spi_probe(struct platform_device *pdev)
416{
417    struct spi_master *master;
418    struct ramips_spi *rs;
419    struct resource *r;
420    int status = 0;
421
422    master = spi_alloc_master(&pdev->dev, sizeof(*rs));
423    if (master == NULL) {
424        dev_dbg(&pdev->dev, "master allocation failed\n");
425        return -ENOMEM;
426    }
427
428    if (pdev->id != -1)
429        master->bus_num = pdev->id;
430
431    /* we support only mode 0, and no options */
432    master->mode_bits = 0;
433
434    master->setup = ramips_spi_setup;
435    master->transfer = ramips_spi_transfer;
436    master->num_chipselect = RALINK_NUM_CHIPSELECTS;
437
438    dev_set_drvdata(&pdev->dev, master);
439
440    rs = spi_master_get_devdata(master);
441    rs->master = master;
442
443    rs->clk = clk_get(NULL, "sys");
444    if (IS_ERR(rs->clk)) {
445        status = PTR_ERR(rs->clk);
446        dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
447            status);
448        goto out_put_master;
449    }
450
451    status = clk_enable(rs->clk);
452    if (status)
453        goto out_put_clk;
454
455    rs->sys_freq = clk_get_rate(rs->clk);
456    spi_debug("%s: sys_freq: %ld\n", __func__, rs->sys_freq);
457
458    r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
459    if (r == NULL) {
460        status = -ENODEV;
461        goto out_disable_clk;
462    }
463
464    if (!request_mem_region(r->start, (r->end - r->start) + 1,
465                dev_name(&pdev->dev))) {
466        status = -EBUSY;
467        goto out_disable_clk;
468    }
469
470    rs->base = ioremap(r->start, resource_size(r));
471    if (rs->base == NULL) {
472        dev_err(&pdev->dev, "ioremap failed\n");
473        status = -ENOMEM;
474        goto out_rel_mem;
475    }
476
477    INIT_WORK(&rs->work, ramips_spi_work);
478
479    spin_lock_init(&rs->lock);
480    INIT_LIST_HEAD(&rs->msg_queue);
481
482    ramips_spi_reset(rs);
483
484    status = spi_register_master(master);
485    if (status)
486        goto out_unmap_base;
487
488    return 0;
489
490out_unmap_base:
491    iounmap(rs->base);
492out_rel_mem:
493    release_mem_region(r->start, (r->end - r->start) + 1);
494out_disable_clk:
495    clk_disable(rs->clk);
496out_put_clk:
497    clk_put(rs->clk);
498out_put_master:
499    spi_master_put(master);
500    return status;
501}
502
503static int __devexit ramips_spi_remove(struct platform_device *pdev)
504{
505    struct spi_master *master;
506    struct ramips_spi *rs;
507    struct resource *r;
508
509    master = dev_get_drvdata(&pdev->dev);
510    rs = spi_master_get_devdata(master);
511
512    cancel_work_sync(&rs->work);
513
514    iounmap(rs->base);
515    r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
516    release_mem_region(r->start, (r->end - r->start) + 1);
517
518    clk_disable(rs->clk);
519    clk_put(rs->clk);
520    spi_unregister_master(master);
521
522    return 0;
523}
524
525MODULE_ALIAS("platform:" DRIVER_NAME);
526
527static struct platform_driver ramips_spi_driver = {
528    .driver = {
529        .name = DRIVER_NAME,
530        .owner = THIS_MODULE,
531    },
532    .remove = __devexit_p(ramips_spi_remove),
533};
534
535static int __init ramips_spi_init(void)
536{
537    ramips_spi_wq = create_singlethread_workqueue(
538                ramips_spi_driver.driver.name);
539    if (ramips_spi_wq == NULL)
540        return -ENOMEM;
541
542    return platform_driver_probe(&ramips_spi_driver, ramips_spi_probe);
543}
544module_init(ramips_spi_init);
545
546static void __exit ramips_spi_exit(void)
547{
548    flush_workqueue(ramips_spi_wq);
549    platform_driver_unregister(&ramips_spi_driver);
550
551    destroy_workqueue(ramips_spi_wq);
552}
553module_exit(ramips_spi_exit);
554
555MODULE_DESCRIPTION("Ralink SPI driver");
556MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
557MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
558MODULE_LICENSE("GPL");
559

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