Root/target/linux/xburst/patches-3.0/0013-Add-jz4740-udc-driver.patch

1From ecd72bc68f9b9a39cb0f1ec456787c61f03be978 Mon Sep 17 00:00:00 2001
2From: Xiangfu Liu <xiangfu@macbook.openmobilefree.net>
3Date: Tue, 13 Sep 2011 16:07:41 +0800
4Subject: [PATCH 13/32] Add jz4740 udc driver
5
6---
7 drivers/usb/gadget/Kconfig | 13 +
8 drivers/usb/gadget/Makefile | 1 +
9 drivers/usb/gadget/gadget_chips.h | 8 +
10 drivers/usb/gadget/jz4740_udc.c | 2188 +++++++++++++++++++++++++++++++++++++
11 drivers/usb/gadget/jz4740_udc.h | 101 ++
12 5 files changed, 2311 insertions(+), 0 deletions(-)
13 create mode 100644 drivers/usb/gadget/jz4740_udc.c
14 create mode 100644 drivers/usb/gadget/jz4740_udc.h
15
16diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
17index 029e288..750480c 100644
18--- a/drivers/usb/gadget/Kconfig
19+++ b/drivers/usb/gadget/Kconfig
20@@ -121,6 +121,19 @@ choice
21 #
22 # Integrated controllers
23 #
24+config USB_GADGET_JZ4740
25+ boolean "JZ4740 UDC"
26+ depends on MACH_JZ4740
27+ select USB_GADGET_SELECTED
28+ select USB_GADGET_DUALSPEED
29+ help
30+ Select this to support the Ingenic JZ4740 processor
31+ high speed USB device controller.
32+
33+config USB_JZ4740
34+ tristate
35+ depends on USB_GADGET_JZ4740
36+ default USB_GADGET
37 
38 config USB_GADGET_AT91
39     boolean "Atmel AT91 USB Device Port"
40diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
41index 4fe92b1..e0e2dd8 100644
42--- a/drivers/usb/gadget/Makefile
43+++ b/drivers/usb/gadget/Makefile
44@@ -29,6 +29,7 @@ obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
45 mv_udc-y := mv_udc_core.o mv_udc_phy.o
46 obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
47 obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
48+obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
49 
50 #
51 # USB gadget drivers
52diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
53index bcdac7c..12f5205 100644
54--- a/drivers/usb/gadget/gadget_chips.h
55+++ b/drivers/usb/gadget/gadget_chips.h
56@@ -15,6 +15,12 @@
57 #ifndef __GADGET_CHIPS_H
58 #define __GADGET_CHIPS_H
59 
60+#ifdef CONFIG_USB_GADGET_JZ4740
61+#define gadget_is_jz4740(g) !strcmp("ingenic_hsusb", (g)->name)
62+#else
63+#define gadget_is_jz4740(g) 0
64+#endif
65+
66 #ifdef CONFIG_USB_GADGET_NET2280
67 #define gadget_is_net2280(g) !strcmp("net2280", (g)->name)
68 #else
69@@ -223,6 +229,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
70         return 0x29;
71     else if (gadget_is_s3c_hsudc(gadget))
72         return 0x30;
73+ else if (gadget_is_jz4740(gadget))
74+ return 0x31;
75 
76     return -ENOENT;
77 }
78diff --git a/drivers/usb/gadget/jz4740_udc.c b/drivers/usb/gadget/jz4740_udc.c
79new file mode 100644
80index 0000000..528fd57
81--- /dev/null
82+++ b/drivers/usb/gadget/jz4740_udc.c
83@@ -0,0 +1,2188 @@
84+/*
85+ * linux/drivers/usb/gadget/jz4740_udc.c
86+ *
87+ * Ingenic JZ4740 on-chip high speed USB device controller
88+ *
89+ * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
90+ * Author: <jlwei@ingenic.cn>
91+ *
92+ * This program is free software; you can redistribute it and/or modify
93+ * it under the terms of the GNU General Public License as published by
94+ * the Free Software Foundation; either version 2 of the License, or
95+ * (at your option) any later version.
96+ */
97+
98+/*
99+ * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
100+ *
101+ * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
102+ * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
103+ */
104+
105+#include <linux/kernel.h>
106+#include <linux/module.h>
107+#include <linux/platform_device.h>
108+#include <linux/delay.h>
109+#include <linux/ioport.h>
110+#include <linux/slab.h>
111+#include <linux/errno.h>
112+#include <linux/init.h>
113+#include <linux/list.h>
114+#include <linux/interrupt.h>
115+#include <linux/proc_fs.h>
116+#include <linux/usb.h>
117+#include <linux/usb/gadget.h>
118+#include <linux/clk.h>
119+
120+#include <asm/byteorder.h>
121+#include <asm/io.h>
122+#include <asm/irq.h>
123+#include <asm/system.h>
124+#include <asm/mach-jz4740/clock.h>
125+
126+#include "jz4740_udc.h"
127+
128+#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
129+#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
130+#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
131+#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
132+#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
133+#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
134+#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
135+#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
136+#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
137+#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
138+#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
139+
140+#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
141+#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
142+#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
143+#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
144+
145+#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
146+#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
147+#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
148+#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
149+
150+#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
151+
152+#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
153+#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
154+
155+#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
156+#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
157+#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
158+#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
159+#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
160+#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
161+#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
162+
163+/* Power register bit masks */
164+#define USB_POWER_SUSPENDM 0x01
165+#define USB_POWER_RESUME 0x04
166+#define USB_POWER_HSMODE 0x10
167+#define USB_POWER_HSENAB 0x20
168+#define USB_POWER_SOFTCONN 0x40
169+
170+/* Interrupt register bit masks */
171+#define USB_INTR_SUSPEND 0x01
172+#define USB_INTR_RESUME 0x02
173+#define USB_INTR_RESET 0x04
174+
175+#define USB_INTR_EP0 0x0001
176+#define USB_INTR_INEP1 0x0002
177+#define USB_INTR_INEP2 0x0004
178+#define USB_INTR_OUTEP1 0x0002
179+
180+/* CSR0 bit masks */
181+#define USB_CSR0_OUTPKTRDY 0x01
182+#define USB_CSR0_INPKTRDY 0x02
183+#define USB_CSR0_SENTSTALL 0x04
184+#define USB_CSR0_DATAEND 0x08
185+#define USB_CSR0_SETUPEND 0x10
186+#define USB_CSR0_SENDSTALL 0x20
187+#define USB_CSR0_SVDOUTPKTRDY 0x40
188+#define USB_CSR0_SVDSETUPEND 0x80
189+
190+/* Endpoint CSR register bits */
191+#define USB_INCSRH_AUTOSET 0x80
192+#define USB_INCSRH_ISO 0x40
193+#define USB_INCSRH_MODE 0x20
194+#define USB_INCSRH_DMAREQENAB 0x10
195+#define USB_INCSRH_DMAREQMODE 0x04
196+#define USB_INCSR_CDT 0x40
197+#define USB_INCSR_SENTSTALL 0x20
198+#define USB_INCSR_SENDSTALL 0x10
199+#define USB_INCSR_FF 0x08
200+#define USB_INCSR_UNDERRUN 0x04
201+#define USB_INCSR_FFNOTEMPT 0x02
202+#define USB_INCSR_INPKTRDY 0x01
203+
204+#define USB_OUTCSRH_AUTOCLR 0x80
205+#define USB_OUTCSRH_ISO 0x40
206+#define USB_OUTCSRH_DMAREQENAB 0x20
207+#define USB_OUTCSRH_DNYT 0x10
208+#define USB_OUTCSRH_DMAREQMODE 0x08
209+#define USB_OUTCSR_CDT 0x80
210+#define USB_OUTCSR_SENTSTALL 0x40
211+#define USB_OUTCSR_SENDSTALL 0x20
212+#define USB_OUTCSR_FF 0x10
213+#define USB_OUTCSR_DATAERR 0x08
214+#define USB_OUTCSR_OVERRUN 0x04
215+#define USB_OUTCSR_FFFULL 0x02
216+#define USB_OUTCSR_OUTPKTRDY 0x01
217+
218+/* DMA control bits */
219+#define USB_CNTL_ENA 0x01
220+#define USB_CNTL_DIR_IN 0x02
221+#define USB_CNTL_MODE_1 0x04
222+#define USB_CNTL_INTR_EN 0x08
223+#define USB_CNTL_EP(n) ((n) << 4)
224+#define USB_CNTL_BURST_0 (0 << 9)
225+#define USB_CNTL_BURST_4 (1 << 9)
226+#define USB_CNTL_BURST_8 (2 << 9)
227+#define USB_CNTL_BURST_16 (3 << 9)
228+
229+
230+#ifndef DEBUG
231+# define DEBUG(fmt,args...) do {} while(0)
232+#endif
233+#ifndef DEBUG_EP0
234+# define NO_STATES
235+# define DEBUG_EP0(fmt,args...) do {} while(0)
236+#endif
237+#ifndef DEBUG_SETUP
238+# define DEBUG_SETUP(fmt,args...) do {} while(0)
239+#endif
240+
241+static struct jz4740_udc jz4740_udc_controller;
242+
243+/*
244+ * Local declarations.
245+ */
246+static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
247+static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
248+
249+static void done(struct jz4740_ep *ep, struct jz4740_request *req,
250+ int status);
251+static void pio_irq_enable(struct jz4740_ep *ep);
252+static void pio_irq_disable(struct jz4740_ep *ep);
253+static void stop_activity(struct jz4740_udc *dev,
254+ struct usb_gadget_driver *driver);
255+static void nuke(struct jz4740_ep *ep, int status);
256+static void flush(struct jz4740_ep *ep);
257+static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
258+
259+/*-------------------------------------------------------------------------*/
260+
261+/* inline functions of register read/write/set/clear */
262+
263+static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
264+{
265+ return readb(udc->base + reg);
266+}
267+
268+static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
269+{
270+ return readw(udc->base + reg);
271+}
272+
273+static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
274+{
275+ return readl(udc->base + reg);
276+}
277+
278+static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
279+{
280+ writeb(val, udc->base + reg);
281+}
282+
283+static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
284+{
285+ writew(val, udc->base + reg);
286+}
287+
288+static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
289+{
290+ writel(val, udc->base + reg);
291+}
292+
293+static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
294+{
295+ usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
296+}
297+
298+static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
299+{
300+ usb_writew(udc, reg, usb_readw(udc, reg) | mask);
301+}
302+
303+static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
304+{
305+ usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
306+}
307+
308+static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
309+{
310+ usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
311+}
312+
313+/*-------------------------------------------------------------------------*/
314+
315+static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
316+{
317+ usb_writeb(udc, JZ_REG_UDC_INDEX, index);
318+}
319+
320+static inline void jz_udc_select_ep(struct jz4740_ep *ep)
321+{
322+ jz_udc_set_index(ep->dev, ep_index(ep));
323+}
324+
325+static inline int write_packet(struct jz4740_ep *ep,
326+ struct jz4740_request *req, unsigned int count)
327+{
328+ uint8_t *buf;
329+ unsigned int length;
330+ void __iomem *fifo = ep->dev->base + ep->fifo;
331+
332+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
333+
334+ buf = req->req.buf + req->req.actual;
335+
336+ length = req->req.length - req->req.actual;
337+ if (length > count)
338+ length = count;
339+ req->req.actual += length;
340+
341+ DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
342+
343+ writesl(fifo, buf, length >> 2);
344+ writesb(fifo, &buf[length - (length & 3)], length & 3);
345+
346+ return length;
347+}
348+
349+static int read_packet(struct jz4740_ep *ep,
350+ struct jz4740_request *req, unsigned int count)
351+{
352+ uint8_t *buf;
353+ unsigned int length;
354+ void __iomem *fifo = ep->dev->base + ep->fifo;
355+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
356+
357+ buf = req->req.buf + req->req.actual;
358+
359+ length = req->req.length - req->req.actual;
360+ if (length > count)
361+ length = count;
362+ req->req.actual += length;
363+
364+ DEBUG("Read %d, fifo %x\n", length, ep->fifo);
365+
366+ readsl(fifo, buf, length >> 2);
367+ readsb(fifo, &buf[length - (length & 3)], length & 3);
368+
369+ return length;
370+}
371+
372+/*-------------------------------------------------------------------------*/
373+
374+/*
375+ * udc_disable - disable USB device controller
376+ */
377+static void udc_disable(struct jz4740_udc *dev)
378+{
379+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
380+
381+ udc_set_address(dev, 0);
382+
383+ /* Disable interrupts */
384+ usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
385+ usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
386+ usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
387+
388+ /* Disable DMA */
389+ usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
390+ usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
391+
392+ /* Disconnect from usb */
393+ usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
394+
395+ /* Disable the USB PHY */
396+ clk_disable(dev->clk);
397+
398+ dev->ep0state = WAIT_FOR_SETUP;
399+ dev->gadget.speed = USB_SPEED_UNKNOWN;
400+
401+ return;
402+}
403+
404+/*
405+ * udc_reinit - initialize software state
406+ */
407+static void udc_reinit(struct jz4740_udc *dev)
408+{
409+ int i;
410+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
411+
412+ /* device/ep0 records init */
413+ INIT_LIST_HEAD(&dev->gadget.ep_list);
414+ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
415+ dev->ep0state = WAIT_FOR_SETUP;
416+
417+ for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
418+ struct jz4740_ep *ep = &dev->ep[i];
419+
420+ if (i != 0)
421+ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
422+
423+ INIT_LIST_HEAD(&ep->queue);
424+ ep->desc = 0;
425+ ep->stopped = 0;
426+ }
427+}
428+
429+/* until it's enabled, this UDC should be completely invisible
430+ * to any USB host.
431+ */
432+static void udc_enable(struct jz4740_udc *dev)
433+{
434+ int i;
435+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
436+
437+ /* UDC state is incorrect - Added by River */
438+ if (dev->state != UDC_STATE_ENABLE) {
439+ return;
440+ }
441+
442+ dev->gadget.speed = USB_SPEED_UNKNOWN;
443+
444+ /* Flush FIFO for each */
445+ for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
446+ struct jz4740_ep *ep = &dev->ep[i];
447+
448+ jz_udc_select_ep(ep);
449+ flush(ep);
450+ }
451+
452+ /* Set this bit to allow the UDC entering low-power mode when
453+ * there are no actions on the USB bus.
454+ * UDC still works during this bit was set.
455+ */
456+ jz4740_clock_udc_enable_auto_suspend();
457+
458+ /* Enable the USB PHY */
459+ clk_enable(dev->clk);
460+
461+ /* Disable interrupts */
462+/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
463+ usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
464+ usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
465+
466+ /* Enable interrupts */
467+ usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
468+ usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
469+ /* Don't enable rest of the interrupts */
470+ /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
471+ usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
472+
473+ /* Enable SUSPEND */
474+ /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
475+
476+ /* Enable HS Mode */
477+ usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
478+
479+ /* Let host detect UDC:
480+ * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
481+ * transistor on and pull the USBDP pin HIGH.
482+ */
483+ usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
484+
485+ return;
486+}
487+
488+/*-------------------------------------------------------------------------*/
489+
490+/* keeping it simple:
491+ * - one bus driver, initted first;
492+ * - one function driver, initted second
493+ */
494+
495+/*
496+ * Register entry point for the peripheral controller driver.
497+ */
498+
499+int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
500+ int (*bind)(struct usb_gadget *))
501+{
502+ struct jz4740_udc *dev = &jz4740_udc_controller;
503+ int retval;
504+
505+ if (!driver || !bind)
506+ return -EINVAL;
507+
508+ if (!dev)
509+ return -ENODEV;
510+
511+ if (dev->driver)
512+ return -EBUSY;
513+
514+ /* hook up the driver */
515+ dev->driver = driver;
516+ dev->gadget.dev.driver = &driver->driver;
517+
518+ retval = bind(&dev->gadget);
519+ if (retval) {
520+ DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
521+ driver->driver.name, retval);
522+ dev->driver = 0;
523+ return retval;
524+ }
525+
526+ /* then enable host detection and ep0; and we're ready
527+ * for set_configuration as well as eventual disconnect.
528+ */
529+ udc_enable(dev);
530+
531+ DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
532+ driver->driver.name);
533+
534+ return 0;
535+}
536+EXPORT_SYMBOL(usb_gadget_probe_driver);
537+
538+static void stop_activity(struct jz4740_udc *dev,
539+ struct usb_gadget_driver *driver)
540+{
541+ int i;
542+
543+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
544+
545+ /* don't disconnect drivers more than once */
546+ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
547+ driver = 0;
548+ dev->gadget.speed = USB_SPEED_UNKNOWN;
549+
550+ /* prevent new request submissions, kill any outstanding requests */
551+ for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
552+ struct jz4740_ep *ep = &dev->ep[i];
553+
554+ ep->stopped = 1;
555+
556+ jz_udc_select_ep(ep);
557+ nuke(ep, -ESHUTDOWN);
558+ }
559+
560+ /* report disconnect; the driver is already quiesced */
561+ if (driver) {
562+ spin_unlock(&dev->lock);
563+ driver->disconnect(&dev->gadget);
564+ spin_lock(&dev->lock);
565+ }
566+
567+ /* re-init driver-visible data structures */
568+ udc_reinit(dev);
569+}
570+
571+
572+/*
573+ * Unregister entry point for the peripheral controller driver.
574+ */
575+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
576+{
577+ struct jz4740_udc *dev = &jz4740_udc_controller;
578+ unsigned long flags;
579+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
580+
581+ if (!dev)
582+ return -ENODEV;
583+ if (!driver || driver != dev->driver)
584+ return -EINVAL;
585+ if (!driver->unbind)
586+ return -EBUSY;
587+
588+ spin_lock_irqsave(&dev->lock, flags);
589+ dev->driver = 0;
590+ stop_activity(dev, driver);
591+ spin_unlock_irqrestore(&dev->lock, flags);
592+
593+ driver->unbind(&dev->gadget);
594+
595+ udc_disable(dev);
596+
597+ DEBUG("unregistered driver '%s'\n", driver->driver.name);
598+
599+ return 0;
600+}
601+
602+EXPORT_SYMBOL(usb_gadget_unregister_driver);
603+
604+/*-------------------------------------------------------------------------*/
605+
606+/** Write request to FIFO (max write == maxp size)
607+ * Return: 0 = still running, 1 = completed, negative = errno
608+ * NOTE: INDEX register must be set for EP
609+ */
610+static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
611+{
612+ struct jz4740_udc *dev = ep->dev;
613+ uint32_t max, csr;
614+
615+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
616+ max = le16_to_cpu(ep->desc->wMaxPacketSize);
617+
618+ csr = usb_readb(dev, ep->csr);
619+
620+ if (!(csr & USB_INCSR_FFNOTEMPT)) {
621+ unsigned count;
622+ int is_last, is_short;
623+
624+ count = write_packet(ep, req, max);
625+ usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
626+
627+ /* last packet is usually short (or a zlp) */
628+ if (unlikely(count != max))
629+ is_last = is_short = 1;
630+ else {
631+ if (likely(req->req.length != req->req.actual)
632+ || req->req.zero)
633+ is_last = 0;
634+ else
635+ is_last = 1;
636+ /* interrupt/iso maxpacket may not fill the fifo */
637+ is_short = unlikely(max < ep_maxpacket(ep));
638+ }
639+
640+ DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
641+ ep->ep.name, count,
642+ is_last ? "/L" : "", is_short ? "/S" : "",
643+ req->req.length - req->req.actual, req);
644+
645+ /* requests complete when all IN data is in the FIFO */
646+ if (is_last) {
647+ done(ep, req, 0);
648+ if (list_empty(&ep->queue)) {
649+ pio_irq_disable(ep);
650+ }
651+ return 1;
652+ }
653+ } else {
654+ DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
655+ }
656+
657+ return 0;
658+}
659+
660+/** Read to request from FIFO (max read == bytes in fifo)
661+ * Return: 0 = still running, 1 = completed, negative = errno
662+ * NOTE: INDEX register must be set for EP
663+ */
664+static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
665+{
666+ struct jz4740_udc *dev = ep->dev;
667+ uint32_t csr;
668+ unsigned count, is_short;
669+
670+ /* make sure there's a packet in the FIFO. */
671+ csr = usb_readb(dev, ep->csr);
672+ if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
673+ DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
674+ return -EINVAL;
675+ }
676+
677+ /* read all bytes from this packet */
678+ count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
679+
680+ is_short = (count < ep->ep.maxpacket);
681+
682+ count = read_packet(ep, req, count);
683+
684+ DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
685+ ep->ep.name, csr, count,
686+ is_short ? "/S" : "", req, req->req.actual, req->req.length);
687+
688+ /* Clear OutPktRdy */
689+ usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
690+
691+ /* completion */
692+ if (is_short || req->req.actual == req->req.length) {
693+ done(ep, req, 0);
694+
695+ if (list_empty(&ep->queue))
696+ pio_irq_disable(ep);
697+ return 1;
698+ }
699+
700+ /* finished that packet. the next one may be waiting... */
701+ return 0;
702+}
703+
704+/*
705+ * done - retire a request; caller blocked irqs
706+ * INDEX register is preserved to keep same
707+ */
708+static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
709+{
710+ unsigned int stopped = ep->stopped;
711+ uint32_t index;
712+
713+ DEBUG("%s, %p\n", __FUNCTION__, ep);
714+ list_del_init(&req->queue);
715+
716+ if (likely(req->req.status == -EINPROGRESS))
717+ req->req.status = status;
718+ else
719+ status = req->req.status;
720+
721+ if (status && status != -ESHUTDOWN)
722+ DEBUG("complete %s req %p stat %d len %u/%u\n",
723+ ep->ep.name, &req->req, status,
724+ req->req.actual, req->req.length);
725+
726+ /* don't modify queue heads during completion callback */
727+ ep->stopped = 1;
728+ /* Read current index (completion may modify it) */
729+ index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
730+ spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
731+
732+ req->req.complete(&ep->ep, &req->req);
733+
734+ spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
735+ /* Restore index */
736+ jz_udc_set_index(ep->dev, index);
737+ ep->stopped = stopped;
738+}
739+
740+static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep)
741+{
742+ if (ep_is_in(ep))
743+ return JZ_REG_UDC_INTRINE;
744+ else
745+ return JZ_REG_UDC_INTROUTE;
746+}
747+
748+/** Enable EP interrupt */
749+static void pio_irq_enable(struct jz4740_ep *ep)
750+{
751+ DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
752+
753+ usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
754+}
755+
756+/** Disable EP interrupt */
757+static void pio_irq_disable(struct jz4740_ep *ep)
758+{
759+ DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
760+
761+ usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
762+}
763+
764+/*
765+ * nuke - dequeue ALL requests
766+ */
767+static void nuke(struct jz4740_ep *ep, int status)
768+{
769+ struct jz4740_request *req;
770+
771+ DEBUG("%s, %p\n", __FUNCTION__, ep);
772+
773+ /* Flush FIFO */
774+ flush(ep);
775+
776+ /* called with irqs blocked */
777+ while (!list_empty(&ep->queue)) {
778+ req = list_entry(ep->queue.next, struct jz4740_request, queue);
779+ done(ep, req, status);
780+ }
781+
782+ /* Disable IRQ if EP is enabled (has descriptor) */
783+ if (ep->desc)
784+ pio_irq_disable(ep);
785+}
786+
787+/** Flush EP FIFO
788+ * NOTE: INDEX register must be set before this call
789+ */
790+static void flush(struct jz4740_ep *ep)
791+{
792+ DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
793+
794+ switch (ep->type) {
795+ case ep_bulk_in:
796+ case ep_interrupt:
797+ usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
798+ break;
799+ case ep_bulk_out:
800+ usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
801+ break;
802+ case ep_control:
803+ break;
804+ }
805+}
806+
807+/**
808+ * jz4740_in_epn - handle IN interrupt
809+ */
810+static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
811+{
812+ uint32_t csr;
813+ struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
814+ struct jz4740_request *req;
815+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
816+
817+ jz_udc_select_ep(ep);
818+
819+ csr = usb_readb(dev, ep->csr);
820+ DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
821+
822+ if (csr & USB_INCSR_SENTSTALL) {
823+ DEBUG("USB_INCSR_SENTSTALL\n");
824+ usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
825+ return;
826+ }
827+
828+ if (!ep->desc) {
829+ DEBUG("%s: NO EP DESC\n", __FUNCTION__);
830+ return;
831+ }
832+
833+ if (!list_empty(&ep->queue)) {
834+ req = list_first_entry(&ep->queue, struct jz4740_request, queue);
835+ write_fifo(ep, req);
836+ }
837+}
838+
839+/*
840+ * Bulk OUT (recv)
841+ */
842+static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
843+{
844+ struct jz4740_ep *ep = &dev->ep[ep_idx];
845+ struct jz4740_request *req;
846+
847+ DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
848+
849+ jz_udc_select_ep(ep);
850+ if (ep->desc) {
851+ uint32_t csr;
852+
853+ while ((csr = usb_readb(dev, ep->csr)) &
854+ (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
855+ DEBUG("%s: %x\n", __FUNCTION__, csr);
856+
857+ if (csr & USB_OUTCSR_SENTSTALL) {
858+ DEBUG("%s: stall sent, flush fifo\n",
859+ __FUNCTION__);
860+ /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
861+ flush(ep);
862+ } else if (csr & USB_OUTCSR_OUTPKTRDY) {
863+ if (list_empty(&ep->queue))
864+ req = 0;
865+ else
866+ req =
867+ list_entry(ep->queue.next,
868+ struct jz4740_request,
869+ queue);
870+
871+ if (!req) {
872+ DEBUG("%s: NULL REQ %d\n",
873+ __FUNCTION__, ep_idx);
874+ break;
875+ } else {
876+ read_fifo(ep, req);
877+ }
878+ }
879+ }
880+ } else {
881+ /* Throw packet away.. */
882+ DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
883+ flush(ep);
884+ }
885+}
886+
887+/** Halt specific EP
888+ * Return 0 if success
889+ * NOTE: Sets INDEX register to EP !
890+ */
891+static int jz4740_set_halt(struct usb_ep *_ep, int value)
892+{
893+ struct jz4740_udc *dev;
894+ struct jz4740_ep *ep;
895+ unsigned long flags;
896+
897+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
898+
899+ ep = container_of(_ep, struct jz4740_ep, ep);
900+ if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
901+ DEBUG("%s, bad ep\n", __FUNCTION__);
902+ return -EINVAL;
903+ }
904+
905+ dev = ep->dev;
906+
907+ spin_lock_irqsave(&dev->lock, flags);
908+
909+ jz_udc_select_ep(ep);
910+
911+ DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
912+
913+ if (ep_index(ep) == 0) {
914+ /* EP0 */
915+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
916+ } else if (ep_is_in(ep)) {
917+ uint32_t csr = usb_readb(dev, ep->csr);
918+ if (value && ((csr & USB_INCSR_FFNOTEMPT)
919+ || !list_empty(&ep->queue))) {
920+ /*
921+ * Attempts to halt IN endpoints will fail (returning -EAGAIN)
922+ * if any transfer requests are still queued, or if the controller
923+ * FIFO still holds bytes that the host hasnÂ’t collected.
924+ */
925+ spin_unlock_irqrestore(&dev->lock, flags);
926+ DEBUG
927+ ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
928+ (csr & USB_INCSR_FFNOTEMPT),
929+ !list_empty(&ep->queue));
930+ return -EAGAIN;
931+ }
932+ flush(ep);
933+ if (value) {
934+ usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
935+ } else {
936+ usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
937+ usb_setb(dev, ep->csr, USB_INCSR_CDT);
938+ }
939+ } else {
940+
941+ flush(ep);
942+ if (value) {
943+ usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
944+ } else {
945+ usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
946+ usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
947+ }
948+ }
949+
950+ ep->stopped = value;
951+
952+ spin_unlock_irqrestore(&dev->lock, flags);
953+
954+ DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
955+
956+ return 0;
957+}
958+
959+
960+static int jz4740_ep_enable(struct usb_ep *_ep,
961+ const struct usb_endpoint_descriptor *desc)
962+{
963+ struct jz4740_ep *ep;
964+ struct jz4740_udc *dev;
965+ unsigned long flags;
966+ uint32_t max, csrh = 0;
967+
968+ DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
969+
970+ if (!_ep || !desc)
971+ return -EINVAL;
972+
973+ ep = container_of(_ep, struct jz4740_ep, ep);
974+ if (ep->desc || ep->type == ep_control
975+ || desc->bDescriptorType != USB_DT_ENDPOINT
976+ || ep->bEndpointAddress != desc->bEndpointAddress) {
977+ DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
978+ return -EINVAL;
979+ }
980+
981+ /* xfer types must match, except that interrupt ~= bulk */
982+ if (ep->bmAttributes != desc->bmAttributes
983+ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
984+ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
985+ DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
986+ return -EINVAL;
987+ }
988+
989+ dev = ep->dev;
990+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
991+ DEBUG("%s, bogus device state\n", __FUNCTION__);
992+ return -ESHUTDOWN;
993+ }
994+
995+ max = le16_to_cpu(desc->wMaxPacketSize);
996+
997+ spin_lock_irqsave(&ep->dev->lock, flags);
998+
999+ /* Configure the endpoint */
1000+ jz_udc_select_ep(ep);
1001+ if (ep_is_in(ep)) {
1002+ usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1003+ switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1004+ case USB_ENDPOINT_XFER_BULK:
1005+ case USB_ENDPOINT_XFER_INT:
1006+ csrh &= ~USB_INCSRH_ISO;
1007+ break;
1008+ case USB_ENDPOINT_XFER_ISOC:
1009+ csrh |= USB_INCSRH_ISO;
1010+ break;
1011+ }
1012+ usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1013+ }
1014+ else {
1015+ usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1016+ switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1017+ case USB_ENDPOINT_XFER_BULK:
1018+ csrh &= ~USB_OUTCSRH_ISO;
1019+ break;
1020+ case USB_ENDPOINT_XFER_INT:
1021+ csrh &= ~USB_OUTCSRH_ISO;
1022+ csrh |= USB_OUTCSRH_DNYT;
1023+ break;
1024+ case USB_ENDPOINT_XFER_ISOC:
1025+ csrh |= USB_OUTCSRH_ISO;
1026+ break;
1027+ }
1028+ usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1029+ }
1030+
1031+
1032+ ep->stopped = 0;
1033+ ep->desc = desc;
1034+ ep->ep.maxpacket = max;
1035+
1036+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1037+
1038+ /* Reset halt state (does flush) */
1039+ jz4740_set_halt(_ep, 0);
1040+
1041+ DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1042+
1043+ return 0;
1044+}
1045+
1046+/** Disable EP
1047+ * NOTE: Sets INDEX register
1048+ */
1049+static int jz4740_ep_disable(struct usb_ep *_ep)
1050+{
1051+ struct jz4740_ep *ep;
1052+ unsigned long flags;
1053+
1054+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
1055+
1056+ ep = container_of(_ep, struct jz4740_ep, ep);
1057+ if (!_ep || !ep->desc) {
1058+ DEBUG("%s, %s not enabled\n", __FUNCTION__,
1059+ _ep ? ep->ep.name : NULL);
1060+ return -EINVAL;
1061+ }
1062+
1063+ spin_lock_irqsave(&ep->dev->lock, flags);
1064+
1065+ jz_udc_select_ep(ep);
1066+
1067+ /* Nuke all pending requests (does flush) */
1068+ nuke(ep, -ESHUTDOWN);
1069+
1070+ /* Disable ep IRQ */
1071+ pio_irq_disable(ep);
1072+
1073+ ep->desc = 0;
1074+ ep->stopped = 1;
1075+
1076+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1077+
1078+ DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1079+ return 0;
1080+}
1081+
1082+static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1083+{
1084+ struct jz4740_request *req;
1085+
1086+ req = kzalloc(sizeof(*req), gfp_flags);
1087+ if (!req)
1088+ return NULL;
1089+
1090+ INIT_LIST_HEAD(&req->queue);
1091+
1092+ return &req->req;
1093+}
1094+
1095+static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1096+{
1097+ struct jz4740_request *req;
1098+
1099+ req = container_of(_req, struct jz4740_request, req);
1100+ WARN_ON(!list_empty(&req->queue));
1101+
1102+ kfree(req);
1103+}
1104+
1105+/*--------------------------------------------------------------------*/
1106+
1107+/** Queue one request
1108+ * Kickstart transfer if needed
1109+ * NOTE: Sets INDEX register
1110+ */
1111+static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1112+ gfp_t gfp_flags)
1113+{
1114+ struct jz4740_request *req;
1115+ struct jz4740_ep *ep;
1116+ struct jz4740_udc *dev;
1117+
1118+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
1119+
1120+ req = container_of(_req, struct jz4740_request, req);
1121+ if (unlikely
1122+ (!_req || !_req->complete || !_req->buf
1123+ || !list_empty(&req->queue))) {
1124+ DEBUG("%s, bad params\n", __FUNCTION__);
1125+ return -EINVAL;
1126+ }
1127+
1128+ ep = container_of(_ep, struct jz4740_ep, ep);
1129+ if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1130+ DEBUG("%s, bad ep\n", __FUNCTION__);
1131+ return -EINVAL;
1132+ }
1133+
1134+ dev = ep->dev;
1135+ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1136+ DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1137+ return -ESHUTDOWN;
1138+ }
1139+
1140+ DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1141+ _req->buf);
1142+
1143+ spin_lock_irqsave(&dev->lock, dev->lock_flags);
1144+
1145+ _req->status = -EINPROGRESS;
1146+ _req->actual = 0;
1147+
1148+ /* kickstart this i/o queue? */
1149+ DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1150+ ep->stopped);
1151+ if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1152+ uint32_t csr;
1153+
1154+ if (unlikely(ep_index(ep) == 0)) {
1155+ /* EP0 */
1156+ list_add_tail(&req->queue, &ep->queue);
1157+ jz4740_ep0_kick(dev, ep);
1158+ req = 0;
1159+ }
1160+ else if (ep_is_in(ep)) {
1161+ /* EP1 & EP2 */
1162+ jz_udc_select_ep(ep);
1163+ csr = usb_readb(dev, ep->csr);
1164+ pio_irq_enable(ep);
1165+ if (!(csr & USB_INCSR_FFNOTEMPT)) {
1166+ if (write_fifo(ep, req) == 1)
1167+ req = 0;
1168+ }
1169+ } else {
1170+ /* EP1 */
1171+ jz_udc_select_ep(ep);
1172+ csr = usb_readb(dev, ep->csr);
1173+ pio_irq_enable(ep);
1174+ if (csr & USB_OUTCSR_OUTPKTRDY) {
1175+ if (read_fifo(ep, req) == 1)
1176+ req = 0;
1177+ }
1178+ }
1179+ }
1180+
1181+ /* pio or dma irq handler advances the queue. */
1182+ if (likely(req != 0))
1183+ list_add_tail(&req->queue, &ep->queue);
1184+
1185+ spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1186+
1187+ return 0;
1188+}
1189+
1190+/* dequeue JUST ONE request */
1191+static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1192+{
1193+ struct jz4740_ep *ep;
1194+ struct jz4740_request *req;
1195+ unsigned long flags;
1196+
1197+ DEBUG("%s, %p\n", __FUNCTION__, _ep);
1198+
1199+ ep = container_of(_ep, struct jz4740_ep, ep);
1200+ if (!_ep || ep->type == ep_control)
1201+ return -EINVAL;
1202+
1203+ spin_lock_irqsave(&ep->dev->lock, flags);
1204+
1205+ /* make sure it's actually queued on this endpoint */
1206+ list_for_each_entry(req, &ep->queue, queue) {
1207+ if (&req->req == _req)
1208+ break;
1209+ }
1210+ if (&req->req != _req) {
1211+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1212+ return -EINVAL;
1213+ }
1214+ done(ep, req, -ECONNRESET);
1215+
1216+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1217+ return 0;
1218+}
1219+
1220+/** Return bytes in EP FIFO
1221+ * NOTE: Sets INDEX register to EP
1222+ */
1223+static int jz4740_fifo_status(struct usb_ep *_ep)
1224+{
1225+ uint32_t csr;
1226+ int count = 0;
1227+ struct jz4740_ep *ep;
1228+ unsigned long flags;
1229+
1230+ ep = container_of(_ep, struct jz4740_ep, ep);
1231+ if (!_ep) {
1232+ DEBUG("%s, bad ep\n", __FUNCTION__);
1233+ return -ENODEV;
1234+ }
1235+
1236+ DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1237+
1238+ /* LPD can't report unclaimed bytes from IN fifos */
1239+ if (ep_is_in(ep))
1240+ return -EOPNOTSUPP;
1241+
1242+ spin_lock_irqsave(&ep->dev->lock, flags);
1243+ jz_udc_select_ep(ep);
1244+
1245+ csr = usb_readb(ep->dev, ep->csr);
1246+ if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1247+ csr & 0x1) {
1248+ count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1249+ }
1250+
1251+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1252+
1253+ return count;
1254+}
1255+
1256+/** Flush EP FIFO
1257+ * NOTE: Sets INDEX register to EP
1258+ */
1259+static void jz4740_fifo_flush(struct usb_ep *_ep)
1260+{
1261+ struct jz4740_ep *ep;
1262+ unsigned long flags;
1263+
1264+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1265+
1266+ ep = container_of(_ep, struct jz4740_ep, ep);
1267+ if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1268+ DEBUG("%s, bad ep\n", __FUNCTION__);
1269+ return;
1270+ }
1271+
1272+ spin_lock_irqsave(&ep->dev->lock, flags);
1273+
1274+ jz_udc_select_ep(ep);
1275+ flush(ep);
1276+
1277+ spin_unlock_irqrestore(&ep->dev->lock, flags);
1278+}
1279+
1280+/****************************************************************/
1281+/* End Point 0 related functions */
1282+/****************************************************************/
1283+
1284+/* return: 0 = still running, 1 = completed, negative = errno */
1285+static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1286+{
1287+ uint32_t max;
1288+ unsigned count;
1289+ int is_last;
1290+
1291+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1292+ max = ep_maxpacket(ep);
1293+
1294+ count = write_packet(ep, req, max);
1295+
1296+ /* last packet is usually short (or a zlp) */
1297+ if (unlikely(count != max))
1298+ is_last = 1;
1299+ else {
1300+ if (likely(req->req.length != req->req.actual) || req->req.zero)
1301+ is_last = 0;
1302+ else
1303+ is_last = 1;
1304+ }
1305+
1306+ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1307+ ep->ep.name, count,
1308+ is_last ? "/L" : "", req->req.length - req->req.actual, req);
1309+
1310+ /* requests complete when all IN data is in the FIFO */
1311+ if (is_last) {
1312+ done(ep, req, 0);
1313+ return 1;
1314+ }
1315+
1316+ return 0;
1317+}
1318+
1319+static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1320+ unsigned char *cp, int max)
1321+{
1322+ int bytes;
1323+ int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1324+
1325+ if (count > max)
1326+ count = max;
1327+ bytes = count;
1328+ while (count--)
1329+ *cp++ = usb_readb(ep->dev, ep->fifo);
1330+
1331+ return bytes;
1332+}
1333+
1334+static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1335+ unsigned char *cp, int count)
1336+{
1337+ DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1338+ while (count--)
1339+ usb_writeb(ep->dev, ep->fifo, *cp++);
1340+}
1341+
1342+static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1343+{
1344+ struct jz4740_udc *dev = ep->dev;
1345+ uint32_t csr;
1346+ uint8_t *buf;
1347+ unsigned bufferspace, count, is_short;
1348+
1349+ DEBUG_EP0("%s\n", __FUNCTION__);
1350+
1351+ csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1352+ if (!(csr & USB_CSR0_OUTPKTRDY))
1353+ return 0;
1354+
1355+ buf = req->req.buf + req->req.actual;
1356+ prefetchw(buf);
1357+ bufferspace = req->req.length - req->req.actual;
1358+
1359+ /* read all bytes from this packet */
1360+ if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1361+ count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1362+ req->req.actual += min(count, bufferspace);
1363+ } else /* zlp */
1364+ count = 0;
1365+
1366+ is_short = (count < ep->ep.maxpacket);
1367+ DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1368+ ep->ep.name, csr, count,
1369+ is_short ? "/S" : "", req, req->req.actual, req->req.length);
1370+
1371+ while (likely(count-- != 0)) {
1372+ uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1373+
1374+ if (unlikely(bufferspace == 0)) {
1375+ /* this happens when the driver's buffer
1376+ * is smaller than what the host sent.
1377+ * discard the extra data.
1378+ */
1379+ if (req->req.status != -EOVERFLOW)
1380+ DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1381+ count);
1382+ req->req.status = -EOVERFLOW;
1383+ } else {
1384+ *buf++ = byte;
1385+ bufferspace--;
1386+ }
1387+ }
1388+
1389+ /* completion */
1390+ if (is_short || req->req.actual == req->req.length) {
1391+ done(ep, req, 0);
1392+ return 1;
1393+ }
1394+
1395+ /* finished that packet. the next one may be waiting... */
1396+ return 0;
1397+}
1398+
1399+/**
1400+ * udc_set_address - set the USB address for this device
1401+ * @address:
1402+ *
1403+ * Called from control endpoint function after it decodes a set address setup packet.
1404+ */
1405+static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1406+{
1407+ DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1408+
1409+ usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1410+}
1411+
1412+/*
1413+ * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1414+ * - if error
1415+ * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1416+ * - else
1417+ * set USB_CSR0_SVDOUTPKTRDY bit
1418+ if last set USB_CSR0_DATAEND bit
1419+ */
1420+static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1421+{
1422+ struct jz4740_request *req;
1423+ struct jz4740_ep *ep = &dev->ep[0];
1424+ int ret;
1425+
1426+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1427+
1428+ if (list_empty(&ep->queue))
1429+ req = 0;
1430+ else
1431+ req = list_entry(ep->queue.next, struct jz4740_request, queue);
1432+
1433+ if (req) {
1434+ if (req->req.length == 0) {
1435+ DEBUG_EP0("ZERO LENGTH OUT!\n");
1436+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1437+ dev->ep0state = WAIT_FOR_SETUP;
1438+ return;
1439+ } else if (kickstart) {
1440+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1441+ return;
1442+ }
1443+ ret = read_fifo_ep0(ep, req);
1444+ if (ret) {
1445+ /* Done! */
1446+ DEBUG_EP0("%s: finished, waiting for status\n",
1447+ __FUNCTION__);
1448+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1449+ dev->ep0state = WAIT_FOR_SETUP;
1450+ } else {
1451+ /* Not done yet.. */
1452+ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1453+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1454+ }
1455+ } else {
1456+ DEBUG_EP0("NO REQ??!\n");
1457+ }
1458+}
1459+
1460+/*
1461+ * DATA_STATE_XMIT
1462+ */
1463+static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1464+{
1465+ struct jz4740_request *req;
1466+ struct jz4740_ep *ep = &dev->ep[0];
1467+ int ret, need_zlp = 0;
1468+
1469+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1470+
1471+ if (list_empty(&ep->queue))
1472+ req = 0;
1473+ else
1474+ req = list_entry(ep->queue.next, struct jz4740_request, queue);
1475+
1476+ if (!req) {
1477+ DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1478+ return 0;
1479+ }
1480+
1481+ if (req->req.length == 0) {
1482+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1483+ dev->ep0state = WAIT_FOR_SETUP;
1484+ return 1;
1485+ }
1486+
1487+ if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1488+ /* Next write will end with the packet size, */
1489+ /* so we need zero-length-packet */
1490+ need_zlp = 1;
1491+ }
1492+
1493+ ret = write_fifo_ep0(ep, req);
1494+
1495+ if (ret == 1 && !need_zlp) {
1496+ /* Last packet */
1497+ DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1498+
1499+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1500+ dev->ep0state = WAIT_FOR_SETUP;
1501+ } else {
1502+ DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1503+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1504+ }
1505+
1506+ if (need_zlp) {
1507+ DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1508+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1509+ dev->ep0state = DATA_STATE_NEED_ZLP;
1510+ }
1511+
1512+ return 1;
1513+}
1514+
1515+static int jz4740_handle_get_status(struct jz4740_udc *dev,
1516+ struct usb_ctrlrequest *ctrl)
1517+{
1518+ struct jz4740_ep *ep0 = &dev->ep[0];
1519+ struct jz4740_ep *qep;
1520+ int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1521+ uint16_t val = 0;
1522+
1523+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1524+
1525+ if (reqtype == USB_RECIP_INTERFACE) {
1526+ /* This is not supported.
1527+ * And according to the USB spec, this one does nothing..
1528+ * Just return 0
1529+ */
1530+ DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1531+ } else if (reqtype == USB_RECIP_DEVICE) {
1532+ DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1533+ val |= (1 << 0); /* Self powered */
1534+ /*val |= (1<<1); *//* Remote wakeup */
1535+ } else if (reqtype == USB_RECIP_ENDPOINT) {
1536+ int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1537+
1538+ DEBUG_SETUP
1539+ ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1540+ ep_num, ctrl->wLength);
1541+
1542+ if (ctrl->wLength > 2 || ep_num > 3)
1543+ return -EOPNOTSUPP;
1544+
1545+ qep = &dev->ep[ep_num];
1546+ if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1547+ && ep_index(qep) != 0) {
1548+ return -EOPNOTSUPP;
1549+ }
1550+
1551+ jz_udc_select_ep(qep);
1552+
1553+ /* Return status on next IN token */
1554+ switch (qep->type) {
1555+ case ep_control:
1556+ val =
1557+ (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1558+ USB_CSR0_SENDSTALL;
1559+ break;
1560+ case ep_bulk_in:
1561+ case ep_interrupt:
1562+ val =
1563+ (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1564+ USB_INCSR_SENDSTALL;
1565+ break;
1566+ case ep_bulk_out:
1567+ val =
1568+ (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1569+ USB_OUTCSR_SENDSTALL;
1570+ break;
1571+ }
1572+
1573+ /* Back to EP0 index */
1574+ jz_udc_set_index(dev, 0);
1575+
1576+ DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1577+ ctrl->wIndex, val);
1578+ } else {
1579+ DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1580+ return -EOPNOTSUPP;
1581+ }
1582+
1583+ /* Clear "out packet ready" */
1584+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1585+ /* Put status to FIFO */
1586+ jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1587+ /* Issue "In packet ready" */
1588+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1589+
1590+ return 0;
1591+}
1592+
1593+/*
1594+ * WAIT_FOR_SETUP (OUTPKTRDY)
1595+ * - read data packet from EP0 FIFO
1596+ * - decode command
1597+ * - if error
1598+ * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1599+ * - else
1600+ * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1601+ */
1602+static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1603+{
1604+ struct jz4740_ep *ep = &dev->ep[0];
1605+ struct usb_ctrlrequest ctrl;
1606+ int i;
1607+
1608+ DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1609+
1610+ /* Nuke all previous transfers */
1611+ nuke(ep, -EPROTO);
1612+
1613+ /* read control req from fifo (8 bytes) */
1614+ jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1615+
1616+ DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1617+ ctrl.bRequestType, ctrl.bRequest,
1618+ ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1619+
1620+ /* Set direction of EP0 */
1621+ if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1622+ ep->bEndpointAddress |= USB_DIR_IN;
1623+ } else {
1624+ ep->bEndpointAddress &= ~USB_DIR_IN;
1625+ }
1626+
1627+ /* Handle some SETUP packets ourselves */
1628+ switch (ctrl.bRequest) {
1629+ case USB_REQ_SET_ADDRESS:
1630+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1631+ break;
1632+
1633+ DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1634+ udc_set_address(dev, ctrl.wValue);
1635+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1636+ return;
1637+
1638+ case USB_REQ_SET_CONFIGURATION:
1639+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1640+ break;
1641+
1642+ DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1643+/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1644+
1645+ /* Enable RESUME and SUSPEND interrupts */
1646+ usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1647+ break;
1648+
1649+ case USB_REQ_SET_INTERFACE:
1650+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1651+ break;
1652+
1653+ DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1654+/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1655+ break;
1656+
1657+ case USB_REQ_GET_STATUS:
1658+ if (jz4740_handle_get_status(dev, &ctrl) == 0)
1659+ return;
1660+
1661+ case USB_REQ_CLEAR_FEATURE:
1662+ case USB_REQ_SET_FEATURE:
1663+ if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1664+ struct jz4740_ep *qep;
1665+ int ep_num = (ctrl.wIndex & 0x0f);
1666+
1667+ /* Support only HALT feature */
1668+ if (ctrl.wValue != 0 || ctrl.wLength != 0
1669+ || ep_num > 3 || ep_num < 1)
1670+ break;
1671+
1672+ qep = &dev->ep[ep_num];
1673+ spin_unlock(&dev->lock);
1674+ if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1675+ DEBUG_SETUP("SET_FEATURE (%d)\n",
1676+ ep_num);
1677+ jz4740_set_halt(&qep->ep, 1);
1678+ } else {
1679+ DEBUG_SETUP("CLR_FEATURE (%d)\n",
1680+ ep_num);
1681+ jz4740_set_halt(&qep->ep, 0);
1682+ }
1683+ spin_lock(&dev->lock);
1684+
1685+ jz_udc_set_index(dev, 0);
1686+
1687+ /* Reply with a ZLP on next IN token */
1688+ usb_setb(dev, JZ_REG_UDC_CSR0,
1689+ (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1690+ return;
1691+ }
1692+ break;
1693+
1694+ default:
1695+ break;
1696+ }
1697+
1698+ /* gadget drivers see class/vendor specific requests,
1699+ * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1700+ * and more.
1701+ */
1702+ if (dev->driver) {
1703+ /* device-2-host (IN) or no data setup command, process immediately */
1704+ spin_unlock(&dev->lock);
1705+
1706+ i = dev->driver->setup(&dev->gadget, &ctrl);
1707+ spin_lock(&dev->lock);
1708+
1709+ if (unlikely(i < 0)) {
1710+ /* setup processing failed, force stall */
1711+ DEBUG_SETUP
1712+ (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1713+ i);
1714+ jz_udc_set_index(dev, 0);
1715+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1716+
1717+ /* ep->stopped = 1; */
1718+ dev->ep0state = WAIT_FOR_SETUP;
1719+ }
1720+ else {
1721+ DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1722+/* if (!ctrl.wLength) {
1723+ usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1724+ }*/
1725+ }
1726+ }
1727+}
1728+
1729+/*
1730+ * DATA_STATE_NEED_ZLP
1731+ */
1732+static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1733+{
1734+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1735+
1736+ usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1737+ dev->ep0state = WAIT_FOR_SETUP;
1738+}
1739+
1740+/*
1741+ * handle ep0 interrupt
1742+ */
1743+static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1744+{
1745+ struct jz4740_ep *ep = &dev->ep[0];
1746+ uint32_t csr;
1747+
1748+ DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1749+ /* Set index 0 */
1750+ jz_udc_set_index(dev, 0);
1751+ csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1752+
1753+ DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1754+
1755+ /*
1756+ * if SENT_STALL is set
1757+ * - clear the SENT_STALL bit
1758+ */
1759+ if (csr & USB_CSR0_SENTSTALL) {
1760+ DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1761+ usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1762+ nuke(ep, -ECONNABORTED);
1763+ dev->ep0state = WAIT_FOR_SETUP;
1764+ return;
1765+ }
1766+
1767+ /*
1768+ * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1769+ * - fill EP0 FIFO
1770+ * - if last packet
1771+ * - set IN_PKT_RDY | DATA_END
1772+ * - else
1773+ * set IN_PKT_RDY
1774+ */
1775+ if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1776+ DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1777+ __FUNCTION__);
1778+
1779+ switch (dev->ep0state) {
1780+ case DATA_STATE_XMIT:
1781+ DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1782+ jz4740_ep0_in(dev, csr);
1783+ return;
1784+ case DATA_STATE_NEED_ZLP:
1785+ DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1786+ jz4740_ep0_in_zlp(dev, csr);
1787+ return;
1788+ default:
1789+ /* Stall? */
1790+// DEBUG_EP0("Odd state!! state = %s\n",
1791+// state_names[dev->ep0state]);
1792+ dev->ep0state = WAIT_FOR_SETUP;
1793+ /* nuke(ep, 0); */
1794+ /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1795+// break;
1796+ return;
1797+ }
1798+ }
1799+
1800+ /*
1801+ * if SETUPEND is set
1802+ * - abort the last transfer
1803+ * - set SERVICED_SETUP_END_BIT
1804+ */
1805+ if (csr & USB_CSR0_SETUPEND) {
1806+ DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1807+
1808+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1809+ nuke(ep, 0);
1810+ dev->ep0state = WAIT_FOR_SETUP;
1811+ }
1812+
1813+ /*
1814+ * if USB_CSR0_OUTPKTRDY is set
1815+ * - read data packet from EP0 FIFO
1816+ * - decode command
1817+ * - if error
1818+ * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1819+ * - else
1820+ * set SVDOUTPKTRDY | DATAEND bits
1821+ */
1822+ if (csr & USB_CSR0_OUTPKTRDY) {
1823+
1824+ DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1825+ csr);
1826+
1827+ switch (dev->ep0state) {
1828+ case WAIT_FOR_SETUP:
1829+ DEBUG_EP0("WAIT_FOR_SETUP\n");
1830+ jz4740_ep0_setup(dev, csr);
1831+ break;
1832+
1833+ case DATA_STATE_RECV:
1834+ DEBUG_EP0("DATA_STATE_RECV\n");
1835+ jz4740_ep0_out(dev, csr, 0);
1836+ break;
1837+
1838+ default:
1839+ /* send stall? */
1840+ DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1841+ dev->ep0state);
1842+ break;
1843+ }
1844+ }
1845+}
1846+
1847+static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1848+{
1849+ uint32_t csr;
1850+
1851+ jz_udc_set_index(dev, 0);
1852+
1853+ DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1854+
1855+ /* Clear "out packet ready" */
1856+
1857+ if (ep_is_in(ep)) {
1858+ usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1859+ csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1860+ dev->ep0state = DATA_STATE_XMIT;
1861+ jz4740_ep0_in(dev, csr);
1862+ } else {
1863+ csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1864+ dev->ep0state = DATA_STATE_RECV;
1865+ jz4740_ep0_out(dev, csr, 1);
1866+ }
1867+}
1868+
1869+/** Handle USB RESET interrupt
1870+ */
1871+static void jz4740_reset_irq(struct jz4740_udc *dev)
1872+{
1873+ dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1874+ USB_SPEED_HIGH : USB_SPEED_FULL;
1875+
1876+ DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
1877+ (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1878+}
1879+
1880+/*
1881+ * jz4740 usb device interrupt handler.
1882+ */
1883+static irqreturn_t jz4740_udc_irq(int irq, void *devid)
1884+{
1885+ struct jz4740_udc *jz4740_udc = devid;
1886+ uint8_t index;
1887+
1888+ uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1889+ uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
1890+ uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
1891+ uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
1892+
1893+ if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1894+ return IRQ_HANDLED;
1895+
1896+
1897+ DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1898+ intr_out, intr_in, intr_usb);
1899+
1900+ spin_lock(&jz4740_udc->lock);
1901+ index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
1902+
1903+ /* Check for resume from suspend mode */
1904+ if ((intr_usb & USB_INTR_RESUME) &&
1905+ (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1906+ DEBUG("USB resume\n");
1907+ jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
1908+ }
1909+
1910+ /* Check for system interrupts */
1911+ if (intr_usb & USB_INTR_RESET) {
1912+ DEBUG("USB reset\n");
1913+ jz4740_reset_irq(jz4740_udc);
1914+ }
1915+
1916+ /* Check for endpoint 0 interrupt */
1917+ if (intr_in & USB_INTR_EP0) {
1918+ DEBUG("USB_INTR_EP0 (control)\n");
1919+ jz4740_handle_ep0(jz4740_udc, intr_in);
1920+ }
1921+
1922+ /* Check for Bulk-IN DMA interrupt */
1923+ if (intr_dma & 0x1) {
1924+ int ep_num;
1925+ struct jz4740_ep *ep;
1926+ ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
1927+ ep = &jz4740_udc->ep[ep_num + 1];
1928+ jz_udc_select_ep(ep);
1929+ usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
1930+/* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
1931+ }
1932+
1933+ /* Check for Bulk-OUT DMA interrupt */
1934+ if (intr_dma & 0x2) {
1935+ int ep_num;
1936+ ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
1937+ jz4740_out_epn(jz4740_udc, ep_num, intr_out);
1938+ }
1939+
1940+ /* Check for each configured endpoint interrupt */
1941+ if (intr_in & USB_INTR_INEP1) {
1942+ DEBUG("USB_INTR_INEP1\n");
1943+ jz4740_in_epn(jz4740_udc, 1, intr_in);
1944+ }
1945+
1946+ if (intr_in & USB_INTR_INEP2) {
1947+ DEBUG("USB_INTR_INEP2\n");
1948+ jz4740_in_epn(jz4740_udc, 2, intr_in);
1949+ }
1950+
1951+ if (intr_out & USB_INTR_OUTEP1) {
1952+ DEBUG("USB_INTR_OUTEP1\n");
1953+ jz4740_out_epn(jz4740_udc, 1, intr_out);
1954+ }
1955+
1956+ /* Check for suspend mode */
1957+ if ((intr_usb & USB_INTR_SUSPEND) &&
1958+ (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
1959+ DEBUG("USB suspend\n");
1960+ jz4740_udc->driver->suspend(&jz4740_udc->gadget);
1961+ /* Host unloaded from us, can do something, such as flushing
1962+ the NAND block cache etc. */
1963+ }
1964+
1965+ jz_udc_set_index(jz4740_udc, index);
1966+
1967+ spin_unlock(&jz4740_udc->lock);
1968+
1969+ return IRQ_HANDLED;
1970+}
1971+
1972+
1973+
1974+/*-------------------------------------------------------------------------*/
1975+
1976+
1977+static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
1978+{
1979+ return container_of(gadget, struct jz4740_udc, gadget);
1980+}
1981+
1982+static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
1983+{
1984+ DEBUG("%s, %p\n", __FUNCTION__, _gadget);
1985+ return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
1986+}
1987+
1988+static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
1989+{
1990+ /* host may not have enabled remote wakeup */
1991+ /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
1992+ return -EHOSTUNREACH;
1993+ udc_set_mask_UDCCR(UDCCR_RSM); */
1994+ return -ENOTSUPP;
1995+}
1996+
1997+static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
1998+{
1999+ struct jz4740_udc *udc = gadget_to_udc(_gadget);
2000+ unsigned long flags;
2001+
2002+ local_irq_save(flags);
2003+
2004+ if (on) {
2005+ udc->state = UDC_STATE_ENABLE;
2006+ udc_enable(udc);
2007+ } else {
2008+ udc->state = UDC_STATE_DISABLE;
2009+ udc_disable(udc);
2010+ }
2011+
2012+ local_irq_restore(flags);
2013+
2014+ return 0;
2015+}
2016+
2017+
2018+static const struct usb_gadget_ops jz4740_udc_ops = {
2019+ .get_frame = jz4740_udc_get_frame,
2020+ .wakeup = jz4740_udc_wakeup,
2021+ .pullup = jz4740_udc_pullup,
2022+};
2023+
2024+static struct usb_ep_ops jz4740_ep_ops = {
2025+ .enable = jz4740_ep_enable,
2026+ .disable = jz4740_ep_disable,
2027+
2028+ .alloc_request = jz4740_alloc_request,
2029+ .free_request = jz4740_free_request,
2030+
2031+ .queue = jz4740_queue,
2032+ .dequeue = jz4740_dequeue,
2033+
2034+ .set_halt = jz4740_set_halt,
2035+ .fifo_status = jz4740_fifo_status,
2036+ .fifo_flush = jz4740_fifo_flush,
2037+};
2038+
2039+
2040+/*-------------------------------------------------------------------------*/
2041+
2042+static struct jz4740_udc jz4740_udc_controller = {
2043+ .gadget = {
2044+ .ops = &jz4740_udc_ops,
2045+ .ep0 = &jz4740_udc_controller.ep[0].ep,
2046+ .name = "jz4740-udc",
2047+ .dev = {
2048+ .init_name = "gadget",
2049+ },
2050+ },
2051+
2052+ /* control endpoint */
2053+ .ep[0] = {
2054+ .ep = {
2055+ .name = "ep0",
2056+ .ops = &jz4740_ep_ops,
2057+ .maxpacket = EP0_MAXPACKETSIZE,
2058+ },
2059+ .dev = &jz4740_udc_controller,
2060+
2061+ .bEndpointAddress = 0,
2062+ .bmAttributes = 0,
2063+
2064+ .type = ep_control,
2065+ .fifo = JZ_REG_UDC_EP_FIFO(0),
2066+ .csr = JZ_REG_UDC_CSR0,
2067+ },
2068+
2069+ /* bulk out endpoint */
2070+ .ep[1] = {
2071+ .ep = {
2072+ .name = "ep1out-bulk",
2073+ .ops = &jz4740_ep_ops,
2074+ .maxpacket = EPBULK_MAXPACKETSIZE,
2075+ },
2076+ .dev = &jz4740_udc_controller,
2077+
2078+ .bEndpointAddress = 1,
2079+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
2080+
2081+ .type = ep_bulk_out,
2082+ .fifo = JZ_REG_UDC_EP_FIFO(1),
2083+ .csr = JZ_REG_UDC_OUTCSR,
2084+ },
2085+
2086+ /* bulk in endpoint */
2087+ .ep[2] = {
2088+ .ep = {
2089+ .name = "ep1in-bulk",
2090+ .ops = &jz4740_ep_ops,
2091+ .maxpacket = EPBULK_MAXPACKETSIZE,
2092+ },
2093+ .dev = &jz4740_udc_controller,
2094+
2095+ .bEndpointAddress = 1 | USB_DIR_IN,
2096+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
2097+
2098+ .type = ep_bulk_in,
2099+ .fifo = JZ_REG_UDC_EP_FIFO(1),
2100+ .csr = JZ_REG_UDC_INCSR,
2101+ },
2102+
2103+ /* interrupt in endpoint */
2104+ .ep[3] = {
2105+ .ep = {
2106+ .name = "ep2in-int",
2107+ .ops = &jz4740_ep_ops,
2108+ .maxpacket = EPINTR_MAXPACKETSIZE,
2109+ },
2110+ .dev = &jz4740_udc_controller,
2111+
2112+ .bEndpointAddress = 2 | USB_DIR_IN,
2113+ .bmAttributes = USB_ENDPOINT_XFER_INT,
2114+
2115+ .type = ep_interrupt,
2116+ .fifo = JZ_REG_UDC_EP_FIFO(2),
2117+ .csr = JZ_REG_UDC_INCSR,
2118+ },
2119+};
2120+
2121+static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2122+{
2123+ struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2124+ int ret;
2125+
2126+ spin_lock_init(&jz4740_udc->lock);
2127+
2128+ jz4740_udc->dev = &pdev->dev;
2129+ jz4740_udc->gadget.dev.parent = &pdev->dev;
2130+ jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
2131+
2132+ ret = device_register(&jz4740_udc->gadget.dev);
2133+ if (ret)
2134+ return ret;
2135+
2136+ jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2137+ if (IS_ERR(jz4740_udc->clk)) {
2138+ ret = PTR_ERR(jz4740_udc->clk);
2139+ dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2140+ goto err_device_unregister;
2141+ }
2142+
2143+ platform_set_drvdata(pdev, jz4740_udc);
2144+
2145+ jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2146+
2147+ if (!jz4740_udc->mem) {
2148+ ret = -ENOENT;
2149+ dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2150+ goto err_clk_put;
2151+ }
2152+
2153+ jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2154+ resource_size(jz4740_udc->mem), pdev->name);
2155+
2156+ if (!jz4740_udc->mem) {
2157+ ret = -EBUSY;
2158+ dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2159+ goto err_device_unregister;
2160+ }
2161+
2162+ jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2163+
2164+ if (!jz4740_udc->base) {
2165+ ret = -EBUSY;
2166+ dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2167+ goto err_release_mem_region;
2168+ }
2169+
2170+ jz4740_udc->irq = platform_get_irq(pdev, 0);
2171+ ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2172+ jz4740_udc);
2173+ if (ret) {
2174+ dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2175+ goto err_iounmap;
2176+ }
2177+
2178+ udc_disable(jz4740_udc);
2179+ udc_reinit(jz4740_udc);
2180+
2181+ return 0;
2182+
2183+err_iounmap:
2184+ iounmap(jz4740_udc->base);
2185+err_release_mem_region:
2186+ release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2187+err_clk_put:
2188+ clk_put(jz4740_udc->clk);
2189+err_device_unregister:
2190+ device_unregister(&jz4740_udc->gadget.dev);
2191+ platform_set_drvdata(pdev, NULL);
2192+
2193+ return ret;
2194+}
2195+
2196+static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2197+{
2198+ struct jz4740_udc *dev = platform_get_drvdata(pdev);
2199+
2200+ if (dev->driver)
2201+ return -EBUSY;
2202+
2203+ udc_disable(dev);
2204+
2205+ free_irq(dev->irq, dev);
2206+ iounmap(dev->base);
2207+ release_mem_region(dev->mem->start, resource_size(dev->mem));
2208+ clk_put(dev->clk);
2209+
2210+ platform_set_drvdata(pdev, NULL);
2211+ device_unregister(&dev->gadget.dev);
2212+
2213+ return 0;
2214+}
2215+
2216+#ifdef CONFIG_PM
2217+
2218+static int jz4740_udc_suspend(struct device *dev)
2219+{
2220+ struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2221+
2222+ if (jz4740_udc->state == UDC_STATE_ENABLE)
2223+ udc_disable(jz4740_udc);
2224+
2225+ return 0;
2226+}
2227+
2228+static int jz4740_udc_resume(struct device *dev)
2229+{
2230+ struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2231+
2232+ if (jz4740_udc->state == UDC_STATE_ENABLE)
2233+ udc_enable(jz4740_udc);
2234+
2235+ return 0;
2236+}
2237+
2238+static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume);
2239+#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2240+
2241+#else
2242+#define JZ4740_UDC_PM_OPS NULL
2243+#endif
2244+
2245+static struct platform_driver udc_driver = {
2246+ .probe = jz4740_udc_probe,
2247+ .remove = __devexit_p(jz4740_udc_remove),
2248+ .driver = {
2249+ .name = "jz-udc",
2250+ .owner = THIS_MODULE,
2251+ .pm = JZ4740_UDC_PM_OPS,
2252+ },
2253+};
2254+
2255+/*-------------------------------------------------------------------------*/
2256+
2257+static int __init udc_init (void)
2258+{
2259+ return platform_driver_register(&udc_driver);
2260+}
2261+module_init(udc_init);
2262+
2263+static void __exit udc_exit (void)
2264+{
2265+ platform_driver_unregister(&udc_driver);
2266+}
2267+module_exit(udc_exit);
2268+
2269+MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2270+MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2271+MODULE_LICENSE("GPL");
2272diff --git a/drivers/usb/gadget/jz4740_udc.h b/drivers/usb/gadget/jz4740_udc.h
2273new file mode 100644
2274index 0000000..53fd1da
2275--- /dev/null
2276+++ b/drivers/usb/gadget/jz4740_udc.h
2277@@ -0,0 +1,101 @@
2278+/*
2279+ * linux/drivers/usb/gadget/jz4740_udc.h
2280+ *
2281+ * Ingenic JZ4740 on-chip high speed USB device controller
2282+ *
2283+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
2284+ * Author: <jlwei@ingenic.cn>
2285+ *
2286+ * This program is free software; you can redistribute it and/or modify
2287+ * it under the terms of the GNU General Public License as published by
2288+ * the Free Software Foundation; either version 2 of the License, or
2289+ * (at your option) any later version.
2290+ */
2291+
2292+#ifndef __USB_GADGET_JZ4740_H__
2293+#define __USB_GADGET_JZ4740_H__
2294+
2295+/*-------------------------------------------------------------------------*/
2296+
2297+// Max packet size
2298+#define EP0_MAXPACKETSIZE 64
2299+#define EPBULK_MAXPACKETSIZE 512
2300+#define EPINTR_MAXPACKETSIZE 64
2301+
2302+#define UDC_MAX_ENDPOINTS 4
2303+
2304+/*-------------------------------------------------------------------------*/
2305+
2306+enum ep_type {
2307+ ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2308+};
2309+
2310+struct jz4740_ep {
2311+ struct usb_ep ep;
2312+ struct jz4740_udc *dev;
2313+
2314+ const struct usb_endpoint_descriptor *desc;
2315+
2316+ uint8_t stopped;
2317+ uint8_t bEndpointAddress;
2318+ uint8_t bmAttributes;
2319+
2320+ enum ep_type type;
2321+ size_t fifo;
2322+ uint32_t csr;
2323+
2324+ uint32_t reg_addr;
2325+ struct list_head queue;
2326+};
2327+
2328+struct jz4740_request {
2329+ struct usb_request req;
2330+ struct list_head queue;
2331+};
2332+
2333+enum ep0state {
2334+ WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2335+ DATA_STATE_XMIT, /* data tx stage */
2336+ DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2337+ WAIT_FOR_OUT_STATUS, /* status stages */
2338+ DATA_STATE_RECV, /* data rx stage */
2339+};
2340+
2341+/* For function binding with UDC Disable - Added by River */
2342+typedef enum {
2343+ UDC_STATE_ENABLE = 0,
2344+ UDC_STATE_DISABLE,
2345+}udc_state_t;
2346+
2347+struct jz4740_udc {
2348+ struct usb_gadget gadget;
2349+ struct usb_gadget_driver *driver;
2350+ struct device *dev;
2351+ spinlock_t lock;
2352+ unsigned long lock_flags;
2353+
2354+ enum ep0state ep0state;
2355+ struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2356+
2357+ udc_state_t state;
2358+
2359+ struct resource *mem;
2360+ void __iomem *base;
2361+ int irq;
2362+
2363+ struct clk *clk;
2364+};
2365+
2366+#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2367+
2368+static inline bool ep_is_in(const struct jz4740_ep *ep)
2369+{
2370+ return (ep->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN;
2371+}
2372+
2373+static inline uint8_t ep_index(const struct jz4740_ep *ep)
2374+{
2375+ return ep->bEndpointAddress & 0xf;
2376+}
2377+
2378+#endif /* __USB_GADGET_JZ4740_H__ */
2379--
23801.7.4.1
2381
2382

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