Root/package/ltq-dsl/src/ifxmips_atm_amazon_se.c

1/******************************************************************************
2**
3** FILE NAME : ifxmips_atm_amazon_se.c
4** PROJECT : UEIP
5** MODULES : ATM
6**
7** DATE : 7 Jul 2009
8** AUTHOR : Xu Liang
9** DESCRIPTION : ATM driver common source file (core functions)
10** COPYRIGHT : Copyright (c) 2006
11** Infineon Technologies AG
12** Am Campeon 1-12, 85579 Neubiberg, Germany
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License as published by
16** the Free Software Foundation; either version 2 of the License, or
17** (at your option) any later version.
18**
19** HISTORY
20** $Date $Author $Comment
21** 07 JUL 2009 Xu Liang Init Version
22*******************************************************************************/
23
24
25
26/*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31
32/*
33 * Common Head File
34 */
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/version.h>
38#include <linux/types.h>
39#include <linux/errno.h>
40#include <linux/proc_fs.h>
41#include <linux/init.h>
42#include <linux/ioctl.h>
43#include <asm/delay.h>
44
45/*
46 * Chip Specific Head File
47 */
48#include <lantiq_soc.h>
49#include "ifxmips_compat.h"
50#include "ifxmips_atm_core.h"
51#include "ifxmips_atm_fw_amazon_se.h"
52
53
54
55/*
56 * ####################################
57 * Definition
58 * ####################################
59 */
60
61/*
62 * EMA Settings
63 */
64#define EMA_CMD_BUF_LEN 0x0040
65#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
66#define EMA_DATA_BUF_LEN 0x0100
67#define EMA_DATA_BASE_ADDR (0x00000B00 << 2)
68#define EMA_WRITE_BURST 0x2
69#define EMA_READ_BURST 0x2
70
71
72
73/*
74 * ####################################
75 * Declaration
76 * ####################################
77 */
78
79/*
80 * Hardware Init/Uninit Functions
81 */
82static inline void init_pmu(void);
83static inline void uninit_pmu(void);
84static inline void reset_ppe(void);
85static inline void init_ema(void);
86static inline void init_mailbox(void);
87static inline void init_atm_tc(void);
88static inline void clear_share_buffer(void);
89
90
91
92/*
93 * ####################################
94 * Local Variable
95 * ####################################
96 */
97
98
99
100/*
101 * ####################################
102 * Local Function
103 * ####################################
104 */
105
106static inline void init_pmu(void)
107{
108    //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
109    //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
110    PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
111    PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
112    PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
113    //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
114    PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
115    DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
116}
117
118static inline void uninit_pmu(void)
119{
120    PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
121    PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
122    PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
123    //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
124    PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
125    DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
126    //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
127}
128
129static inline void reset_ppe(void)
130{
131#ifdef MODULE
132/* unsigned int etop_cfg;
133    unsigned int etop_mdio_cfg;
134    unsigned int etop_ig_plen_ctrl;
135    unsigned int enet_mac_cfg;
136
137    etop_cfg = *IFX_PP32_ETOP_CFG;
138    etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
139    etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
140    enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
141
142    *IFX_PP32_ETOP_CFG = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001;
143
144    // reset PPE
145    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
146
147    *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
148    *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
149    *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
150    *IFX_PP32_ETOP_CFG = etop_cfg;*/
151#endif
152}
153
154static inline void init_ema(void)
155{
156    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
157    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
158    IFX_REG_W32(0x000000FF, EMA_IER);
159    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
160}
161
162static inline void init_mailbox(void)
163{
164    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
165    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
166    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
167    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
168}
169
170static inline void init_atm_tc(void)
171{
172    IFX_REG_W32(0x0000, DREG_AT_CTRL);
173    IFX_REG_W32(0x0000, DREG_AR_CTRL);
174    IFX_REG_W32(0x0, DREG_AT_IDLE0);
175    IFX_REG_W32(0x0, DREG_AT_IDLE1);
176    IFX_REG_W32(0x0, DREG_AR_IDLE0);
177    IFX_REG_W32(0x0, DREG_AR_IDLE1);
178    IFX_REG_W32(0x40, RFBI_CFG);
179    IFX_REG_W32(0x0700, SFSM_DBA0);
180    IFX_REG_W32(0x0818, SFSM_DBA1);
181    IFX_REG_W32(0x0930, SFSM_CBA0);
182    IFX_REG_W32(0x0944, SFSM_CBA1);
183    IFX_REG_W32(0x14014, SFSM_CFG0);
184    IFX_REG_W32(0x14014, SFSM_CFG1);
185    IFX_REG_W32(0x0958, FFSM_DBA0);
186    IFX_REG_W32(0x09AC, FFSM_DBA1);
187    IFX_REG_W32(0x10006, FFSM_CFG0);
188    IFX_REG_W32(0x10006, FFSM_CFG1);
189    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
190    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
191}
192
193static inline void clear_share_buffer(void)
194{
195    volatile u32 *p = SB_RAM0_ADDR(0);
196    unsigned int i;
197
198    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ )
199        IFX_REG_W32(0, p++);
200}
201
202/*
203 * Description:
204 * Download PPE firmware binary code.
205 * Input:
206 * src --- u32 *, binary code buffer
207 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
208 * Output:
209 * int --- IFX_SUCCESS: Success
210 * else: Error Code
211 */
212static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
213{
214    volatile u32 *dest;
215
216    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
217        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
218        return IFX_ERROR;
219
220    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
221        IFX_REG_W32(0x00, CDM_CFG);
222    else
223        IFX_REG_W32(0x04, CDM_CFG);
224
225    /* copy code */
226    dest = CDM_CODE_MEMORY(0, 0);
227    while ( code_dword_len-- > 0 )
228        IFX_REG_W32(*code_src++, dest++);
229
230    /* copy data */
231    dest = CDM_DATA_MEMORY(0, 0);
232    while ( data_dword_len-- > 0 )
233        IFX_REG_W32(*data_src++, dest++);
234
235    return IFX_SUCCESS;
236}
237
238
239
240/*
241 * ####################################
242 * Global Function
243 * ####################################
244 */
245
246extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
247{
248    ASSERT(major != NULL, "pointer is NULL");
249    ASSERT(minor != NULL, "pointer is NULL");
250
251#ifdef VER_IN_FIRMWARE
252    *major = FW_VER_ID->major;
253    *minor = FW_VER_ID->minor;
254#else
255    *major = ATM_FW_VER_MAJOR;
256    *minor = ATM_FW_VER_MINOR;
257#endif
258}
259
260void ifx_atm_init_chip(void)
261{
262    init_pmu();
263
264    reset_ppe();
265
266    init_ema();
267
268    init_mailbox();
269
270    init_atm_tc();
271
272    clear_share_buffer();
273}
274
275void ifx_atm_uninit_chip(void)
276{
277    uninit_pmu();
278}
279
280/*
281 * Description:
282 * Initialize and start up PP32.
283 * Input:
284 * none
285 * Output:
286 * int --- IFX_SUCCESS: Success
287 * else: Error Code
288 */
289int ifx_pp32_start(int pp32)
290{
291    int ret;
292
293    /* download firmware */
294    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
295    if ( ret != IFX_SUCCESS )
296        return ret;
297
298    /* run PP32 */
299    IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL);
300
301    /* idle for a while to let PP32 init itself */
302    udelay(10);
303
304    return IFX_SUCCESS;
305}
306
307/*
308 * Description:
309 * Halt PP32.
310 * Input:
311 * none
312 * Output:
313 * none
314 */
315void ifx_pp32_stop(int pp32)
316{
317    /* halt PP32 */
318    IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL);
319}
320

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