| 1 | /****************************************************************************** |
| 2 | ** |
| 3 | ** FILE NAME : ifxmips_atm_fw_regs_danube.h |
| 4 | ** PROJECT : UEIP |
| 5 | ** MODULES : ATM (ADSL) |
| 6 | ** |
| 7 | ** DATE : 1 AUG 2005 |
| 8 | ** AUTHOR : Xu Liang |
| 9 | ** DESCRIPTION : ATM Driver (Firmware Registers) |
| 10 | ** COPYRIGHT : Copyright (c) 2006 |
| 11 | ** Infineon Technologies AG |
| 12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
| 13 | ** |
| 14 | ** This program is free software; you can redistribute it and/or modify |
| 15 | ** it under the terms of the GNU General Public License as published by |
| 16 | ** the Free Software Foundation; either version 2 of the License, or |
| 17 | ** (at your option) any later version. |
| 18 | ** |
| 19 | ** HISTORY |
| 20 | ** $Date $Author $Comment |
| 21 | ** 4 AUG 2005 Xu Liang Initiate Version |
| 22 | ** 23 OCT 2006 Xu Liang Add GPL header. |
| 23 | ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer) |
| 24 | *******************************************************************************/ |
| 25 | |
| 26 | |
| 27 | |
| 28 | #ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H |
| 29 | #define IFXMIPS_ATM_FW_REGS_DANUBE_H |
| 30 | |
| 31 | |
| 32 | |
| 33 | /* |
| 34 | * Host-PPE Communication Data Address Mapping |
| 35 | */ |
| 36 | #define FW_VER_ID ((volatile struct fw_ver_id *) SB_BUFFER(0x2001)) |
| 37 | #define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */ |
| 38 | #define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */ |
| 39 | #define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */ |
| 40 | #define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */ |
| 41 | #define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */ |
| 42 | #define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */ |
| 43 | #define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */ |
| 44 | #define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */ |
| 45 | #define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20)) |
| 46 | #define WRX_QUEUE_CONTEXT(i) ((struct wrx_queue_context*) SB_BUFFER(0x2504 + (i) * 20)) |
| 47 | #define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7)) |
| 48 | #define WRX_DESC_CONTEXT(i) ((struct wrx_desc_context*) SB_BUFFER(0x2643 + (i) * 7)) |
| 49 | #define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i))) |
| 50 | #define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27)) |
| 51 | #define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27)) |
| 52 | #define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410)) |
| 53 | #if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX |
| 54 | #define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i))) |
| 55 | #define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i))) |
| 56 | #define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i))) |
| 57 | #else |
| 58 | #define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2020 + (i))) |
| 59 | #define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2040 + (i))) |
| 60 | #define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2060 + (i))) |
| 61 | #endif |
| 62 | |
| 63 | #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX |
| 64 | |
| 65 | #define RETX_MODE_CFG ((volatile struct Retx_mode_cfg *) SB_BUFFER(0x2408)) |
| 66 | #define RETX_TSYNC_CFG ((volatile struct Retx_Tsync_cfg *) SB_BUFFER(0x2409)) |
| 67 | #define RETX_TD_CFG ((volatile struct Retx_Td_cfg *) SB_BUFFER(0x240A)) |
| 68 | #define RETX_MIB_TIMER_CFG ((volatile struct Retx_MIB_Timer_cfg *) SB_BUFFER(0x240B)) |
| 69 | #define RETX_PLAYOUT_BUFFER_BASE SB_BUFFER(0x240D) |
| 70 | #define RETX_SERVICE_HEADER_CFG SB_BUFFER(0x240E) |
| 71 | #define RETX_MASK_HEADER_CFG SB_BUFFER(0x240F) |
| 72 | |
| 73 | #define RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) PPE_REG_ADDR(0x0D78)) |
| 74 | #define BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AC)) |
| 75 | #define FIRST_BAD_REC_RETX_ADSL_PPE_INTF ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AE)) |
| 76 | |
| 77 | #define PB_BUFFER_USAGE SB_BUFFER(0x2100) |
| 78 | #define DTU_STAT_INFO ((volatile struct DTU_stat_info *) SB_BUFFER(0x2180)) |
| 79 | #define DTU_VLD_STAT SB_BUFFER(0x2380) |
| 80 | |
| 81 | |
| 82 | //===================================================================== |
| 83 | // retx firmware mib, for debug purpose |
| 84 | // address : 0x2388 - 0x238F |
| 85 | // size : 8 |
| 86 | //===================================================================== |
| 87 | #define URETX_RX_TOTAL_DTU SB_BUFFER(0x2388) |
| 88 | #define URETX_RX_BAD_DTU SB_BUFFER(0x2389) |
| 89 | #define URETX_RX_GOOD_DTU SB_BUFFER(0x238A) |
| 90 | #define URETX_RX_CORRECTED_DTU SB_BUFFER(0x238B) |
| 91 | #define URETX_RX_OUTOFDATE_DTU SB_BUFFER(0x238C) |
| 92 | #define URETX_RX_DUPLICATE_DTU SB_BUFFER(0x238D) |
| 93 | #define URETX_RX_TIMEOUT_DTU SB_BUFFER(0x238E) |
| 94 | |
| 95 | #define URETX_ALPHA_SWITCH_TO_HUNT_TIMES SB_BUFFER(0x238F) |
| 96 | |
| 97 | // cell counter for debug purpose |
| 98 | #define WRX_BC0_CELL_NUM SB_BUFFER(0x23E0) |
| 99 | #define WRX_BC0_DROP_CELL_NUM SB_BUFFER(0x23E1) |
| 100 | #define WRX_BC0_NONRETX_CELL_NUM SB_BUFFER(0x23E2) |
| 101 | #define WRX_BC0_RETX_CELL_NUM SB_BUFFER(0x23E3) |
| 102 | #define WRX_BC0_OUTOFDATE_CELL_NUM SB_BUFFER(0x23E4) |
| 103 | #define WRX_BC0_DIRECTUP_NUM SB_BUFFER(0x23E5) |
| 104 | #define WRX_BC0_PBW_TOTAL_NUM SB_BUFFER(0x23E6) |
| 105 | #define WRX_BC0_PBW_SUCC_NUM SB_BUFFER(0x23E7) |
| 106 | #define WRX_BC0_PBW_FAIL_NUM SB_BUFFER(0x23E8) |
| 107 | #define WRX_BC1_CELL_NUM SB_BUFFER(0x23E9) |
| 108 | |
| 109 | // debug info (interface) |
| 110 | |
| 111 | #define DBG_DTU_INTF_WRPTR SB_BUFFER(0x2390) |
| 112 | #define DBG_INTF_FCW_DUP_CNT SB_BUFFER(0x2391) |
| 113 | #define DBG_INTF_SID_CHANGE_IN_DTU_CNT SB_BUFFER(0x2392) |
| 114 | #define DBG_INTF_LCW_DUP_CNT SB_BUFFER(0x2393) |
| 115 | |
| 116 | #define DBG_RFBI_DONE_INT_CNT SB_BUFFER(0x2394) |
| 117 | #define DBG_DREG_BEG_END SB_BUFFER(0x2395) |
| 118 | #define DBG_RFBI_BC0_INVALID_CNT SB_BUFFER(0x2396) |
| 119 | #define DBG_RFBI_LAST_T SB_BUFFER(0x2397) |
| 120 | |
| 121 | #define DBG_RFBI_INTV0 SB_BUFFER(0x23EE) |
| 122 | #define DBG_RFBI_INTV1 SB_BUFFER(0x23EF) |
| 123 | |
| 124 | #define DBG_INTF_INFO(i) ((volatile struct Retx_adsl_ppe_intf_rec *) SB_BUFFER(0x23F0 + i)) |
| 125 | |
| 126 | // Internal status |
| 127 | #define URetx_curr_time SB_BUFFER(0x2398) |
| 128 | #define URetx_sec_counter SB_BUFFER(0x2399) |
| 129 | #define RxCURR_EFB SB_BUFFER(0x239A) |
| 130 | #define RxDTURetransmittedCNT SB_BUFFER(0x239B) |
| 131 | |
| 132 | //===================================================================== |
| 133 | // standardized MIB counter |
| 134 | // address : 0x239C - 0x239F |
| 135 | // size : 4 |
| 136 | //===================================================================== |
| 137 | #define RxLastEFBCNT SB_BUFFER(0x239C) |
| 138 | #define RxDTUCorrectedCNT SB_BUFFER(0x239D) |
| 139 | #define RxDTUCorruptedCNT SB_BUFFER(0x239E) |
| 140 | #define RxRetxDTUUncorrectedCNT SB_BUFFER(0x239F) |
| 141 | |
| 142 | |
| 143 | //===================================================================== |
| 144 | // General URetx Context |
| 145 | // address : 0x23A0 - 0x23AF |
| 146 | // size : 16 |
| 147 | //===================================================================== |
| 148 | #define NEXT_DTU_SID_OUT SB_BUFFER(0x23A0) |
| 149 | #define LAST_DTU_SID_IN SB_BUFFER(0x23A1) |
| 150 | #define NEXT_CELL_SID_OUT SB_BUFFER(0x23A2) |
| 151 | #define ISR_CELL_ID SB_BUFFER(0x23A3) |
| 152 | #define PB_CELL_SEARCH_IDX SB_BUFFER(0x23A4) |
| 153 | #define PB_READ_PEND_FLAG SB_BUFFER(0x23A5) |
| 154 | #define RFBI_FIRST_CW SB_BUFFER(0x23A6) |
| 155 | #define RFBI_BAD_CW SB_BUFFER(0x23A7) |
| 156 | #define RFBI_INVALID_CW SB_BUFFER(0x23A8) |
| 157 | #define RFBI_RETX_CW SB_BUFFER(0x23A9) |
| 158 | #define RFBI_CHK_DTU_STATUS SB_BUFFER(0x23AA) |
| 159 | |
| 160 | //===================================================================== |
| 161 | // per PVC counter for RX error_pdu and correct_pdu |
| 162 | // address : 0x23B0 - 0x23CF |
| 163 | // size : 32 |
| 164 | //===================================================================== |
| 165 | #define WRX_PER_PVC_CORRECT_PDU_BASE SB_BUFFER(0x23B0) |
| 166 | #define WRX_PER_PVC_ERROR_PDU_BASE SB_BUFFER(0x23C0) |
| 167 | |
| 168 | #define __WRXCTXT_L2_RdPtr(i) SB_BUFFER(0x2422 + (i)) |
| 169 | #define __WRXCTXT_L2Pages(i) SB_BUFFER(0x2424 + (i)) |
| 170 | |
| 171 | #define __WTXCTXT_TC_WRPTR(i) SB_BUFFER(0x2450 + (i)) |
| 172 | #define __WRXCTXT_PortState(i) SB_BUFFER(0x242A + (i)) |
| 173 | |
| 174 | #endif |
| 175 | |
| 176 | |
| 177 | |
| 178 | #endif // IFXMIPS_ATM_FW_REGS_DANUBE_H |
| 179 | |
