| 1 | /* |
| 2 | * (C) Copyright 2003-2005 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * This file contains the configuration parameters for the Danube reference board. |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | #define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */ |
| 32 | #define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */ |
| 33 | #define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */ |
| 34 | |
| 35 | #define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */ |
| 36 | |
| 37 | #define CONFIG_USE_DDR_RAM |
| 38 | |
| 39 | #define CONFIG_FLASH_CFI_DRIVER 1 |
| 40 | |
| 41 | #define CONFIG_SYS_INIT_RAM_LOCK_MIPS |
| 42 | |
| 43 | #ifdef CONFIG_SYS_RAMBOOT |
| 44 | //#warning CONFIG_SYS_RAMBOOT |
| 45 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 46 | #else /* CONFIG_SYS_RAMBOOT */ |
| 47 | #define CONFIG_SYS_EBU_BOOT |
| 48 | #define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */ |
| 49 | #endif /* CONFIG_SYS_RAMBOOT */ |
| 50 | |
| 51 | #if 1 |
| 52 | #ifndef CPU_CLOCK_RATE |
| 53 | #define CPU_CLOCK_RATE (ifx_get_cpuclk()) |
| 54 | #endif |
| 55 | #endif |
| 56 | |
| 57 | #undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ |
| 58 | |
| 59 | /* |
| 60 | * Include common defines/options for all Infineon boards |
| 61 | */ |
| 62 | #include "ifx-common.h" |
| 63 | |
| 64 | |
| 65 | #undef CONFIG_EXTRA_ENV_SETTINGS |
| 66 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 67 | "ram_addr=0x80500000\0" \ |
| 68 | "kernel_addr=0xb0020000\0" \ |
| 69 | "flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \ |
| 70 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 71 | "nfsroot=${serverip}:${rootpath} \0" \ |
| 72 | "addip=setenv bootargs ${bootargs} " \ |
| 73 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 74 | ":${hostname}:${netdev}:off\0" \ |
| 75 | "addmisc=setenv bootargs ${bootargs} init=/etc/preinit " \ |
| 76 | "console=ttyS1,115200 ethaddr=${ethaddr} " \ |
| 77 | "${mtdparts}\0" \ |
| 78 | "flash_flash=run flashargs addip addmisc;" \ |
| 79 | "bootm ${kernel_addr}\0" \ |
| 80 | "flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \ |
| 81 | "net_flash=run load_kernel flashargs addip addmisc;" \ |
| 82 | "bootm ${ram_addr}\0" \ |
| 83 | "net_nfs=run load_kernel nfsargs addip addmisc;" \ |
| 84 | "bootm ${ram_addr}\0" \ |
| 85 | "load_kernel=tftp ${ram_addr} " \ |
| 86 | "${tftppath}openwrt-ifxmips-uImage\0" \ |
| 87 | "update_uboot=tftp 0x80500000 ${tftppath}u-boot-" CONFIG_ARCADYAN ".bin;era 0xb0000000 +${filesize};" \ |
| 88 | "cp.b 0x80500000 0xb0000000 ${filesize}\0" \ |
| 89 | "update_openwrt=tftp ${ram_addr} " \ |
| 90 | "${tftppath}" CONFIG_ARCADYAN "-squashfs.image;" \ |
| 91 | "era ${kernel_addr} +${filesize};" \ |
| 92 | "cp.b ${ram_addr} ${kernel_addr} ${filesize}\0" |
| 93 | |
| 94 | /* |
| 95 | * Cache Configuration (cpu/chip specific, Danube) |
| 96 | */ |
| 97 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
| 98 | #define CONFIG_SYS_ICACHE_SIZE 16384 |
| 99 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
| 100 | #define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA |
| 101 | |
| 102 | #define CONFIG_NET_MULTI |
| 103 | |
| 104 | #define CONFIG_IFX_ETOP |
| 105 | //#define CLK_OUT2_25MHZ |
| 106 | |
| 107 | #define CONFIG_MII |
| 108 | #undef CONFIG_CMD_MII |
| 109 | |
| 110 | #define CONFIG_IFX_ASC |
| 111 | |
| 112 | #ifdef CONFIG_USE_ASC0 |
| 113 | #define CONFIG_SYS_IFX_ASC_BASE 0x1E100400 |
| 114 | #else |
| 115 | #define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00 |
| 116 | #endif |
| 117 | |
| 118 | #ifdef CONFIG_SYS_RAMBOOT |
| 119 | /* Configuration of EBU: */ |
| 120 | /* starting address from 0xb0000000 */ |
| 121 | /* make the flash available from RAM boot */ |
| 122 | # define CONFIG_EBU_ADDSEL0 0x10000031 |
| 123 | # define CONFIG_EBU_BUSCON0 0x0001D7FF |
| 124 | # define CONFIG_EBU_ADDSEL1 0x14000001 |
| 125 | # define CONFIG_EBU_BUSCON1 0x4041D7FD |
| 126 | #endif |
| 127 | |
| 128 | #define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */ |
| 129 | |
| 130 | #define CONFIG_IPADDR 192.168.1.1 |
| 131 | #define CONFIG_SERVERIP 192.168.1.101 |
| 132 | #define CONFIG_GATEWAYIP 192.168.1.254 |
| 133 | #define CONFIG_NETMASK 255.255.255.0 |
| 134 | #define CONFIG_ROOTPATH "/export" |
| 135 | |
| 136 | #ifdef CONFIG_BOOTSTRAP |
| 137 | #define CONFIG_BOOTSTRAP_BASE CONFIG_BOOTSTRAP_TEXT_BASE |
| 138 | #define CONFIG_BOOTSTRAP_BAUDRATE CONFIG_BAUDRATE |
| 139 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 140 | #define CONFIG_BOOTSTRAP_LZMA |
| 141 | //#define CONFIG_BOOTSTRAP_SERIAL |
| 142 | #endif |
| 143 | |
| 144 | |
| 145 | |
| 146 | #endif /* __CONFIG_H */ |
| 147 | |
