| 1 | --- a/drivers/net/cpmac.c |
| 2 | +++ b/drivers/net/cpmac.c |
| 3 | @@ -1155,6 +1155,8 @@ static int __devinit cpmac_probe(struct |
| 4 | goto fail; |
| 5 | } |
| 6 | |
| 7 | + ar7_device_reset(pdata->reset_bit); |
| 8 | + |
| 9 | dev->irq = platform_get_irq_byname(pdev, "irq"); |
| 10 | |
| 11 | dev->netdev_ops = &cpmac_netdev_ops; |
| 12 | @@ -1231,7 +1233,7 @@ int __devinit cpmac_init(void) |
| 13 | cpmac_mii->reset = cpmac_mdio_reset; |
| 14 | cpmac_mii->irq = mii_irqs; |
| 15 | |
| 16 | - cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256); |
| 17 | + cpmac_mii->priv = ioremap(ar7_is_titan() ? TITAN_REGS_MDIO : AR7_REGS_MDIO, 256); |
| 18 | |
| 19 | if (!cpmac_mii->priv) { |
| 20 | printk(KERN_ERR "Can't ioremap mdio registers\n"); |
| 21 | @@ -1242,10 +1244,16 @@ int __devinit cpmac_init(void) |
| 22 | #warning FIXME: unhardcode gpio&reset bits |
| 23 | ar7_gpio_disable(26); |
| 24 | ar7_gpio_disable(27); |
| 25 | - ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); |
| 26 | - ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); |
| 27 | + |
| 28 | + if (!ar7_is_titan()) { |
| 29 | + ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); |
| 30 | + ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); |
| 31 | + } |
| 32 | ar7_device_reset(AR7_RESET_BIT_EPHY); |
| 33 | |
| 34 | + if (ar7_is_titan()) |
| 35 | + ar7_device_reset(TITAN_RESET_BIT_EPHY1); |
| 36 | + |
| 37 | cpmac_mii->reset(cpmac_mii); |
| 38 | |
| 39 | for (i = 0; i < 300; i++) |
| 40 | @@ -1260,7 +1268,8 @@ int __devinit cpmac_init(void) |
| 41 | mask = 0; |
| 42 | } |
| 43 | |
| 44 | - cpmac_mii->phy_mask = ~(mask | 0x80000000); |
| 45 | + cpmac_mii->phy_mask = ar7_is_titan()? ~(mask | 0x80000000 | 0x40000000) : |
| 46 | + ~(mask | 0x80000000); |
| 47 | snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1"); |
| 48 | |
| 49 | res = mdiobus_register(cpmac_mii); |
| 50 | |
