Root/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c

1/*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/etherdevice.h>
20#include <linux/platform_device.h>
21#include <linux/serial_8250.h>
22
23#include <asm/mach-ath79/ath79.h>
24#include <asm/mach-ath79/ar71xx_regs.h>
25#include <asm/mach-ath79/irq.h>
26
27#include "common.h"
28#include "dev-eth.h"
29
30unsigned char ath79_mac_base[ETH_ALEN] __initdata;
31
32static struct resource ath79_mdio0_resources[] = {
33    {
34        .name = "mdio_base",
35        .flags = IORESOURCE_MEM,
36        .start = AR71XX_GE0_BASE,
37        .end = AR71XX_GE0_BASE + 0x200 - 1,
38    }
39};
40
41static struct ag71xx_mdio_platform_data ath79_mdio0_data;
42
43struct platform_device ath79_mdio0_device = {
44    .name = "ag71xx-mdio",
45    .id = 0,
46    .resource = ath79_mdio0_resources,
47    .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
48    .dev = {
49        .platform_data = &ath79_mdio0_data,
50    },
51};
52
53static struct resource ath79_mdio1_resources[] = {
54    {
55        .name = "mdio_base",
56        .flags = IORESOURCE_MEM,
57        .start = AR71XX_GE1_BASE,
58        .end = AR71XX_GE1_BASE + 0x200 - 1,
59    }
60};
61
62static struct ag71xx_mdio_platform_data ath79_mdio1_data;
63
64struct platform_device ath79_mdio1_device = {
65    .name = "ag71xx-mdio",
66    .id = 1,
67    .resource = ath79_mdio1_resources,
68    .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
69    .dev = {
70        .platform_data = &ath79_mdio1_data,
71    },
72};
73
74static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
75{
76    void __iomem *base;
77    u32 t;
78
79    base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
80
81    t = __raw_readl(base + cfg_reg);
82    t &= ~(3 << shift);
83    t |= (2 << shift);
84    __raw_writel(t, base + cfg_reg);
85    udelay(100);
86
87    __raw_writel(pll_val, base + pll_reg);
88
89    t |= (3 << shift);
90    __raw_writel(t, base + cfg_reg);
91    udelay(100);
92
93    t &= ~(3 << shift);
94    __raw_writel(t, base + cfg_reg);
95    udelay(100);
96
97    printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98        (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
99
100    iounmap(base);
101}
102
103static void __init ath79_mii_ctrl_set_if(unsigned int reg,
104                      unsigned int mii_if)
105{
106    void __iomem *base;
107    u32 t;
108
109    base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
110
111    t = __raw_readl(base + reg);
112    t &= ~(AR71XX_MII_CTRL_IF_MASK);
113    t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114    __raw_writel(t, base + reg);
115
116    iounmap(base);
117}
118
119static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
120{
121    void __iomem *base;
122    unsigned int mii_speed;
123    u32 t;
124
125    switch (speed) {
126    case SPEED_10:
127        mii_speed = AR71XX_MII_CTRL_SPEED_10;
128        break;
129    case SPEED_100:
130        mii_speed = AR71XX_MII_CTRL_SPEED_100;
131        break;
132    case SPEED_1000:
133        mii_speed = AR71XX_MII_CTRL_SPEED_1000;
134        break;
135    default:
136        BUG();
137    }
138
139    base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
140
141    t = __raw_readl(base + reg);
142    t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143    t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144    __raw_writel(t, base + reg);
145
146    iounmap(base);
147}
148
149void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
150{
151    struct platform_device *mdio_dev;
152    struct ag71xx_mdio_platform_data *mdio_data;
153    unsigned int max_id;
154
155    if (ath79_soc == ATH79_SOC_AR9341 ||
156        ath79_soc == ATH79_SOC_AR9342 ||
157        ath79_soc == ATH79_SOC_AR9344)
158        max_id = 1;
159    else
160        max_id = 0;
161
162    if (id > max_id) {
163        printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
164        return;
165    }
166
167    switch (ath79_soc) {
168    case ATH79_SOC_AR7241:
169    case ATH79_SOC_AR9330:
170    case ATH79_SOC_AR9331:
171        mdio_dev = &ath79_mdio1_device;
172        mdio_data = &ath79_mdio1_data;
173        break;
174
175    case ATH79_SOC_AR9341:
176    case ATH79_SOC_AR9342:
177    case ATH79_SOC_AR9344:
178        if (id == 0) {
179            mdio_dev = &ath79_mdio0_device;
180            mdio_data = &ath79_mdio0_data;
181        } else {
182            mdio_dev = &ath79_mdio1_device;
183            mdio_data = &ath79_mdio1_data;
184        }
185        break;
186
187    case ATH79_SOC_AR7242:
188        ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189                   AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190                   AR71XX_ETH0_PLL_SHIFT);
191        /* fall through */
192    default:
193        mdio_dev = &ath79_mdio0_device;
194        mdio_data = &ath79_mdio0_data;
195        break;
196    }
197
198    mdio_data->phy_mask = phy_mask;
199
200    switch (ath79_soc) {
201    case ATH79_SOC_AR7240:
202    case ATH79_SOC_AR7241:
203    case ATH79_SOC_AR9330:
204    case ATH79_SOC_AR9331:
205        mdio_data->is_ar7240 = 1;
206        break;
207
208    case ATH79_SOC_AR9341:
209    case ATH79_SOC_AR9342:
210    case ATH79_SOC_AR9344:
211        if (id == 1)
212            mdio_data->is_ar7240 = 1;
213        break;
214
215    default:
216        break;
217    }
218
219    platform_device_register(mdio_dev);
220}
221
222struct ath79_eth_pll_data ath79_eth0_pll_data;
223struct ath79_eth_pll_data ath79_eth1_pll_data;
224
225static u32 ath79_get_eth_pll(unsigned int mac, int speed)
226{
227    struct ath79_eth_pll_data *pll_data;
228    u32 pll_val;
229
230    switch (mac) {
231    case 0:
232        pll_data = &ath79_eth0_pll_data;
233        break;
234    case 1:
235        pll_data = &ath79_eth1_pll_data;
236        break;
237    default:
238        BUG();
239    }
240
241    switch (speed) {
242    case SPEED_10:
243        pll_val = pll_data->pll_10;
244        break;
245    case SPEED_100:
246        pll_val = pll_data->pll_100;
247        break;
248    case SPEED_1000:
249        pll_val = pll_data->pll_1000;
250        break;
251    default:
252        BUG();
253    }
254
255    return pll_val;
256}
257
258static void ath79_set_speed_ge0(int speed)
259{
260    u32 val = ath79_get_eth_pll(0, speed);
261
262    ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
263            val, AR71XX_ETH0_PLL_SHIFT);
264    ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
265}
266
267static void ath79_set_speed_ge1(int speed)
268{
269    u32 val = ath79_get_eth_pll(1, speed);
270
271    ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
272             val, AR71XX_ETH1_PLL_SHIFT);
273    ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
274}
275
276static void ar724x_set_speed_ge0(int speed)
277{
278    /* TODO */
279}
280
281static void ar724x_set_speed_ge1(int speed)
282{
283    /* TODO */
284}
285
286static void ar7242_set_speed_ge0(int speed)
287{
288    u32 val = ath79_get_eth_pll(0, speed);
289    void __iomem *base;
290
291    base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
292    __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
293    iounmap(base);
294}
295
296static void ar91xx_set_speed_ge0(int speed)
297{
298    u32 val = ath79_get_eth_pll(0, speed);
299
300    ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
301             val, AR913X_ETH0_PLL_SHIFT);
302    ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
303}
304
305static void ar91xx_set_speed_ge1(int speed)
306{
307    u32 val = ath79_get_eth_pll(1, speed);
308
309    ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
310             val, AR913X_ETH1_PLL_SHIFT);
311    ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
312}
313
314static void ar933x_set_speed_ge0(int speed)
315{
316    /* TODO */
317}
318
319static void ar933x_set_speed_ge1(int speed)
320{
321    /* TODO */
322}
323
324static void ar934x_set_speed_ge0(int speed)
325{
326    /* TODO */
327}
328
329static void ar934x_set_speed_ge1(int speed)
330{
331    /* TODO */
332}
333
334static void ath79_ddr_flush_ge0(void)
335{
336    ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
337}
338
339static void ath79_ddr_flush_ge1(void)
340{
341    ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
342}
343
344static void ar724x_ddr_flush_ge0(void)
345{
346    ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
347}
348
349static void ar724x_ddr_flush_ge1(void)
350{
351    ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
352}
353
354static void ar91xx_ddr_flush_ge0(void)
355{
356    ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
357}
358
359static void ar91xx_ddr_flush_ge1(void)
360{
361    ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
362}
363
364static void ar933x_ddr_flush_ge0(void)
365{
366    ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
367}
368
369static void ar933x_ddr_flush_ge1(void)
370{
371    ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
372}
373
374static void ar934x_ddr_flush_ge0(void)
375{
376    ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE0);
377}
378
379static void ar934x_ddr_flush_ge1(void)
380{
381    ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE1);
382}
383
384static struct resource ath79_eth0_resources[] = {
385    {
386        .name = "mac_base",
387        .flags = IORESOURCE_MEM,
388        .start = AR71XX_GE0_BASE,
389        .end = AR71XX_GE0_BASE + 0x200 - 1,
390    }, {
391        .name = "mac_irq",
392        .flags = IORESOURCE_IRQ,
393        .start = ATH79_CPU_IRQ_GE0,
394        .end = ATH79_CPU_IRQ_GE0,
395    },
396};
397
398struct ag71xx_platform_data ath79_eth0_data = {
399    .reset_bit = AR71XX_RESET_GE0_MAC,
400};
401
402struct platform_device ath79_eth0_device = {
403    .name = "ag71xx",
404    .id = 0,
405    .resource = ath79_eth0_resources,
406    .num_resources = ARRAY_SIZE(ath79_eth0_resources),
407    .dev = {
408        .platform_data = &ath79_eth0_data,
409    },
410};
411
412static struct resource ath79_eth1_resources[] = {
413    {
414        .name = "mac_base",
415        .flags = IORESOURCE_MEM,
416        .start = AR71XX_GE1_BASE,
417        .end = AR71XX_GE1_BASE + 0x200 - 1,
418    }, {
419        .name = "mac_irq",
420        .flags = IORESOURCE_IRQ,
421        .start = ATH79_CPU_IRQ_GE1,
422        .end = ATH79_CPU_IRQ_GE1,
423    },
424};
425
426struct ag71xx_platform_data ath79_eth1_data = {
427    .reset_bit = AR71XX_RESET_GE1_MAC,
428};
429
430struct platform_device ath79_eth1_device = {
431    .name = "ag71xx",
432    .id = 1,
433    .resource = ath79_eth1_resources,
434    .num_resources = ARRAY_SIZE(ath79_eth1_resources),
435    .dev = {
436        .platform_data = &ath79_eth1_data,
437    },
438};
439
440struct ag71xx_switch_platform_data ath79_switch_data;
441
442#define AR71XX_PLL_VAL_1000 0x00110000
443#define AR71XX_PLL_VAL_100 0x00001099
444#define AR71XX_PLL_VAL_10 0x00991099
445
446#define AR724X_PLL_VAL_1000 0x00110000
447#define AR724X_PLL_VAL_100 0x00001099
448#define AR724X_PLL_VAL_10 0x00991099
449
450#define AR7242_PLL_VAL_1000 0x16000000
451#define AR7242_PLL_VAL_100 0x00000101
452#define AR7242_PLL_VAL_10 0x00001616
453
454#define AR913X_PLL_VAL_1000 0x1a000000
455#define AR913X_PLL_VAL_100 0x13000a44
456#define AR913X_PLL_VAL_10 0x00441099
457
458#define AR933X_PLL_VAL_1000 0x00110000
459#define AR933X_PLL_VAL_100 0x00001099
460#define AR933X_PLL_VAL_10 0x00991099
461
462#define AR934X_PLL_VAL_1000 0x00110000
463#define AR934X_PLL_VAL_100 0x00001099
464#define AR934X_PLL_VAL_10 0x00991099
465
466static void __init ath79_init_eth_pll_data(unsigned int id)
467{
468    struct ath79_eth_pll_data *pll_data;
469    u32 pll_10, pll_100, pll_1000;
470
471    switch (id) {
472    case 0:
473        pll_data = &ath79_eth0_pll_data;
474        break;
475    case 1:
476        pll_data = &ath79_eth1_pll_data;
477        break;
478    default:
479        BUG();
480    }
481
482    switch (ath79_soc) {
483    case ATH79_SOC_AR7130:
484    case ATH79_SOC_AR7141:
485    case ATH79_SOC_AR7161:
486        pll_10 = AR71XX_PLL_VAL_10;
487        pll_100 = AR71XX_PLL_VAL_100;
488        pll_1000 = AR71XX_PLL_VAL_1000;
489        break;
490
491    case ATH79_SOC_AR7240:
492    case ATH79_SOC_AR7241:
493        pll_10 = AR724X_PLL_VAL_10;
494        pll_100 = AR724X_PLL_VAL_100;
495        pll_1000 = AR724X_PLL_VAL_1000;
496        break;
497
498    case ATH79_SOC_AR7242:
499        pll_10 = AR7242_PLL_VAL_10;
500        pll_100 = AR7242_PLL_VAL_100;
501        pll_1000 = AR7242_PLL_VAL_1000;
502        break;
503
504    case ATH79_SOC_AR9130:
505    case ATH79_SOC_AR9132:
506        pll_10 = AR913X_PLL_VAL_10;
507        pll_100 = AR913X_PLL_VAL_100;
508        pll_1000 = AR913X_PLL_VAL_1000;
509        break;
510
511    case ATH79_SOC_AR9330:
512    case ATH79_SOC_AR9331:
513        pll_10 = AR933X_PLL_VAL_10;
514        pll_100 = AR933X_PLL_VAL_100;
515        pll_1000 = AR933X_PLL_VAL_1000;
516        break;
517
518    case ATH79_SOC_AR9341:
519    case ATH79_SOC_AR9342:
520    case ATH79_SOC_AR9344:
521        pll_10 = AR934X_PLL_VAL_10;
522        pll_100 = AR934X_PLL_VAL_100;
523        pll_1000 = AR934X_PLL_VAL_1000;
524        break;
525
526    default:
527        BUG();
528    }
529
530    if (!pll_data->pll_10)
531        pll_data->pll_10 = pll_10;
532
533    if (!pll_data->pll_100)
534        pll_data->pll_100 = pll_100;
535
536    if (!pll_data->pll_1000)
537        pll_data->pll_1000 = pll_1000;
538}
539
540static int __init ath79_setup_phy_if_mode(unsigned int id,
541                       struct ag71xx_platform_data *pdata)
542{
543    unsigned int mii_if;
544
545    switch (id) {
546    case 0:
547        switch (ath79_soc) {
548        case ATH79_SOC_AR7130:
549        case ATH79_SOC_AR7141:
550        case ATH79_SOC_AR7161:
551        case ATH79_SOC_AR9130:
552        case ATH79_SOC_AR9132:
553            switch (pdata->phy_if_mode) {
554            case PHY_INTERFACE_MODE_MII:
555                mii_if = AR71XX_MII0_CTRL_IF_MII;
556                break;
557            case PHY_INTERFACE_MODE_GMII:
558                mii_if = AR71XX_MII0_CTRL_IF_GMII;
559                break;
560            case PHY_INTERFACE_MODE_RGMII:
561                mii_if = AR71XX_MII0_CTRL_IF_RGMII;
562                break;
563            case PHY_INTERFACE_MODE_RMII:
564                mii_if = AR71XX_MII0_CTRL_IF_RMII;
565                break;
566            default:
567                return -EINVAL;
568            }
569            ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
570            break;
571
572        case ATH79_SOC_AR7240:
573        case ATH79_SOC_AR7241:
574        case ATH79_SOC_AR9330:
575        case ATH79_SOC_AR9331:
576            pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
577            break;
578
579        case ATH79_SOC_AR7242:
580            /* FIXME */
581
582        case ATH79_SOC_AR9341:
583        case ATH79_SOC_AR9342:
584        case ATH79_SOC_AR9344:
585            switch (pdata->phy_if_mode) {
586            case PHY_INTERFACE_MODE_MII:
587            case PHY_INTERFACE_MODE_GMII:
588            case PHY_INTERFACE_MODE_RGMII:
589            case PHY_INTERFACE_MODE_RMII:
590                break;
591            default:
592                return -EINVAL;
593            }
594            break;
595
596        default:
597            BUG();
598        }
599        break;
600    case 1:
601        switch (ath79_soc) {
602        case ATH79_SOC_AR7130:
603        case ATH79_SOC_AR7141:
604        case ATH79_SOC_AR7161:
605        case ATH79_SOC_AR9130:
606        case ATH79_SOC_AR9132:
607            switch (pdata->phy_if_mode) {
608            case PHY_INTERFACE_MODE_RMII:
609                mii_if = AR71XX_MII1_CTRL_IF_RMII;
610                break;
611            case PHY_INTERFACE_MODE_RGMII:
612                mii_if = AR71XX_MII1_CTRL_IF_RGMII;
613                break;
614            default:
615                return -EINVAL;
616            }
617            ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
618            break;
619
620        case ATH79_SOC_AR7240:
621        case ATH79_SOC_AR7241:
622        case ATH79_SOC_AR9330:
623        case ATH79_SOC_AR9331:
624            pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
625            break;
626
627        case ATH79_SOC_AR7242:
628            /* FIXME */
629
630        case ATH79_SOC_AR9341:
631        case ATH79_SOC_AR9342:
632        case ATH79_SOC_AR9344:
633            switch (pdata->phy_if_mode) {
634            case PHY_INTERFACE_MODE_MII:
635            case PHY_INTERFACE_MODE_GMII:
636                break;
637            default:
638                return -EINVAL;
639            }
640            break;
641
642        default:
643            BUG();
644        }
645        break;
646    }
647
648    return 0;
649}
650
651static int ath79_eth_instance __initdata;
652void __init ath79_register_eth(unsigned int id)
653{
654    struct platform_device *pdev;
655    struct ag71xx_platform_data *pdata;
656    int err;
657
658    if (id > 1) {
659        printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
660        return;
661    }
662
663    ath79_init_eth_pll_data(id);
664
665    if (id == 0)
666        pdev = &ath79_eth0_device;
667    else
668        pdev = &ath79_eth1_device;
669
670    pdata = pdev->dev.platform_data;
671
672    err = ath79_setup_phy_if_mode(id, pdata);
673    if (err) {
674        printk(KERN_ERR
675               "ar71xx: invalid PHY interface mode for GE%u\n", id);
676        return;
677    }
678
679    switch (ath79_soc) {
680    case ATH79_SOC_AR7130:
681        if (id == 0) {
682            pdata->ddr_flush = ath79_ddr_flush_ge0;
683            pdata->set_speed = ath79_set_speed_ge0;
684        } else {
685            pdata->ddr_flush = ath79_ddr_flush_ge1;
686            pdata->set_speed = ath79_set_speed_ge1;
687        }
688        break;
689
690    case ATH79_SOC_AR7141:
691    case ATH79_SOC_AR7161:
692        if (id == 0) {
693            pdata->ddr_flush = ath79_ddr_flush_ge0;
694            pdata->set_speed = ath79_set_speed_ge0;
695        } else {
696            pdata->ddr_flush = ath79_ddr_flush_ge1;
697            pdata->set_speed = ath79_set_speed_ge1;
698        }
699        pdata->has_gbit = 1;
700        break;
701
702    case ATH79_SOC_AR7242:
703        if (id == 0) {
704            pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
705                        AR71XX_RESET_GE0_PHY;
706            pdata->ddr_flush = ar724x_ddr_flush_ge0;
707            pdata->set_speed = ar7242_set_speed_ge0;
708        } else {
709            pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
710                        AR71XX_RESET_GE1_PHY;
711            pdata->ddr_flush = ar724x_ddr_flush_ge1;
712            pdata->set_speed = ar724x_set_speed_ge1;
713        }
714        pdata->has_gbit = 1;
715        pdata->is_ar724x = 1;
716
717        if (!pdata->fifo_cfg1)
718            pdata->fifo_cfg1 = 0x0010ffff;
719        if (!pdata->fifo_cfg2)
720            pdata->fifo_cfg2 = 0x015500aa;
721        if (!pdata->fifo_cfg3)
722            pdata->fifo_cfg3 = 0x01f00140;
723        break;
724
725    case ATH79_SOC_AR7241:
726        if (id == 0)
727            pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
728        else
729            pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
730        /* fall through */
731    case ATH79_SOC_AR7240:
732        if (id == 0) {
733            pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
734            pdata->ddr_flush = ar724x_ddr_flush_ge0;
735            pdata->set_speed = ar724x_set_speed_ge0;
736
737            pdata->phy_mask = BIT(4);
738        } else {
739            pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
740            pdata->ddr_flush = ar724x_ddr_flush_ge1;
741            pdata->set_speed = ar724x_set_speed_ge1;
742
743            pdata->speed = SPEED_1000;
744            pdata->duplex = DUPLEX_FULL;
745            pdata->switch_data = &ath79_switch_data;
746        }
747        pdata->has_gbit = 1;
748        pdata->is_ar724x = 1;
749        if (ath79_soc == ATH79_SOC_AR7240)
750            pdata->is_ar7240 = 1;
751
752        if (!pdata->fifo_cfg1)
753            pdata->fifo_cfg1 = 0x0010ffff;
754        if (!pdata->fifo_cfg2)
755            pdata->fifo_cfg2 = 0x015500aa;
756        if (!pdata->fifo_cfg3)
757            pdata->fifo_cfg3 = 0x01f00140;
758        break;
759
760    case ATH79_SOC_AR9130:
761        if (id == 0) {
762            pdata->ddr_flush = ar91xx_ddr_flush_ge0;
763            pdata->set_speed = ar91xx_set_speed_ge0;
764        } else {
765            pdata->ddr_flush = ar91xx_ddr_flush_ge1;
766            pdata->set_speed = ar91xx_set_speed_ge1;
767        }
768        pdata->is_ar91xx = 1;
769        break;
770
771    case ATH79_SOC_AR9132:
772        if (id == 0) {
773            pdata->ddr_flush = ar91xx_ddr_flush_ge0;
774            pdata->set_speed = ar91xx_set_speed_ge0;
775        } else {
776            pdata->ddr_flush = ar91xx_ddr_flush_ge1;
777            pdata->set_speed = ar91xx_set_speed_ge1;
778        }
779        pdata->is_ar91xx = 1;
780        pdata->has_gbit = 1;
781        break;
782
783    case ATH79_SOC_AR9330:
784    case ATH79_SOC_AR9331:
785        if (id == 0) {
786            pdata->reset_bit = AR933X_RESET_GE0_MAC |
787                       AR933X_RESET_GE0_MDIO;
788            pdata->ddr_flush = ar933x_ddr_flush_ge0;
789            pdata->set_speed = ar933x_set_speed_ge0;
790
791            pdata->phy_mask = BIT(4);
792        } else {
793            pdata->reset_bit = AR933X_RESET_GE1_MAC |
794                       AR933X_RESET_GE1_MDIO;
795            pdata->ddr_flush = ar933x_ddr_flush_ge1;
796            pdata->set_speed = ar933x_set_speed_ge1;
797
798            pdata->speed = SPEED_1000;
799            pdata->duplex = DUPLEX_FULL;
800            pdata->switch_data = &ath79_switch_data;
801        }
802
803        pdata->has_gbit = 1;
804        pdata->is_ar724x = 1;
805
806        if (!pdata->fifo_cfg1)
807            pdata->fifo_cfg1 = 0x0010ffff;
808        if (!pdata->fifo_cfg2)
809            pdata->fifo_cfg2 = 0x015500aa;
810        if (!pdata->fifo_cfg3)
811            pdata->fifo_cfg3 = 0x01f00140;
812        break;
813
814    case ATH79_SOC_AR9341:
815    case ATH79_SOC_AR9342:
816    case ATH79_SOC_AR9344:
817        if (id == 0) {
818            pdata->reset_bit = AR934X_RESET_GE0_MAC |
819                       AR934X_RESET_GE0_MDIO;
820            pdata->ddr_flush =ar934x_ddr_flush_ge0;
821            pdata->set_speed = ar934x_set_speed_ge0;
822        } else {
823            pdata->reset_bit = AR934X_RESET_GE1_MAC |
824                       AR934X_RESET_GE1_MDIO;
825            pdata->ddr_flush = ar934x_ddr_flush_ge1;
826            pdata->set_speed = ar934x_set_speed_ge1;
827
828            pdata->switch_data = &ath79_switch_data;
829        }
830
831        pdata->has_gbit = 1;
832        pdata->is_ar724x = 1;
833
834        if (!pdata->fifo_cfg1)
835            pdata->fifo_cfg1 = 0x0010ffff;
836        if (!pdata->fifo_cfg2)
837            pdata->fifo_cfg2 = 0x015500aa;
838        if (!pdata->fifo_cfg3)
839            pdata->fifo_cfg3 = 0x01f00140;
840        break;
841
842    default:
843        BUG();
844    }
845
846    switch (pdata->phy_if_mode) {
847    case PHY_INTERFACE_MODE_GMII:
848    case PHY_INTERFACE_MODE_RGMII:
849        if (!pdata->has_gbit) {
850            printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
851                    id);
852            return;
853        }
854        /* fallthrough */
855    default:
856        break;
857    }
858
859    if (!is_valid_ether_addr(pdata->mac_addr)) {
860        random_ether_addr(pdata->mac_addr);
861        printk(KERN_DEBUG
862            "ar71xx: using random MAC address for eth%d\n",
863            ath79_eth_instance);
864    }
865
866    if (pdata->mii_bus_dev == NULL) {
867        switch (ath79_soc) {
868        case ATH79_SOC_AR9341:
869        case ATH79_SOC_AR9342:
870        case ATH79_SOC_AR9344:
871            if (id == 0)
872                pdata->mii_bus_dev = &ath79_mdio0_device.dev;
873            else
874                pdata->mii_bus_dev = &ath79_mdio1_device.dev;
875            break;
876
877        case ATH79_SOC_AR7241:
878        case ATH79_SOC_AR9330:
879        case ATH79_SOC_AR9331:
880            pdata->mii_bus_dev = &ath79_mdio1_device.dev;
881            break;
882
883        default:
884            pdata->mii_bus_dev = &ath79_mdio0_device.dev;
885            break;
886        }
887    }
888
889    /* Reset the device */
890    ath79_device_reset_set(pdata->reset_bit);
891    mdelay(100);
892
893    ath79_device_reset_clear(pdata->reset_bit);
894    mdelay(100);
895
896    platform_device_register(pdev);
897    ath79_eth_instance++;
898}
899
900void __init ath79_set_mac_base(unsigned char *mac)
901{
902    memcpy(ath79_mac_base, mac, ETH_ALEN);
903}
904
905void __init ath79_parse_mac_addr(char *mac_str)
906{
907    u8 tmp[ETH_ALEN];
908    int t;
909
910    t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
911            &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
912
913    if (t != ETH_ALEN)
914        t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
915            &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
916
917    if (t == ETH_ALEN)
918        ath79_set_mac_base(tmp);
919    else
920        printk(KERN_DEBUG "ar71xx: failed to parse mac address "
921                "\"%s\"\n", mac_str);
922}
923
924static int __init ath79_ethaddr_setup(char *str)
925{
926    ath79_parse_mac_addr(str);
927    return 1;
928}
929__setup("ethaddr=", ath79_ethaddr_setup);
930
931static int __init ath79_kmac_setup(char *str)
932{
933    ath79_parse_mac_addr(str);
934    return 1;
935}
936__setup("kmac=", ath79_kmac_setup);
937
938void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
939                int offset)
940{
941    int t;
942
943    if (!is_valid_ether_addr(src)) {
944        memset(dst, '\0', ETH_ALEN);
945        return;
946    }
947
948    t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
949    t += offset;
950
951    dst[0] = src[0];
952    dst[1] = src[1];
953    dst[2] = src[2];
954    dst[3] = (t >> 16) & 0xff;
955    dst[4] = (t >> 8) & 0xff;
956    dst[5] = t & 0xff;
957}
958
959void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
960{
961    int i;
962
963    if (!is_valid_ether_addr(src)) {
964        memset(dst, '\0', ETH_ALEN);
965        return;
966    }
967
968    for (i = 0; i < ETH_ALEN; i++)
969        dst[i] = src[i];
970    dst[0] |= 0x02;
971}
972

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