| 1 | /* |
| 2 | * Atheros AP96 board support |
| 3 | * |
| 4 | * Copyright (C) 2009 Marco Porsch |
| 5 | * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> |
| 6 | * Copyright (C) 2010 Atheros Communications |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License version 2 as published |
| 10 | * by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/mtd/mtd.h> |
| 15 | #include <linux/mtd/partitions.h> |
| 16 | #include <linux/delay.h> |
| 17 | |
| 18 | #include <asm/mach-ath79/ath79.h> |
| 19 | |
| 20 | #include "dev-ap9x-pci.h" |
| 21 | #include "dev-eth.h" |
| 22 | #include "dev-gpio-buttons.h" |
| 23 | #include "dev-leds-gpio.h" |
| 24 | #include "dev-m25p80.h" |
| 25 | #include "dev-usb.h" |
| 26 | #include "machtypes.h" |
| 27 | |
| 28 | #define AP96_GPIO_LED_12_GREEN 0 |
| 29 | #define AP96_GPIO_LED_3_GREEN 1 |
| 30 | #define AP96_GPIO_LED_2_GREEN 2 |
| 31 | #define AP96_GPIO_LED_WPS_GREEN 4 |
| 32 | #define AP96_GPIO_LED_5_GREEN 5 |
| 33 | #define AP96_GPIO_LED_4_ORANGE 6 |
| 34 | |
| 35 | /* Reset button - next to the power connector */ |
| 36 | #define AP96_GPIO_BTN_RESET 3 |
| 37 | /* WPS button - next to a led on right */ |
| 38 | #define AP96_GPIO_BTN_WPS 8 |
| 39 | |
| 40 | #define AP96_KEYS_POLL_INTERVAL 20 /* msecs */ |
| 41 | #define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL) |
| 42 | |
| 43 | #define AP96_WMAC0_MAC_OFFSET 0x120c |
| 44 | #define AP96_WMAC1_MAC_OFFSET 0x520c |
| 45 | #define AP96_CALDATA0_OFFSET 0x1000 |
| 46 | #define AP96_CALDATA1_OFFSET 0x5000 |
| 47 | |
| 48 | static struct mtd_partition ap96_partitions[] = { |
| 49 | { |
| 50 | .name = "uboot", |
| 51 | .offset = 0, |
| 52 | .size = 0x030000, |
| 53 | .mask_flags = MTD_WRITEABLE, |
| 54 | }, { |
| 55 | .name = "env", |
| 56 | .offset = 0x030000, |
| 57 | .size = 0x010000, |
| 58 | .mask_flags = MTD_WRITEABLE, |
| 59 | }, { |
| 60 | .name = "rootfs", |
| 61 | .offset = 0x040000, |
| 62 | .size = 0x600000, |
| 63 | }, { |
| 64 | .name = "uImage", |
| 65 | .offset = 0x640000, |
| 66 | .size = 0x1b0000, |
| 67 | }, { |
| 68 | .name = "caldata", |
| 69 | .offset = 0x7f0000, |
| 70 | .size = 0x010000, |
| 71 | .mask_flags = MTD_WRITEABLE, |
| 72 | } |
| 73 | }; |
| 74 | |
| 75 | static struct flash_platform_data ap96_flash_data = { |
| 76 | .parts = ap96_partitions, |
| 77 | .nr_parts = ARRAY_SIZE(ap96_partitions), |
| 78 | }; |
| 79 | |
| 80 | /* |
| 81 | * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12 |
| 82 | * below (from left to right on the board). Led 1 seems to be on whenever the |
| 83 | * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange; |
| 84 | * others are green. |
| 85 | * |
| 86 | * In addition, there is one led next to a button on the right side for WPS. |
| 87 | */ |
| 88 | static struct gpio_led ap96_leds_gpio[] __initdata = { |
| 89 | { |
| 90 | .name = "ap96:green:led2", |
| 91 | .gpio = AP96_GPIO_LED_2_GREEN, |
| 92 | .active_low = 1, |
| 93 | }, { |
| 94 | .name = "ap96:green:led3", |
| 95 | .gpio = AP96_GPIO_LED_3_GREEN, |
| 96 | .active_low = 1, |
| 97 | }, { |
| 98 | .name = "ap96:orange:led4", |
| 99 | .gpio = AP96_GPIO_LED_4_ORANGE, |
| 100 | .active_low = 1, |
| 101 | }, { |
| 102 | .name = "ap96:green:led5", |
| 103 | .gpio = AP96_GPIO_LED_5_GREEN, |
| 104 | .active_low = 1, |
| 105 | }, { |
| 106 | .name = "ap96:green:led12", |
| 107 | .gpio = AP96_GPIO_LED_12_GREEN, |
| 108 | .active_low = 1, |
| 109 | }, { /* next to a button on right */ |
| 110 | .name = "ap96:green:wps", |
| 111 | .gpio = AP96_GPIO_LED_WPS_GREEN, |
| 112 | .active_low = 1, |
| 113 | } |
| 114 | }; |
| 115 | |
| 116 | static struct gpio_keys_button ap96_gpio_keys[] __initdata = { |
| 117 | { |
| 118 | .desc = "reset", |
| 119 | .type = EV_KEY, |
| 120 | .code = KEY_RESTART, |
| 121 | .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, |
| 122 | .gpio = AP96_GPIO_BTN_RESET, |
| 123 | .active_low = 1, |
| 124 | }, { |
| 125 | .desc = "wps", |
| 126 | .type = EV_KEY, |
| 127 | .code = KEY_WPS_BUTTON, |
| 128 | .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, |
| 129 | .gpio = AP96_GPIO_BTN_WPS, |
| 130 | .active_low = 1, |
| 131 | } |
| 132 | }; |
| 133 | |
| 134 | #define AP96_WAN_PHYMASK 0x10 |
| 135 | #define AP96_LAN_PHYMASK 0x0f |
| 136 | |
| 137 | static void __init ap96_setup(void) |
| 138 | { |
| 139 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
| 140 | |
| 141 | ath79_register_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK)); |
| 142 | |
| 143 | ath79_init_mac(ath79_eth0_data.mac_addr, art, 0); |
| 144 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
| 145 | ath79_eth0_data.phy_mask = AP96_LAN_PHYMASK; |
| 146 | ath79_eth0_data.speed = SPEED_1000; |
| 147 | ath79_eth0_data.duplex = DUPLEX_FULL; |
| 148 | |
| 149 | ath79_register_eth(0); |
| 150 | |
| 151 | ath79_init_mac(ath79_eth1_data.mac_addr, art, 1); |
| 152 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
| 153 | ath79_eth1_data.phy_mask = AP96_WAN_PHYMASK; |
| 154 | |
| 155 | ath79_eth1_pll_data.pll_1000 = 0x1f000000; |
| 156 | |
| 157 | ath79_register_eth(1); |
| 158 | |
| 159 | ath79_register_usb(); |
| 160 | |
| 161 | ath79_register_m25p80(&ap96_flash_data); |
| 162 | |
| 163 | ath79_register_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio), |
| 164 | ap96_leds_gpio); |
| 165 | |
| 166 | ath79_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL, |
| 167 | ARRAY_SIZE(ap96_gpio_keys), |
| 168 | ap96_gpio_keys); |
| 169 | |
| 170 | ap94_pci_init(art + AP96_CALDATA0_OFFSET, |
| 171 | art + AP96_WMAC0_MAC_OFFSET, |
| 172 | art + AP96_CALDATA1_OFFSET, |
| 173 | art + AP96_WMAC1_MAC_OFFSET); |
| 174 | } |
| 175 | |
| 176 | MIPS_MACHINE(ATH79_MACH_AP96, "AP96", "Atheros AP96", ap96_setup); |
| 177 | |
