Root/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c

1/*
2 * D-Link DIR-600 rev. A1 board support
3 *
4 * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2012 Vadim Girlin <vadimgirlin@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14
15#include <asm/mach-ath79/ath79.h>
16#include <asm/mach-ath79/ar71xx_regs.h>
17
18#include "common.h"
19#include "dev-ap9x-pci.h"
20#include "dev-eth.h"
21#include "dev-gpio-buttons.h"
22#include "dev-leds-gpio.h"
23#include "dev-m25p80.h"
24#include "machtypes.h"
25#include "nvram.h"
26
27#define DIR_600_A1_GPIO_LED_WPS 0
28#define DIR_600_A1_GPIO_LED_POWER_AMBER 1
29#define DIR_600_A1_GPIO_LED_POWER_GREEN 6
30#define DIR_600_A1_GPIO_LED_LAN1 13
31#define DIR_600_A1_GPIO_LED_LAN2 14
32#define DIR_600_A1_GPIO_LED_LAN3 15
33#define DIR_600_A1_GPIO_LED_LAN4 16
34#define DIR_600_A1_GPIO_LED_WAN_AMBER 7
35#define DIR_600_A1_GPIO_LED_WAN_GREEN 17
36
37#define DIR_600_A1_GPIO_BTN_RESET 8
38#define DIR_600_A1_GPIO_BTN_WPS 12
39
40#define DIR_600_A1_KEYS_POLL_INTERVAL 20 /* msecs */
41#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL)
42
43#define DIR_600_A1_NVRAM_ADDR 0x1f030000
44#define DIR_600_A1_NVRAM_SIZE 0x10000
45
46static struct mtd_partition dir_600_a1_partitions[] = {
47    {
48        .name = "u-boot",
49        .offset = 0,
50        .size = 0x030000,
51        .mask_flags = MTD_WRITEABLE,
52    }, {
53        .name = "nvram",
54        .offset = 0x030000,
55        .size = 0x010000,
56    }, {
57        .name = "kernel",
58        .offset = 0x040000,
59        .size = 0x0e0000,
60    }, {
61        .name = "rootfs",
62        .offset = 0x120000,
63        .size = 0x2c0000,
64    }, {
65        .name = "mac",
66        .offset = 0x3e0000,
67        .size = 0x010000,
68        .mask_flags = MTD_WRITEABLE,
69    }, {
70        .name = "art",
71        .offset = 0x3f0000,
72        .size = 0x010000,
73        .mask_flags = MTD_WRITEABLE,
74    }, {
75        .name = "firmware",
76        .offset = 0x040000,
77        .size = 0x3a0000,
78    }
79};
80
81static struct flash_platform_data dir_600_a1_flash_data = {
82    .parts = dir_600_a1_partitions,
83    .nr_parts = ARRAY_SIZE(dir_600_a1_partitions),
84};
85
86static struct gpio_led dir_600_a1_leds_gpio[] __initdata = {
87    {
88        .name = "d-link:green:power",
89        .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN,
90    }, {
91        .name = "d-link:amber:power",
92        .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER,
93    }, {
94        .name = "d-link:amber:wan",
95        .gpio = DIR_600_A1_GPIO_LED_WAN_AMBER,
96    }, {
97        .name = "d-link:green:wan",
98        .gpio = DIR_600_A1_GPIO_LED_WAN_GREEN,
99        .active_low = 1,
100    }, {
101        .name = "d-link:green:lan1",
102        .gpio = DIR_600_A1_GPIO_LED_LAN1,
103        .active_low = 1,
104    }, {
105        .name = "d-link:green:lan2",
106        .gpio = DIR_600_A1_GPIO_LED_LAN2,
107        .active_low = 1,
108    }, {
109        .name = "d-link:green:lan3",
110        .gpio = DIR_600_A1_GPIO_LED_LAN3,
111        .active_low = 1,
112    }, {
113        .name = "d-link:green:lan4",
114        .gpio = DIR_600_A1_GPIO_LED_LAN4,
115        .active_low = 1,
116    }, {
117        .name = "d-link:blue:wps",
118        .gpio = DIR_600_A1_GPIO_LED_WPS,
119        .active_low = 1,
120    }
121};
122
123static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = {
124    {
125        .desc = "reset",
126        .type = EV_KEY,
127        .code = KEY_RESTART,
128        .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL,
129        .gpio = DIR_600_A1_GPIO_BTN_RESET,
130        .active_low = 1,
131    }, {
132        .desc = "wps",
133        .type = EV_KEY,
134        .code = KEY_WPS_BUTTON,
135        .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL,
136        .gpio = DIR_600_A1_GPIO_BTN_WPS,
137        .active_low = 1,
138    }
139};
140
141static void __init dir_600_a1_setup(void)
142{
143    const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR);
144    u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
145    u8 mac_buff[6];
146    u8 *mac = NULL;
147
148    if (ath79_nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE,
149                       "lan_mac=", mac_buff) == 0) {
150        ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0);
151        ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1);
152        mac = mac_buff;
153    }
154
155    ath79_register_m25p80(&dir_600_a1_flash_data);
156
157    ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
158                    AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
159                    AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
160                    AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
161                    AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
162
163    ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio),
164                 dir_600_a1_leds_gpio);
165
166    ath79_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL,
167                    ARRAY_SIZE(dir_600_a1_gpio_keys),
168                    dir_600_a1_gpio_keys);
169
170    ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
171    ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
172
173    ath79_register_mdio(0, 0x0);
174
175    /* LAN ports */
176    ath79_register_eth(1);
177
178    /* WAN port */
179    ath79_register_eth(0);
180
181    ap91_pci_init(ee, mac);
182}
183
184MIPS_MACHINE(ATH79_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1",
185         dir_600_a1_setup);
186
187static void __init dir_615_e4_setup(void)
188{
189    dir_600_a1_setup();
190    ap9x_pci_setup_wmac_led_pin(0, 1);
191}
192
193MIPS_MACHINE(ATH79_MACH_DIR_615_E4, "DIR-615-E4", "D-Link DIR-615 rev. E4",
194         dir_615_e4_setup);
195

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