Root/target/linux/ar71xx/patches-3.3/124-MIPS-ath79-add-clock-initialization-code-for-AR934X.patch

1From 783addfa256e79892f889e95ec5cda34f4e91eb7 Mon Sep 17 00:00:00 2001
2From: Gabor Juhos <juhosg@openwrt.org>
3Date: Fri, 9 Dec 2011 20:36:32 +0100
4Subject: [PATCH 24/35] MIPS: ath79: add clock initialization code for AR934X
5
6Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
8---
9 arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++
10 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++
11 2 files changed, 134 insertions(+), 0 deletions(-)
12
13--- a/arch/mips/ath79/clock.c
14+++ b/arch/mips/ath79/clock.c
15@@ -1,8 +1,11 @@
16 /*
17  * Atheros AR71XX/AR724X/AR913X common routines
18  *
19+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
20  * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
21  *
22+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
23+ *
24  * This program is free software; you can redistribute it and/or modify it
25  * under the terms of the GNU General Public License version 2 as published
26  * by the Free Software Foundation.
27@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo
28     ath79_uart_clk.rate = ath79_ref_clk.rate;
29 }
30 
31+static void __init ar934x_clocks_init(void)
32+{
33+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
34+ u32 cpu_pll, ddr_pll;
35+ u32 bootstrap;
36+
37+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
38+ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
39+ ath79_ref_clk.rate = 40 * 1000 * 1000;
40+ else
41+ ath79_ref_clk.rate = 25 * 1000 * 1000;
42+
43+ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
44+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
45+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
46+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
47+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
48+ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
49+ AR934X_PLL_CPU_CONFIG_NINT_MASK;
50+ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
51+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
52+
53+ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
54+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
55+ cpu_pll /= (1 << out_div);
56+
57+ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
58+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
59+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
60+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
61+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
62+ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
63+ AR934X_PLL_DDR_CONFIG_NINT_MASK;
64+ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
65+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
66+
67+ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
68+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
69+ ddr_pll /= (1 << out_div);
70+
71+ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
72+
73+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
74+ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
75+
76+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
77+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
78+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
79+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
80+ else
81+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
82+
83+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
84+ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
85+
86+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
87+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
88+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
89+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
90+ else
91+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
92+
93+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
94+ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
95+
96+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
97+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
98+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
99+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
100+ else
101+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
102+
103+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
104+ ath79_uart_clk.rate = ath79_ref_clk.rate;
105+}
106+
107 void __init ath79_clocks_init(void)
108 {
109     if (soc_is_ar71xx())
110@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void)
111         ar913x_clocks_init();
112     else if (soc_is_ar933x())
113         ar933x_clocks_init();
114+ else if (soc_is_ar934x())
115+ ar934x_clocks_init();
116     else
117         BUG();
118 
119--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
120+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
121@@ -151,6 +151,41 @@
122 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
123 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
124 
125+#define AR934X_PLL_CPU_CONFIG_REG 0x00
126+#define AR934X_PLL_DDR_CONFIG_REG 0x04
127+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
128+
129+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
130+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
131+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
132+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
133+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
134+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
135+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
136+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
137+
138+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
139+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
140+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
141+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
142+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
143+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
144+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
145+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
146+
147+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
148+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
149+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
150+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
151+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
152+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
153+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
154+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
155+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
156+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
157+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
158+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
159+
160 /*
161  * USB_CONFIG block
162  */
163@@ -186,6 +221,8 @@
164 #define AR933X_RESET_REG_RESET_MODULE 0x1c
165 #define AR933X_RESET_REG_BOOTSTRAP 0xac
166 
167+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
168+
169 #define MISC_INT_ETHSW BIT(12)
170 #define MISC_INT_TIMER4 BIT(10)
171 #define MISC_INT_TIMER3 BIT(9)
172@@ -242,6 +279,22 @@
173 
174 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
175 
176+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
177+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
178+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
179+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
180+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
181+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
182+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
183+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
184+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
185+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
186+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
187+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
188+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
189+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
190+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
191+
192 #define REV_ID_MAJOR_MASK 0xfff0
193 #define REV_ID_MAJOR_AR71XX 0x00a0
194 #define REV_ID_MAJOR_AR913X 0x00b0
195

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