Root/target/linux/ar71xx/patches-3.3/127-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch

1From 9db6021011556948d2d28d6957cee451bc2985aa Mon Sep 17 00:00:00 2001
2From: Gabor Juhos <juhosg@openwrt.org>
3Date: Fri, 9 Dec 2011 21:59:50 +0100
4Subject: [PATCH 27/35] MIPS: ath79: add IRQ handling code for AR934X
5
6Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
8---
9 arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++-
10 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++
11 arch/mips/include/asm/mach-ath79/irq.h | 6 ++-
12 3 files changed, 83 insertions(+), 3 deletions(-)
13
14--- a/arch/mips/ath79/irq.c
15+++ b/arch/mips/ath79/irq.c
16@@ -1,10 +1,11 @@
17 /*
18  * Atheros AR71xx/AR724x/AR913x specific interrupt handling
19  *
20+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
21  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
22  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
23  *
24- * Parts of this file are based on Atheros' 2.6.15 BSP
25+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
26  *
27  * This program is free software; you can redistribute it and/or modify it
28  * under the terms of the GNU General Public License version 2 as published
29@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v
30 
31     if (soc_is_ar71xx() || soc_is_ar913x())
32         ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
33- else if (soc_is_ar724x() || soc_is_ar933x())
34+ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
35         ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
36     else
37         BUG();
38@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v
39     irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
40 }
41 
42+static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
43+{
44+ u32 status;
45+
46+ disable_irq_nosync(irq);
47+
48+ status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
49+
50+ if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
51+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
52+ generic_handle_irq(ATH79_IP2_IRQ(0));
53+ } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
54+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
55+ generic_handle_irq(ATH79_IP2_IRQ(1));
56+ } else {
57+ spurious_interrupt();
58+ }
59+
60+ enable_irq(irq);
61+}
62+
63+static void ar934x_ip2_irq_init(void)
64+{
65+ int i;
66+
67+ for (i = ATH79_IP2_IRQ_BASE;
68+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
69+ irq_set_chip_and_handler(i, &dummy_irq_chip,
70+ handle_level_irq);
71+
72+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
73+}
74+
75 asmlinkage void plat_irq_dispatch(void)
76 {
77     unsigned long pending;
78@@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void)
79     do_IRQ(ATH79_CPU_IRQ_IP2);
80 }
81 
82+static void ar934x_ip2_handler(void)
83+{
84+ do_IRQ(ATH79_CPU_IRQ_IP2);
85+}
86+
87 static void ar71xx_ip3_handler(void)
88 {
89     ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
90@@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void)
91     do_IRQ(ATH79_CPU_IRQ_USB);
92 }
93 
94+static void ar934x_ip3_handler(void)
95+{
96+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
97+ do_IRQ(ATH79_CPU_IRQ_USB);
98+}
99+
100 void __init arch_init_irq(void)
101 {
102     if (soc_is_ar71xx()) {
103@@ -240,6 +285,9 @@ void __init arch_init_irq(void)
104     } else if (soc_is_ar933x()) {
105         ath79_ip2_handler = ar933x_ip2_handler;
106         ath79_ip3_handler = ar933x_ip3_handler;
107+ } else if (soc_is_ar934x()) {
108+ ath79_ip2_handler = ar934x_ip2_handler;
109+ ath79_ip3_handler = ar934x_ip3_handler;
110     } else {
111         BUG();
112     }
113@@ -247,4 +295,7 @@ void __init arch_init_irq(void)
114     cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
115     mips_cpu_irq_init();
116     ath79_misc_irq_init();
117+
118+ if (soc_is_ar934x())
119+ ar934x_ip2_irq_init();
120 }
121--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
122+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
123@@ -92,6 +92,12 @@
124 #define AR933X_DDR_REG_FLUSH_USB 0x84
125 #define AR933X_DDR_REG_FLUSH_WMAC 0x88
126 
127+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
128+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
129+#define AR934X_DDR_REG_FLUSH_USB 0xa4
130+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
131+#define AR934X_DDR_REG_FLUSH_WMAC 0xac
132+
133 /*
134  * PLL block
135  */
136@@ -222,6 +228,7 @@
137 #define AR933X_RESET_REG_BOOTSTRAP 0xac
138 
139 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
140+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
141 
142 #define MISC_INT_ETHSW BIT(12)
143 #define MISC_INT_TIMER4 BIT(10)
144@@ -295,6 +302,24 @@
145 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
146 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
147 
148+#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
149+#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
150+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
151+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
152+#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
153+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
154+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
155+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
156+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
157+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
158+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
159+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
160+
161+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
162+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
163+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
164+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
165+
166 #define REV_ID_MAJOR_MASK 0xfff0
167 #define REV_ID_MAJOR_AR71XX 0x00a0
168 #define REV_ID_MAJOR_AR913X 0x00b0
169--- a/arch/mips/include/asm/mach-ath79/irq.h
170+++ b/arch/mips/include/asm/mach-ath79/irq.h
171@@ -10,7 +10,7 @@
172 #define __ASM_MACH_ATH79_IRQ_H
173 
174 #define MIPS_CPU_IRQ_BASE 0
175-#define NR_IRQS 46
176+#define NR_IRQS 48
177 
178 #define ATH79_MISC_IRQ_BASE 8
179 #define ATH79_MISC_IRQ_COUNT 32
180@@ -19,6 +19,10 @@
181 #define ATH79_PCI_IRQ_COUNT 6
182 #define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
183 
184+#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
185+#define ATH79_IP2_IRQ_COUNT 2
186+#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
187+
188 #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
189 #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
190 #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
191

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