| 1 | --- a/arch/mips/ath79/mach-db120.c |
| 2 | +++ b/arch/mips/ath79/mach-db120.c |
| 3 | @@ -37,17 +37,26 @@ |
| 4 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 5 | */ |
| 6 | |
| 7 | +#include <linux/mtd/mtd.h> |
| 8 | +#include <linux/mtd/partitions.h> |
| 9 | #include <linux/pci.h> |
| 10 | +#include <linux/platform_device.h> |
| 11 | #include <linux/ath9k_platform.h> |
| 12 | |
| 13 | -#include "machtypes.h" |
| 14 | +#include <asm/mach-ath79/ar71xx_regs.h> |
| 15 | + |
| 16 | +#include "common.h" |
| 17 | +#include "dev-ap9x-pci.h" |
| 18 | +#include "dev-eth.h" |
| 19 | #include "dev-gpio-buttons.h" |
| 20 | #include "dev-leds-gpio.h" |
| 21 | +#include "dev-m25p80.h" |
| 22 | #include "dev-spi.h" |
| 23 | #include "dev-usb.h" |
| 24 | #include "dev-wmac.h" |
| 25 | -#include "pci.h" |
| 26 | +#include "machtypes.h" |
| 27 | |
| 28 | +#define DB120_GPIO_LED_USB 11 |
| 29 | #define DB120_GPIO_LED_WLAN_5G 12 |
| 30 | #define DB120_GPIO_LED_WLAN_2G 13 |
| 31 | #define DB120_GPIO_LED_STATUS 14 |
| 32 | @@ -58,8 +67,50 @@ |
| 33 | #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ |
| 34 | #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) |
| 35 | |
| 36 | -#define DB120_WMAC_CALDATA_OFFSET 0x1000 |
| 37 | -#define DB120_PCIE_CALDATA_OFFSET 0x5000 |
| 38 | +#define DB120_MAC0_OFFSET 0 |
| 39 | +#define DB120_MAC1_OFFSET 6 |
| 40 | +#define DB120_WMAC_CALDATA_OFFSET 0x1000 |
| 41 | +#define DB120_PCIE_CALDATA_OFFSET 0x5000 |
| 42 | + |
| 43 | +static struct mtd_partition db120_partitions[] = { |
| 44 | + { |
| 45 | + .name = "u-boot", |
| 46 | + .offset = 0, |
| 47 | + .size = 0x040000, |
| 48 | + .mask_flags = MTD_WRITEABLE, |
| 49 | + }, |
| 50 | + { |
| 51 | + .name = "u-boot-env", |
| 52 | + .offset = 0x040000, |
| 53 | + .size = 0x010000, |
| 54 | + }, |
| 55 | + { |
| 56 | + .name = "rootfs", |
| 57 | + .offset = 0x050000, |
| 58 | + .size = 0x630000, |
| 59 | + }, |
| 60 | + { |
| 61 | + .name = "uImage", |
| 62 | + .offset = 0x680000, |
| 63 | + .size = 0x160000, |
| 64 | + }, |
| 65 | + { |
| 66 | + .name = "NVRAM", |
| 67 | + .offset = 0x7E0000, |
| 68 | + .size = 0x010000, |
| 69 | + }, |
| 70 | + { |
| 71 | + .name = "ART", |
| 72 | + .offset = 0x7F0000, |
| 73 | + .size = 0x010000, |
| 74 | + .mask_flags = MTD_WRITEABLE, |
| 75 | + } |
| 76 | +}; |
| 77 | + |
| 78 | +static struct flash_platform_data db120_flash_data = { |
| 79 | + .parts = db120_partitions, |
| 80 | + .nr_parts = ARRAY_SIZE(db120_partitions), |
| 81 | +}; |
| 82 | |
| 83 | static struct gpio_led db120_leds_gpio[] __initdata = { |
| 84 | { |
| 85 | @@ -82,6 +133,11 @@ static struct gpio_led db120_leds_gpio[] |
| 86 | .gpio = DB120_GPIO_LED_WLAN_2G, |
| 87 | .active_low = 1, |
| 88 | }, |
| 89 | + { |
| 90 | + .name = "db120:green:usb", |
| 91 | + .gpio = DB120_GPIO_LED_USB, |
| 92 | + .active_low = 1, |
| 93 | + } |
| 94 | }; |
| 95 | |
| 96 | static struct gpio_keys_button db120_gpio_keys[] __initdata = { |
| 97 | @@ -95,66 +151,65 @@ static struct gpio_keys_button db120_gpi |
| 98 | }, |
| 99 | }; |
| 100 | |
| 101 | -static struct ath79_spi_controller_data db120_spi0_data = { |
| 102 | - .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, |
| 103 | - .cs_line = 0, |
| 104 | -}; |
| 105 | - |
| 106 | -static struct spi_board_info db120_spi_info[] = { |
| 107 | - { |
| 108 | - .bus_num = 0, |
| 109 | - .chip_select = 0, |
| 110 | - .max_speed_hz = 25000000, |
| 111 | - .modalias = "s25sl064a", |
| 112 | - .controller_data = &db120_spi0_data, |
| 113 | - } |
| 114 | -}; |
| 115 | - |
| 116 | -static struct ath79_spi_platform_data db120_spi_data = { |
| 117 | - .bus_num = 0, |
| 118 | - .num_chipselect = 1, |
| 119 | -}; |
| 120 | - |
| 121 | -#ifdef CONFIG_PCI |
| 122 | -static struct ath9k_platform_data db120_ath9k_data; |
| 123 | - |
| 124 | -static int db120_pci_plat_dev_init(struct pci_dev *dev) |
| 125 | +static void __init db120_gmac_setup(void) |
| 126 | { |
| 127 | - switch (PCI_SLOT(dev->devfn)) { |
| 128 | - case 0: |
| 129 | - dev->dev.platform_data = &db120_ath9k_data; |
| 130 | - break; |
| 131 | - } |
| 132 | + void __iomem *base; |
| 133 | + u32 t; |
| 134 | |
| 135 | - return 0; |
| 136 | -} |
| 137 | + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); |
| 138 | |
| 139 | -static void __init db120_pci_init(u8 *eeprom) |
| 140 | -{ |
| 141 | - memcpy(db120_ath9k_data.eeprom_data, eeprom, |
| 142 | - sizeof(db120_ath9k_data.eeprom_data)); |
| 143 | + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); |
| 144 | + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 | |
| 145 | + AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); |
| 146 | + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); |
| 147 | |
| 148 | - ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); |
| 149 | - ath79_register_pci(); |
| 150 | + iounmap(base); |
| 151 | } |
| 152 | -#else |
| 153 | -static inline void db120_pci_init(void) {} |
| 154 | -#endif /* CONFIG_PCI */ |
| 155 | |
| 156 | static void __init db120_setup(void) |
| 157 | { |
| 158 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
| 159 | |
| 160 | + ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO); |
| 161 | + ath79_register_m25p80(&db120_flash_data); |
| 162 | + |
| 163 | ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), |
| 164 | db120_leds_gpio); |
| 165 | ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, |
| 166 | ARRAY_SIZE(db120_gpio_keys), |
| 167 | db120_gpio_keys); |
| 168 | - ath79_register_spi(&db120_spi_data, db120_spi_info, |
| 169 | - ARRAY_SIZE(db120_spi_info)); |
| 170 | ath79_register_usb(); |
| 171 | ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); |
| 172 | - db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); |
| 173 | + ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL); |
| 174 | + |
| 175 | + db120_gmac_setup(); |
| 176 | + |
| 177 | + ath79_register_mdio(0, 0x0); |
| 178 | + ath79_register_mdio(1, 0x0); |
| 179 | + |
| 180 | + ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0); |
| 181 | +#if 0 |
| 182 | + /* GMAC0 is connected to an AR8327 switch */ |
| 183 | + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
| 184 | + ath79_eth0_data.speed = SPEED_1000; |
| 185 | + ath79_eth0_data.duplex = DUPLEX_FULL; |
| 186 | +#else |
| 187 | + /* GMAC0 is connected to PHY4 of the internal switch */ |
| 188 | + ath79_switch_data.phy4_mii_en = 1; |
| 189 | + |
| 190 | + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
| 191 | + ath79_eth0_data.phy_mask = BIT(4); |
| 192 | + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; |
| 193 | +#endif |
| 194 | + ath79_register_eth(0); |
| 195 | + |
| 196 | + /* GMAC1 is connected to the internal switch */ |
| 197 | + ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0); |
| 198 | + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
| 199 | + ath79_eth1_data.speed = SPEED_1000; |
| 200 | + ath79_eth1_data.duplex = DUPLEX_FULL; |
| 201 | + |
| 202 | + ath79_register_eth(1); |
| 203 | } |
| 204 | |
| 205 | MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", |
| 206 | --- a/arch/mips/ath79/Kconfig |
| 207 | +++ b/arch/mips/ath79/Kconfig |
| 208 | @@ -31,9 +31,11 @@ config ATH79_MACH_AP81 |
| 209 | config ATH79_MACH_DB120 |
| 210 | bool "Atheros DB120 reference board" |
| 211 | select SOC_AR934X |
| 212 | + select ATH79_DEV_AP9X_PCI if PCI |
| 213 | + select ATH79_DEV_ETH |
| 214 | select ATH79_DEV_GPIO_BUTTONS |
| 215 | select ATH79_DEV_LEDS_GPIO |
| 216 | - select ATH79_DEV_SPI |
| 217 | + select ATH79_DEV_M25P80 |
| 218 | select ATH79_DEV_USB |
| 219 | select ATH79_DEV_WMAC |
| 220 | help |
| 221 | |
