Root/target/linux/atheros/patches-2.6.37/120-spiflash.patch

1--- a/drivers/mtd/devices/Kconfig
2+++ b/drivers/mtd/devices/Kconfig
3@@ -112,6 +112,10 @@ config MTD_SST25L
4       Set up your spi devices with the right board-specific platform data,
5       if you want to specify device partitioning.
6 
7+config MTD_AR2315
8+ tristate "Atheros AR2315+ SPI Flash support"
9+ depends on ATHEROS_AR2315
10+
11 config MTD_SLRAM
12     tristate "Uncached system RAM"
13     help
14--- a/drivers/mtd/devices/Makefile
15+++ b/drivers/mtd/devices/Makefile
16@@ -17,3 +17,4 @@ obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd
17 obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
18 obj-$(CONFIG_MTD_M25P80) += m25p80.o
19 obj-$(CONFIG_MTD_SST25L) += sst25l.o
20+obj-$(CONFIG_MTD_AR2315) += ar2315.o
21--- /dev/null
22+++ b/drivers/mtd/devices/ar2315.c
23@@ -0,0 +1,517 @@
24+
25+/*
26+ * MTD driver for the SPI Flash Memory support on Atheros AR2315
27+ *
28+ * Copyright (c) 2005-2006 Atheros Communications Inc.
29+ * Copyright (C) 2006-2007 FON Technology, SL.
30+ * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
31+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
32+ *
33+ * This code is free software; you can redistribute it and/or modify
34+ * it under the terms of the GNU General Public License version 2 as
35+ * published by the Free Software Foundation.
36+ *
37+ */
38+
39+#include <linux/kernel.h>
40+#include <linux/module.h>
41+#include <linux/types.h>
42+#include <linux/version.h>
43+#include <linux/errno.h>
44+#include <linux/slab.h>
45+#include <linux/mtd/mtd.h>
46+#include <linux/mtd/partitions.h>
47+#include <linux/platform_device.h>
48+#include <linux/sched.h>
49+#include <linux/root_dev.h>
50+#include <linux/delay.h>
51+#include <asm/delay.h>
52+#include <asm/io.h>
53+
54+#include <ar2315_spiflash.h>
55+#include <ar231x_platform.h>
56+#include <ar231x.h>
57+
58+
59+#define SPIFLASH "spiflash: "
60+#define busy_wait(_priv, _condition, _wait) do { \
61+ while (_condition) { \
62+ spin_unlock_bh(&_priv->lock); \
63+ if (_wait > 1) \
64+ msleep(_wait); \
65+ else if ((_wait == 1) && need_resched()) \
66+ schedule(); \
67+ else \
68+ udelay(1); \
69+ spin_lock_bh(&_priv->lock); \
70+ } \
71+} while (0)
72+
73+enum {
74+ FLASH_NONE,
75+ FLASH_1MB,
76+ FLASH_2MB,
77+ FLASH_4MB,
78+ FLASH_8MB,
79+ FLASH_16MB,
80+};
81+
82+/* Flash configuration table */
83+struct flashconfig {
84+ u32 byte_cnt;
85+ u32 sector_cnt;
86+ u32 sector_size;
87+};
88+
89+const struct flashconfig flashconfig_tbl[] = {
90+ [FLASH_NONE] = { 0, 0, 0},
91+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE},
92+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE},
93+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE},
94+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE},
95+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE}
96+};
97+
98+/* Mapping of generic opcodes to STM serial flash opcodes */
99+enum {
100+ SPI_WRITE_ENABLE,
101+ SPI_WRITE_DISABLE,
102+ SPI_RD_STATUS,
103+ SPI_WR_STATUS,
104+ SPI_RD_DATA,
105+ SPI_FAST_RD_DATA,
106+ SPI_PAGE_PROGRAM,
107+ SPI_SECTOR_ERASE,
108+ SPI_BULK_ERASE,
109+ SPI_DEEP_PWRDOWN,
110+ SPI_RD_SIG,
111+};
112+
113+struct opcodes {
114+ __u16 code;
115+ __s8 tx_cnt;
116+ __s8 rx_cnt;
117+};
118+const struct opcodes stm_opcodes[] = {
119+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
120+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
121+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
122+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
123+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
124+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
125+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
126+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
127+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
128+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
129+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
130+};
131+
132+/* Driver private data structure */
133+struct spiflash_priv {
134+ struct mtd_info mtd;
135+ void *readaddr; /* memory mapped data for read */
136+ void *mmraddr; /* memory mapped register space */
137+ wait_queue_head_t wq;
138+ spinlock_t lock;
139+ int state;
140+};
141+
142+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
143+
144+enum {
145+ FL_READY,
146+ FL_READING,
147+ FL_ERASING,
148+ FL_WRITING
149+};
150+
151+/***************************************************************************************************/
152+
153+static u32
154+spiflash_read_reg(struct spiflash_priv *priv, int reg)
155+{
156+ return ar231x_read_reg((u32) priv->mmraddr + reg);
157+}
158+
159+static void
160+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
161+{
162+ ar231x_write_reg((u32) priv->mmraddr + reg, data);
163+}
164+
165+static u32
166+spiflash_wait_busy(struct spiflash_priv *priv)
167+{
168+ u32 reg;
169+
170+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
171+ SPI_CTL_BUSY, 0);
172+ return reg;
173+}
174+
175+static u32
176+spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr)
177+{
178+ const struct opcodes *op;
179+ u32 reg, mask;
180+
181+ op = &stm_opcodes[opcode];
182+ reg = spiflash_wait_busy(priv);
183+ spiflash_write_reg(priv, SPI_FLASH_OPCODE,
184+ ((u32) op->code) | (addr << 8));
185+
186+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
187+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
188+
189+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
190+ spiflash_wait_busy(priv);
191+
192+ if (!op->rx_cnt)
193+ return 0;
194+
195+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
196+
197+ switch (op->rx_cnt) {
198+ case 1:
199+ mask = 0x000000ff;
200+ break;
201+ case 2:
202+ mask = 0x0000ffff;
203+ break;
204+ case 3:
205+ mask = 0x00ffffff;
206+ break;
207+ default:
208+ mask = 0xffffffff;
209+ break;
210+ }
211+ reg &= mask;
212+
213+ return reg;
214+}
215+
216+
217+/*
218+ * Probe SPI flash device
219+ * Function returns 0 for failure.
220+ * and flashconfig_tbl array index for success.
221+ */
222+static int
223+spiflash_probe_chip (struct spiflash_priv *priv)
224+{
225+ u32 sig;
226+ int flash_size;
227+
228+ /* Read the signature on the flash device */
229+ spin_lock_bh(&priv->lock);
230+ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
231+ spin_unlock_bh(&priv->lock);
232+
233+ switch (sig) {
234+ case STM_8MBIT_SIGNATURE:
235+ flash_size = FLASH_1MB;
236+ break;
237+ case STM_16MBIT_SIGNATURE:
238+ flash_size = FLASH_2MB;
239+ break;
240+ case STM_32MBIT_SIGNATURE:
241+ flash_size = FLASH_4MB;
242+ break;
243+ case STM_64MBIT_SIGNATURE:
244+ flash_size = FLASH_8MB;
245+ break;
246+ case STM_128MBIT_SIGNATURE:
247+ flash_size = FLASH_16MB;
248+ break;
249+ default:
250+ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
251+ return 0;
252+ }
253+
254+ return flash_size;
255+}
256+
257+
258+/* wait until the flash chip is ready and grab a lock */
259+static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
260+{
261+ DECLARE_WAITQUEUE(wait, current);
262+
263+retry:
264+ spin_lock_bh(&priv->lock);
265+ if (priv->state != FL_READY) {
266+ set_current_state(TASK_UNINTERRUPTIBLE);
267+ add_wait_queue(&priv->wq, &wait);
268+ spin_unlock_bh(&priv->lock);
269+ schedule();
270+ remove_wait_queue(&priv->wq, &wait);
271+
272+ if(signal_pending(current))
273+ return 0;
274+
275+ goto retry;
276+ }
277+ priv->state = state;
278+
279+ return 1;
280+}
281+
282+static inline void spiflash_done(struct spiflash_priv *priv)
283+{
284+ priv->state = FL_READY;
285+ spin_unlock_bh(&priv->lock);
286+ wake_up(&priv->wq);
287+}
288+
289+static void
290+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
291+{
292+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
293+ SPI_STATUS_WIP, timeout);
294+ spiflash_done(priv);
295+}
296+
297+
298+
299+static int
300+spiflash_erase (struct mtd_info *mtd, struct erase_info *instr)
301+{
302+ struct spiflash_priv *priv = to_spiflash(mtd);
303+ const struct opcodes *op;
304+ u32 temp, reg;
305+
306+ if (instr->addr + instr->len > mtd->size)
307+ return -EINVAL;
308+
309+ if (!spiflash_wait_ready(priv, FL_ERASING))
310+ return -EINTR;
311+
312+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
313+ reg = spiflash_wait_busy(priv);
314+
315+ op = &stm_opcodes[SPI_SECTOR_ERASE];
316+ temp = ((u32)instr->addr << 8) | (u32)(op->code);
317+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
318+
319+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
320+ reg |= op->tx_cnt | SPI_CTL_START;
321+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
322+
323+ spiflash_wait_complete(priv, 20);
324+
325+ instr->state = MTD_ERASE_DONE;
326+ mtd_erase_callback(instr);
327+
328+ return 0;
329+}
330+
331+static int
332+spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
333+{
334+ struct spiflash_priv *priv = to_spiflash(mtd);
335+ u8 *read_addr;
336+
337+ if (!len)
338+ return 0;
339+
340+ if (from + len > mtd->size)
341+ return -EINVAL;
342+
343+ *retlen = len;
344+
345+ if (!spiflash_wait_ready(priv, FL_READING))
346+ return -EINTR;
347+
348+ read_addr = (u8 *)(priv->readaddr + from);
349+ memcpy_fromio(buf, read_addr, len);
350+ spiflash_done(priv);
351+
352+ return 0;
353+}
354+
355+static int
356+spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf)
357+{
358+ struct spiflash_priv *priv = to_spiflash(mtd);
359+ u32 opcode, bytes_left;
360+
361+ *retlen = 0;
362+
363+ if (!len)
364+ return 0;
365+
366+ if (to + len > mtd->size)
367+ return -EINVAL;
368+
369+ bytes_left = len;
370+
371+ do {
372+ u32 read_len, reg, page_offset, spi_data = 0;
373+
374+ read_len = min(bytes_left, sizeof(u32));
375+
376+ /* 32-bit writes cannot span across a page boundary
377+ * (256 bytes). This types of writes require two page
378+ * program operations to handle it correctly. The STM part
379+ * will write the overflow data to the beginning of the
380+ * current page as opposed to the subsequent page.
381+ */
382+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
383+
384+ if (page_offset > STM_PAGE_SIZE)
385+ read_len -= (page_offset - STM_PAGE_SIZE);
386+
387+ if (!spiflash_wait_ready(priv, FL_WRITING))
388+ return -EINTR;
389+
390+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
391+ spi_data = 0;
392+ switch (read_len) {
393+ case 4:
394+ spi_data |= buf[3] << 24;
395+ /* fall through */
396+ case 3:
397+ spi_data |= buf[2] << 16;
398+ /* fall through */
399+ case 2:
400+ spi_data |= buf[1] << 8;
401+ /* fall through */
402+ case 1:
403+ spi_data |= buf[0] & 0xff;
404+ break;
405+ default:
406+ break;
407+ }
408+
409+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
410+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
411+ (to & 0x00ffffff) << 8;
412+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
413+
414+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
415+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
416+ reg |= (read_len + 4) | SPI_CTL_START;
417+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
418+
419+ spiflash_wait_complete(priv, 1);
420+
421+ bytes_left -= read_len;
422+ to += read_len;
423+ buf += read_len;
424+
425+ *retlen += read_len;
426+ } while (bytes_left != 0);
427+
428+ return 0;
429+}
430+
431+
432+#ifdef CONFIG_MTD_PARTITIONS
433+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
434+#endif
435+
436+
437+static int
438+spiflash_probe(struct platform_device *pdev)
439+{
440+ struct spiflash_priv *priv;
441+ struct mtd_partition *parts;
442+ struct mtd_info *mtd;
443+ int index, num_parts;
444+ int result = 0;
445+
446+ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
447+ spin_lock_init(&priv->lock);
448+ init_waitqueue_head(&priv->wq);
449+ priv->state = FL_READY;
450+ mtd = &priv->mtd;
451+
452+ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
453+ if (!priv->mmraddr) {
454+ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n");
455+ goto error;
456+ }
457+
458+ index = spiflash_probe_chip(priv);
459+ if (!index) {
460+ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
461+ goto error;
462+ }
463+
464+ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
465+ if (!priv->readaddr) {
466+ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
467+ goto error;
468+ }
469+
470+ platform_set_drvdata(pdev, priv);
471+ mtd->name = "spiflash";
472+ mtd->type = MTD_NORFLASH;
473+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
474+ mtd->size = flashconfig_tbl[index].byte_cnt;
475+ mtd->erasesize = flashconfig_tbl[index].sector_size;
476+ mtd->writesize = 1;
477+ mtd->numeraseregions = 0;
478+ mtd->eraseregions = NULL;
479+ mtd->erase = spiflash_erase;
480+ mtd->read = spiflash_read;
481+ mtd->write = spiflash_write;
482+ mtd->owner = THIS_MODULE;
483+
484+#ifdef CONFIG_MTD_PARTITIONS
485+ /* parse redboot partitions */
486+ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0);
487+ if (!num_parts)
488+ goto error;
489+
490+ result = add_mtd_partitions(mtd, parts, num_parts);
491+#endif
492+
493+ return result;
494+
495+error:
496+ if (priv->mmraddr)
497+ iounmap(priv->mmraddr);
498+ kfree(priv);
499+ return -ENXIO;
500+}
501+
502+static int
503+spiflash_remove (struct platform_device *pdev)
504+{
505+ struct spiflash_priv *priv = platform_get_drvdata(pdev);
506+ struct mtd_info *mtd = &priv->mtd;
507+
508+ del_mtd_partitions(mtd);
509+ iounmap(priv->mmraddr);
510+ iounmap(priv->readaddr);
511+ kfree(priv);
512+
513+ return 0;
514+}
515+
516+struct platform_driver spiflash_driver = {
517+ .driver.name = "spiflash",
518+ .probe = spiflash_probe,
519+ .remove = spiflash_remove,
520+};
521+
522+int __init
523+spiflash_init (void)
524+{
525+ return platform_driver_register(&spiflash_driver);
526+}
527+
528+void __exit
529+spiflash_exit (void)
530+{
531+ return platform_driver_unregister(&spiflash_driver);
532+}
533+
534+module_init (spiflash_init);
535+module_exit (spiflash_exit);
536+
537+MODULE_LICENSE("GPL");
538+MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
539+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
540+
541--- /dev/null
542+++ b/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h
543@@ -0,0 +1,116 @@
544+/*
545+ * SPI Flash Memory support header file.
546+ *
547+ * Copyright (c) 2005, Atheros Communications Inc.
548+ * Copyright (C) 2006 FON Technology, SL.
549+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
550+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
551+ *
552+ * This code is free software; you can redistribute it and/or modify
553+ * it under the terms of the GNU General Public License version 2 as
554+ * published by the Free Software Foundation.
555+ *
556+ */
557+#ifndef __AR2315_SPIFLASH_H
558+#define __AR2315_SPIFLASH_H
559+
560+#define STM_PAGE_SIZE 256
561+
562+#define SFI_WRITE_BUFFER_SIZE 4
563+#define SFI_FLASH_ADDR_MASK 0x00ffffff
564+
565+#define STM_8MBIT_SIGNATURE 0x13
566+#define STM_M25P80_BYTE_COUNT 1048576
567+#define STM_M25P80_SECTOR_COUNT 16
568+#define STM_M25P80_SECTOR_SIZE 0x10000
569+
570+#define STM_16MBIT_SIGNATURE 0x14
571+#define STM_M25P16_BYTE_COUNT 2097152
572+#define STM_M25P16_SECTOR_COUNT 32
573+#define STM_M25P16_SECTOR_SIZE 0x10000
574+
575+#define STM_32MBIT_SIGNATURE 0x15
576+#define STM_M25P32_BYTE_COUNT 4194304
577+#define STM_M25P32_SECTOR_COUNT 64
578+#define STM_M25P32_SECTOR_SIZE 0x10000
579+
580+#define STM_64MBIT_SIGNATURE 0x16
581+#define STM_M25P64_BYTE_COUNT 8388608
582+#define STM_M25P64_SECTOR_COUNT 128
583+#define STM_M25P64_SECTOR_SIZE 0x10000
584+
585+#define STM_128MBIT_SIGNATURE 0x17
586+#define STM_M25P128_BYTE_COUNT 16777216
587+#define STM_M25P128_SECTOR_COUNT 256
588+#define STM_M25P128_SECTOR_SIZE 0x10000
589+
590+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
591+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
592+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
593+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
594+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
595+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
596+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
597+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
598+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
599+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
600+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
601+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
602+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
603+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
604+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
605+
606+/*
607+ * ST Microelectronics Opcodes for Serial Flash
608+ */
609+
610+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
611+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
612+#define STM_OP_RD_STATUS 0x05 /* Read Status */
613+#define STM_OP_WR_STATUS 0x01 /* Write Status */
614+#define STM_OP_RD_DATA 0x03 /* Read Data */
615+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
616+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
617+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
618+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
619+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
620+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
621+
622+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
623+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
624+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
625+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
626+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
627+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
628+
629+/*
630+ * SPI Flash Interface Registers
631+ */
632+#define AR531XPLUS_SPI_READ 0x08000000
633+#define AR531XPLUS_SPI_MMR 0x11300000
634+#define AR531XPLUS_SPI_MMR_SIZE 12
635+
636+#define AR531XPLUS_SPI_CTL 0x00
637+#define AR531XPLUS_SPI_OPCODE 0x04
638+#define AR531XPLUS_SPI_DATA 0x08
639+
640+#define SPI_FLASH_READ AR531XPLUS_SPI_READ
641+#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR
642+#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE
643+#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL
644+#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE
645+#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA
646+
647+#define SPI_CTL_START 0x00000100
648+#define SPI_CTL_BUSY 0x00010000
649+#define SPI_CTL_TXCNT_MASK 0x0000000f
650+#define SPI_CTL_RXCNT_MASK 0x000000f0
651+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
652+#define SPI_CTL_SIZE_MASK 0x00060000
653+
654+#define SPI_CTL_CLK_SEL_MASK 0x03000000
655+#define SPI_OPCODE_MASK 0x000000ff
656+
657+#define SPI_STATUS_WIP STM_STATUS_WIP
658+
659+#endif
660

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