Root/target/linux/brcm63xx/patches-3.3/240-spi.patch

1--- /dev/null
2+++ b/arch/mips/bcm63xx/dev-spi.c
3@@ -0,0 +1,99 @@
4+/*
5+ * This file is subject to the terms and conditions of the GNU General Public
6+ * License. See the file "COPYING" in the main directory of this archive
7+ * for more details.
8+ *
9+ * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
10+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
11+ */
12+
13+#include <linux/init.h>
14+#include <linux/kernel.h>
15+#include <linux/platform_device.h>
16+#include <linux/export.h>
17+
18+#include <bcm63xx_cpu.h>
19+#include <bcm63xx_dev_spi.h>
20+#include <bcm63xx_regs.h>
21+
22+#ifdef BCMCPU_RUNTIME_DETECT
23+/*
24+ * register offsets
25+ */
26+static const unsigned long bcm96338_regs_spi[] = {
27+ __GEN_SPI_REGS_TABLE(6338)
28+};
29+
30+static const unsigned long bcm96348_regs_spi[] = {
31+ __GEN_SPI_REGS_TABLE(6348)
32+};
33+
34+static const unsigned long bcm96358_regs_spi[] = {
35+ __GEN_SPI_REGS_TABLE(6358)
36+};
37+
38+const unsigned long *bcm63xx_regs_spi;
39+EXPORT_SYMBOL(bcm63xx_regs_spi);
40+
41+static __init void bcm63xx_spi_regs_init(void)
42+{
43+ if (BCMCPU_IS_6338())
44+ bcm63xx_regs_spi = bcm96338_regs_spi;
45+ if (BCMCPU_IS_6348())
46+ bcm63xx_regs_spi = bcm96348_regs_spi;
47+ if (BCMCPU_IS_6358())
48+ bcm63xx_regs_spi = bcm96358_regs_spi;
49+}
50+#else
51+static __init void bcm63xx_spi_regs_init(void) { }
52+#endif
53+
54+static struct resource spi_resources[] = {
55+ {
56+ .start = -1, /* filled at runtime */
57+ .end = -1, /* filled at runtime */
58+ .flags = IORESOURCE_MEM,
59+ },
60+ {
61+ .start = -1, /* filled at runtime */
62+ .flags = IORESOURCE_IRQ,
63+ },
64+};
65+
66+static struct bcm63xx_spi_pdata spi_pdata = {
67+ .bus_num = 0,
68+ .num_chipselect = 8,
69+ .speed_hz = 50000000, /* Fclk */
70+};
71+
72+static struct platform_device bcm63xx_spi_device = {
73+ .name = "bcm63xx-spi",
74+ .id = 0,
75+ .num_resources = ARRAY_SIZE(spi_resources),
76+ .resource = spi_resources,
77+ .dev = {
78+ .platform_data = &spi_pdata,
79+ },
80+};
81+
82+int __init bcm63xx_spi_register(void)
83+{
84+ spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
85+ spi_resources[0].end = spi_resources[0].start;
86+ spi_resources[0].end += RSET_SPI_SIZE - 1;
87+ spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
88+
89+ if (BCMCPU_IS_6345())
90+ return -ENODEV;
91+
92+ /* Fill in platform data */
93+ if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
94+ spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
95+
96+ if (BCMCPU_IS_6358())
97+ spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
98+
99+ bcm63xx_spi_regs_init();
100+
101+ return platform_device_register(&bcm63xx_spi_device);
102+}
103--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
104+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
105@@ -138,6 +138,7 @@ enum bcm63xx_regs_set {
106 #define RSET_ENET_SIZE 2048
107 #define RSET_ENETDMA_SIZE 2048
108 #define RSET_ENETSW_SIZE 65536
109+#define RSET_SPI_SIZE 256
110 #define RSET_UART_SIZE 24
111 #define RSET_UDC_SIZE 256
112 #define RSET_OHCI_SIZE 256
113@@ -289,7 +290,7 @@ enum bcm63xx_regs_set {
114 #define BCM_6358_UART0_BASE (0xfffe0100)
115 #define BCM_6358_UART1_BASE (0xfffe0120)
116 #define BCM_6358_GPIO_BASE (0xfffe0080)
117-#define BCM_6358_SPI_BASE (0xdeadbeef)
118+#define BCM_6358_SPI_BASE (0xfffe0800)
119 #define BCM_6358_SPI2_BASE (0xfffe0800)
120 #define BCM_6358_UDC0_BASE (0xfffe0400)
121 #define BCM_6358_OHCI0_BASE (0xfffe1400)
122@@ -478,6 +479,7 @@ static inline unsigned long bcm63xx_regs
123  */
124 enum bcm63xx_irq {
125     IRQ_TIMER = 0,
126+ IRQ_SPI,
127     IRQ_UART0,
128     IRQ_UART1,
129     IRQ_DSL,
130@@ -571,6 +573,7 @@ enum bcm63xx_irq {
131  * 6348 irqs
132  */
133 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
134+#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
135 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
136 #define BCM_6348_UART1_IRQ 0
137 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
138@@ -608,6 +611,7 @@ enum bcm63xx_irq {
139  * 6358 irqs
140  */
141 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
142+#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
143 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
144 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
145 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
146--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
147+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
148@@ -1007,4 +1007,116 @@
149 #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
150 #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
151 
152+/*************************************************************************
153+ * _REG relative to RSET_SPI
154+ *************************************************************************/
155+
156+/* BCM 6338 SPI core */
157+#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
158+#define SPI_BCM_6338_SPI_INT_STATUS 0x02
159+#define SPI_BCM_6338_SPI_INT_MASK_ST 0x03
160+#define SPI_BCM_6338_SPI_INT_MASK 0x04
161+#define SPI_BCM_6338_SPI_ST 0x05
162+#define SPI_BCM_6338_SPI_CLK_CFG 0x06
163+#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
164+#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
165+#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
166+#define SPI_BCM_6338_SPI_MSG_CTL 0x40
167+#define SPI_BCM_6338_SPI_MSG_DATA 0x41
168+#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
169+#define SPI_BCM_6338_SPI_RX_DATA 0x80
170+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
171+
172+/* BCM 6348 SPI core */
173+#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
174+#define SPI_BCM_6348_SPI_INT_STATUS 0x02
175+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
176+#define SPI_BCM_6348_SPI_INT_MASK 0x04
177+#define SPI_BCM_6348_SPI_ST 0x05
178+#define SPI_BCM_6348_SPI_CLK_CFG 0x06
179+#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
180+#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
181+#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
182+#define SPI_BCM_6348_SPI_MSG_CTL 0x40
183+#define SPI_BCM_6348_SPI_MSG_DATA 0x41
184+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
185+#define SPI_BCM_6348_SPI_RX_DATA 0x80
186+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
187+
188+/* BCM 6358 SPI core */
189+#define SPI_BCM_6358_SPI_MSG_CTL 0x00 /* 16-bits register */
190+
191+#define SPI_BCM_6358_SPI_MSG_DATA 0x02
192+#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
193+
194+#define SPI_BCM_6358_SPI_RX_DATA 0x400
195+#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
196+
197+#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
198+
199+#define SPI_BCM_6358_SPI_INT_STATUS 0x702
200+#define SPI_BCM_6358_SPI_INT_MASK_ST 0x703
201+
202+#define SPI_BCM_6358_SPI_INT_MASK 0x704
203+
204+#define SPI_BCM_6358_SPI_ST 0x705
205+
206+#define SPI_BCM_6358_SPI_CLK_CFG 0x706
207+
208+#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
209+#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
210+#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
211+
212+/* Shared SPI definitions */
213+
214+/* Message configuration */
215+#define SPI_FD_RW 0x00
216+#define SPI_HD_W 0x01
217+#define SPI_HD_R 0x02
218+#define SPI_BYTE_CNT_SHIFT 0
219+#define SPI_MSG_TYPE_SHIFT 14
220+
221+/* Command */
222+#define SPI_CMD_NOOP 0x00
223+#define SPI_CMD_SOFT_RESET 0x01
224+#define SPI_CMD_HARD_RESET 0x02
225+#define SPI_CMD_START_IMMEDIATE 0x03
226+#define SPI_CMD_COMMAND_SHIFT 0
227+#define SPI_CMD_COMMAND_MASK 0x000f
228+#define SPI_CMD_DEVICE_ID_SHIFT 4
229+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
230+#define SPI_CMD_ONE_BYTE_SHIFT 11
231+#define SPI_CMD_ONE_WIRE_SHIFT 12
232+#define SPI_DEV_ID_0 0
233+#define SPI_DEV_ID_1 1
234+#define SPI_DEV_ID_2 2
235+#define SPI_DEV_ID_3 3
236+
237+/* Interrupt mask */
238+#define SPI_INTR_CMD_DONE 0x01
239+#define SPI_INTR_RX_OVERFLOW 0x02
240+#define SPI_INTR_TX_UNDERFLOW 0x04
241+#define SPI_INTR_TX_OVERFLOW 0x08
242+#define SPI_INTR_RX_UNDERFLOW 0x10
243+#define SPI_INTR_CLEAR_ALL 0x1f
244+
245+/* Status */
246+#define SPI_RX_EMPTY 0x02
247+#define SPI_CMD_BUSY 0x04
248+#define SPI_SERIAL_BUSY 0x08
249+
250+/* Clock configuration */
251+#define SPI_CLK_20MHZ 0x00
252+#define SPI_CLK_0_391MHZ 0x01
253+#define SPI_CLK_0_781MHZ 0x02 /* default */
254+#define SPI_CLK_1_563MHZ 0x03
255+#define SPI_CLK_3_125MHZ 0x04
256+#define SPI_CLK_6_250MHZ 0x05
257+#define SPI_CLK_12_50MHZ 0x06
258+#define SPI_CLK_25MHZ 0x07
259+#define SPI_CLK_MASK 0x07
260+#define SPI_SSOFFTIME_MASK 0x38
261+#define SPI_SSOFFTIME_SHIFT 3
262+#define SPI_BYTE_SWAP 0x80
263+
264 #endif /* BCM63XX_REGS_H_ */
265--- /dev/null
266+++ b/drivers/spi/bcm63xx_spi.c
267@@ -0,0 +1,496 @@
268+/*
269+ * Broadcom BCM63xx SPI controller support
270+ *
271+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
272+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
273+ *
274+ * This program is free software; you can redistribute it and/or
275+ * modify it under the terms of the GNU General Public License
276+ * as published by the Free Software Foundation; either version 2
277+ * of the License, or (at your option) any later version.
278+ *
279+ * This program is distributed in the hope that it will be useful,
280+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
281+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
282+ * GNU General Public License for more details.
283+ *
284+ * You should have received a copy of the GNU General Public License
285+ * along with this program; if not, write to the
286+ * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
287+ */
288+
289+#include <linux/kernel.h>
290+#include <linux/init.h>
291+#include <linux/clk.h>
292+#include <linux/module.h>
293+#include <linux/platform_device.h>
294+#include <linux/delay.h>
295+#include <linux/interrupt.h>
296+#include <linux/spi/spi.h>
297+#include <linux/completion.h>
298+#include <linux/err.h>
299+
300+#include <bcm63xx_dev_spi.h>
301+
302+#define PFX KBUILD_MODNAME
303+#define DRV_VER "0.1.2"
304+
305+struct bcm63xx_spi {
306+ spinlock_t lock;
307+ int stopping;
308+ struct completion done;
309+
310+ void __iomem *regs;
311+ int irq;
312+
313+ /* Platform data */
314+ u32 speed_hz;
315+ unsigned fifo_size;
316+
317+ /* Data buffers */
318+ const unsigned char *tx_ptr;
319+ unsigned char *rx_ptr;
320+
321+ /* data iomem */
322+ u8 __iomem *tx_io;
323+ const u8 __iomem *rx_io;
324+
325+ int remaining_bytes;
326+
327+ struct clk *clk;
328+ struct platform_device *pdev;
329+};
330+
331+static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
332+ unsigned int offset)
333+{
334+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
335+}
336+
337+static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
338+ unsigned int offset)
339+{
340+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
341+}
342+
343+static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
344+ u8 value, unsigned int offset)
345+{
346+ bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
347+}
348+
349+static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
350+ u16 value, unsigned int offset)
351+{
352+ bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
353+}
354+
355+static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
356+ struct spi_transfer *t)
357+{
358+ u8 bits_per_word;
359+ u8 clk_cfg;
360+ u32 hz;
361+ unsigned int div;
362+
363+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
364+
365+ bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
366+ hz = (t) ? t->speed_hz : spi->max_speed_hz;
367+ if (bits_per_word != 8) {
368+ dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
369+ __func__, bits_per_word);
370+ return -EINVAL;
371+ }
372+
373+ if (spi->chip_select > spi->master->num_chipselect) {
374+ dev_err(&spi->dev, "%s, unsupported slave %d\n",
375+ __func__, spi->chip_select);
376+ return -EINVAL;
377+ }
378+
379+ /* Check clock setting */
380+ div = (bs->speed_hz / hz);
381+ switch (div) {
382+ case 2:
383+ clk_cfg = SPI_CLK_25MHZ;
384+ break;
385+ case 4:
386+ clk_cfg = SPI_CLK_12_50MHZ;
387+ break;
388+ case 8:
389+ clk_cfg = SPI_CLK_6_250MHZ;
390+ break;
391+ case 16:
392+ clk_cfg = SPI_CLK_3_125MHZ;
393+ break;
394+ case 32:
395+ clk_cfg = SPI_CLK_1_563MHZ;
396+ break;
397+ case 64:
398+ clk_cfg = SPI_CLK_0_781MHZ;
399+ break;
400+ case 128:
401+ default:
402+ /* Set to slowest mode for compatibility */
403+ clk_cfg = SPI_CLK_0_391MHZ;
404+ break;
405+ }
406+
407+ bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
408+ dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
409+ div, hz, clk_cfg);
410+
411+ return 0;
412+}
413+
414+/* the spi->mode bits understood by this driver: */
415+#define MODEBITS (SPI_CPOL | SPI_CPHA)
416+
417+static int bcm63xx_spi_setup(struct spi_device *spi)
418+{
419+ struct bcm63xx_spi *bs;
420+ int ret;
421+
422+ bs = spi_master_get_devdata(spi->master);
423+
424+ if (bs->stopping)
425+ return -ESHUTDOWN;
426+
427+ if (!spi->bits_per_word)
428+ spi->bits_per_word = 8;
429+
430+ if (spi->mode & ~MODEBITS) {
431+ dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
432+ __func__, spi->mode & ~MODEBITS);
433+ return -EINVAL;
434+ }
435+
436+ ret = bcm63xx_spi_setup_transfer(spi, NULL);
437+ if (ret < 0) {
438+ dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
439+ spi->mode & ~MODEBITS);
440+ return ret;
441+ }
442+
443+ dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
444+ __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
445+
446+ return 0;
447+}
448+
449+/* Fill the TX FIFO with as many bytes as possible */
450+static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
451+{
452+ u8 size;
453+
454+ /* Fill the Tx FIFO with as many bytes as possible */
455+ size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
456+ bs->fifo_size;
457+ memcpy_toio(bs->tx_io, bs->tx_ptr, size);
458+ bs->remaining_bytes -= size;
459+}
460+
461+static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
462+{
463+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
464+ u16 msg_ctl;
465+ u16 cmd;
466+
467+ dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
468+ t->tx_buf, t->rx_buf, t->len);
469+
470+ /* Transmitter is inhibited */
471+ bs->tx_ptr = t->tx_buf;
472+ bs->rx_ptr = t->rx_buf;
473+ init_completion(&bs->done);
474+
475+ if (t->tx_buf) {
476+ bs->remaining_bytes = t->len;
477+ bcm63xx_spi_fill_tx_fifo(bs);
478+ }
479+
480+ /* Enable the command done interrupt which
481+ * we use to determine completion of a command */
482+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
483+
484+ /* Fill in the Message control register */
485+ msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
486+
487+ if (t->rx_buf && t->tx_buf)
488+ msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
489+ else if (t->rx_buf)
490+ msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
491+ else if (t->tx_buf)
492+ msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
493+
494+ bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
495+
496+ /* Issue the transfer */
497+ cmd = SPI_CMD_START_IMMEDIATE;
498+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
499+ cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
500+ bcm_spi_writew(bs, cmd, SPI_CMD);
501+ wait_for_completion(&bs->done);
502+
503+ /* Disable the CMD_DONE interrupt */
504+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
505+
506+ return t->len - bs->remaining_bytes;
507+}
508+
509+static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
510+{
511+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
512+ struct spi_transfer *t;
513+ int ret = 0;
514+
515+ if (unlikely(list_empty(&m->transfers)))
516+ return -EINVAL;
517+
518+ if (bs->stopping)
519+ return -ESHUTDOWN;
520+
521+ list_for_each_entry(t, &m->transfers, transfer_list) {
522+ ret += bcm63xx_txrx_bufs(spi, t);
523+ }
524+
525+ m->complete(m->context);
526+
527+ return ret;
528+}
529+
530+/* This driver supports single master mode only. Hence
531+ * CMD_DONE is the only interrupt we care about
532+ */
533+static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
534+{
535+ struct spi_master *master = (struct spi_master *)dev_id;
536+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
537+ u8 intr;
538+ u16 cmd;
539+
540+ /* Read interupts and clear them immediately */
541+ intr = bcm_spi_readb(bs, SPI_INT_STATUS);
542+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
543+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
544+
545+ /* A tansfer completed */
546+ if (intr & SPI_INTR_CMD_DONE) {
547+ u8 rx_tail;
548+
549+ rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
550+
551+ /* Read out all the data */
552+ if (rx_tail)
553+ memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
554+
555+ /* See if there is more data to send */
556+ if (bs->remaining_bytes > 0) {
557+ bcm63xx_spi_fill_tx_fifo(bs);
558+
559+ /* Start the transfer */
560+ bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
561+ SPI_MSG_CTL);
562+ cmd = bcm_spi_readw(bs, SPI_CMD);
563+ cmd |= SPI_CMD_START_IMMEDIATE;
564+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
565+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
566+ bcm_spi_writew(bs, cmd, SPI_CMD);
567+ } else {
568+ complete(&bs->done);
569+ }
570+ }
571+
572+ return IRQ_HANDLED;
573+}
574+
575+
576+static int __init bcm63xx_spi_probe(struct platform_device *pdev)
577+{
578+ struct resource *r;
579+ struct device *dev = &pdev->dev;
580+ struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
581+ int irq;
582+ struct spi_master *master;
583+ struct clk *clk;
584+ struct bcm63xx_spi *bs;
585+ int ret;
586+
587+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
588+ if (!r) {
589+ dev_err(dev, "no iomem\n");
590+ ret = -ENXIO;
591+ goto out;
592+ }
593+
594+ irq = platform_get_irq(pdev, 0);
595+ if (irq < 0) {
596+ dev_err(dev, "no irq\n");
597+ ret = -ENXIO;
598+ goto out;
599+ }
600+
601+ clk = clk_get(dev, "spi");
602+ if (IS_ERR(clk)) {
603+ dev_err(dev, "no clock for device\n");
604+ ret = -ENODEV;
605+ goto out;
606+ }
607+
608+ master = spi_alloc_master(dev, sizeof(*bs));
609+ if (!master) {
610+ dev_err(dev, "out of memory\n");
611+ ret = -ENOMEM;
612+ goto out_free;
613+ }
614+
615+ bs = spi_master_get_devdata(master);
616+ init_completion(&bs->done);
617+
618+ platform_set_drvdata(pdev, master);
619+ bs->pdev = pdev;
620+
621+ if (!request_mem_region(r->start, r->end - r->start, PFX)) {
622+ dev_err(dev, "iomem request failed\n");
623+ ret = -ENXIO;
624+ goto out_put_master;
625+ }
626+
627+ bs->regs = ioremap_nocache(r->start, r->end - r->start);
628+ if (!bs->regs) {
629+ dev_err(dev, "unable to ioremap regs\n");
630+ ret = -ENOMEM;
631+ goto out_put_master;
632+ }
633+ bs->irq = irq;
634+ bs->clk = clk;
635+ bs->fifo_size = pdata->fifo_size;
636+
637+ ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
638+ if (ret) {
639+ dev_err(dev, "unable to request irq\n");
640+ goto out_unmap;
641+ }
642+
643+ master->bus_num = pdata->bus_num;
644+ master->num_chipselect = pdata->num_chipselect;
645+ master->setup = bcm63xx_spi_setup;
646+ master->transfer = bcm63xx_transfer;
647+ bs->speed_hz = pdata->speed_hz;
648+ bs->stopping = 0;
649+ bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
650+ bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
651+ spin_lock_init(&bs->lock);
652+
653+ /* Initialize hardware */
654+ clk_enable(bs->clk);
655+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
656+
657+ /* register and we are done */
658+ ret = spi_register_master(master);
659+ if (ret) {
660+ dev_err(dev, "spi register failed\n");
661+ goto out_reset_hw;
662+ }
663+
664+ dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
665+ r->start, irq, bs->fifo_size, DRV_VER);
666+
667+ return 0;
668+
669+out_reset_hw:
670+ clk_disable(clk);
671+ free_irq(irq, master);
672+out_unmap:
673+ iounmap(bs->regs);
674+out_put_master:
675+ spi_master_put(master);
676+out_free:
677+ clk_put(clk);
678+out:
679+ return ret;
680+}
681+
682+static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
683+{
684+ struct spi_master *master = platform_get_drvdata(pdev);
685+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
686+ struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
687+
688+ /* reset spi block */
689+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
690+ spin_lock(&bs->lock);
691+ bs->stopping = 1;
692+
693+ /* HW shutdown */
694+ clk_disable(bs->clk);
695+ clk_put(bs->clk);
696+
697+ spin_unlock(&bs->lock);
698+
699+ free_irq(bs->irq, master);
700+ iounmap(bs->regs);
701+ release_mem_region(r->start, r->end - r->start);
702+ platform_set_drvdata(pdev, 0);
703+ spi_unregister_master(master);
704+
705+ return 0;
706+}
707+
708+#ifdef CONFIG_PM
709+static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
710+{
711+ struct spi_master *master = platform_get_drvdata(pdev);
712+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
713+
714+ clk_disable(bs->clk);
715+
716+ return 0;
717+}
718+
719+static int bcm63xx_spi_resume(struct platform_device *pdev)
720+{
721+ struct spi_master *master = platform_get_drvdata(pdev);
722+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
723+
724+ clk_enable(bs->clk);
725+
726+ return 0;
727+}
728+#else
729+#define bcm63xx_spi_suspend NULL
730+#define bcm63xx_spi_resume NULL
731+#endif
732+
733+static struct platform_driver bcm63xx_spi_driver = {
734+ .driver = {
735+ .name = "bcm63xx-spi",
736+ .owner = THIS_MODULE,
737+ },
738+ .probe = bcm63xx_spi_probe,
739+ .remove = __exit_p(bcm63xx_spi_remove),
740+ .suspend = bcm63xx_spi_suspend,
741+ .resume = bcm63xx_spi_resume,
742+};
743+
744+
745+static int __init bcm63xx_spi_init(void)
746+{
747+ return platform_driver_register(&bcm63xx_spi_driver);
748+}
749+
750+static void __exit bcm63xx_spi_exit(void)
751+{
752+ platform_driver_unregister(&bcm63xx_spi_driver);
753+}
754+
755+module_init(bcm63xx_spi_init);
756+module_exit(bcm63xx_spi_exit);
757+
758+MODULE_ALIAS("platform:bcm63xx_spi");
759+MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
760+MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
761+MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
762+MODULE_LICENSE("GPL");
763+MODULE_VERSION(DRV_VER);
764--- a/drivers/spi/Kconfig
765+++ b/drivers/spi/Kconfig
766@@ -74,6 +74,12 @@ config SPI_ATMEL
767       This selects a driver for the Atmel SPI Controller, present on
768       many AT32 (AVR32) and AT91 (ARM) chips.
769 
770+config SPI_BCM63XX
771+ tristate "Broadcom BCM63xx SPI controller"
772+ depends on BCM63XX
773+ help
774+ This is the SPI controller master driver for Broadcom BCM63xx SoC.
775+
776 config SPI_BFIN
777     tristate "SPI controller driver for ADI Blackfin5xx"
778     depends on BLACKFIN
779--- a/drivers/spi/Makefile
780+++ b/drivers/spi/Makefile
781@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.
782 obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
783 obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
784 obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
785+obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
786 obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
787 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
788 obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
789--- /dev/null
790+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
791@@ -0,0 +1,85 @@
792+#ifndef BCM63XX_DEV_SPI_H
793+#define BCM63XX_DEV_SPI_H
794+
795+#include <linux/types.h>
796+#include <bcm63xx_io.h>
797+#include <bcm63xx_regs.h>
798+
799+int __init bcm63xx_spi_register(void);
800+
801+struct bcm63xx_spi_pdata {
802+ unsigned int fifo_size;
803+ int bus_num;
804+ int num_chipselect;
805+ u32 speed_hz;
806+};
807+
808+enum bcm63xx_regs_spi {
809+ SPI_CMD,
810+ SPI_INT_STATUS,
811+ SPI_INT_MASK_ST,
812+ SPI_INT_MASK,
813+ SPI_ST,
814+ SPI_CLK_CFG,
815+ SPI_FILL_BYTE,
816+ SPI_MSG_TAIL,
817+ SPI_RX_TAIL,
818+ SPI_MSG_CTL,
819+ SPI_MSG_DATA,
820+ SPI_RX_DATA,
821+};
822+
823+#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
824+ case SPI_## __rset: \
825+ return SPI_BCM_## __cpu ##_SPI_## __rset;
826+
827+#define __GEN_SPI_RSET(__cpu) \
828+ switch (reg) { \
829+ __GEN_SPI_RSET_BASE(__cpu, CMD) \
830+ __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
831+ __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
832+ __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
833+ __GEN_SPI_RSET_BASE(__cpu, ST) \
834+ __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
835+ __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
836+ __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
837+ __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
838+ __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
839+ __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
840+ __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
841+ }
842+
843+#define __GEN_SPI_REGS_TABLE(__cpu) \
844+ [SPI_CMD] = SPI_BCM_## __cpu ##_SPI_CMD, \
845+ [SPI_INT_STATUS] = SPI_BCM_## __cpu ##_SPI_INT_STATUS, \
846+ [SPI_INT_MASK_ST] = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST, \
847+ [SPI_INT_MASK] = SPI_BCM_## __cpu ##_SPI_INT_MASK, \
848+ [SPI_ST] = SPI_BCM_## __cpu ##_SPI_ST, \
849+ [SPI_CLK_CFG] = SPI_BCM_## __cpu ##_SPI_CLK_CFG, \
850+ [SPI_FILL_BYTE] = SPI_BCM_## __cpu ##_SPI_FILL_BYTE, \
851+ [SPI_MSG_TAIL] = SPI_BCM_## __cpu ##_SPI_MSG_TAIL, \
852+ [SPI_RX_TAIL] = SPI_BCM_## __cpu ##_SPI_RX_TAIL, \
853+ [SPI_MSG_CTL] = SPI_BCM_## __cpu ##_SPI_MSG_CTL, \
854+ [SPI_MSG_DATA] = SPI_BCM_## __cpu ##_SPI_MSG_DATA, \
855+ [SPI_RX_DATA] = SPI_BCM_## __cpu ##_SPI_RX_DATA,
856+
857+static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
858+{
859+#ifdef BCMCPU_RUNTIME_DETECT
860+ extern const unsigned long *bcm63xx_regs_spi;
861+ return bcm63xx_regs_spi[reg];
862+#else
863+#ifdef CONFIG_BCM63XX_CPU_6338
864+ __GEN_SPI_RSET(6338)
865+#endif
866+#ifdef CONFIG_BCM63XX_CPU_6348
867+ __GEN_SPI_RSET(6348)
868+#endif
869+#ifdef CONFIG_BCM63XX_CPU_6358
870+ __GEN_SPI_RSET(6358)
871+#endif
872+#endif
873+ return 0;
874+}
875+
876+#endif /* BCM63XX_DEV_SPI_H */
877--- a/arch/mips/bcm63xx/Makefile
878+++ b/arch/mips/bcm63xx/Makefile
879@@ -1,5 +1,5 @@
880 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
881- dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o \
882+ dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \
883            dev-usb-ehci.o dev-usb-ohci.o dev-usb-udc.o dev-wdt.o
884 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
885 
886--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
887+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
888@@ -31,6 +31,7 @@
889 #include <bcm63xx_dev_usb_ohci.h>
890 #include <bcm63xx_dev_usb_ehci.h>
891 #include <bcm63xx_dev_usb_udc.h>
892+#include <bcm63xx_dev_spi.h>
893 #include <board_bcm963xx.h>
894 
895 #define PFX "board_bcm963xx: "
896@@ -955,6 +956,8 @@ int __init board_register_devices(void)
897     if (board.num_spis)
898         spi_register_board_info(board.spis, board.num_spis);
899 
900+ bcm63xx_spi_register();
901+
902     /* read base address of boot chip select (0) */
903     val = bcm_mpi_readl(MPI_CSBASE_REG(0));
904     val &= MPI_CSBASE_BASE_MASK;
905

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