Root/target/linux/cns21xx/patches-2.6.37/100-cns21xx-core.patch

1--- a/arch/arm/Kconfig
2+++ b/arch/arm/Kconfig
3@@ -179,6 +179,11 @@ config ARM_L1_CACHE_SHIFT_6
4     help
5       Setting ARM L1 cache line size to 64 Bytes.
6 
7+config ARM_L1_CACHE_SHIFT_4
8+ bool
9+ help
10+ Setting ARM L1 cache line size to 16 bytes.
11+
12 config VECTORS_BASE
13     hex
14     default 0xffff0000 if MMU || CPU_HIGH_VECTOR
15@@ -286,6 +291,15 @@ config ARCH_BCMRING
16     help
17       Support for Broadcom's BCMRing platform.
18 
19+config ARCH_CNS21XX
20+ bool "Cavium Networks CNS21xx family"
21+ select CPU_FA526
22+ select PLAT_FA
23+ select PLAT_FA_TIME
24+ select ARM_L1_CACHE_SHIFT_4
25+ help
26+ Support for Cavium Networks CNS21xx family.
27+
28 config ARCH_CLPS711X
29     bool "Cirrus Logic CLPS711x/EP721x-based"
30     select CPU_ARM720T
31@@ -864,6 +878,8 @@ source "arch/arm/mach-davinci/Kconfig"
32 
33 source "arch/arm/mach-dove/Kconfig"
34 
35+source "arch/arm/mach-cns21xx/Kconfig"
36+
37 source "arch/arm/mach-ep93xx/Kconfig"
38 
39 source "arch/arm/mach-footbridge/Kconfig"
40--- /dev/null
41+++ b/arch/arm/mach-cns21xx/Kconfig
42@@ -0,0 +1,6 @@
43+if ARCH_CNS21XX
44+
45+menu "Cavium Networks CNS21xx based machines"
46+endmenu
47+
48+endif
49--- /dev/null
50+++ b/arch/arm/mach-cns21xx/Makefile
51@@ -0,0 +1,10 @@
52+#
53+# Makefile for the linux kernel.
54+#
55+
56+# Object file lists.
57+
58+obj-y := core.o irq.o mm.o time.o
59+
60+# machine specific files
61+
62--- /dev/null
63+++ b/arch/arm/mach-cns21xx/Makefile.boot
64@@ -0,0 +1,3 @@
65+ zreladdr-y := 0x00008000
66+params_phys-y := 0x00000100
67+initrd_phys-y := 0x00C00000
68--- a/arch/arm/Makefile
69+++ b/arch/arm/Makefile
70@@ -129,6 +129,7 @@ endif
71 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
72 machine-$(CONFIG_ARCH_AT91) := at91
73 machine-$(CONFIG_ARCH_BCMRING) := bcmring
74+machine-$(CONFIG_ARCH_CNS21XX) := cns21xx
75 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
76 machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
77 machine-$(CONFIG_ARCH_DAVINCI) := davinci
78--- /dev/null
79+++ b/arch/arm/mach-cns21xx/common.h
80@@ -0,0 +1,18 @@
81+/*
82+ * Copyright (c) 2008 Cavium Networks
83+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
84+ *
85+ * This file is free software; you can redistribute it and/or modify
86+ * it under the terms of the GNU General Public License, Version 2, as
87+ * published by the Free Software Foundation.
88+ */
89+
90+#ifndef _MACH_CNS21XX_COMMON_H
91+#define _MACH_CNS21XX_COMMON_H
92+
93+void __init cns21xx_map_io(void);
94+void __init cns21xx_init_irq(void);
95+
96+extern struct sys_timer cns21xx_timer;
97+
98+#endif /* _MACH_CNS21XX_COMMON_H */
99--- /dev/null
100+++ b/arch/arm/mach-cns21xx/mm.c
101@@ -0,0 +1,170 @@
102+/*
103+ * Copyright (c) 2008 Cavium Networks
104+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
105+ *
106+ * This file is free software; you can redistribute it and/or modify
107+ * it under the terms of the GNU General Public License, Version 2, as
108+ * published by the Free Software Foundation.
109+ */
110+
111+#include <linux/mm.h>
112+#include <linux/init.h>
113+
114+#include <asm/mach/map.h>
115+
116+#include <mach/hardware.h>
117+#include <mach/cns21xx.h>
118+
119+#include "common.h"
120+
121+/*
122+ * Standard IO mapping
123+ */
124+static struct map_desc cns21xx_io_desc[] __initdata = {
125+ {
126+ .virtual = CNS21XX_FLASH_BANK0_BASE_VIRT,
127+ .pfn = __phys_to_pfn(CNS21XX_FLASH_BANK0_BASE),
128+ .length = SZ_256M,
129+ .type = MT_DEVICE
130+ }, {
131+ .virtual = CNS21XX_IDE_DEVICE_BASE_VIRT,
132+ .pfn = __phys_to_pfn(CNS21XX_IDE_DEVICE_BASE),
133+ .length = SZ_4K,
134+ .type = MT_DEVICE
135+ }, {
136+ .virtual = CNS21XX_GDMAC_BASE_VIRT,
137+ .pfn = __phys_to_pfn(CNS21XX_GDMAC_BASE),
138+ .length = SZ_4K,
139+ .type = MT_DEVICE
140+ }, {
141+ .virtual = CNS21XX_NIC_BASE_VIRT,
142+ .pfn = __phys_to_pfn(CNS21XX_NIC_BASE),
143+ .length = SZ_4K,
144+ .type = MT_DEVICE
145+ }, {
146+ .virtual = CNS21XX_SPI_BASE_VIRT,
147+ .pfn = __phys_to_pfn(CNS21XX_SPI_BASE),
148+ .length = SZ_4K,
149+ .type = MT_DEVICE
150+ }, {
151+ .virtual = CNS21XX_PCM_BASE_VIRT,
152+ .pfn = __phys_to_pfn(CNS21XX_PCM_BASE),
153+ .length = SZ_4K,
154+ .type = MT_DEVICE
155+ }, {
156+ .virtual = CNS21XX_I2C_BASE_VIRT,
157+ .pfn = __phys_to_pfn(CNS21XX_I2C_BASE),
158+ .length = SZ_4K,
159+ .type = MT_DEVICE
160+ }, {
161+ .virtual = CNS21XX_I2S_BASE_VIRT,
162+ .pfn = __phys_to_pfn(CNS21XX_I2S_BASE),
163+ .length = SZ_4K,
164+ .type = MT_DEVICE
165+ }, {
166+ .virtual = CNS21XX_DDRC_BASE_VIRT,
167+ .pfn = __phys_to_pfn(CNS21XX_DDRC_BASE),
168+ .length = SZ_4K,
169+ .type = MT_DEVICE
170+ }, {
171+ .virtual = CNS21XX_SMC_BASE_VIRT,
172+ .pfn = __phys_to_pfn(CNS21XX_SMC_BASE),
173+ .length = SZ_4K,
174+ .type = MT_DEVICE
175+ }, {
176+ .virtual = CNS21XX_IDE_CTRL_BASE_VIRT,
177+ .pfn = __phys_to_pfn(CNS21XX_IDE_CTRL_BASE),
178+ .length = SZ_4K,
179+ .type = MT_DEVICE
180+ }, {
181+ .virtual = CNS21XX_MISC_BASE_VIRT,
182+ .pfn = __phys_to_pfn(CNS21XX_MISC_BASE),
183+ .length = SZ_4K,
184+ .type = MT_DEVICE
185+ }, {
186+ .virtual = CNS21XX_CPM_BASE_VIRT,
187+ .pfn = __phys_to_pfn(CNS21XX_CPM_BASE),
188+ .length = SZ_4K,
189+ .type = MT_DEVICE
190+ }, {
191+ .virtual = CNS21XX_UART0_BASE_VIRT,
192+ .pfn = __phys_to_pfn(CNS21XX_UART0_BASE),
193+ .length = SZ_4K,
194+ .type = MT_DEVICE
195+ }, {
196+ .virtual = CNS21XX_UART1_BASE_VIRT,
197+ .pfn = __phys_to_pfn(CNS21XX_UART1_BASE),
198+ .length = SZ_4K,
199+ .type = MT_DEVICE
200+ }, {
201+ .virtual = CNS21XX_TIMER_BASE_VIRT,
202+ .pfn = __phys_to_pfn(CNS21XX_TIMER_BASE),
203+ .length = SZ_4K,
204+ .type = MT_DEVICE
205+ }, {
206+ .virtual = CNS21XX_WDT_BASE_VIRT,
207+ .pfn = __phys_to_pfn(CNS21XX_WDT_BASE),
208+ .length = SZ_4K,
209+ .type = MT_DEVICE
210+ }, {
211+ .virtual = CNS21XX_RTC_BASE_VIRT,
212+ .pfn = __phys_to_pfn(CNS21XX_RTC_BASE),
213+ .length = SZ_4K,
214+ .type = MT_DEVICE
215+ }, {
216+ .virtual = CNS21XX_GPIOA_BASE_VIRT,
217+ .pfn = __phys_to_pfn(CNS21XX_GPIOA_BASE),
218+ .length = SZ_4K,
219+ .type = MT_DEVICE
220+ }, {
221+ .virtual = CNS21XX_GPIOB_BASE_VIRT,
222+ .pfn = __phys_to_pfn(CNS21XX_GPIOB_BASE),
223+ .length = SZ_4K,
224+ .type = MT_DEVICE
225+ }, {
226+ .virtual = CNS21XX_PCI_CFGDATA_BASE_VIRT,
227+ .pfn = __phys_to_pfn(CNS21XX_PCI_CFGDATA_BASE),
228+ .length = SZ_4K,
229+ .type = MT_DEVICE
230+ }, {
231+ .virtual = CNS21XX_PCI_CFGADDR_BASE_VIRT,
232+ .pfn = __phys_to_pfn(CNS21XX_PCI_CFGADDR_BASE),
233+ .length = SZ_4K,
234+ .type = MT_DEVICE
235+ }, {
236+ .virtual = CNS21XX_OHCI_CONFIG_BASE_VIRT,
237+ .pfn = __phys_to_pfn(CNS21XX_OHCI_CONFIG_BASE),
238+ .length = SZ_4K,
239+ .type = MT_DEVICE
240+ }, {
241+ .virtual = CNS21XX_OHCI_CTRL_BASE_VIRT,
242+ .pfn = __phys_to_pfn(CNS21XX_OHCI_CTRL_BASE),
243+ .length = SZ_4K,
244+ .type = MT_DEVICE
245+ }, {
246+ .virtual = CNS21XX_EHCI_CONFIG_BASE_VIRT,
247+ .pfn = __phys_to_pfn(CNS21XX_EHCI_CONFIG_BASE),
248+ .length = SZ_4K,
249+ .type = MT_DEVICE
250+ }, {
251+ .virtual = CNS21XX_EHCI_CTRL_BASE_VIRT,
252+ .pfn = __phys_to_pfn(CNS21XX_EHCI_CTRL_BASE),
253+ .length = SZ_4K,
254+ .type = MT_DEVICE
255+ }, {
256+ .virtual = CNS21XX_USB_DEVICE_BASE_VIRT,
257+ .pfn = __phys_to_pfn(CNS21XX_USB_DEVICE_BASE),
258+ .length = SZ_4K,
259+ .type = MT_DEVICE
260+ }, {
261+ .virtual = CNS21XX_INTC_BASE_VIRT,
262+ .pfn = __phys_to_pfn(CNS21XX_INTC_BASE),
263+ .length = SZ_4K,
264+ .type = MT_DEVICE
265+ }
266+};
267+
268+void __init cns21xx_map_io(void)
269+{
270+ iotable_init(cns21xx_io_desc, ARRAY_SIZE(cns21xx_io_desc));
271+}
272--- /dev/null
273+++ b/arch/arm/mach-cns21xx/include/mach/hardware.h
274@@ -0,0 +1,23 @@
275+/*
276+ * Copyright (c) 2008 Cavium Networks
277+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
278+ *
279+ * This file is free software; you can redistribute it and/or modify
280+ * it under the terms of the GNU General Public License, Version 2, as
281+ * published by the Free Software Foundation.
282+ */
283+
284+#ifndef _CNS21XX_HARDWARE_H
285+#define _CNS21XX_HARDWARE_H
286+
287+#define PCIBIOS_MIN_IO 0x00000000
288+#define PCIBIOS_MIN_MEM 0x00000000
289+
290+#ifndef __ASSEMBLY__
291+extern unsigned long cns21xx_get_pll_freq(void);
292+extern unsigned long cns21xx_get_cpu_freq(void);
293+extern unsigned long cns21xx_get_ahb_freq(void);
294+extern unsigned long cns21xx_get_apb_freq(void);
295+#endif
296+
297+#endif /* _CNS21XX_HARDWARE_H */
298--- /dev/null
299+++ b/arch/arm/mach-cns21xx/include/mach/vmalloc.h
300@@ -0,0 +1,15 @@
301+/*
302+ * Copyright (c) 2008 Cavium Networks
303+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
304+ *
305+ * This file is free software; you can redistribute it and/or modify
306+ * it under the terms of the GNU General Public License, Version 2, as
307+ * published by the Free Software Foundation.
308+ */
309+
310+#ifndef _CNS21XX_VMALLOC_H
311+#define _CNS21XX_VMALLOC_H
312+
313+#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
314+
315+#endif /* _CNS21XX_VMALLOC_H */
316--- /dev/null
317+++ b/arch/arm/mach-cns21xx/include/mach/debug-macro.S
318@@ -0,0 +1,25 @@
319+/*
320+ * Copyright (c) 2008 Cavium Networks
321+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
322+ *
323+ * This file is free software; you can redistribute it and/or modify
324+ * it under the terms of the GNU General Public License, Version 2, as
325+ * published by the Free Software Foundation.
326+ */
327+
328+#include <mach/cns21xx.h>
329+
330+/* TODO: make it configurable */
331+#define CNS21XX_DEBUG_UART_BASE CNS21XX_UART0_BASE
332+#define CNS21XX_DEBUG_UART_BASE_VIRT CNS21XX_UART0_BASE_VIRT
333+
334+ .macro addruart, rp, rv
335+ mov \rp, #(CNS21XX_DEBUG_UART_BASE) @ physical
336+ mov \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0xff000000) @virtual
337+ orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x00ff0000)
338+ orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x0000ff00)
339+ orr \rv, \rv, #(CNS21XX_DEBUG_UART_BASE_VIRT & 0x000000ff)
340+ .endm
341+
342+#define UART_SHIFT 2
343+#include <asm/hardware/debug-8250.S>
344--- /dev/null
345+++ b/arch/arm/mach-cns21xx/include/mach/entry-macro.S
346@@ -0,0 +1,39 @@
347+/*
348+ * Copyright (c) 2008 Cavium Networks
349+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
350+ *
351+ * This file is free software; you can redistribute it and/or modify
352+ * it under the terms of the GNU General Public License, Version 2, as
353+ * published by the Free Software Foundation.
354+ */
355+
356+#include <mach/cns21xx.h>
357+#include <mach/irqs.h>
358+
359+#define INTC_IRQ_STATUS 0x1c
360+
361+ .macro disable_fiq
362+ .endm
363+
364+ .macro get_irqnr_preamble, base, tmp
365+ .endm
366+
367+ .macro arch_ret_to_user, tmp1, tmp2
368+ .endm
369+
370+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
371+ ldr \base, =(CNS21XX_INTC_BASE_VIRT + INTC_IRQ_STATUS)
372+ ldr \irqstat, [\base]
373+ mov \irqnr, #0
374+9001:
375+ tst \irqstat, #1
376+ bne 9002f
377+ add \irqnr, \irqnr, #1
378+ mov \irqstat, \irqstat, lsr #1
379+ cmp \irqnr, #CNS21XX_NR_INTC_IRQS
380+ bcc 9001b
381+9002:
382+ .endm
383+
384+ .macro irq_prio_table
385+ .endm
386--- /dev/null
387+++ b/arch/arm/mach-cns21xx/include/mach/io.h
388@@ -0,0 +1,18 @@
389+/*
390+ * Copyright (c) 2008 Cavium Networks
391+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
392+ *
393+ * This file is free software; you can redistribute it and/or modify
394+ * it under the terms of the GNU General Public License, Version 2, as
395+ * published by the Free Software Foundation.
396+ */
397+
398+#ifndef _CNS21XX_IO_H
399+#define _CNS21XX_IO_H
400+
401+#define IO_SPACE_LIMIT 0xffffffff
402+
403+#define __io(p) __typesafe_io(p)
404+#define __mem_pci(a) (a)
405+
406+#endif /* _CNS21XX_IO_H */
407--- /dev/null
408+++ b/arch/arm/mach-cns21xx/include/mach/irqs.h
409@@ -0,0 +1,53 @@
410+/*
411+ * Copyright (c) 2008 Cavium Networks
412+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
413+ *
414+ * This file is free software; you can redistribute it and/or modify
415+ * it under the terms of the GNU General Public License, Version 2, as
416+ * published by the Free Software Foundation.
417+ */
418+
419+#ifndef _CNS21XX_IRQS_H
420+#define _CNS21XX_IRQS_H
421+
422+#define CNS21XX_IRQ_TIMER1 0
423+#define CNS21XX_IRQ_TIMER2 1
424+#define CNS21XX_IRQ_CPM 2
425+#define CNS21XX_IRQ_WDT 3
426+#define CNS21XX_IRQ_GPIO 4
427+#define CNS21XX_IRQ_PCI_INTA 5
428+#define CNS21XX_IRQ_PCI_INTB 6
429+#define CNS21XX_IRQ_PCI_BROKEN 7
430+#define CNS21XX_IRQ_AHB2PCI 8
431+#define CNS21XX_IRQ_UART0 9
432+#define CNS21XX_IRQ_UART1 10
433+#define CNS21XX_IRQ_GDMAC_TC 11
434+#define CNS21XX_IRQ_GDMAC_ERR 12
435+#define CNS21XX_IRQ_PCMCIA 13
436+#define CNS21XX_IRQ_RTC 14
437+#define CNS21XX_IRQ_PCM 15
438+#define CNS21XX_IRQ_USB_DEVICE 16
439+#define CNS21XX_IRQ_IDE 17
440+#define CNS21XX_IRQ_NIC_STATUS 18
441+#define CNS21XX_IRQ_NIC_TXTC 19
442+#define CNS21XX_IRQ_NIC_RXRC 20
443+#define CNS21XX_IRQ_NIC_TXQE 21
444+#define CNS21XX_IRQ_NIC_RXQF 22
445+#define CNS21XX_IRQ_OHCI 23
446+#define CNS21XX_IRQ_EHCI 24
447+#define CNS21XX_IRQ_I2S 25
448+#define CNS21XX_IRQ_SPI 26
449+#define CNS21XX_IRQ_I2C 27
450+#define CNS21XX_IRQ_USB_VBUS 28
451+#define CNS21XX_IRQ_EXT_29 29
452+#define CNS21XX_IRQ_EXT_30 30
453+#define CNS21XX_IRQ_HSDMAC 31
454+
455+#define CNS21XX_GPIO_IRQ_BASE 32
456+
457+#define CNS21XX_NR_INTC_IRQS 32
458+#define CNS21XX_NR_GPIO_IRQS 64
459+
460+#define NR_IRQS 96
461+
462+#endif /* _CNS21XX_IRQS_H */
463--- /dev/null
464+++ b/arch/arm/mach-cns21xx/include/mach/timex.h
465@@ -0,0 +1,15 @@
466+/*
467+ * Copyright (c) 2008 Cavium Networks
468+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
469+ *
470+ * This file is free software; you can redistribute it and/or modify
471+ * it under the terms of the GNU General Public License, Version 2, as
472+ * published by the Free Software Foundation.
473+ */
474+
475+#ifndef _CNS21XX_TIMEX_H
476+#define _CNS21XX_TIMEX_H
477+
478+#define CLOCK_TICK_RATE 43750000
479+
480+#endif /* _CNS21XX_TIMEX_H */
481--- /dev/null
482+++ b/arch/arm/mach-cns21xx/include/mach/uncompress.h
483@@ -0,0 +1,40 @@
484+/*
485+ * Copyright (c) 2008 Cavium Networks
486+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
487+ *
488+ * This file is free software; you can redistribute it and/or modify
489+ * it under the terms of the GNU General Public License, Version 2, as
490+ * published by the Free Software Foundation.
491+ */
492+
493+#ifndef _CNS21XX_UNCOMPRESS_H
494+#define _CNS21XX_UNCOMPRESS_H
495+
496+#define UART_BASE 0x78000000
497+
498+#define UART_REG(offs) (*((volatile unsigned int *)(UART_BASE + offs)))
499+
500+#define UART_THR UART_REG(0x00)
501+#define UART_LSR UART_REG(0x14)
502+#define THR_EMPTY (1 << 5)
503+
504+#define UART_THR_EMPTY() (((UART_LSR) & THR_EMPTY) == (THR_EMPTY))
505+
506+static void putc(int c)
507+{
508+ if (c != 0) {
509+ while (!UART_THR_EMPTY())
510+ barrier();
511+
512+ UART_THR = (int)(c & 0xFF);
513+ }
514+}
515+
516+static inline void flush(void)
517+{
518+}
519+
520+#define arch_decomp_setup()
521+#define arch_decomp_wdog()
522+
523+#endif /* _CNS21XX_UNCOMPRESS_H */
524--- /dev/null
525+++ b/arch/arm/mach-cns21xx/include/mach/memory.h
526@@ -0,0 +1,15 @@
527+/*
528+ * Copyright (c) 2008 Cavium Networks
529+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
530+ *
531+ * This file is free software; you can redistribute it and/or modify
532+ * it under the terms of the GNU General Public License, Version 2, as
533+ * published by the Free Software Foundation.
534+ */
535+
536+#ifndef _CNS21XX_MEMORY_H
537+#define _CNS21XX_MEMORY_H
538+
539+#define PHYS_OFFSET UL(0x00000000)
540+
541+#endif /* _CNS21XX_MEMORY_H */
542--- /dev/null
543+++ b/arch/arm/mach-cns21xx/include/mach/system.h
544@@ -0,0 +1,38 @@
545+/*
546+ * Copyright (c) 2008 Cavium Networks
547+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
548+ *
549+ * This file is free software; you can redistribute it and/or modify
550+ * it under the terms of the GNU General Public License, Version 2, as
551+ * published by the Free Software Foundation.
552+ */
553+
554+#ifndef _CNS21XX_SYSTEM_H
555+#define _CNS21XX_SYSTEM_H
556+
557+#include <mach/cns21xx.h>
558+#include <mach/cns21xx_powermgmt.h>
559+
560+static inline void arch_idle(void)
561+{
562+ /*
563+ * Because of broken hardware we have to enable interrupts or the CPU
564+ * will never wakeup... Acctualy it is not very good to enable
565+ * interrupts here since scheduler can miss a tick, but there is
566+ * no other way around this. Platforms that needs it for power saving
567+ * should call enable_hlt() in init code, since by default it is
568+ * disabled.
569+ */
570+ local_irq_enable();
571+ cpu_do_idle();
572+}
573+
574+static inline void arch_reset(char mode, const char *cmd)
575+{
576+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |=
577+ (1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
578+ PWRMGT_SOFTWARE_RESET_CONTROL_REG &=
579+ ~(1UL << PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX);
580+}
581+
582+#endif /* _CNS21XX_SYSTEM_H */
583--- /dev/null
584+++ b/arch/arm/mach-cns21xx/irq.c
585@@ -0,0 +1,174 @@
586+/*
587+ * Copyright (c) 2008 Cavium Networks
588+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
589+ *
590+ * This file is free software; you can redistribute it and/or modify
591+ * it under the terms of the GNU General Public License, Version 2, as
592+ * published by the Free Software Foundation.
593+ */
594+
595+#include <linux/init.h>
596+#include <linux/interrupt.h>
597+#include <linux/irq.h>
598+#include <linux/io.h>
599+#include <linux/ioport.h>
600+
601+#include <mach/cns21xx.h>
602+
603+#define INTC_INTERRUPT_RAW_STATUS_REG 0x000
604+#define INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG 0x004
605+#define INTC_INTERRUPT_MASK_REG 0x008
606+#define INTC_INTERRUPT_MASK_CLEAR_REG 0x00c
607+#define INTC_INTERRUPT_TRIGGER_MODE_REG 0x010
608+#define INTC_INTERRUPT_TRIGGER_LEVEL_REG 0x014
609+#define INTC_FIQ_SELECT_REG 0x018
610+#define INTC_IRQ_STATUS_REG 0x01c
611+#define INTC_FIQ_STATUS_REG 0x020
612+#define INTC_SOFTWARE_INTERRUPT_REG 0x024
613+#define INTC_SOFTWARE_INTERRUPT_CLEAR_REG 0x028
614+#define INTC_SOFTWARE_PRIORITY_MASK_REG 0x02c
615+#define INTC_POWER_MANAGEMENT_INTERRUPT_REG 0x034
616+
617+#define INTC_VECTOR_ADDRESS_REG(_x) ((_x) + 0x040)
618+#define INTC_PRIORITY_REG(_x) ((_x) + 0x0c0)
619+#define INTC_IRQ_VECTOR_ADDRESS_REG 0x140
620+#define INTC_VECTOR_INTERRUPT_ENABLE_REG 0x144
621+
622+#define INTC_SIZE 0x148
623+
624+static unsigned int cns21xx_irq_types[CNS21XX_NR_INTC_IRQS] = {
625+ [CNS21XX_IRQ_TIMER1] = IRQ_TYPE_EDGE_RISING,
626+ [CNS21XX_IRQ_TIMER2] = IRQ_TYPE_EDGE_RISING,
627+ [CNS21XX_IRQ_CPM] = IRQ_TYPE_EDGE_FALLING,
628+ [CNS21XX_IRQ_WDT] = IRQ_TYPE_EDGE_RISING,
629+ [CNS21XX_IRQ_GPIO] = IRQ_TYPE_NONE,
630+ [CNS21XX_IRQ_PCI_INTA] = IRQ_TYPE_LEVEL_LOW,
631+ [CNS21XX_IRQ_PCI_INTB] = IRQ_TYPE_LEVEL_LOW,
632+ [CNS21XX_IRQ_PCI_BROKEN] = IRQ_TYPE_LEVEL_HIGH,
633+ [CNS21XX_IRQ_AHB2PCI] = IRQ_TYPE_LEVEL_HIGH,
634+ [CNS21XX_IRQ_UART0] = IRQ_TYPE_LEVEL_HIGH,
635+ [CNS21XX_IRQ_UART1] = IRQ_TYPE_LEVEL_HIGH,
636+ [CNS21XX_IRQ_GDMAC_TC] = IRQ_TYPE_LEVEL_HIGH,
637+ [CNS21XX_IRQ_GDMAC_ERR] = IRQ_TYPE_LEVEL_HIGH,
638+ [CNS21XX_IRQ_PCMCIA] = IRQ_TYPE_NONE,
639+ [CNS21XX_IRQ_RTC] = IRQ_TYPE_LEVEL_HIGH,
640+ [CNS21XX_IRQ_PCM] = IRQ_TYPE_LEVEL_LOW,
641+ [CNS21XX_IRQ_USB_DEVICE] = IRQ_TYPE_LEVEL_LOW,
642+ [CNS21XX_IRQ_IDE] = IRQ_TYPE_LEVEL_HIGH,
643+ [CNS21XX_IRQ_NIC_STATUS] = IRQ_TYPE_LEVEL_HIGH,
644+ [CNS21XX_IRQ_NIC_TXTC] = IRQ_TYPE_EDGE_RISING,
645+ [CNS21XX_IRQ_NIC_RXRC] = IRQ_TYPE_EDGE_RISING,
646+ [CNS21XX_IRQ_NIC_TXQE] = IRQ_TYPE_EDGE_RISING,
647+ [CNS21XX_IRQ_NIC_RXQF] = IRQ_TYPE_EDGE_RISING,
648+ [CNS21XX_IRQ_OHCI] = IRQ_TYPE_LEVEL_LOW,
649+ [CNS21XX_IRQ_EHCI] = IRQ_TYPE_LEVEL_LOW,
650+ [CNS21XX_IRQ_I2S] = IRQ_TYPE_LEVEL_LOW,
651+ [CNS21XX_IRQ_SPI] = IRQ_TYPE_LEVEL_LOW,
652+ [CNS21XX_IRQ_I2C] = IRQ_TYPE_LEVEL_LOW,
653+ [CNS21XX_IRQ_USB_VBUS] = IRQ_TYPE_EDGE_RISING,
654+ [CNS21XX_IRQ_EXT_29] = IRQ_TYPE_NONE,
655+ [CNS21XX_IRQ_EXT_30] = IRQ_TYPE_NONE,
656+ [CNS21XX_IRQ_HSDMAC] = IRQ_TYPE_EDGE_RISING,
657+};
658+
659+static void __iomem *cns21xx_intc_base;
660+
661+static inline void cns21xx_intc_writel(u32 val, unsigned int reg)
662+{
663+ __raw_writel(val, cns21xx_intc_base + reg);
664+}
665+
666+static inline u32 cns21xx_intc_readl(unsigned int reg)
667+{
668+ return __raw_readl(cns21xx_intc_base + reg);
669+}
670+
671+static void cns21xx_irq_ack(unsigned int irq)
672+{
673+ cns21xx_intc_writel(1 << irq, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
674+}
675+
676+static void cns21xx_irq_mask(unsigned int irq)
677+{
678+ cns21xx_intc_writel(1 << irq, INTC_INTERRUPT_MASK_REG);
679+}
680+
681+static void cns21xx_irq_unmask(unsigned int irq)
682+{
683+ cns21xx_intc_writel(1 << irq, INTC_INTERRUPT_MASK_CLEAR_REG);
684+}
685+
686+static struct irq_chip cns21xx_irq_chip = {
687+ .name = "INTC",
688+ .ack = cns21xx_irq_ack,
689+ .mask = cns21xx_irq_mask,
690+ .unmask = cns21xx_irq_unmask,
691+};
692+
693+static struct resource cns21xx_intc_resource = {
694+ .name = "INTC",
695+ .flags = IORESOURCE_MEM,
696+ .start = CNS21XX_INTC_BASE,
697+ .end = CNS21XX_INTC_BASE + INTC_SIZE - 1,
698+};
699+
700+void __init cns21xx_init_irq(void)
701+{
702+ unsigned int mode = 0;
703+ unsigned int level = 0;
704+ int i;
705+
706+ /*
707+ * Disable arch_idle() by default since it is buggy
708+ * For more info see arch/arm/mach-cns21xx/include/mach/system.h
709+ */
710+ disable_hlt();
711+
712+ request_resource(&iomem_resource, &cns21xx_intc_resource);
713+ cns21xx_intc_base = ioremap(cns21xx_intc_resource.start, INTC_SIZE);
714+
715+ cns21xx_intc_writel(0xffffffff, INTC_INTERRUPT_MASK_REG);
716+ cns21xx_intc_writel(0xffffffff, INTC_EDGE_INTERRUPT_SOURCE_CLEAR_REG);
717+ cns21xx_intc_writel(0xffffffff, INTC_SOFTWARE_INTERRUPT_CLEAR_REG);
718+ cns21xx_intc_writel(0, INTC_SOFTWARE_PRIORITY_MASK_REG);
719+ cns21xx_intc_writel(0, INTC_FIQ_SELECT_REG);
720+ cns21xx_intc_writel(0, INTC_VECTOR_INTERRUPT_ENABLE_REG);
721+
722+ for (i = 0; i < ARRAY_SIZE(cns21xx_irq_types); i++) {
723+ irq_flow_handler_t handler;
724+
725+ switch (cns21xx_irq_types[i]) {
726+ case IRQ_TYPE_EDGE_RISING:
727+ handler = handle_edge_irq;
728+ mode |= (1 << i);
729+ break;
730+
731+ case IRQ_TYPE_EDGE_FALLING:
732+ handler = handle_edge_irq;
733+ mode |= (1 << i);
734+ level |= (1 << i);
735+ break;
736+
737+ case IRQ_TYPE_LEVEL_LOW:
738+ handler = handle_level_irq;
739+ level |= (1 << i);
740+ break;
741+
742+ case IRQ_TYPE_LEVEL_HIGH:
743+ case IRQ_TYPE_NONE:
744+ handler = handle_level_irq;
745+ break;
746+
747+ default:
748+ BUG();
749+ break;
750+ }
751+
752+ set_irq_chip(i, &cns21xx_irq_chip);
753+ set_irq_handler(i, handler);
754+ set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
755+ }
756+
757+ cns21xx_intc_writel(mode, INTC_INTERRUPT_TRIGGER_MODE_REG);
758+ cns21xx_intc_writel(level, INTC_INTERRUPT_TRIGGER_LEVEL_REG);
759+}
760--- /dev/null
761+++ b/arch/arm/mach-cns21xx/time.c
762@@ -0,0 +1,28 @@
763+/*
764+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
765+ *
766+ * This file is free software; you can redistribute it and/or modify
767+ * it under the terms of the GNU General Public License, Version 2, as
768+ * published by the Free Software Foundation.
769+ */
770+
771+#include <linux/init.h>
772+#include <linux/irq.h>
773+
774+#include <asm/mach/time.h>
775+
776+#include <plat/time.h>
777+#include <mach/hardware.h>
778+#include <mach/cns21xx.h>
779+
780+#include "common.h"
781+
782+static void __init cns21xx_timer_init(void)
783+{
784+ fa_timer_init(CNS21XX_TIMER_BASE, CNS21XX_IRQ_TIMER1, FA_TIMER1,
785+ cns21xx_get_apb_freq());
786+}
787+
788+struct sys_timer cns21xx_timer = {
789+ .init = cns21xx_timer_init,
790+};
791--- /dev/null
792+++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_powermgmt.h
793@@ -0,0 +1,591 @@
794+/*
795+ * Copyright (c) 2008 Cavium Networks
796+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
797+ *
798+ * This file is free software; you can redistribute it and/or modify
799+ * it under the terms of the GNU General Public License, Version 2, as
800+ * published by the Free Software Foundation.
801+ */
802+
803+#ifndef _CNS21XX_POWERMGMT_H
804+#define _CNS21XX_POWERMGMT_H
805+
806+#define PWRMGT_MEM_MAP_VALUE(reg_offset) \
807+ (*((u32 volatile *)(CNS21XX_CPM_BASE_VIRT + reg_offset)))
808+
809+/*
810+ * define access macros
811+ */
812+#define PWRMGT_CLOCK_GATE_CONTROL0_REG PWRMGT_MEM_MAP_VALUE(0x00)
813+#define PWRMGT_CLOCK_GATE_CONTROL1_REG PWRMGT_MEM_MAP_VALUE(0x04)
814+#define PWRMGT_SOFTWARE_RESET_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x08)
815+#define PWRMGT_SYSTEM_CLOCK_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x0C)
816+#define PWRMGT_PLL_POWER_DOWN_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x10)
817+#define PWRMGT_CPU_INITIALIZATION_REG PWRMGT_MEM_MAP_VALUE(0x14)
818+#define PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x1C)
819+#define PWRMGT_USB_DEVICE_POWERMGT_REG PWRMGT_MEM_MAP_VALUE(0x20)
820+#define PWRMGT_REGULATOR_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x24)
821+#define PWRMGT_RTC_XTAL_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x28)
822+#define PWRMGT_PLL250_CONTROL_REG PWRMGT_MEM_MAP_VALUE(0x2C)
823+
824+
825+/*
826+ * define constants macros
827+ */
828+#define PWRMGT_GLOBAL_SOFTWARE_RESET_MASK_BIT_INDEX 0
829+#define PWRMGT_PCMCIA_SOFTWARE_RESET_BIT_INDEX 1
830+#define PWRMGT_IDE_SOFTWARE_RESET_BIT_INDEX 2
831+#define PWRMGT_VIC_SOFTWARE_RESET_BIT_INDEX 3
832+#define PWRMGT_DMA_SOFTWARE_RESET_BIT_INDEX 4
833+#define PWRMGT_NIC_SOFTWARE_RESET_BIT_INDEX 5
834+#define PWRMGT_USB_HOST_SOFTWARE_RESET_BIT_INDEX 6
835+#define PWRMGT_PCI_BRIDGE_SOFTWARE_RESET_BIT_INDEX 7
836+#define PWRMGT_P2S_SOFTWARE_RESET_BIT_INDEX 8
837+#define PWRMGT_UART0_SOFTWARE_RESET_BIT_INDEX 9
838+#define PWRMGT_UART1_SOFTWARE_RESET_BIT_INDEX 10
839+#define PWRMGT_TIMER_SOFTWARE_RESET_BIT_INDEX 11
840+#define PWRMGT_WDTIMER_SOFTWARE_RESET_BIT_INDEX 12
841+#define PWRMGT_GPIO_SOFTWARE_RESET_BIT_INDEX 13
842+#define PWRMGT_USB_DEVICE_SOFTWARE_RESET_BIT_INDEX 14
843+#define PWRMGT_FAST_ETHERNET_PHY_SOFTWARE_RESET_BIT_INDEX 15
844+#define PWRMGT_HSDMA_SOFTWARE_RESET_BIT_INDEX 16
845+
846+#define PWRMGT_PLL_FREQUENCY_175MHZ (0 << 0)
847+#define PWRMGT_PLL_FREQUENCY_200MHZ (1 << 0)
848+#define PWRMGT_PLL_FREQUENCY_225MHZ (2 << 0)
849+#define PWRMGT_PLL_FREQUENCY_250MHZ (3 << 0)
850+
851+#define PWRMGT_CPUCLK_DIVIDER_BY_1 (0 << 2)
852+#define PWRMGT_CPUCLK_DIVIDER_BY_2 (1 << 2)
853+#define PWRMGT_CPUCLK_DIVIDER_BY_3 (2 << 2)
854+#define PWRMGT_CPUCLK_DIVIDER_BY_4 (3 << 2)
855+
856+#define PWRMGT_HCLK_DIVIDER_BY_1 (0 << 4)
857+#define PWRMGT_HCLK_DIVIDER_BY_2 (1 << 4)
858+#define PWRMGT_HCLK_DIVIDER_BY_3 (2 << 4)
859+#define PWRMGT_HCLK_DIVIDER_BY_4 (3 << 4)
860+
861+#define PWRMGT_HCLK_SOURCE_FCLK (0 << 6)
862+#define PWRMGT_HCLK_SOURCE_125MHZ (1 << 6)
863+
864+#define PWRMGT_PCLK_DIVIDER_BY_1 (0 << 8)
865+#define PWRMGT_PCLK_DIVIDER_BY_2 (1 << 8)
866+#define PWRMGT_PCLK_DIVIDER_BY_3 (2 << 8)
867+#define PWRMGT_PCLK_DIVIDER_BY_4 (3 << 8)
868+
869+#define PWRMGT_PCICLK_DIVIDER_BY_1 (0 << 10)
870+#define PWRMGT_PCICLK_DIVIDER_BY_2 (1 << 10)
871+#define PWRMGT_PCICLK_DIVIDER_BY_3 (2 << 10)
872+#define PWRMGT_PCICLK_DIVIDER_BY_4 (3 << 10)
873+
874+
875+#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_1 1
876+#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_2 2
877+#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_3 3
878+#define PWRMGT_PLLCLK_TO_CPUCLK_RATIO_BY_4 4
879+
880+#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_1 1
881+#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_2 2
882+#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_3 3
883+#define PWRMGT_CPUCLK_TO_HCLK_RATIO_BY_4 4
884+
885+#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_1 1
886+#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_2 2
887+#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_3 3
888+#define PWRMGT_HCLK_TO_PCLK_RATIO_BY_4 4
889+
890+/*
891+ * Macro defines for Clock Gate Control
892+ */
893+#define HAL_PWRMGT_DISABLE_DRAMC_CLOCK() \
894+{ \
895+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1); \
896+}
897+
898+
899+#define HAL_PWRMGT_ENABLE_NIC_CLOCK() \
900+{ \
901+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0); \
902+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x0F << 20); \
903+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 5); \
904+}
905+
906+#define HAL_PWRMGT_DISABLE_NIC_CLOCK() \
907+{ \
908+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x0F << 20); \
909+}
910+
911+
912+#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_33M_CLOCK() \
913+{ \
914+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
915+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
916+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 10); \
917+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
918+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
919+}
920+
921+#define HAL_PWRMGT_ENABLE_PCI_BRIDGE_66M_CLOCK() \
922+{ \
923+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1); \
924+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 10); \
925+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 10); \
926+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 28) | (0x1 << 30); \
927+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 7); \
928+}
929+
930+#define HAL_PWRMGT_DISABLE_PCI_CLOCK() \
931+{ \
932+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 28) | (0x1 << 30)); \
933+}
934+
935+
936+#define HAL_PWRMGT_ENABLE_USB_CLOCK() \
937+{ \
938+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0xF << 1); \
939+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 24); \
940+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 28); \
941+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 6) | (0x1 << 14); \
942+}
943+
944+#define HAL_PWRMGT_DISABLE_USB_CLOCK() \
945+{ \
946+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 24); \
947+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 28); \
948+}
949+
950+
951+#define HAL_PWRMGT_ENABLE_DMA_CLOCK() \
952+{ \
953+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 16); \
954+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 4); \
955+}
956+
957+#define HAL_PWRMGT_DISABLE_DMA_CLOCK() \
958+{ \
959+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 16); \
960+}
961+
962+
963+#define HAL_PWRMGT_ENABLE_IDE_CLOCK() \
964+{ \
965+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 8) | (0x1 << 9); \
966+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 2); \
967+}
968+
969+#define HAL_PWRMGT_DISABLE_IDE_CLOCK() \
970+{ \
971+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 8) | (0x1 << 9)); \
972+}
973+
974+
975+#define HAL_PWRMGT_ENABLE_UART0_CLOCK() \
976+{ \
977+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) | (0x1 << 2) | (0x1 << 5)); \
978+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 12); \
979+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 9); \
980+}
981+
982+#define HAL_PWRMGT_DISABLE_UART0_CLOCK() \
983+{ \
984+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 12); \
985+}
986+
987+
988+#define HAL_PWRMGT_ENABLE_UART1_CLOCK() \
989+{ \
990+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 1) | (0x1 << 2) | (0x1 << 5)); \
991+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 13); \
992+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 10); \
993+}
994+
995+#define HAL_PWRMGT_DISABLE_UART1_CLOCK() \
996+{ \
997+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 13); \
998+}
999+
1000+
1001+#define HAL_PWRMGT_ENABLE_PCMCIA_CLOCK() \
1002+{ \
1003+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
1004+}
1005+
1006+#define HAL_PWRMGT_DISABLE_PCMCIA_CLOCK() \
1007+{ \
1008+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
1009+}
1010+
1011+
1012+#define HAL_PWRMGT_ENABLE_GPIO_CLOCK() \
1013+{ \
1014+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 25); \
1015+}
1016+
1017+#define HAL_PWRMGT_DISABLE_GPIO_CLOCK() \
1018+{ \
1019+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 25); \
1020+}
1021+
1022+
1023+#define HAL_PWRMGT_ENABLE_WDTIMER_CLOCK() \
1024+{ \
1025+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 21) | (0x1 << 22); \
1026+}
1027+
1028+#define HAL_PWRMGT_DISABLE_WDTIMER_CLOCK() \
1029+{ \
1030+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 21) | (0x1 << 22)); \
1031+}
1032+
1033+
1034+#define HAL_PWRMGT_ENABLE_RTC_CLOCK() \
1035+{ \
1036+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 23); \
1037+}
1038+
1039+#define HAL_PWRMGT_DISABLE_RTC_CLOCK() \
1040+{ \
1041+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 23); \
1042+}
1043+
1044+
1045+#define HAL_PWRMGT_ENABLE_TIMER_CLOCK() \
1046+{ \
1047+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 17) | (0x1 << 18) | (0x1 << 19); \
1048+}
1049+
1050+#define HAL_PWRMGT_DISABLE_TIMER_CLOCK() \
1051+{ \
1052+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 17) | (0x1 << 18) | (0x1 << 19)); \
1053+}
1054+
1055+
1056+#define HAL_PWRMGT_ENABLE_I2C_CLOCK() \
1057+{ \
1058+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1); \
1059+}
1060+
1061+#define HAL_PWRMGT_DISABLE_I2C_CLOCK() \
1062+{ \
1063+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 1); \
1064+}
1065+
1066+
1067+#define HAL_PWRMGT_ENABLE_I2S_CLOCK() \
1068+{ \
1069+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~((0x1 << 5) | (0x1 << 6)); \
1070+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 10); \
1071+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1072+}
1073+
1074+#define HAL_PWRMGT_DISABLE_I2S_CLOCK() \
1075+{ \
1076+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 10)); \
1077+}
1078+
1079+
1080+#define HAL_PWRMGT_ENABLE_PCM_CLOCK() \
1081+{ \
1082+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5); \
1083+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 1) | (0x1 << 6); \
1084+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 8); \
1085+}
1086+
1087+#define HAL_PWRMGT_DISABLE_PCM_CLOCK() \
1088+{ \
1089+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 1) | (0x1 << 6)); \
1090+}
1091+
1092+
1093+#define HAL_PWRMGT_ENABLE_SPI_CLOCK() \
1094+{ \
1095+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 0) | (0x1 << 1); \
1096+}
1097+
1098+#define HAL_PWRMGT_DISABLE_SPI_CLOCK() \
1099+{ \
1100+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~((0x1 << 0) | (0x1 << 1)); \
1101+}
1102+
1103+
1104+#define HAL_PWRMGT_ENABLE_VIC_CLOCK() \
1105+{ \
1106+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 12); \
1107+}
1108+
1109+#define HAL_PWRMGT_DISABLE_VIC_CLOCK() \
1110+{ \
1111+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~(0x1 << 12); \
1112+}
1113+
1114+
1115+#define HAL_PWRMGT_ENABLE_SMC_CLOCK() \
1116+{ \
1117+ PWRMGT_CLOCK_GATE_CONTROL0_REG |= (0x1 << 4) | (0x1 << 5); \
1118+}
1119+
1120+#define HAL_PWRMGT_DISABLE_SMC_CLOCK() \
1121+{ \
1122+ PWRMGT_CLOCK_GATE_CONTROL0_REG &= ~((0x1 << 4) | (0x1 << 5)); \
1123+}
1124+
1125+
1126+#define HAL_PWRMGT_ENABLE_HSDMA_CLOCK() \
1127+{ \
1128+ PWRMGT_CLOCK_GATE_CONTROL1_REG |= (0x1 << 29); \
1129+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1 << 16); \
1130+}
1131+
1132+#define HAL_PWRMGT_DISABLE_HSDMA_CLOCK() \
1133+{ \
1134+ PWRMGT_CLOCK_GATE_CONTROL1_REG &= ~(0x1 << 29); \
1135+}
1136+
1137+
1138+
1139+/*
1140+ * Macro defines for Reset Control
1141+ */
1142+#define HAL_PWRMGT_GLOBAL_SOFTWARE_RESET() \
1143+{ \
1144+ PWRMGT_SOFTWARE_RESET_CONTROL_REG |= (0x1); \
1145+ PWRMGT_SOFTWARE_RESET_CONTROL_REG &= ~(0x1); \
1146+}
1147+
1148+
1149+/*
1150+ * Macro defines for System Clock Control
1151+ */
1152+#define HAL_PWRMGT_SET_PLL_FREQUENCY_175MHZ() \
1153+{ \
1154+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1155+}
1156+
1157+
1158+#define HAL_PWRMGT_SET_PLL_FREQUENCY_200MHZ() \
1159+{ \
1160+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1161+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x1; \
1162+}
1163+
1164+
1165+#define HAL_PWRMGT_SET_PLL_FREQUENCY_225MHZ() \
1166+{ \
1167+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1168+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x2; \
1169+}
1170+
1171+
1172+#define HAL_PWRMGT_SET_PLL_FREQUENCY_250MHZ() \
1173+{ \
1174+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~0x3; \
1175+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= 0x3; \
1176+}
1177+
1178+
1179+#define HAL_PWRMGT_CONFIG_PLLCLK_TO_CPUCLK_RATIO(ratio) \
1180+{ \
1181+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 2); \
1182+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 2); \
1183+}
1184+
1185+
1186+#define HAL_PWRMGT_CONFIG_CPUCLK_TO_HCLK_RATIO(ratio) \
1187+{ \
1188+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 4); \
1189+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 4); \
1190+}
1191+
1192+
1193+#define HAL_PWRMGT_HCLK_SOURCE_FCLK() \
1194+{ \
1195+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 6); \
1196+}
1197+
1198+
1199+#define HAL_PWRMGT_HCLK_SOURCE_125MHZ() \
1200+{ \
1201+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 6); \
1202+}
1203+
1204+
1205+#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_HCLK() \
1206+{ \
1207+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x1 << 7); \
1208+}
1209+
1210+
1211+#define HAL_PWRMGT_GIGA_NIC_CLOCK_SOURCE_62_5MHZ() \
1212+{ \
1213+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 7); \
1214+}
1215+
1216+
1217+#define HAL_PWRMGT_CONFIG_HCLK_TO_PCLK_RATIO(ratio) \
1218+{ \
1219+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 8); \
1220+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (((ratio - 1) & 0x3) << 8); \
1221+}
1222+
1223+
1224+#define HAL_PWRMGT_I2S_CLOCK_SOURCE_8192000HZ() \
1225+{ \
1226+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1227+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x0 << 12); \
1228+}
1229+
1230+
1231+#define HAL_PWRMGT_I2S_CLOCK_SOURCE_11289600HZ() \
1232+{ \
1233+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1234+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x1 << 12); \
1235+}
1236+
1237+
1238+#define HAL_PWRMGT_I2S_CLOCK_SOURCE_12288000HZ() \
1239+{ \
1240+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 12); \
1241+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= (0x2 << 12); \
1242+}
1243+
1244+
1245+#define HAL_PWRMGT_CONFIGURE_MDC_CLOCK_DIVIDER(divided_value) \
1246+{ \
1247+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3 << 14); \
1248+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 14); \
1249+}
1250+
1251+
1252+#define HAL_PWRMGT_CONFIGURE_CLOCK_OUT_PIN(pin_source_select, divided_value) \
1253+{ \
1254+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG &= ~(0x3F << 16); \
1255+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((pin_source_select & 0xF) << 16); \
1256+ PWRMGT_SYSTEM_CLOCK_CONTROL_REG |= ((divided_value & 0x3) << 20); \
1257+}
1258+
1259+
1260+/*
1261+ * Macro defines for PLL Power Down Control
1262+ */
1263+#define HAL_PWRMGT_POWER_DOWN_SYSTEM_XTAL_PAD() \
1264+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 7)
1265+
1266+#define HAL_PWRMGT_POWER_ON_SYSTEM_XTAL_PAD() \
1267+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 7)
1268+
1269+
1270+#define HAL_PWRMGT_POWER_DOWN_PLL_X5() \
1271+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 0)
1272+
1273+#define HAL_PWRMGT_POWER_ON_PLL_X5() \
1274+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 0)
1275+
1276+
1277+#define HAL_PWRMGT_POWER_DOWN_PLL_X8() \
1278+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 1)
1279+
1280+#define HAL_PWRMGT_POWER_ON_PLL_X8() \
1281+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 1)
1282+
1283+
1284+#define HAL_PWRMGT_POWER_DOWN_PLL_X3() \
1285+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 2)
1286+
1287+#define HAL_PWRMGT_POWER_ON_PLL_X3() \
1288+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 2)
1289+
1290+
1291+#define HAL_PWRMGT_POWER_DOWN_USBH_PHY_PLL() \
1292+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 3)
1293+
1294+#define HAL_PWRMGT_POWER_ON_USBH_PHY_PLL() \
1295+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 3)
1296+
1297+
1298+#define HAL_PWRMGT_POWER_DOWN_USBD_PHY_PLL() \
1299+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 4)
1300+
1301+#define HAL_PWRMGT_POWER_ON_USBD_PHY_PLL() \
1302+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 4)
1303+
1304+
1305+#define HAL_PWRMGT_POWER_DOWN_PLL_X2250() \
1306+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 5)
1307+
1308+#define HAL_PWRMGT_POWER_ON_PLL_X2250() \
1309+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 5)
1310+
1311+
1312+#define HAL_PWRMGT_POWER_DOWN_PLL_X7() \
1313+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG |= (0x1 << 6)
1314+
1315+#define HAL_PWRMGT_POWER_ON_PLL_X7() \
1316+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG &= ~(0x1 << 6)
1317+
1318+
1319+#define HAL_PWRMGT_POWER_DOWN_ALL_PLL() \
1320+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG = 0x7F;
1321+
1322+#define HAL_PWRMGT_POWER_ON_ALL_PLL() \
1323+ PWRMGT_PLL_POWER_DOWN_CONTROL_REG = 0;
1324+
1325+
1326+/*
1327+ * Macro defines for Pad Drive Strength Control
1328+ */
1329+#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCMCIA_CARDBUS_MODE() \
1330+{ \
1331+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1332+}
1333+
1334+#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_PCI_MODE() \
1335+{ \
1336+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x3 << 0); \
1337+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 0); \
1338+}
1339+
1340+#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_MII_MODE() \
1341+{ \
1342+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 2); \
1343+}
1344+
1345+#define HAL_PWRMGT_SELECT_PAD_DRIVE_STRENGTH_RGMII_MODE() \
1346+{ \
1347+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 2); \
1348+}
1349+
1350+#define HAL_PWRMGT_ENABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1351+{ \
1352+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG |= (0x1 << 3); \
1353+}
1354+
1355+#define HAL_PWRMGT_DISABLE_MII_PAD_SIGNAL_NOT_BOUNDED() \
1356+{ \
1357+ PWRMGT_PAD_DRIVE_STRENGTH_CONTROL_REG &= ~(0x1 << 3); \
1358+}
1359+
1360+
1361+/*
1362+ * Macro defines for USB Device Power Management
1363+ */
1364+#define HAL_PWRMGT_REMOTE_WAKEUP_USB_HOST() \
1365+{ \
1366+ PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 4); \
1367+}
1368+
1369+#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_EXTERNAL_12MHZ() \
1370+{ \
1371+ PWRMGT_USB_DEVICE_POWERMGT_REG &= ~(0x1 << 5); \
1372+}
1373+
1374+#define HAL_PWRMGT_USB_DEVICE_PHY_CLOCK_SOURCE_INTERNAL_12MHZ() \
1375+{ \
1376+ PWRMGT_USB_DEVICE_POWERMGT_REG |= (0x1 << 5); \
1377+}
1378+
1379+
1380+/*
1381+ * Macro defines for Regulator Control
1382+ */
1383+
1384+#endif /* _CNS21XX_POWERMGMT_H */
1385--- /dev/null
1386+++ b/arch/arm/mach-cns21xx/include/mach/cns21xx.h
1387@@ -0,0 +1,88 @@
1388+/*
1389+ * Copyright (c) 2008 Cavium Networks
1390+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
1391+ *
1392+ * This file is free software; you can redistribute it and/or modify
1393+ * it under the terms of the GNU General Public License, Version 2, as
1394+ * published by the Free Software Foundation.
1395+ */
1396+
1397+#ifndef _CNS21XX_H
1398+#define _CNS21XX_H
1399+
1400+#define CNS21XX_FLASH_BANK0_BASE 0x10000000
1401+#define CNS21XX_FLASH_BANK1_BASE 0x11000000
1402+#define CNS21XX_FLASH_BANK2_BASE 0x12000000
1403+#define CNS21XX_FLASH_BANK3_BASE 0x13000000
1404+#define CNS21XX_PCMCIA_ATTR_BASE 0x14000000
1405+#define CNS21XX_PCMCIA_MEM_BASE 0x15000000
1406+#define CNS21XX_PCMCIA_IO_BASE 0x16000000
1407+#define CNS21XX_IDE_DEVICE_BASE 0x18000000
1408+#define CNS21XX_SDRAM_MEMORY_BASE 0x20000000
1409+#define CNS21XX_GDMAC_BASE 0x60000000
1410+#define CNS21XX_NIC_BASE 0x70000000
1411+#define CNS21XX_SPI_BASE 0x71000000
1412+#define CNS21XX_PCM_BASE 0x71000000
1413+#define CNS21XX_I2C_BASE 0x71000000
1414+#define CNS21XX_I2S_BASE 0x71000000
1415+#define CNS21XX_DDRC_BASE 0x72000000
1416+#define CNS21XX_SMC_BASE 0x73000000
1417+#define CNS21XX_PCMCIA_CTRL_BASE 0x73000000
1418+#define CNS21XX_IDE_CTRL_BASE 0x74000000
1419+#define CNS21XX_MISC_BASE 0x76000000
1420+#define CNS21XX_CPM_BASE 0x77000000
1421+#define CNS21XX_UART0_BASE 0x78000000
1422+#define CNS21XX_UART1_BASE 0x78800000
1423+#define CNS21XX_TIMER_BASE 0x79000000
1424+#define CNS21XX_WDT_BASE 0x7a000000
1425+#define CNS21XX_RTC_BASE 0x7b000000
1426+#define CNS21XX_GPIOA_BASE 0x7c000000
1427+#define CNS21XX_GPIOB_BASE 0x7c800000
1428+#define CNS21XX_PCI_CFGDATA_BASE 0xa0000000
1429+#define CNS21XX_PCI_CFGADDR_BASE 0xa4000000
1430+#define CNS21XX_PCI_IO_BASE 0xa8000000
1431+#define CNS21XX_PCI_MEMORY_BASE 0xb0000000
1432+#define CNS21XX_OHCI_CONFIG_BASE 0xc0000000
1433+#define CNS21XX_OHCI_CTRL_BASE 0xc4000000
1434+#define CNS21XX_EHCI_CONFIG_BASE 0xc8000000
1435+#define CNS21XX_EHCI_CTRL_BASE 0xcc000000
1436+#define CNS21XX_USB_DEVICE_BASE 0xd0000000
1437+#define CNS21XX_INTC_BASE 0xfffff000
1438+
1439+#define CNS21XX_FLASH_BANK0_BASE_VIRT 0xe0000000
1440+#define CNS21XX_FLASH_BANK1_BASE_VIRT 0xe2000000
1441+#define CNS21XX_FLASH_BANK2_BASE_VIRT 0xe4000000
1442+#define CNS21XX_FLASH_BANK3_BASE_VIRT 0xe8000000
1443+#define CNS21XX_IDE_DEVICE_BASE_VIRT 0xfff00000
1444+#define CNS21XX_GDMAC_BASE_VIRT 0xfff01000
1445+#define CNS21XX_NIC_BASE_VIRT 0xfff02000
1446+#define CNS21XX_SPI_BASE_VIRT 0xfff03000
1447+#define CNS21XX_PCM_BASE_VIRT 0xfff04000
1448+#define CNS21XX_I2C_BASE_VIRT 0xfff05000
1449+#define CNS21XX_I2S_BASE_VIRT 0xfff06000
1450+#define CNS21XX_DDRC_BASE_VIRT 0xfff07000
1451+#define CNS21XX_SMC_BASE_VIRT 0xfff08000
1452+#define CNS21XX_PCMCIA_CTRL_BASE_VIRT 0xfff09000
1453+#define CNS21XX_IDE_CTRL_BASE_VIRT 0xfff0A000
1454+#define CNS21XX_MISC_BASE_VIRT 0xfff0B000
1455+#define CNS21XX_CPM_BASE_VIRT 0xfff0C000
1456+#define CNS21XX_UART0_BASE_VIRT 0xfff0D000
1457+#define CNS21XX_UART1_BASE_VIRT 0xfff0E000
1458+#define CNS21XX_TIMER_BASE_VIRT 0xfff0F000
1459+#define CNS21XX_WDT_BASE_VIRT 0xfff10000
1460+#define CNS21XX_RTC_BASE_VIRT 0xfff11000
1461+#define CNS21XX_GPIOA_BASE_VIRT 0xfff12000
1462+#define CNS21XX_GPIOB_BASE_VIRT 0xfff13000
1463+#define CNS21XX_PCI_CFGDATA_BASE_VIRT 0xfff14000
1464+#define CNS21XX_PCI_CFGADDR_BASE_VIRT 0xfff15000
1465+#define CNS21XX_OHCI_CONFIG_BASE_VIRT 0xfff16000
1466+#define CNS21XX_OHCI_CTRL_BASE_VIRT 0xfff17000
1467+#define CNS21XX_EHCI_CONFIG_BASE_VIRT 0xfff18000
1468+#define CNS21XX_EHCI_CTRL_BASE_VIRT 0xfff19000
1469+#define CNS21XX_USB_DEVICE_BASE_VIRT 0xfff1a000
1470+#define CNS21XX_INTC_BASE_VIRT 0xfff1b000
1471+
1472+#define CNS21XX_PHYS_IO CNS21XX_UART0_BASE
1473+#define CNS21XX_IO_PAGE_OFFSET ((CNS21XX_UART0_BASE_VIRT) >> 18) & 0xfffc
1474+
1475+#endif /* _CNS21XX_H */
1476--- /dev/null
1477+++ b/arch/arm/mach-cns21xx/core.c
1478@@ -0,0 +1,77 @@
1479+/*
1480+ * Copyright (c) 2008 Cavium Networks
1481+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
1482+ *
1483+ * This file is free software; you can redistribute it and/or modify
1484+ * it under the terms of the GNU General Public License, Version 2, as
1485+ * published by the Free Software Foundation.
1486+ */
1487+
1488+#include <linux/kernel.h>
1489+
1490+#include <mach/hardware.h>
1491+#include <mach/cns21xx.h>
1492+#include <mach/cns21xx_powermgmt.h>
1493+
1494+static unsigned long cns21xx_pll_freq;
1495+static unsigned long cns21xx_cpu_freq;
1496+static unsigned long cns21xx_ahb_freq;
1497+static unsigned long cns21xx_apb_freq;
1498+
1499+static void cns21xx_init_freq(void)
1500+{
1501+ static int freq_init_done;
1502+ unsigned int t;
1503+
1504+ if (freq_init_done)
1505+ return;
1506+
1507+ t = PWRMGT_SYSTEM_CLOCK_CONTROL_REG;
1508+ switch (t & 0x3) {
1509+ case 0x00:
1510+ cns21xx_pll_freq = 175000000;
1511+ break;
1512+
1513+ case 0x01:
1514+ cns21xx_pll_freq = 200000000;
1515+ break;
1516+
1517+ case 0x02:
1518+ cns21xx_pll_freq = 225000000;
1519+ break;
1520+
1521+ case 0x03:
1522+ cns21xx_pll_freq = 250000000;
1523+ break;
1524+ }
1525+
1526+ cns21xx_cpu_freq = cns21xx_pll_freq / (((t >> 2) & 0x3) + 1);
1527+ cns21xx_ahb_freq = cns21xx_cpu_freq / (((t >> 4) & 0x3) + 1);
1528+ cns21xx_apb_freq = cns21xx_ahb_freq / (((t >> 8) & 0x3) + 1);
1529+
1530+ freq_init_done = 1;
1531+}
1532+
1533+unsigned long cns21xx_get_pll_freq(void)
1534+{
1535+ cns21xx_init_freq();
1536+ return cns21xx_pll_freq;
1537+}
1538+
1539+unsigned long cns21xx_get_cpu_freq(void)
1540+{
1541+ cns21xx_init_freq();
1542+ return cns21xx_cpu_freq;
1543+}
1544+
1545+unsigned long cns21xx_get_ahb_freq(void)
1546+{
1547+ cns21xx_init_freq();
1548+ return cns21xx_ahb_freq;
1549+}
1550+
1551+unsigned long cns21xx_get_apb_freq(void)
1552+{
1553+ cns21xx_init_freq();
1554+ return cns21xx_apb_freq;
1555+}
1556--- a/arch/arm/mm/Kconfig
1557+++ b/arch/arm/mm/Kconfig
1558@@ -807,6 +807,7 @@ config CACHE_XSC3L2
1559 config ARM_L1_CACHE_SHIFT
1560     int
1561     default 6 if ARM_L1_CACHE_SHIFT_6
1562+ default 4 if ARM_L1_CACHE_SHIFT_4
1563     default 5
1564 
1565 config ARM_DMA_MEM_BUFFERABLE
1566--- a/arch/arm/mm/cache-fa.S
1567+++ b/arch/arm/mm/cache-fa.S
1568@@ -28,7 +28,7 @@
1569 /*
1570  * The total size of the data cache.
1571  */
1572-#ifdef CONFIG_ARCH_GEMINI
1573+#if (defined(CONFIG_ARCH_GEMINI) || defined(CONFIG_ARCH_CNS21XX))
1574 #define CACHE_DSIZE 8192
1575 #else
1576 #define CACHE_DSIZE 16384
1577--- /dev/null
1578+++ b/arch/arm/mach-cns21xx/include/mach/cns21xx_misc.h
1579@@ -0,0 +1,507 @@
1580+/*******************************************************************************
1581+ *
1582+ * Copyright (c) 2008 Cavium Networks
1583+ *
1584+ * This file is free software; you can redistribute it and/or modify
1585+ * it under the terms of the GNU General Public License, Version 2, as
1586+ * published by the Free Software Foundation.
1587+ *
1588+ * This file is distributed in the hope that it will be useful,
1589+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
1590+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1591+ * NONINFRINGEMENT. See the GNU General Public License for more details.
1592+ *
1593+ * You should have received a copy of the GNU General Public License
1594+ * along with this file; if not, write to the Free Software
1595+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
1596+ * visit http://www.gnu.org/licenses/.
1597+ *
1598+ * This file may also be available under a different license from Cavium.
1599+ * Contact Cavium Networks for more information
1600+ *
1601+ ******************************************************************************/
1602+
1603+#ifndef _STAR_MISC_H_
1604+#define _STAR_MISC_H_
1605+
1606+#include <mach/cns21xx.h>
1607+
1608+#define MISC_MEM_MAP_VALUE(reg_offset) \
1609+ (*((u32 volatile *)(CNS21XX_MISC_BASE_VIRT + reg_offset)))
1610+
1611+/*
1612+ * define access macros
1613+ */
1614+#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
1615+#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
1616+#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
1617+#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
1618+#define MISC_PCI_CONTROL_BROKEN_MASK_REG MISC_MEM_MAP_VALUE(0x10)
1619+#define MISC_PCI_BROKEN_STATUS_REG MISC_MEM_MAP_VALUE(0x14)
1620+#define MISC_PCI_DEVICE_VENDOR_ID_REG MISC_MEM_MAP_VALUE(0x18)
1621+#define MISC_USB_HOST_PHY_CONTROL_TEST_REG MISC_MEM_MAP_VALUE(0x1C)
1622+#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x20)
1623+#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x24)
1624+#define MISC_GPIOA_RESISTOR_CONFIG_REG MISC_MEM_MAP_VALUE(0x28)
1625+#define MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG MISC_MEM_MAP_VALUE(0x2C)
1626+#define MISC_FAST_ETHERNET_PHY_CONFIG_REG MISC_MEM_MAP_VALUE(0x30)
1627+#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x38)
1628+#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x3C)
1629+
1630+#define MISC_E_FUSE_0_REG MISC_MEM_MAP_VALUE(0x60)
1631+#define MISC_E_FUSE_1_REG MISC_MEM_MAP_VALUE(0x64)
1632+
1633+
1634+/*
1635+ * define constants macros
1636+ */
1637+#define MISC_PARALLEL_FLASH_BOOT 0
1638+#define MISC_SPI_SERIAL_FLASH_BOOT 1
1639+
1640+#define MISC_LITTLE_ENDIAN 0
1641+#define MISC_BIG_ENDIAN 1
1642+
1643+#define MISC_FARADAY_ICE 0
1644+#define MISC_ARM_ICE 1
1645+
1646+#define MISC_EXT_INT29_PINS ((0x1 << 0))
1647+#define MISC_EXT_INT30_PINS ((0x1 << 1))
1648+#define MISC_EXT_INT31_PINS ((0x1 << 2))
1649+#define MISC_I2C_PINS ((0x1 << 13) | (0x1 << 14))
1650+#define MISC_I2S_PINS ((0x1 << 15) | (0x1 << 16) | (0x1 << 17))
1651+#define MISC_I2SSD_PINS (1 << 15)
1652+#define MISC_I2SWS_PINS (1 << 16)
1653+#define MISC_I2SCLK_PINS (1 << 17)
1654+#define MISC_PCM_PINS ((0x1 << 18) | (0x1 << 19) | (0x1 << 20) | (0x1 << 21))
1655+#define MISC_PCMDR_PINS (1 << 18)
1656+#define MISC_PCMDT_PINS (1 << 19)
1657+#define MISC_PCMFS_PINS (1 << 20)
1658+#define MISC_PCMCLK_PINS (1 << 21)
1659+#define MISC_LED0_PINS ((0x1 << 22))
1660+#define MISC_LED1_PINS ((0x1 << 23))
1661+#define MISC_LED2_PINS ((0x1 << 24))
1662+#define MISC_LED012_PINS ((0x1 << 22) | (0x1 << 23) | (0x1 << 24))
1663+#define MISC_WDTIMER_RESET_PINS ((0x1 << 25))
1664+#define MISC_SPIDR_PINS (0x1 << 26)
1665+#define MISC_SPICLK_PINS (0x1 << 27)
1666+#define MISC_SPICSN0_PINS (0x1 << 28)
1667+#define MISC_SPICSN1_PINS (0x1 << 29)
1668+#define MISC_SPICSN2_PINS (0x1 << 30)
1669+#define MISC_SPICSN3_PINS (0x1 << 31)
1670+#define MISC_SPI_PINS ((0x1 << 26) | (0x1 << 27) | (0x1 << 28) | (0x1 << 29) | (0x1 << 30) | (0x1 << 31))
1671+#define MISC_MDC_MDIO_PINS ((0x1 << 0) | (0x1 << 1))
1672+#define MISC_NIC_COL_PINS ((0x1 << 2))
1673+#define MISC_IDE_PINS ((0xFF << 3))
1674+#define MISC_SRAM_BANK1_PINS ((0x1 << 11) | (0x1 << 14))
1675+#define MISC_SRAM_BANK2_PINS ((0x1 << 12) | (0x1 << 15))
1676+#define MISC_SRAM_BANK3_PINS ((0x1 << 13) | (0x1 << 16))
1677+#define MISC_PCMCIA_PINS ((0x1 << 17) | (0x1 << 18) | (0x1 << 19) | (0x1 << 20))
1678+#define MISC_UART1_PINS ((0x1 << 21) | (0x1 << 22))
1679+#define MISC_PCI_PINS (((u32)0x1FF << 23))
1680+
1681+#define MISC_UART0_ACT0_Pin (0x1 << 2)
1682+#define MISC_UART1_ACT1_Pin (0x1 << 3)
1683+
1684+#define MISC_GPIOA_PIN_0 0
1685+#define MISC_GPIOA_PIN_1 1
1686+#define MISC_GPIOA_PIN_2 2
1687+#define MISC_GPIOA_PIN_3 3
1688+#define MISC_GPIOA_PIN_4 4
1689+#define MISC_GPIOA_PIN_5 5
1690+#define MISC_GPIOA_PIN_6 6
1691+#define MISC_GPIOA_PIN_7 7
1692+#define MISC_GPIOA_PIN_8 8
1693+#define MISC_GPIOA_PIN_9 9
1694+#define MISC_GPIOA_PIN_10 10
1695+
1696+#define MISC_GPIOA_75K_RESISTOR_PULL_DOWN 1
1697+#define MISC_GPIOA_75K_RESISTOR_PULL_UP 2
1698+#define MISC_GPIOA_75K_RESISTOR_PULL_KEEPER 3
1699+
1700+#define MISC_GPIOA_DRIVE_STRENGTH_4MA 0
1701+#define MISC_GPIOA_DRIVE_STRENGTH_8MA 1
1702+
1703+
1704+/*
1705+ * macro declarations
1706+ */
1707+#define HAL_MISC_ENABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1708+{ \
1709+ (MISC_CHIP_CONFIG_REG) |= (0x1 << 4); \
1710+}
1711+
1712+#define HAL_MISC_DISABLE_SPI_SERIAL_FLASH_BANK_ACCESS() \
1713+{ \
1714+ (MISC_CHIP_CONFIG_REG) &= ~(0x1 << 4); \
1715+}
1716+
1717+
1718+/*
1719+ * Macro defines for GPIOA and GPIOB Pin Enable Register
1720+ */
1721+#define HAL_MISC_ENABLE_EXT_INT29_PINS() \
1722+{ \
1723+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_EXT_INT29_PINS); \
1724+}
1725+
1726+#define HAL_MISC_DISABLE_EXT_INT29_PINS() \
1727+{ \
1728+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_EXT_INT29_PINS); \
1729+}
1730+
1731+#define HAL_MISC_ENABLE_EXT_INT30_PINS() \
1732+{ \
1733+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_EXT_INT30_PINS); \
1734+}
1735+
1736+#define HAL_MISC_DISABLE_EXT_INT30_PINS() \
1737+{ \
1738+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_EXT_INT30_PINS); \
1739+}
1740+
1741+#define HAL_MISC_ENABLE_I2C_PINS() \
1742+{ \
1743+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2C_PINS); \
1744+}
1745+
1746+#define HAL_MISC_DISABLE_I2C_PINS() \
1747+{ \
1748+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2C_PINS); \
1749+}
1750+
1751+#define HAL_MISC_ENABLE_I2S_PINS() \
1752+{ \
1753+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_I2S_PINS); \
1754+}
1755+
1756+#define HAL_MISC_DISABLE_I2S_PINS() \
1757+{ \
1758+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2S_PINS); \
1759+}
1760+
1761+#define HAL_MISC_DISABLE_I2SSD_PINS() \
1762+{ \
1763+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SSD_PINS); \
1764+}
1765+
1766+#define HAL_MISC_DISABLE_I2SWS_PINS() \
1767+{ \
1768+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SWS_PINS); \
1769+}
1770+
1771+#define HAL_MISC_DISABLE_I2SCLK_PINS() \
1772+{ \
1773+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_I2SCLK_PINS); \
1774+}
1775+
1776+#define HAL_MISC_ENABLE_PCM_PINS() \
1777+{ \
1778+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_PCM_PINS); \
1779+}
1780+
1781+#define HAL_MISC_DISABLE_PCM_PINS() \
1782+{ \
1783+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCM_PINS); \
1784+}
1785+
1786+#define HAL_MISC_DISABLE_PCMDR_PINS() \
1787+{ \
1788+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMDR_PINS); \
1789+}
1790+
1791+#define HAL_MISC_DISABLE_PCMDT_PINS() \
1792+{ \
1793+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMDT_PINS); \
1794+}
1795+
1796+#define HAL_MISC_DISABLE_PCMFS_PINS() \
1797+{ \
1798+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMFS_PINS); \
1799+}
1800+
1801+#define HAL_MISC_DISABLE_PCMCLK_PINS() \
1802+{ \
1803+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_PCMCLK_PINS); \
1804+}
1805+
1806+#define HAL_MISC_ENABLE_LED0_PINS() \
1807+{ \
1808+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED0_PINS); \
1809+}
1810+
1811+#define HAL_MISC_DISABLE_LED0_PINS() \
1812+{ \
1813+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED0_PINS); \
1814+}
1815+
1816+#define HAL_MISC_ENABLE_LED1_PINS() \
1817+{ \
1818+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED1_PINS); \
1819+}
1820+
1821+#define HAL_MISC_DISABLE_LED1_PINS() \
1822+{ \
1823+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED1_PINS); \
1824+}
1825+
1826+#define HAL_MISC_ENABLE_LED2_PINS() \
1827+{ \
1828+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED2_PINS); \
1829+}
1830+
1831+#define HAL_MISC_DISABLE_LED2_PINS() \
1832+{ \
1833+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED2_PINS); \
1834+}
1835+
1836+#define HAL_MISC_ENABLE_LED012_PINS() \
1837+{ \
1838+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_LED012_PINS); \
1839+}
1840+
1841+#define HAL_MISC_DISABLE_LED012_PINS() \
1842+{ \
1843+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_LED012_PINS); \
1844+}
1845+
1846+#define HAL_MISC_ENABLE_WDTIMER_RESET_PINS() \
1847+{ \
1848+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_WDTIMER_RESET_PINS); \
1849+}
1850+
1851+#define HAL_MISC_DISABLE_WDTIMER_RESET_PINS() \
1852+{ \
1853+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_WDTIMER_RESET_PINS); \
1854+}
1855+
1856+#define HAL_MISC_ENABLE_SPI_PINS() \
1857+{ \
1858+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPI_PINS); \
1859+}
1860+
1861+#define HAL_MISC_ENABLE_SPIDR_PINS() \
1862+{ \
1863+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPIDR_PINS); \
1864+}
1865+
1866+#define HAL_MISC_ENABLE_SPICLK_PINS() \
1867+{ \
1868+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICLK_PINS); \
1869+}
1870+
1871+#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1872+{ \
1873+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN0_PINS); \
1874+}
1875+
1876+#define HAL_MISC_ENABLE_SPICSN0_PINS() \
1877+{ \
1878+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN0_PINS); \
1879+}
1880+
1881+#define HAL_MISC_ENABLE_SPICSN1_PINS() \
1882+{ \
1883+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN1_PINS); \
1884+}
1885+
1886+#define HAL_MISC_ENABLE_SPICSN2_PINS() \
1887+{ \
1888+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN2_PINS); \
1889+}
1890+
1891+#define HAL_MISC_ENABLE_SPICSN3_PINS() \
1892+{ \
1893+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_SPICSN3_PINS); \
1894+}
1895+
1896+#define HAL_MISC_DISABLE_SPI_PINS() \
1897+{ \
1898+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPI_PINS); \
1899+}
1900+
1901+#define HAL_MISC_DISABLE_SPIDR_PINS() \
1902+{ \
1903+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPIDR_PINS); \
1904+}
1905+
1906+#define HAL_MISC_DISABLE_SPICLK_PINS() \
1907+{ \
1908+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICLK_PINS); \
1909+}
1910+
1911+#define HAL_MISC_DISABLE_SPICSN0_PINS() \
1912+{ \
1913+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN0_PINS); \
1914+}
1915+
1916+#define HAL_MISC_DISABLE_SPICSN1_PINS() \
1917+{ \
1918+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN1_PINS); \
1919+}
1920+
1921+#define HAL_MISC_DISABLE_SPICSN2_PINS() \
1922+{ \
1923+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN2_PINS); \
1924+}
1925+
1926+#define HAL_MISC_DISABLE_SPICSN3_PINS() \
1927+{ \
1928+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_SPICSN3_PINS); \
1929+}
1930+
1931+#define HAL_MISC_ENABLE_UART0_ACT0_PIN() \
1932+{ \
1933+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART0_ACT0_Pin); \
1934+}
1935+
1936+#define HAL_MISC_DISABLE_UART0_ACT0_PIN() \
1937+{ \
1938+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART0_ACT0_Pin); \
1939+}
1940+
1941+#define HAL_MISC_ENABLE_UART1_ACT1_PIN() \
1942+{ \
1943+ (MISC_GPIOA_PIN_ENABLE_REG) |= (MISC_UART1_ACT1_Pin); \
1944+}
1945+
1946+#define HAL_MISC_DISABLE_UART1_ACT1_PIN() \
1947+{ \
1948+ (MISC_GPIOA_PIN_ENABLE_REG) &= ~(MISC_UART1_ACT1_Pin); \
1949+}
1950+
1951+#define HAL_MISC_ENABLE_MDC_MDIO_PINS() \
1952+{ \
1953+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_MDC_MDIO_PINS); \
1954+}
1955+
1956+#define HAL_MISC_DISABLE_MDC_MDIO_PINS() \
1957+{ \
1958+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_MDC_MDIO_PINS); \
1959+}
1960+
1961+#define HAL_MISC_ENABLE_NIC_COL_PINS() \
1962+{ \
1963+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_NIC_COL_PINS); \
1964+}
1965+
1966+#define HAL_MISC_DISABLE_NIC_COL_PINS() \
1967+{ \
1968+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_NIC_COL_PINS); \
1969+}
1970+
1971+#define HAL_MISC_ENABLE_IDE_PINS() \
1972+{ \
1973+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_IDE_PINS); \
1974+}
1975+
1976+#define HAL_MISC_DISABLE_IDE_PINS() \
1977+{ \
1978+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_IDE_PINS); \
1979+}
1980+
1981+#define HAL_MISC_ENABLE_SRAM_BANK1_PINS() \
1982+{ \
1983+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK1_PINS); \
1984+}
1985+
1986+#define HAL_MISC_DISABLE_SRAM_BANK1_PINS() \
1987+{ \
1988+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK1_PINS); \
1989+}
1990+
1991+#define HAL_MISC_ENABLE_SRAM_BANK2_PINS() \
1992+{ \
1993+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK2_PINS); \
1994+}
1995+
1996+#define HAL_MISC_DISABLE_SRAM_BANK2_PINS() \
1997+{ \
1998+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK2_PINS); \
1999+}
2000+
2001+#define HAL_MISC_ENABLE_SRAM_BANK3_PINS() \
2002+{ \
2003+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_SRAM_BANK3_PINS); \
2004+}
2005+
2006+#define HAL_MISC_DISABLE_SRAM_BANK3_PINS() \
2007+{ \
2008+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_SRAM_BANK3_PINS); \
2009+}
2010+
2011+#define HAL_MISC_ENABLE_PCMCIA_PINS() \
2012+{ \
2013+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCMCIA_PINS); \
2014+}
2015+
2016+#define HAL_MISC_DISABLE_PCMCIA_PINS() \
2017+{ \
2018+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCMCIA_PINS); \
2019+}
2020+
2021+#define HAL_MISC_ENABLE_UART1_PINS() \
2022+{ \
2023+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_UART1_PINS); \
2024+}
2025+
2026+#define HAL_MISC_DISABLE_UART1_PINS() \
2027+{ \
2028+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_UART1_PINS); \
2029+}
2030+
2031+#define HAL_MISC_ENABLE_PCI_PINS() \
2032+{ \
2033+ (MISC_GPIOB_PIN_ENABLE_REG) |= (MISC_PCI_PINS); \
2034+}
2035+
2036+#define HAL_MISC_DISABLE_PCI_PINS() \
2037+{ \
2038+ (MISC_GPIOB_PIN_ENABLE_REG) &= ~(MISC_PCI_PINS); \
2039+}
2040+
2041+#define HAL_MISC_ENABLE_ALL_SHARED_GPIO_PINS() \
2042+{ \
2043+ (MISC_GPIOA_PIN_ENABLE_REG) = (0x0); \
2044+ (MISC_GPIOB_PIN_ENABLE_REG) = (0x0); \
2045+}
2046+
2047+#define HAL_MISC_DISABLE_ALL_SHARED_GPIO_PINS() \
2048+{ \
2049+ (MISC_GPIOA_PIN_ENABLE_REG) = (0xFFFFFFFF); \
2050+ (MISC_GPIOB_PIN_ENABLE_REG) = (0xFFFFFFFF); \
2051+}
2052+
2053+#define HAL_MISC_CONFIGURE_GPIOA_RESISTOR(pin_index, value) \
2054+{ \
2055+ (MISC_GPIOA_RESISTOR_CONFIG_REG) &= ~(0x3 << (2 * pin_index)); \
2056+ (MISC_GPIOA_RESISTOR_CONFIG_REG) |= ((value & 0x3) << (2 * pin_index)); \
2057+}
2058+
2059+#define HAL_MISC_CONFIGURE_GPIOA_DRIVE_STRENGTH(pin_index, value) \
2060+{ \
2061+ (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) &= ~(0x1 << pin_index); \
2062+ (MISC_GPIOA_DRIVE_STRENGTH_CONFIG_REG) |= (value << pin_index); \
2063+}
2064+
2065+#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE0() \
2066+{ \
2067+ (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x0); \
2068+}
2069+
2070+#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE1() \
2071+{ \
2072+ (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x1); \
2073+}
2074+
2075+#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE2() \
2076+{ \
2077+ (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x2); \
2078+}
2079+
2080+#define HAL_MISC_SELECT_FAST_ETHERNET_PHY_LED_MODE3() \
2081+{ \
2082+ (MISC_FAST_ETHERNET_PHY_CONFIG_REG) = (0x3); \
2083+}
2084+
2085+
2086+#endif // end of #ifndef _STAR_MISC_H_
2087

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