| 1 | /* |
| 2 | * include/asm-m68k/cfcache.h - Coldfire Cache Controller |
| 3 | * |
| 4 | * Kurt Mahan kmahan@freescale.com |
| 5 | * |
| 6 | * Copyright Freescale Semiconductor, Inc. 2007 |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | */ |
| 13 | #ifndef CF_CFCACHE_H |
| 14 | #define CF_CFCACHE_H |
| 15 | |
| 16 | /* |
| 17 | * CACR Cache Control Register |
| 18 | */ |
| 19 | #define CF_CACR_DEC (0x80000000) /* Data Cache Enable */ |
| 20 | #define CF_CACR_DW (0x40000000) /* Data default Write-protect */ |
| 21 | #define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */ |
| 22 | #define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */ |
| 23 | #define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */ |
| 24 | #define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */ |
| 25 | #define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */ |
| 26 | #define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */ |
| 27 | #define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */ |
| 28 | #define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */ |
| 29 | #define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */ |
| 30 | #define CF_CACR_IVO (0x00100000) /* Invalidate only */ |
| 31 | #define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */ |
| 32 | #define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */ |
| 33 | #define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */ |
| 34 | #define CF_CACR_SPA (0x00004000) /* Search by Physical Address */ |
| 35 | #define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */ |
| 36 | #define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */ |
| 37 | #define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */ |
| 38 | #define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */ |
| 39 | #define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */ |
| 40 | #define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */ |
| 41 | #define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */ |
| 42 | |
| 43 | #ifdef CONFIG_M5445X |
| 44 | /* |
| 45 | * M5445x Cache Configuration |
| 46 | * - cache line size is 16 bytes |
| 47 | * - cache is 4-way set associative |
| 48 | * - each cache has 256 sets (64k / 16bytes / 4way) |
| 49 | * - I-Cache size is 16KB |
| 50 | * - D-Cache size is 16KB |
| 51 | */ |
| 52 | #define ICACHE_SIZE 0x4000 /* instruction - 16k */ |
| 53 | #define DCACHE_SIZE 0x4000 /* data - 16k */ |
| 54 | |
| 55 | #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ |
| 56 | #define CACHE_SETS 0x0100 /* 256 sets */ |
| 57 | #define CACHE_WAYS 0x0004 /* 4 way */ |
| 58 | |
| 59 | #define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \ |
| 60 | CF_CACR_BCINVA+ \ |
| 61 | CF_CACR_ICINVA) |
| 62 | |
| 63 | #ifndef CONFIG_M5445X_DISABLE_CACHE |
| 64 | #define CACHE_INITIAL_MODE (CF_CACR_DEC+ \ |
| 65 | CF_CACR_BEC+ \ |
| 66 | CF_CACR_IEC+ \ |
| 67 | CF_CACR_DESB+ \ |
| 68 | CF_CACR_EUSP) |
| 69 | #else |
| 70 | /* cache disabled for testing */ |
| 71 | #define CACHE_INITIAL_MODE (CF_CACR_EUSP) |
| 72 | #endif /* CONFIG_M5445X_DISABLE_CACHE */ |
| 73 | |
| 74 | #elif defined(CONFIG_M547X_8X) |
| 75 | /* |
| 76 | * * M547x/M548x Cache Configuration |
| 77 | * * - cache line size is 16 bytes |
| 78 | * * - cache is 4-way set associative |
| 79 | * * - each cache has 512 sets (128k / 16bytes / 4way) |
| 80 | * * - I-Cache size is 32KB |
| 81 | * * - D-Cache size is 32KB |
| 82 | * */ |
| 83 | #define ICACHE_SIZE 0x8000 /* instruction - 32k */ |
| 84 | #define DCACHE_SIZE 0x8000 /* data - 32k */ |
| 85 | |
| 86 | #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ |
| 87 | #define CACHE_SETS 0x0200 /* 512 sets */ |
| 88 | #define CACHE_WAYS 0x0004 /* 4 way */ |
| 89 | |
| 90 | /* in for the old cpushl caching code */ |
| 91 | #define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS) |
| 92 | #define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS) |
| 93 | #define LAST_DCACHE_ADDR _DCACHE_SET_MASK |
| 94 | #define LAST_ICACHE_ADDR _ICACHE_SET_MASK |
| 95 | |
| 96 | #define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \ |
| 97 | CF_CACR_BCINVA+ \ |
| 98 | CF_CACR_ICINVA) |
| 99 | |
| 100 | #define CACHE_INITIAL_MODE (CF_CACR_DEC+ \ |
| 101 | CF_CACR_BEC+ \ |
| 102 | CF_CACR_IEC+ \ |
| 103 | CF_CACR_DESB+ \ |
| 104 | CF_CACR_EUSP) |
| 105 | #endif /* CONFIG_M547X_8X */ |
| 106 | |
| 107 | #ifndef __ASSEMBLY__ |
| 108 | |
| 109 | extern unsigned long shadow_cacr; |
| 110 | extern void cacr_set(unsigned long x); |
| 111 | |
| 112 | #endif /* !__ASSEMBLY__ */ |
| 113 | |
| 114 | #endif /* CF_CACHE_H */ |
| 115 | |
